Modular SOC Testing With Reduced Wrapper

Count

Qiang Xu; Nicolici, N., “Modular SOC testing with reduced wrapper count”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Dec. 2005, Page(s): 1894- 1908.

Presented By: Yuyan Xue (April. 2007)

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MotivationModular test strategies (Wrapper, dedicated bus-based TAM) enable the reusability, scalability and interoperability in DFT.Modular test strategies add the overall cost of the test. Modular test strategies deteriorate the system performance if they stand on the critical path.

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ObjectiveReduce the wrapper count, meanwhile maintaining the benefits of modular SOC testing. Compatible to IEEE P1500 standard, meanwhile investigate the suitability of reusing the functional interconnect for transferring test data

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Idea from IEEE P1500

INTEST/EXTESTProducer/ConsumerA core can be tested without wrapping its terminals as long as all its producers and consumers are P1500-wrapped.

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New Wrapper Design for Embedded Cores

No wrapper at all (INTEST/EXTEST modes only)Light wrapper without WBR (RAM/ROM for BIST)Parallel Bypass Register (WBY)Revised P1500 Wrapper for P/C cores.

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New Test Conflicts Caused Traditional TAM lines conflict in IEEE P1500New test conflicts

Producer-CUT Core6->2,5,9

CUT-ConsumerCore2->6,7,8,9

Shared-ProducerCore7,8->2

Shared-ConsumerCore3,6->5

Shared-BusCore1,5->8

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TAM Division Into Three Groups

Flexible-width test for GCUT

Daisy chain for Gpro

d and Gcons

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Wrapper/TAM Co-optimization

Given: PIs, POs, bidirectional I/Os, test patterns, scan chains and scan chain length, total TAM width, wrapper design constrainsOutput: the width of each TAM group, wrapper design for each core, the test schedule Satisfy: wrapper design constrains, maximized light-wrapper number, TAM width constrains, minimized overall SOC TAT

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Three Types of Wrapper Design Constraints

Critical Path -> Light wrapperCores with P1500 wrapper providedTwo-pattern tested ( delay and stuck-open fault)

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TAM Division and Test Scheduling Algorithm

Determine light-wrapped cores <-functional interconnection & wrapper design constraintsCreate Test Incompatible Graph (TIG)Enumeratively find the optimal TAM division and the minimum system TAT. Worst case complexity

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Decide Wrapper TypeGiven: the set of cores, the functional interconnect relationship, wrapper design constrainsOutput: wrapper type for each coreMethodology:

Wrapper status initialization ( wrapper constraints)Light-wrapped as default and compute test dependency.Choose cores with less test dependency

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Construct TIG

Given: the set of cores, test conflictsOutput: node for core and edge for conflicts between two coresConflicts only exist between:

Two light-wrapped coresA Light-wrapped core and

its producers/consumers

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Rectangle representation for P1500-wrapped core

Rectangle representation for light-wrapped core

Dynamic Rectangle Representation

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Adaptive Dynamic Rectangle Packing

Given: the set of cores, TIG, TAM divisionOutput: schedule for each core, overall TAT of the SOCMethodology:

Find out pareto-optimal TAM widthSchedule cores using the preferred width, as long as TAM width is sufficientPack the idle time with remaining testRepeat scheduling process for remaining test if one test is completed

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Experimental Result

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Experimental Result (Continued)

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Contributions

Light-wrapped core is introduced to reduce the number of wrapper cells in the SOC without impacting its testability. Up to half of the cores can be unwrapped without affecting the test quality.New modular SOC test architecture is proposed, which employs three separate TAM groups and facilitates concurrent testing of both P1500-wrapped cores and light-wrapped cores.New algorithms for wrapper/TAM co-optimization and test scheduling is introduced.