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MODULE I

CPU - Arithmetic: Signed addition and subtraction BCD adder

Multiplication Array multiplier Booths Algorithm, Division Restoring and non-restoring division.

INTRODUCTION

In describing computer system, a distinction is often made between

computer architecture and computer organization. Computer architecture refers

to those attributes of a system visible to a programmer, or put another way, thoseattributes that have a direct impact on the logical execution of a

program. Computer organization refers to the operational units and their

interconnection that realize the architecture specification.

Examples of architecture attributes include the instruction set, the number of

bits to represent various data types (e.g.., numbers, and characters), I/O

mechanisms, and technique for addressing memory. Examples of organization

attributes include those hardware details transparent to the programmer, such as

control signals, interfaces between the computer and peripherals, and the memory

technology used.

As an example, it is an architectural design issue whether a computer will

have a multiply instruction. It is an organizational issue whether that instruction

will be implemented by a special multiply unit or by a mechanism that makes

repeated use of the add unit of the system. The organization decision may be bases

on the anticipated frequency of use of the multiply instruction, the relative speed of

the two approaches, and the cost and physical size of a special multiply unit.

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Historically, and still today, the distinction between architecture and

organization has been an important one. Many computer manufacturers offer a

family of computer model, all with the same architecture but with differences in

organization. Consequently, the different models in the family have different price

and performance characteristics. Furthermore, an architecture may survive many

years, but its organization changes with changing technology.

Basic Structure of a Computer

Figure shows the general structure of the computer. It consists of:

A main memory, which stores both data and instructions.

An arithmetic-logical unit (ALU) capable of operating on binary data. A control unit, which interprets the instructions in memory and causes them

to be executed.

Input and output (I/O) equipment operated by the control unit .

Basic structure of a computer

Input Unit

A computer must receive both data and program statements to function properly

and be able to solve problems. Computer accepts the information through input

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devices. Computer input devices read data from a source, such as magnetic disks,

and translate that data into electronic impulses for transfer into the CPU. Some

typical input devices are a keyboard, a mouse, or a scanner.

Arithmetic & Logic Unit

The arithmetic-logic section performs arithmetic operations, such as

addition, subtraction, multiplication, and division. Through internal logic

capability, it tests various conditions encountered during processing and takes

action based on the result.

Control Unit

The control section directs the flow of traffic (operations) and data. It also

maintains order within the computer. The control section selects one program

statement at a time from the program storage area, interprets the statement, and

sends the appropriate electronic impulses to the arithmetic-logic and storage

sections so they can carry out the instructions. The control section does not

perform actual processing operations on the data. The control section instructs theinput device on when to start and stop transferring data to the input storage area. It

also tells the output device when to start and stop receiving data from the output

storage area.

ALU &Control Unit together called Central Processing Unit ( CPU). CPU is the

brain of a computer system. The CPU processes data transferred to it from one of

the various input devices. It then transfers either an intermediate or final result ofthe CPU to one or more output devices. A central control section and work areas

are required to perform calculations or manipulate data. The CPU is the

computing center of the system. It consists of a control unit and an arithmetic-logic

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unit. Each section within the CPU serves a specific function and has a particular

relationship with the other sections within the CPU.

Memory unit

The memory unit is sometimes called primary storage or main storage because this

section functions similar to our own human memory. The storage section serves

different purposes; some relate to retention (holding) of data during processing.

First, data is transferred from an input device to the memory unit where it

remains until the computer is ready to process it. Second, a "scratch pad"

memory within the storage section holds both the data being processed and the

intermediate results of the arithmetic-logic operations. Third, the

storage section retains the processing. From there the processing results can be

transferred to an output device. The fourth purpose is to store program statements

transferred from an input device to process the data.

Output Unit

As program statements and data are received by the CPU from an input device, the

results of the processed data are sent from the CPU to an output device. These

results are transferred from the output storage area onto an output medium, such as

a floppy disk, hard drive, video display, printer, and so on.

The operations performed by a computer using the functional components

can be summarized as follows:

It accepts information (program and data) through input unit and transfers it tothe memory

Information stored in the memory is fetched, under program control, into an

arithmetic and logic unit for processing

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Processed information leaves the computer through an output unit The control unit controls all activities taking place inside a computer.

CPU-ARITHMETIC

Data is manipulated by using the arithmetic instructions in digital computers.

Data is manipulated to produce results necessary to give solution for the

computationproblems. The Addition, subtraction, multiplication and division are

the four basic arithmetic operations. If we want then we can derive other

operations by using these four operations. To execute arithmetic operations there is

a separate section called arithmetic processing unit in central processing unit. The

arithmetic instructions are performed generally on binary or decimal data.Binary number system

The number system followed by computers

Base is two and any number is represented as an array containing 1s and 0s

representing coefficients of power of two.

Used in computer systems because of the ease of representing 1 and 0 as two

levels of voltage/power high and low To represent decimal system, 10 levels of voltage would be required!

Correspondingly complex hardware too

Binary arithmetic

Addition Subtraction

Multiplication Division

Binary addition

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Four basic rules for elementary addition

0 + 0 = 0 ; 0 + 1 = 1; 1 + 0 = 1; 1 + 1 = 10;

Carry -overs are performed in the same manner as in decimal addition

11001 +

1001

100010

Binary subtraction

Four rules for elementary subtraction

0 0 = 0; 1 0 = 1; 1 1 = 0; 0 1 = 1, but with a borrow of 1 from the next column of minuend

1101

1100

0001

Integer RepresentationIntegers are whole numbers or fixed-point numbers with the radix point fixed after the least-significant bit. They are contrast to real numbers or floating-point numbers , where the position of theradix point varies. It is important to take note that integers and floating-point numbers are treateddifferently in computers. They have different representation and are processed differently (e.g.,floating-point numbers are processed in a so-called floating-point processor). Floating-pointnumbers will be discussed later.Computers use a fixed number of bits to represent an integer. The commonly-used bit-lengths forintegers are 8-bit, 16-bit, 32-bit or 64-bit. Besides bit-lengths, there are two representation schemesfor integers:

1. Unsigned Integers : can represent zero and positive integers.2. Signed Integers : can represent zero, positive and negative integers. Three representation

schemes had been proposed for signed integers:

a. Sign-Magnitude representation

b. 1's Complement representation

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c. 2's Complement representation

n -bit Unsigned Integers

Unsigned integers can represent zero and positive integers, but not negative integers. The value ofan unsigned integer is interpreted as " the magnitude of its underlying binary pattern ".Example 1: Suppose that n =8 and the binary pattern is 0100 0001B , the value of this unsignedinteger is 12^0 + 12^6 = 65D .Example 2: Suppose that n =16 and the binary pattern is 0001 0000 0000 1000B , the value of thisunsigned integer is 12^3 + 12^12 = 4104D .Example 3: Suppose that n =16 and the binary pattern is 0000 0000 0000 0000B , the value of thisunsigned integer is 0 .An n-bit pattern can represent 2^ n distinct integers. An n-bit unsigned integer can represent integersfrom 0 to (2^ n )-1 , as tabulated below:

n Minimum Maximum

8 0 (2^8)-1 (=255)

16 0 (2^16)-1 (=65,535)

Signed Integers

Signed integers can represent zero, positive integers, as well as negative integers. Threerepresentation schemes are available for signed integers:

1. Sign-Magnitude representation

2. 1's Complement representation

3. 2's Complement representation

In all the above three schemes, the most-significant bit (msb) is called the sign bit . The sign bit is usedto represent the sign of the integer - with 0 for positive integers and 1 for negative integers.The magnitude of the integer, however, is interpreted differently in different schemes.

n -bit Sign Integers in Sign-Magnitude Representation

In sign-magnitude representation:

The most-significant bit (msb) is the sign bit , with value of 0 representing positive integer and 1representing negative integer.

The remaining n-1 bits represents the magnitude (absolute value) of the integer. The absolutevalue of the integer is interpreted as "the magnitude of the ( n-1)-bit binary pattern".

Example 1 : Suppose that n =8 and the binary representation is 0 100 0001B .Sign bit is 0 positive

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Absolute value is 100 0001B = 65D Hence, the integer is +65D

Example 2 : Suppose that n =8 and the binary representation is 1 000 0001B .Sign bit is 1 negative

Absolute value is 000 0001B = 1D Hence, the integer is -1D Example 3 : Suppose that n =8 and the binary representation is 0 000 0000B .

Sign bit is 0 positiveAbsolute value is 000 0000B = 0D Hence, the integer is +0D

Example 4 : Suppose that n =8 and the binary representation is 1 000 0000B .Sign bit is 1 negativeAbsolute value is 000 0000B = 0D Hence, the integer is -0D

The drawbacks of sign-magnitude representation are:

1. There are two representations ( 0000 0000B and 1000 0000B ) for the number zero, which couldlead to inefficiency and confusion.

2. Positive and negative integers need to be processed separately.

4 n -bit Sign Integers in 1's Complement Representation

In 1's complement representation:

Again, the most significant bit (msb) is the sign bit , with value of 0 representing positive integers

and 1 representing negative integers. The remaining n-1 bits represents the magnitude of the integer, as follows:

o for positive integers, the absolute value of the integer is equal to "the magnitude of the ( n-1)-bit binary pattern".

o for negative integers, the absolute value of the integer is equal to "the magnitude ofthe complement (inverse ) of the ( n-1)-bit binary pattern" (hence called 1's complement).

Example 1 : Suppose that n =8 and the binary representation 0 100 0001B .Sign bit is 0 positiveAbsolute value is 100 0001B = 65D Hence, the integer is +65D

Example 2 : Suppose that n =8 and the binary representation 1 000 0001B .Sign bit is 1 negativeAbsolute value is the complement of 000 0001B , i.e., 111 1110B = 126D Hence, the integer is -126D

Example 3 : Suppose that n =8 and the binary representation 0 000 0000B .Sign bit is 0 positive

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Absolute value is 000 0000B = 0D Hence, the integer is +0D

Example 4 : Suppose that n =8 and the binary representation 1 111 1111B .Sign bit is 1 negative

Absolute value is the complement of 111 1111B , i.e., 000 0000B = 0D Hence, the integer is -0D

Again, the drawbacks are:

1. There are two representations ( 0000 0000B and 1111 1111B ) for zero.The positive integers and negative integers need to be processed separately

n -bit Sign Integers in 2's Complement Representation

In 2's complement representation:

Again, the most significant bit (msb) is the sign bit , with value of 0 representing positive integersand 1 representing negative integers.

The remaining n-1 bits represents the magnitude of the integer, as follows:o for positive integers, the absolute value of the integer is equal to "the magnitude of the ( n-

1)-bit binary pattern".o for negative integers, the absolute value of the integer is equal to "the magnitude of

the complement of the ( n-1)-bit binary pattern plus one " (hence called 2's complement).Example 1 : Suppose that n =8 and the binary representation 0 100 0001B .

Sign bit is 0 positiveAbsolute value is 100 0001B = 65D

Hence, the integer is+65D

Example 2 : Suppose that n =8 and the binary representation 1 000 0001B .Sign bit is 1 negativeAbsolute value is the complement of 000 0001B plus 1 , i.e., 111 1110B + 1B = 127D Hence, the integer is -127D

Example 3 : Suppose that n =8 and the binary representation 0 000 0000B .Sign bit is 0 positiveAbsolute value is 000 0000B = 0D Hence, the integer is +0D

Example 4 : Suppose that n =8 and the binary representation 1 111 1111B .

Sign bit is 1 negativeAbsolute value is the complement of 111 1111B plus 1 , i.e., 000 0000B + 1B = 1D Hence, the integer is -1D

Computers use 2's Complement Representation for SignedIntegers

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The answer is the positive binary number 0001101=13 10.

Example 2 : 22 - 35, again both represented as 7-bit numbers with a sign bit.

+22 in binary is: 00010110

+35 in binary is: 00100011

-35 in binary is: 10100011

-35 in 1's complement is: 11011100

The sum to be calculated is below

00010110

+11011100

11110010

This time the addition does not produce a 9th bit, but the sign bit is 1. In this case it

again tells us two things:

the answer is negative

the answer is represented in 1's complement notation

So to get the final answer we need to turn our answer into binary. If the 1'scomplement notation is 11110010 then the binary representation is 10001101 (note

- the sign bit doesn't change, it's still a negative number!). This is the binary for -

13.

2's Complement Addition

Two's complement addition follows the same rules as binary addition.

Add the numbers and if carry occurs discard the carry.

Example

5 + (-3) = 2 0000 0101 = +5

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+ 1111 1101 = -3

--------------------------------------------------------------------------------

0000 0010 = +2

2's Complement Subtraction

Take the 2s complement of the subtrahend Add to the minuend If carry occurs then discard the carry.

Example: 7 - 12 = (-5) 0000 0111 = +7

+ 1111 0100 = -12

--------------------------------------------------------------------------------

1111 1011 = -5

Overflow

A situation occurs because the magnitude of the results of arithmetic operations

has become too large for the fixed word length of the computer to represent them

properly. (If the result is out of the range then overflow occurs.)

Eg: using 4- bit (signed numbers)

710 - 3 10

0007

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9997+

0004

-710 + 3 10 9993

0003+

9996

710 + 3 10 0007

0003+

0010

Example :

7 3 = 2 remainder 1 0000 0111 = +7 0000 0100 = +4

+ 1111 1101 = -3 0000 0100 = -3

--------------------------------------------------------------------------------

+ 1111 1101 = +4 0000 0001 = +1 (remainder)

Overflow occurs when adding two numbers have same sign. If X and Y are two numbers having the same sign then an overflow occurs

when the sum is having different sign

SIGNED ADDITION AND SUBTRACTION

We designate the magnitude of the two numbers by A and B. Where the

signed numbers are added or subtracted, we find that there are eight different

conditions to consider, depending on the sign of the numbers and the operation

performed. These conditions are listed in the first column of table given below.

The other columns in the table show the actual operation to be performed with the

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magnitude of the numbers. The last column is needed to present a negative zero. In

other words, when two equal numbers are subtracted, the result should be +0 not -

0.

Operation Add

Magnitudes

Subtract Magnitudes

When A > B When A < B When A = B

(+A) + (+B) +(A + B)

(+A) + ( B) + (A B) (B A) + (A B)

( A) + (+ B) (A B) + (B A) + (A B)

( A) + ( B) (A + B)

(+ A) (+ B) + (A + B) (B A) + (A B)(+ A) ( B) + (A + B)

( A) (+B) (A + B)

( A) ( B) (A B) + (B A) + (A B)

The algorithms for addition and subtraction are derived from the table and can be

stated as follows.

Algorithm for Addition

When the signs of A and B are same, add the two magnitudes and attach the

sign of result is that of A. When the signs of A and B are not same, compare the

magnitudes and subtract the smaller number from the larger. Choose the sign of the

result to be the same as A, if A > B or the complement of the sign of A if A < B. If

the two magnitudes are equal, subtract B from A and make the sign of the result

will be positive .

Algorithm for Subtraction

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When the signs of A and B are different, add the two magnitudes and attach

the sign of result is that of A. When the signs of A and B are same, compare the

magnitudes and subtract the smaller number from the larger. Choose the sign of the

result to be the same as A, if A > B or the complement of the sign of A if A < B. If

the two magnitudes are equal, subtract B from A and make the sign of the result

will be positive .

Hardware Implementation

Let A and b to registers that hold the magnitude of the numbers , and As and

Bs be two flip flop that hold the corresponding signs . The result of the operation

may be transferred to registers A and As . Thus A and As together form andaccumulator registers .

Subtraction is done by adding A to the 2s complement of B.The output

carry is transferred to flip-flop E.The add overflow flip-flop AVF holds the

overflow bit when A and B are added.

The addition of A + B is done through the parallel adder. The S (sum) of

adder is applied to input of A register . The complementer provides an output of B

or complement of B depending on the state of mode control M . The M signal is

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also applied to the input carry is 0 . and the output of the adder is equal to sum

A+B. When M = 1 ,The 1s complement of B is applied to the adder , the input

carry is 1 , and output S=A+b+1 . T his is equal to A plus the 2s complement of b

, which is equal to the subtraction , A B.

Flowchart

The two signs As and Bs are compared by an exclusive OR gate . If the

output of the gate is 0,the signs are identical; if it is 1 ,the signs are different. For

an add operation, identical signs dictate that magnitudes be added. For a subtract

operation, different s dictates that the magnitudes be added . The magnitudes areadded with a microoperation EA = A+B ,where EA is a register that combines E

and A. The carry in E after the addition constitutes an overflow if it is equal to 1.

The value of E is transferred into the add-overflow flip flop AVF.

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The two magnitudes are subtracted if the signs are different for an add

operation or identical for a subtract operation. The magnitudes are subtracted by

adding A to operation or identical for a subtract operation . The magnitudes are

subtracted by adding a to the 2s complement of B. No over flow can occur if thenumbers are subtracted so AVF is cleared to 0.A 1 in E indicates that A>B and the

number in A is the correct result.If this number is zero,the sign As must be made

positive to avoid a negative 0. A 0 in E indicates that A

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out of the addition . When the two carries are applied to an exclusive - Or gate ,

overflow is detected when the output of the gate is equal to 1. The register

configuration for the hardware implementation is shown in figure . We name the A

register AC (accumulator) and the B register BR .

Algorithm for adding and subtracting numbers in signed 2s

complement representation

The leftmost bit in AC and BR represent the sign bits of the numbers . The

two sign bits are added or subtracted together with the other bits in the

complementer and parallel adder . The overflow flip-flop V is set to 1 if there is

an overflow . The outout carry in this case is discarded.

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The subtraction operation is accomplished by addibg the content of AC to

the 2s compl ement of BR . Taking the 2s compl ement of BR has the effect of

changing is +ve number to ve , and vice versa. An overflow must be checked

during this operation because the two numbers added could have the same sign.

The sum obtained by adding the contents of AC ad BR . The over flow bit V is aset to 1 if the exclusive-OR of the last two carries is 1 , and it is cleared to 0

otherwise.

BCD ADDER

BCD means that each decimal digit is represented by a nibble(binary code of 4

digit).Though 16 numbers can be represented by 4 bits,only 10 of these are

used.The ramaining 6 codes are invalid.

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BCD Addition

The rules for BCD addition are

1.Add the two numbers using binary addition.If the four bit sum is equal or less

than nine(1001) it is a valid BCD number.

2.If the four bit sum is more than 9 or a carry is generated from the group of 4

bits,the result is invalid.In such a case add 6(0110) to the four bit sum to skip the

six invalid states.If a carry is generated when adding 6,add the carry to the next

four bit group.

For example, let's consider the addition of the two BCD digits 5 and 3:

Decimal BCD

0 0000

1 0001

2 00103 0011

4 0100

5 0101

6 0110

7 0111

8 1000

9 1001

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Now consider the sum of 5 and 8:

The sum is 1101 2 = 13, but this result should be correctly represented as

0001 0011 in BCD notation. Fortunately, there is a simple way to find the correct

result. We add 6 (0110 2) to the digit sum if it exceeds 9. Let's examine the

following cases:

In both cases, by adding six we obtain the correct answer in BCD.

1001+1001

10010 ,carry generated,so add 01100110

11000=0001 1000=18 If sum is up to 9

Use the regular Adder. If the sum > 9

The cases where the sum of two 4-bit numbers is greater than 9 are in the

following table:

S4 S 3 S2 S1 S0

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Use the regular adder and add 6 to the result

Whenever S 4=1 (sums greater than 15)

Whenever S 3=1 and either S 2 or S 1 or both are 1 (sums 10 to 15)

The previous table can be expressed as: X = S 4 + S 3 ( S 2 + S 1)

So, whenever X = 1 we should add a correction of 0110 to the sum.

BCD Adder Circuit

0 1 0 1 0 10

0 1 0 1 1 11

0 1 1 0 0 12

0 1 1 0 1 13

0 1 1 1 0 14

0 1 1 1 1 15

1 0 0 0 0 16

1 0 0 0 1 17

1 0 0 1 0 18

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MULTIPLICATION

Rules of Binary Multiplication

0 x 0 = 0

0 x 1 = 0

1 x 0 = 0

1 x 1 = 1, and no carry or borrow bits

Multiplication of two fixed point binary numbers in signed magnitude

representation is done with paper and pencil by a process of successive shift adds

operations. The process consist of looking at successive bits of the multiplier ,

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least significant bit first . If the multiplier bit is a 1 , the multiplicand is coppied

down ; otherwise , zeros are copied down . the number copied down in successive

lines are shifted one position to the left from the previous number . Finally ,the

numbers are added and their sum forms are product.

For example,

23 10111 Multiplicand19 x 10011 Multiplier

1011110111

00000 +00000

10111437 110110101 Product

Multiplication of Signed Magnitude Data

provide an adder for the summation of only two binary numbers and

succesfully accumulate the partial products in a register .

instead of shifting the multiplicant to the left ,the partial product is shifted to

the right,which results in leaving the partial product and multiplicand in the

required relative positions.

when the corresponding bit of the multiplier is zero,there is no need to add

all zeros to the partial product since it will not alter its value.

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Hardware Implementation

The hardware for multiplication is shown in the figure. The multiplier is stored in

the Q register and its sign in Qs.The sequence counter SC is initially set to a

number equalt to the number of bits in a multiplier. The counter is decremented by

1, after forming each partial product. When the content of the counter reaches 0,the

product is formed and the process is stop.

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Flowchart

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Initially,the multiplicand is in B and the multiplier in Q and their corresponding

signs are in Bs and Qs respectively.The signs are compared,and the both A and Q

are set to correspond to the sign of product since a double length product will be

stored in registers A and Q.Registers A and E are cleared and the sequence

counter SC is set,to a number equal to the number of the bits in the multiplier.

After the initialisation ,the lower order bit of the mutiplier in Qn is tested. If it is

a 1,the multiplicand in B is added to the present partial product in B .If it is

0,nothing is done.Register EAQ is then shifted once to the right to form the new

partial product. The sequence counter is decrementd by 1 and its new value is

checked. If it is not equal to 0,the process is repeated and a new partial product is

formed. The process stops when SC =0. The final product is available in both A

and Q, with A holding the most significant bits and Q holding the least significant

bits.

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Example

ARRAY MULTIPLIER

To check the bits of the multiplier one at a time and forming partial products

is a sequential operation requiring a sequence of add and shift micro-operations.

The multiplication of two binary numbers can be done with one micro-operation

by using combinational circuit that forms the product bits all at once. This is a fast

way since all it takes is the time for the signals to propagate through the gates that

form the multiplication array. However, an array multiplier requires a large number

of gates, and so it is not an economical unit for the development of ICs.

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2-bit by 2-bit array multiplier

Consider the multiplication of two 2-bit numbers as shown in Fig. The

multiplicand bits are b1 and b0, the multiplier bits are a1 and a0, and the product is

c3 c2 c1 c0. The first partial product is obtained by multiplying a0 by b1b0. The

multiplication of two bits gives a 1 if both bits are 1; otherwise, it produces a 0.

This is identical to an AND operation and can we implement it with an AND gate.

As shown in the diagram, the first partial product is formed by means of two AND

gates. The second partial product is formed by multiplying a1 by b1b0 and is

shifted one position to the left. The two partial products are added with two half-

adder (HA) circuits. Usually, there are more bits in the partial products and it will

be necessary to use full-adders to produce the sum. Note that the least significant

bit of the product does not have to go through an adder since it is formed by theoutput of the first AND gate .

A combinational circuit binary multiplier with more bits can be constructed

in a similar fashion. A bit of the multiplier is ANDed with each bit of the

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multiplicand in as many levels as there are bits in the multiplier. The binary output

in each level AND gates is added in parallel with the partial product of the

previous level to form a new partial product. The last level produces the product.

For j multiplier bits and k multiplicand bits we need j * k AND gates and (j 1) k-

bit adders to produce a product of j + k bits .

As a second example, consider a multiplier circuit that multiplies a binary

number of four bits with a number of three bits. Let the multiplicand be

represented by b3b2b1b0 and the multiplier by a2a1a0. Since k=4 and j=3, we need

12 AND gates and two 4-bit adders to produce a product of seven bits. The logic

diagram of the multiplier is shown in Figure.

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4-bit by 3-bit array multiplier

BOOTHS MULTIPLICATION ALGORITHM

If the numbers are represented in signed 2s complement then we can

multiply them by using Booth algorithm.

Booth algorithm needs examination of the multiplier bits and shifting of the partial

product. Prior to the shifting, the multiplicand added to the partial product,

subtracted from the partial product, or left unchanged by the following rules:

1. The multiplicand is subtracted from the partial product when we get the first

least significant 1 in a string of 1's in the multiplier.

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2. The multiplicand is added to the partial product when we get the first Q

(provided that there was a previous 1) in a string of 0's in the multiplier.

3. The partial product does not change when the multiplier bit is the same as

the previous multiplier bit.

The algorithm applies to both positive and negative multipliers in 2's

complement representation.

Hardware Implementation

The hardware implementation of Booth algorithm requires the register

configuration shown in Figure . Qn represents the least significant bit of the

multiplier in register QR. An extra flip-flop Qn+1 is appended to QR to provide a

double bit inspection of the multiplier. The flowchart for Booth algorithm is shown

in Figure . AC and the appended bit Qn+1 are initially set to 0 and the sequence

counter SC is set to a number n equal to the number of bits in the multiplier.

The two bits of the multiplier in Qn and Qn+1 are inspected. If the two bits are

10, it means that the first 1 in a string of 1's has been encountered. This needs a

subtraction of the multiplicand from the partial product in AC. If the two bits are

equal to 01. It means that the first 0 in a string of 0's has been encountered. This

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needs the addition of the multiplicand to the partial product in AC. When the two

bits are equal, the partial product does not change. An overflow cannot occur

because the addition and subtraction of the multiplicand follow each other. Hence,

the two numbers that are added always have opposite sign, a condition that

excludes an overflow. Next step is to shift right the partial product and the

multiplier (including bit Qn+1). This is an arithmetic shift right (ashr) operation

which shifts AC and QR to the right and leaves the sign bit in AC same The

sequence counter decrements and the computational loop is repeated n times.

Flowchart for Booth s Algorithm

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Example

A numerical example of Booth algorithm is given in Table for n = 5. It

gives the multiplication of (-9) x (-13) = +117. Note that the multiplier in QR is

negative and that the multiplicand in BR is also negative. The 10-bit product

appears in AC. The final value of Qn+1 is the original sign bit of the multiplier and

should not be taken as part of the product.

DIVISION ALGORITHMS

Division of two fixed-point binary numbers in signed magnitude

representation is performed with paper and pencil by a process of successive

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compare, shift and subtract operations. Binary division is much simpler than

decimal division because here the quotient digits are either 0 or 1 and there is no

need to estimate how many times the dividend or partial remainder fits into the

divisor. The division process is described below. The divisor B has five bits and

the dividend A has ten.

The devisor is compared with the five most significant bits of the dividend.

Since the 5-bit number is smaller than B, we again repeat the same process. Now

the 6-bit number is greater than B, so we place a 1 for the quotient bit in the sixth

position above the dividend. Now we shift the divisor once to the right and subtract

it from the dividend. The difference is known as a partial remainder because the

division could have stopped here to obtain a quotient of 1 and a remainder equal to

the partial remainder. Comparing a partial remainder with the divisor continues the

process. If the partial remainder is greater than or equal to the divisor, the quotient

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bit is equal to 1. The divisor is then shifted right and subtracted from the partial

remainder. If the partial remainder is smaller than the divisor, the quotient bit is 0

and no subtraction is needed. The divisor is shifted once to the right in any case.

Obviously the result gives both a quotient and a remainder.

There are two types of division algorithms:

1. Restoring

2. Non-restoring

RESTORING ALGORITHM

Hardware Implementation for Signed-Magnitude Data

In hardware implementation for signed-magnitude data in a digital

computer, it is convenient to change the process slightly. Instead of shifting the

divisor to the right, two dividends, or partial remainders, are shifted to the left, thus

leaving the two numbers in the required relative position. Subtraction is achieved

by adding A to the 2's complement of B. End carry gives the information about the

relative magnitudes.The hardware required is identical to that of multiplication. Register EAQ is

now shifted to the left with 0 inserted into Qn and the previous value of E is lost.

Example

The divisor is stored in the B register and the double-length dividend is stored in

registers A and Q. The dividend is shifted to the left and the divisor is subtracted

by adding its 2's complement value. A quotient bit 1 is inserted into Qn and the

partial remainder is shifted to the left to repeat the process when E = 1. If E = 0, it

signifies that A < B so the quotient in Qn remains a 0 (inserted during the shift). To

restore the partial remainder in A the value of B is then added to its previous value.

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The partial remainder is shifted to the left and the process is repeated again until

we get all five quotient-bits. Note that while the partial remainder is shifted left,

the quotient bits are shifted also and after five shifts, the quotient is in Q and A has

the final remainder. The sign of the quotient is obtained from the signs of the

dividend and the divisor. If the two signs are same, the sign of the quotient is plus.

If they are not identical, the sign is minus. The sign of the remainder is the same

as that of the dividend.

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Flowchart

A and Q contain the dividend and B has the divisor. The sign of the result is

transferred into Q. A constant is set into the sequence counter SC to specify the

number of bits in the quotient. As in multiplication, we assume that operands are

transferred to registers from a memory unit that has words of n bits. Since an

operand must be stored with its sign, one bit of the word will be occupied by the

sign and the magnitude will have n-1 bits.

We can check a divide-overflow condition by subtracting the divisor (B)

from half of the bits of the dividend stored (A). If A

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The division of the magnitudes begins by shifting the dividend in AQ to

the left with the high-order bit shifted into E. If the bit shifted into E is 1, we know

that EA>B because EA consists of 1 followed by n-1 bits while B consists of only

n-1 bits. In this case, B must be subtracted from EA and 1 inserted into Qn for the

quotient bit. Since in register A, the high-order bit of the dividend (which is in E)

is missing, its value is EA 2n-1. Adding to this value the 2 s complement of B

results in:

(EA 2n-1) + (2n-1 B) = EA B

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If we want E to remain a 1, the carry from this addition is not transferred

to E. If the shift-left operation inserts a 0 into E, we subtract the divisor by adding

its 2s complement value and the carry is transferred into E. If E=1, it shows that

A< B, therefore Qn is set. If E = 0, it signifies that A < B and the original number

is restored by B + A. In the latter case we leave a 0 in Qn.

We repeat this process with register A holding the partial remainder.

After n-1 loops, the quotient magnitude is stored in register Q and the remainder is

found in register A. The quotient sign is in Qs and the sign of the remainder is in

As.

Divide Overflow

An overflow may occur in the division operation, which may be easy to handle if

we are using paper and pencil but is not easy when are using hardware. This is

because the length of registers is finite and will not hold a number that exceeds the

standard length. To see this, let us consider a system that has 5-bit registers. We

use one register to hold the divisor and two registers to hold the dividend.

From the example , the quotient will consist of six bits if the five most

significant bits of the dividend constitute a number greater than the divisor. The

quotient is to be stored in a standard 5-bit register, so the overflow bit will require

one more flip-flop for storing the sixth bit. This divide-overflow condition must be

avoided in normal computer operations because the entire quotient will be too long

for transfer into a memory unit that has words of standard length, that is, the same

as the length of registers. Provisions to ensure that this condition is detected must

be included in either the hardware or the software of the computer, or in a

combination of the two.

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When the dividend is twice as long as the divisor, we can understand the

condition for overflow as follows:

A divide-overflow occurs if the high-order half bits of the dividend makes a

number greater than or equal to the divisor. Another problem associated with

division is the fact that a division by zero must be avoided. The divide-overflow

condition takes care of this condition as well. This occurs because any dividend

will be greater than or equal to a divisor, which is equal to zero. Overflow

condition is usually detected when a special flip-flop is set. We will call it a divide-

overflow flip-flop and label it DVF.

NON RESTORING DIVISION

In this restoring can be avoided.

Algorithm:

Step 1: Do the following n times

a) If the sign of A is 0 , then shift A &Q left one bit and subtract M from

A, otherwise shift A &Q left one bit and add M to A

b) If the sign of A is 0 then set q 0 to 1, otherwise set q 0 to 0.

Step2: If the sign of A is 1 then add M to A.

Step 2 is needed to leave the proper positive remainder in A at the end of n cycles

of step 1.

Example: Example: 1000/11

A= 000000, M=00011, Q=1000

A Q M=00011

00000 1000 Initial

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Quotient=0010 in Register Q

Remainder=11111 in Register A is negative, so restore the remainder by performA+M=11111+00011=0010

Hardware circuit non restoring and restoring division is same.

References:

1.Computer SystemArchitecture-Morris Mano

2.Computer Organization-Carl Hamacher3. www.nptel.iitm.ac.in

value

00001 000- Shift

11110 0000 Subtract/set

q0

11100 000- Shift

11111 0000 Add/set q 0

11110 000- Shift

00001 0001 Add/set q 0

00010 001- Shift

11111 0010 Subtract/setq0