Upload
others
View
3
Download
0
Embed Size (px)
Citation preview
Construction Analysis
Mosel Vitelic MS62256CLL-70PC256Kbit SRAM
Report Number: SCA 9703-499
®
Serv
ing
the
Glob
alSem
iconductor IndustrySince
1964
17350 N. Hartford DriveScottsdale, AZ 85255Phone: 602-515-9780Fax: 602-515-9781
e-mail: [email protected]: http://www.ice-corp.com
- i -
INDEX TO TEXT
TITLE PAGE
INTRODUCTION 1
MAJOR FINDINGS 1
TECHNOLOGY DESCRIPTION
Assembly 2
Die Process 2 - 3
ANALYSIS RESULTS I
Assembly 4
ANALYSIS RESULTS II
Die Process and Design 5 - 7
ANALYSIS PROCEDURE 8
TABLES
Overall Evaluation 9
Package Markings 10
Wirebond Strength 10
Die Material Analysis 10
Horizontal Dimensions 11
Vertical Dimensions 12
- 1 -
INTRODUCTION
This report describes a construction analysis of the MOSEL VITELIC MS62256CLL-70PC,
256Kbit SRAM. Two devices packaged in 28-pin Plastic Dual In-Line Packages (PDIPs) were
received for the analysis. Devices were date coded 9543.
MAJOR FINDINGS
Questionable Items:1
• Aluminum thinned up to 95 percent2 at contact edges. Barrier maintained contact
and reduced overall thinning to 90 percent (Figure 14).
• Silicon nodules were noted occupying 53 percent2 of metal line width (Fig. 16).
Nodules of equal size were also noted in contacts occupying 100 percent1 of the
aluminum thickness (Fig. 16).
• Overlay passivation cussped over contact holes creating voids (Fig. 15).
Special Features:
• Sub-micron gate lengths (0.7 micron N- and 0.7 micron P-channel).
• Poly 2 contact pads over N+ diffusions.
1These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application.
2Seriousness depends on design margins.
- 2 -
TECHNOLOGY DESCRIPTION
Assembly:
• Devices were packaged in 28-pin Plastic Dual In-Line Packages (PDIPs).
• The leadframe was constructed of copper and plated externally with tin-lead solder
and internally with silver.
• Die separation was by sawing (90 percent sawn). No cracks or chips were present
at the die surface. Silver-filled epoxy was used to attach the die to the paddle.
• Lead-locking leadframe design (anchors) at all pins.
• Wirebonding was by the thermosonic ball bond method employing 1.1 mil O.D.
gold wire.
• No multiple bond wires were present.
Die Process :
• Devices were fabricated using a selective oxidation, twin-well CMOS process in an
N substrate. No epi was used.
• No die coat was present.
• Passivation consisted of a layer of nitride over a layer of glass. Overlay integrity
tests indicated a defect-free passivation.
• A single level of aluminum on titanium-nitride on titanium was used for metal
interconnect.
- 3 -
TECHNOLOGY DESCRIPTION (continued)
• Pre-metal dielectric consisted of a layer of reflow glass (probably BPSG) over
densified oxides. The glass was reflowed prior to contact cuts only.
• Two layers of polysilicon were used on the die. Polycide 1 (poly 1 and tungsten
silicide) was used to form all standard gates. Poly 2 was used in the cell array to
form “pull-up” resistors and distribute Vcc. Poly 2 was also used to form fuse
structures (Figures 22-24), and to form poly contact pads on N+ diffusions (Fig.
14). Direct poly 2-to-N+ diffusion (buried) contacts were used throughout the die.
Definition of both poly layers was by a dry etch of normal quality.
• Standard implanted N+ and P+ diffusions formed the sources/drains of the CMOS
transistors. An LDD process was used with oxide sidewall spacers left in place.
• Local oxide (LOCOS) isolation. There was no evidence of a step at the well
boundary but according to manufacturer’s data sheet, a twin-well process was
employed on the device.
• A standard 4T NMOS SRAM cell design was used. Metal lines were used to form
the bit lines, and to distribute Gnd. Poly 2 was used to form “pull-up” resistors and
distribute Vcc. Polycide 1 was used to form all gates.
• Poly 2 fuses were present. No cutout was present over fuses, and the design
appears to possibly use current to blow the fuses although this appearance may
simply be misleading. No blown fuses were found.
- 4 -
ANALYSIS RESULTS I
Package and Assembly: Figures 1 - 5
Questionable Items:1 None.
General Items:
• Devices were packaged in 28-pin Plastic Dual In-Line Packages (PDIPs).
• The leadframe was constructed of copper and plated externally with tin-lead solder
and internally with silver. All pins were well formed and there were no gaps at the
lead exits.
• Die separation was by sawing (90 percent sawn). No cracks or chips were present
at the die surface. Silver-filled epoxy was used to attach the die to the
header/paddle. No problems were found.
• Lead-locking leadframe design (anchors) at all pins.
• Wirebonding was by the thermosonic ball bond method employing 1.1 mil O.D.
gold wire. Bonds were well formed and placement was good. No bond lifts
occurred and bond pull strengths were good.
• No multiple bond wires were present.
• No die coat was employed.
1These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application.
- 5 -
ANALYSIS RESULTS II
Die Process: Figures 6 - 32
Questionable Items:1
• Aluminum thinned up to 95 percent2 at contact edges. Barrier maintained contact
and reduced overall thinning to 90 percent (Figure 14).
• Silicon nodules were noted occupying 53 percent2 of metal line width (Fig. 16).
Nodules of equal size were also noted in contacts occupying 100 percent1 of the
aluminum thickness(Fig. 16).
• Overlay passivation cussped over contact holes creating voids (Fig. 15).
Special Features:
• Sub-micron gate lengths (0.7 micron N- and 0.7 micron P-channel).
• Poly 2 contact pads on N+ diffusions.
General Items:
• Fabrication process: Devices were fabricated using a selective oxidation, twin-well
CMOS process in an N substrate. No epi was used.
• Process implementation: Die layout was clean and efficient. Alignment was good at
all levels. No damage or contamination was found.
1These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application.
2Seriousness depends on design margins.
- 6 -
ANALYSIS RESULTS II (continued)
• Die coat: No die coat was present.
• Overlay passivation: A layer of nitride over a layer of glass. Overlay integrity test
indicated defect-free passivation. Edge seal was good.
• Metal integrity: The single layer of metal consisted of aluminum on a titanium-
nitride on titanium barrier. No cap layer was used. The aluminum thinned up to 95
percent at some contact steps but the condition did not appear dangerous.
• Metal patterning: metal was patterned by a dry etch of normal quality. No special
stress reducing designs were present at die corners.
• Metal defects: Silicon nodules were noted occupying 53 percent of line width and
56 percent of line thickness. Silicon nodules were also found in metal contacts
occupying 100 percent of the aluminum thickness. Hillocks in the metal lines were
also noted. Improvements in control of the metal process are desirable.
• Metal step coverage: Aluminum thinned up to 95 percent at contact edges. Total
metal thinning (including barrier) was typically 80 percent.
• Pre-metal dielectric: A layer of reflow glass (probably BPSG) over various
densified oxides was used. Reflow was performed prior to contact cuts only. No
problems were found.
• Contact defects: Contact cuts were defined by a two step process. No over-etching
of the contacts was noted.
- 7 -
ANALYSIS RESULTS II (continued)
• Two layers of polysilicon were used on the die. Polycide 1 (poly 1 and tungsten
silicide) was used to form all standard gates. Poly 2 was used in the cell array to
form “pull-up” resistors and distribute Vcc. Poly 2 was also used to form fuse
structures (Figures 22-24), and to form poly pads over N+ diffusions. Direct poly
2-to-N+ diffusion (buried) contacts were used throughout the die. Definition of
both poly layers was by a dry etch of normal quality.
• Standard implanted N+ and P+ diffusions formed the sources/drains of the CMOS
transistors. An LDD process was used with oxide sidewall spacers left in place. No
problems were found.
• Local oxide (LOCOS) isolation was used. There was no evidence of a step present
at the well boundary but the manufacturer states that a twin-well process is used.
• A standard 4T NMOS SRAM cell design was used. Metal lines were used to form
the bit lines, and to distribute Gnd. Poly 2 was used to form “pull-up” resistors and
distribute Vcc. Polycide 1 was used to form all gates. No problem areas were
identified.
• Poly 2 fuses were present on the die. An oxide cutout was not present over fuses.
No blown fuses were noted. As noted previously, the design may be intended to
blow fuses by current instead of laser.
- 8 -
PROCEDURE
The devices were subjected to the following analysis procedures:
External inspection
X-Ray
Decapsulation
Internal optical inspection
SEM of assembly features
SEM of passivation
Passivation integrity test
Passivation removal
Delayer to metal 1 and inspect
Metal 1 removal and inspect barrier
Delayer to silicon and inspect poly/die surface
Die sectioning (90° for SEM)*
Die material analysis
Measure horizontal dimensions
Measure vertical dimensions
*Delineation of cross-sections is by silicon etch unless otherwise indicated.
- 9 -
OVERALL QUALITY EVALUATION: Overall Rating: Normal/Poor
DETAIL OF EVALUATION
Package integrity N
Package markings G
Die placement N
Wirebond placement G
Wire spacing G
Wirebond quality N
Die attach quality N
Dicing quality N
Die attach method Silver-epoxy
Dicing method Sawn (90 percent)
Wirebond method Thermosonic ball bonds using 1.1 mil O.D. gold wire
Die surface integrity:
Toolmarks (absence) G
Particles (absence) G
Contamination (absence) G
Process defects (absence) N
General workmanship N
Passivation integrity N
Metal definition N
Metal integrity P*
Metal registration N
Contact coverage N
Contact registration N
* Thinning and large silicon nodules.
G = Good, P = Poor, N = Normal, NP = Normal/Poor
- 10 -
PACKAGE MARKINGS
TOP BOTTOM
(LOGO) F50929NA
MS62256CLL-70PC TWN
9543
WIREBOND STRENGTH
Wire material: 1.1 mil diameter gold
Die pad material: Aluminum
Material at package lands: Silver
# of wires pulled: 15
Bond lifts: 0
Force to break - high: 12.0g
- low: 9.0g
- avg.: 10.3g
- std. dev.: 0.93
DIE MATERIAL ANALYSIS
Overlay passivation: A layer of nitride over a layer of glass.
Metallization: Silicon-doped aluminum (Al) with a titanium-nitride (TiN) barrier.
Polycide metal: Tungsten.
- 11 -
HORIZONTAL DIMENSIONS
Die size: 6.6 x 3.6 mm (260 x 143 mils)
Die area: 24.0 mm2 (37,180 mils2)
Min pad size: 0.14 x 0.14 mm (5.5 x 5.5 mils)
Min pad window: 0.12 x 0.12 mm (4.7 x 4.7 mils)
Min pad space: 34.0 microns (1.3 mils)
Min metal width: 1.5 micron
Min metal space: 1.4 micron
Min metal pitch: 2.9 micron
Min contact size: 0.9 micron
Min poly 2 width (array): 0.6 micron
Min polycide 1 width: 0.7 micron
Min polycide 1 space: 1.0 micron
Min gate length* - (N-channel): 0.7 micron
- (P-channel): 0.7 micron
Min diffusion space: 1.0 micron
*Physical gate length
- 12 -
VERTICAL DIMENSIONS
Die thickness: 0.5 mm (19 mils)
Layers:
Passivation 2: 0.5 micron
Passivation 1: 0.2 micron
Metal 1 - aluminum: 0.9 micron
- barrier: 0.11 micron
Pre-metal dielectric: 0.35 micron (average)
Oxide on poly 2: 0.15 micron
Poly 2: 0.1 micron (approximate)
Interpoly oxide: 0.15 micron
Polycide 1 - silicide: 0.13 micron
- poly: 0.12 micron
Local oxide: 0.4 micron
N+ S/D: 0.2 micron
P + S/D: 0.4 micron
P-well: 4.5 microns (approximate)
- ii -
INDEX TO FIGURES
ASSEMBLY Figures 1 - 5
DIE LAYOUT AND IDENTIFICATION Figures 6 - 8
PHYSICAL DIE STRUCTURES Figures 9 - 32
FUSES Figures 22- 24
COLOR DRAWING OF DIE STRUCTURE Figure 25
SRAM MEMORY CELL STRUCTURES Figures 26 - 31
CIRCUIT LAYOUT AND I/O Figure 32
Figure 1. Package photographs and pinout of the Mosel Vitelic MS62256CLL-70PC.Mag. 2.7x.
Integrated Circuit Engineering CorporationMosel Vitelic MS62256CLL-70PC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
GND
CCV
W
A13
A8
A9
A11
G
A10
E
DQ8
DQ7
DQ6
DQ5
DQ4
MS62256C
side
top
Figure 2. X-ray views of the package. Mag. 3x.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
PIN 1
Mag. 400x
Mag. 550x
Figure 3. SEM views of typical wirebonding. 60°.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Au
BOND PAD
Au
LEADFRAME
Mag. 1600x
Mag. 140x
Figure 4. SEM views of dicing and edge seal. 60°.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
PADDLE
EDGE OFPASSIVATION
Mag. 10,000x
Mag. 1600x
Figure 5. SEM section views of the edge seal.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
EDGE OFPASSIVATION
DIE
EDGE OF DIE
EDGE OFPASSIVATION
METAL 1
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Figure 6. Whole die photograph of the Mosel Vitelic MS62256CLL-70PC. Mag. 32x.
Mag. 410x
Mag. 1540x
Mag. 1540x
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Figure 7. Optical views of die markings.
Figure 8. Optical views of die corners. Mag. 150x.
Integrated Circuit E
ngineering Corporation
Mosel V
itelic MS
62256CLL-70P
C
silicon etch
glass etch
Figure 9. SEM section views illustrating general structure. Mag. 13,000x.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
PASSIVATION 2
PASSIVATION 1
POLYCIDE 1
METAL 1
PASSIVATION 2
PASSIVATION 1
POLYCIDE 1GATE
METAL 1
N+ S/D
POLY 2 PAD
Mag. 18,000x
Mag. 4400x
Figure 10. Perspective SEM views illustrating overlay passivation coverage. 60°.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Mag. 26,000x
Mag. 13,000x
Figure 11. SEM section views of metal line profiles.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
METAL
PASSIVATION 2
POLY 2PAD POLYCIDE 1
GATE
N+ S/D
PASSIVATION 2
ALUMINUM
TiN BARRIER
Mag. 3200x
Mag. 3200x
Mag. 5000x
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Figure 12. Topological SEM views of metal patterning. 0°.
METAL
CONTACT
Mag. 5000x
Mag. 5000x
Mag. 14,000x
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Figure 13. Perspective SEM views illustrating metal step coverage. 60°.
Mag. 26,000x
Mag. 26,000x
Mag. 52,000x
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Figure 14. SEM section views illustrating typical metal contacts.
PASSIVATION 2
METAL
P+ S/D
95%THINNING
PASSIVATION 2
N+ S/D
POLYCIDE 1
ALUMINUM
POLY 2 PAD
N+ S/D
TiN BARRIER
Si
Si
Mag. 26,000x
Mag. 13,000x
Figure 15. SEM section views illustrating a hillock and a metal contact.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
PASSIVATION 2
METAL
REFLOW GLASS
HILLOCK
PASSIVATION 2
VOID
METAL
POLYCIDE 1
Mag. 26,000x, 0°
glass etch,Mag. 26,000x
glass etch,Mag. 52,000x
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Figure 16. SEM views illustrating silicon nodules.
CONTACT
TiN BARRIER
Si 0.8µ 1.5µ
PASSIVATION 2
POLYCIDE 1
POLY 2
ALUMINUM
0.5µ
Si
0.9µ
ALUMINUM
TiN BARRIER
POLY 2 PAD
Si
SECTIONINGARTIFACT
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Figure 17. Topological SEM views of polycide 1 patterning. Mag. 3200x, 0°.
P+ N+
POLYCIDE 1
POLY 2 PAD
POLYCIDE 1
P+
Mag. 4200x
Mag. 7400x
Mag. 20,000x
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Figure 18. Perspective SEMviews illustrating polycide 1 coverage. 60°.
POLYCIDE 1 GATE
LOCOS
N+ DIFFUSION
POLY 2 PAD
P-channel
N-channel
glass etch
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Figure 19. SEM section views of typical transistors. Mag. 52,000x.
REFLOW GLASS
POLYCIDE 1 GATE
GATE OXIDE
P+ S/D
REFLOW GLASS
POLYCIDE 1 GATE
N+ S/D
POLY 2 PAD
POLY 2 PAD
POLYCIDE 1
GATE OXIDE
SIDEWALLSPACER
Figure 20. SEM section views illustrating a birdsbeak and field oxide isolation.Mag. 52,000x.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
LOCOS
POLYCIDE 1
REFLOW GLASS
GATE OXIDE
LOCOS
REFLOW GLASS
N+
POLY 2
N+
Mag. 1200x
Mag. 6500x
Mag. 26,000x
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Figure 21. Section views illustrating well structure.
P-WELL
N-SUBSTRATE
P-WELL
N-SUBSTRATE
P+
N+
POLYCIDE 1
LOCOS
P-WELL
passivation removed, Mag. 6500x, 0°
Mag. 800x
Figure 22. Topological views illustrating fuse structures.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
POLY 2 FUSEMETAL
Mag. 3200x
Mag. 10,000x
Mag. 13,000x
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Figure 23. SEM section views illustrating a fuse.
PASSIVATION 2
N+ GUARDBAND
METAL
METAL
POLY 2POLYCIDE 1
Si
PASSIVATION 1PASSIVATION 2
LOCOS
POLY 2 FUSE
Mag. 26,000x
Mag. 18,000x
Figure 24. Additional SEM section views of a fuse.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
METAL
N+ GUARDBAND
POLY 2 POLYCIDE 1
METAL
POLY 2
LOCOS
POLYCIDE 1POLYCIDE 1
Figure 25. Color cross section drawing illustrating device structure.
Blue = Metal, Yellow = Oxide, Green = Poly,
Red = Diffusion, and Gray = Substrate
Integrated Circuit E
ngineering Corporation
Mosel V
itelic MS
62256CLL-70P
C
����������������������������������
������������������������
���������������������������
OXIDE ON N+ POLY 2 PAD
OXIDE ON POLY 2PRE-METAL DIELECTRIC
OXIDE ON P+
POLYCIDE 1
OXIDE ON POLYCIDE 1
ALUMINUM
PASSIVATION 1
PASSIVATION 2
TiN BARRIER
N+ S/D
P-WELL
P+ S/DGATE OXIDEN-WELL
N SUBSTRATE
unlayered
metal
Figure 26. Perspective SEM views of the SRAM cell. Mag. 6500x, 60°.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
GND
BIT
WORD
GND
VCC
Figure 27. Detailed SEM views of the SRAM cell at poly. Mag. 30,000x, 60°.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
POLY 2
POLYCIDE 1
POLY 2
POLYCIDE 1
unlayered
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
metal
Figure 28. Topological SEM views of the SRAM cell array. Mag. 3200x, 0°.
GND
BIT
BIT
WORD LINE
Figure 29. Detailed topological SEM views and schematic of the SRAM cell.Mag. 6500x, 0°.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
WORD
BITBIT 1
4
2
3
VCC VCC
unlayered
metal
GND
BIT
BIT
BIT
BIT 1
23
R1
R2
4
GND
VCC
Mag. 6500x
Mag. 20,000x
Mag. 52,000x
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Figure 30. SEM section views of the SRAM cell array.
METAL BIT LINE
POLYCIDE 1STORAGE GATE
N+ S/D
METAL BIT LINE
POLYCIDE 1SELECT GATE
N+ S/D
POLY 2 PAD
REFLOW GLASS
POLYCIDE 1SELECT GATE
GATE OXIDE
N+ S/D
Mag. 26,000x
Mag. 52,000x
Mag. 13,000x
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Figure 31. Additional SEM section views of the SRAM cell array.
METAL BIT LINE
POLY 2
POLYCIDE 1 STORAGE GATE
POLY 2POLYCIDE 1
LOCOS
N+ S/D
POLYCIDE 1GND CONNECT
N+ S/D OFSTORAGE GATES
POLY 2
Mag. 825x
Mag. 350x
Figure 32. Optical views of the input protection and typical device circuit layout.
Integrated Circuit Engineering CorporationMosel V itelic MS62256CLL-70PC
Title PageIndex to TextIntroductionMajor FindingsTechnology DescriptionAssemblyDie Process.1Die Process. 2
Analysis Results IPackage & Assembly
Analysis Results IIDie Process.1Die Process.2Die Process.3
ProcedureTablesOverall EvaluationPackage MarkingsWirebond StrengthDie Material AnalysisHorizontal DimensionsVerical Dimensions
Index to FiguresPackage photographsPInout diagramX-ray viewsTypical wirebondsDie cornerEdge seal.60°Edge seal.sectionWhole dieDie markingsDie cornersGeneral structurePassivation coverageMetalLine profilesPatterningIntegrityTypical contactsHillockMetal contactSIlicon nodules
Polycide 1 patterningPolycide 1 coverageTypical transistorsBirdsbeakField oxide isolationWell structureFuse structureFuse.sectionFuse.sectionColor section drawingSRAM cell arrayCell.60°Details.60°Cell.0°Cell.0°Cell schematicCell.sectionCell.section
Input protectionTypical circuitry