MPC5643L Microcontroller Reference Manual - nxp.com · MPC5643L Microcontroller Reference Manual, Rev. 10 Freescale Semiconductor 1 MPC5643L Microcontroller Reference Manual Devices

MPC5643L Microcontroller Reference Manual, Rev. 10

Freescale Semiconductor 1

MPC5643L MicrocontrollerReference Manual

Devices Supported:MPC5643L

MPC5643LRMRev. 10

26 June 2013


2 Freescale Semiconductor



Chapter 1Introduction

1.1 The MPC5643L microcontroller .....................................................................................................291.2 MPC5643L device summary ...........................................................................................................291.3 Device block diagram ......................................................................................................................311.4 Feature summary .............................................................................................................................321.5 Feature details .................................................................................................................................34

1.5.1 High-performance e200z4d core ....................................................................................341.5.2 Crossbar switch (XBAR) ................................................................................................351.5.3 Memory Protection Unit (MPU) ....................................................................................361.5.4 Enhanced Direct Memory Access (eDMA) ...................................................................361.5.5 On-chip flash memory with ECC ...................................................................................361.5.6 On-chip SRAM with ECC ..............................................................................................371.5.7 Platform flash memory controller ..................................................................................371.5.8 Platform Static RAM Controller (SRAMC) ...................................................................381.5.9 Memory subsystem access time .....................................................................................381.5.10 Error Correction Status Module (ECSM) .......................................................................391.5.11 Peripheral bridge (PBRIDGE) ........................................................................................391.5.12 Interrupt Controller (INTC) ............................................................................................391.5.13 System clocks and clock generation ...............................................................................401.5.14 Frequency-Modulated Phase-Locked Loop (FMPLL) ...................................................401.5.15 Main oscillator ................................................................................................................411.5.16 Internal Reference Clock (RC) oscillator .......................................................................411.5.17 Clock, reset, power, mode and test control modules (MC_CGM, MC_RGM, MC_PCU, and MC_ME) ...................................................................................................................................421.5.18 Periodic Interrupt Timer Module (PIT) ..........................................................................421.5.19 System Timer Module (STM) ........................................................................................421.5.20 Software Watchdog Timer (SWT) ..................................................................................421.5.21 Fault Collection and Control Unit (FCCU) ....................................................................431.5.22 System Integration Unit Lite (SIUL) ..............................................................................431.5.23 Non-Maskable Interrupt (NMI) ......................................................................................431.5.24 Boot Assist Module (BAM) ...........................................................................................431.5.25 System Status and Configuration Module (SSCM) ........................................................441.5.26 FlexCAN .........................................................................................................................441.5.27 FlexRay ...........................................................................................................................451.5.28 Serial communication interface module (LINFlexD) .....................................................451.5.29 Deserial Serial Peripheral Interface (DSPI) ...................................................................461.5.30 FlexPWM .......................................................................................................................471.5.31 eTimer module ................................................................................................................481.5.32 Sine Wave Generator (SWG) .........................................................................................481.5.33 Analog-to-Digital Converter module (ADC) .................................................................491.5.34 Cross Triggering Unit (CTU) .........................................................................................491.5.35 Cyclic Redundancy Checker (CRC) Unit .......................................................................501.5.36 Redundancy Control and Checker Unit (RCCU) ...........................................................511.5.37 Junction temperature sensor ...........................................................................................51



1.5.38 Nexus Port Controller (NPC) .........................................................................................511.5.39 IEEE 1149.1 JTAG Controller (JTAGC) ........................................................................521.5.40 Voltage regulator / Power Management Unit (PMU) .....................................................531.5.41 Built-In Self-Test (BIST) capability ...............................................................................53

Chapter 2Memory Map

Chapter 3Signal Description

3.1 Package pinouts ...............................................................................................................................613.2 Supply pins ......................................................................................................................................913.3 System pins .....................................................................................................................................933.4 Pin muxing ......................................................................................................................................943.5 Mapping of ports to PGPDO/I registers ........................................................................................117

Chapter 4Operating Modes

4.1 Overview .......................................................................................................................................1214.2 Lock Step Mode (LSM) ................................................................................................................1214.3 Decoupled Parallel Mode (DPM) ..................................................................................................1224.4 Selecting LSM or DPM .................................................................................................................122

4.4.1 Entering LSM ...............................................................................................................1234.4.2 Entering DPM ...............................................................................................................123

Chapter 5Device Boot Modes

5.1 Boot mode functionality ................................................................................................................1255.2 Hardware configuration .................................................................................................................125

5.2.1 Single Chip boot mode .................................................................................................1255.3 Boot-sector search .........................................................................................................................126

5.3.1 Potential boot sectors ....................................................................................................1265.3.2 Reset Configuration Half-Word ....................................................................................1275.3.3 Boot and alternate boot .................................................................................................128

5.4 Device behavior by boot mode ......................................................................................................1285.4.1 Single Chip Mode Unsecured ..................................................................................1285.4.2 Single Chip Mode Secured ......................................................................................1285.4.3 Serial Boot Loader Mode Public Password Enabled ...............................................1295.4.4 Serial Boot Loader Mode Flash Memory Password Enabled .................................1295.4.5 Standby Boot Mode ......................................................................................................1295.4.6 Static Mode ...................................................................................................................129

Chapter 6Device Security

6.1 Security ..........................................................................................................................................131



6.1.1 Securing the microcontroller ........................................................................................1316.1.2 Unsecuring the microcontroller ....................................................................................132

6.2 Serial access ..................................................................................................................................133

Chapter 7Functional Safety

7.1 Overview .......................................................................................................................................1357.2 Redundancy ...................................................................................................................................1357.3 Built-In Self-Test (BIST) ...............................................................................................................135

7.3.1 BIST during boot ..........................................................................................................1357.3.2 Software-triggered BIST during operation ...................................................................1367.3.3 Software-triggered self-tests after boot ........................................................................136

7.4 Memory error detection and correction .........................................................................................1367.5 Monitoring .....................................................................................................................................1367.6 Software measures .........................................................................................................................1377.7 Fault reaction .................................................................................................................................1377.8 External measures .........................................................................................................................137

Chapter 8Analog-to-Digital Converter (ADC)

8.1 Introduction ...................................................................................................................................1398.2 Features .........................................................................................................................................1398.3 Memory map and register descriptions .........................................................................................140

8.3.1 Memory map ................................................................................................................1408.3.2 Control logic registers ..................................................................................................1438.3.3 Interrupt registers ..........................................................................................................1478.3.4 Watchdog Threshold Interrupt Status Register (WTISR) .............................................1498.3.5 Watchdog Threshold Interrupt Mask Register (WTIMR) ............................................1508.3.6 DMA Enable Register (DMAE) ...................................................................................1518.3.7 DMA Channel Select Register 0 (DMAR0) .................................................................1518.3.8 Threshold Registers (THRHLRn) ................................................................................1528.3.9 Presampling registers ....................................................................................................1538.3.10 Conversion timing registers ..........................................................................................1548.3.11 Mask registers ...............................................................................................................1568.3.12 Power Down Exit Delay Register (PDEDR) ................................................................1578.3.13 Channel Data Registers (CDRn) ..................................................................................1588.3.14 Channel Watchdog Selection Registers (CWSELn) .....................................................1598.3.15 Channel Watchdog Enable Register 0 (CWENR0) ......................................................1608.3.16 Analog Watchdog Out of Range Register 0 (AWORR0) .............................................1608.3.17 Self test registers ...........................................................................................................161

8.4 Functional description ...................................................................................................................1758.4.1 Inter-module communication .......................................................................................1758.4.2 Analog channel conversion ..........................................................................................1768.4.3 Analog clock generator and conversion timings ..........................................................1798.4.4 ADC sampling and conversion timing .........................................................................179



8.4.5 Presampling ..................................................................................................................1808.4.6 Programmable analog watchdog ..................................................................................1818.4.7 DMA functionality .......................................................................................................1828.4.8 Interrupts .......................................................................................................................1828.4.9 Power-down mode ........................................................................................................1838.4.10 Auto-clock-off mode ....................................................................................................1848.4.11 Self testing ....................................................................................................................184

Chapter 9Boot Assist Module (BAM)

9.1 Overview .......................................................................................................................................1939.2 Features .........................................................................................................................................1939.3 Memory map .................................................................................................................................1949.4 Functional description ...................................................................................................................194

9.4.1 Entering boot modes .....................................................................................................1949.4.2 Boot through BAM .......................................................................................................1959.4.3 UART Boot autobaud disabled ................................................................................2009.4.4 CAN Boot autobaud disabled ..................................................................................2019.4.5 Boot with Autobaud feature [cut2/3 only] ....................................................................2039.4.6 Reading from Test Flash [cut2/3only] ..........................................................................2089.4.7 Inhibiting BAM operation ............................................................................................2099.4.8 Interrupt ........................................................................................................................209

Chapter 10Clock Architecture

10.1 Clock generation ...........................................................................................................................21110.2 Clock distribution ..........................................................................................................................21110.3 Detailed module descriptions ........................................................................................................214

Chapter 11Clock Generation Module (MC_CGM)

11.1 Introduction ...................................................................................................................................21511.1.1 Overview ......................................................................................................................21511.1.2 Features .........................................................................................................................216

11.2 External signal description ............................................................................................................21711.3 Memory map and register definition .............................................................................................217

11.3.1 Register descriptions ....................................................................................................22111.4 Functional description ...................................................................................................................230

11.4.1 System clock generation ...............................................................................................23011.4.2 Auxiliary clock generation ...........................................................................................23111.4.3 Functional description of dividers ................................................................................23511.4.4 Output clock multiplexing ............................................................................................23511.4.5 Output Clock Division Selection ..................................................................................235



Chapter 12Clock Monitor Unit (CMU)

12.1 Overview .......................................................................................................................................23712.2 Main features .................................................................................................................................23712.3 Memory map and register description ...........................................................................................237

12.3.1 Control status register (CMU_CSR) ............................................................................23812.3.2 Frequency display register (CMU_FDR) .....................................................................23912.3.3 High-frequency reference register A (CMU_HFREFR_A) .........................................24012.3.4 Low-frequency reference register A (CMU_LFREFR_A) ..........................................24012.3.5 Interrupt status register (CMU_ISR) ............................................................................24112.3.6 Measurement duration register (CMU_MDR) .............................................................242

12.4 Functional description ...................................................................................................................24212.4.1 XOSC clock monitor ....................................................................................................242

Chapter 13Cross-Triggering Unit (CTU)

13.1 Introduction ...................................................................................................................................24713.2 Block diagram ...............................................................................................................................24713.3 CTU overview ...............................................................................................................................24713.4 Functional description ...................................................................................................................248

13.4.1 Interaction with other peripherals .................................................................................24813.4.2 Trigger events features .................................................................................................24913.4.3 Trigger generator subunit (TGS) ..................................................................................24913.4.4 TGS in triggered mode .................................................................................................25013.4.5 TGS in sequential mode ...............................................................................................25113.4.6 TGS counter ..................................................................................................................252

13.5 Scheduler subunit (SU) .................................................................................................................25313.5.1 ADC commands list .....................................................................................................25513.5.2 ADC commands list format ..........................................................................................25513.5.3 ADC results ..................................................................................................................256

13.6 Reload mechanism ........................................................................................................................25613.7 Power safety mode ........................................................................................................................257

13.7.1 STOP mode ..................................................................................................................25713.8 Interrupts and DMA requests ........................................................................................................258

13.8.1 DMA support ................................................................................................................25813.8.2 CTU faults and errors ...................................................................................................25813.8.3 CTU interrupt/DMA requests .......................................................................................259

13.9 Conversion time evaluate ..............................................................................................................26113.10 Memory map .................................................................................................................................261

13.10.1 Trigger generator subunit input selection register (TGSISR) ......................................26313.10.2 Trigger generator subunit control register (TGSCR) ...................................................26513.10.3 TxCR - Trigger x compare register (x = 0,...,7) ...........................................................26613.10.4 TGS counter compare register (TGSCCR) ...................................................................26613.10.5 TGS counter reload register (TGSCRR) ......................................................................26613.10.6 Commands list control register 1 (CLCR1) ..................................................................267



13.10.7 Commands list control register 2 (CLCR2) ..................................................................26713.10.8 Trigger handler control registers (THCR1 and THCR2) ..............................................26813.10.9 Commands list register x (x = 1,...,24) (CLRx) ............................................................26913.10.10 Cross triggering unit error flag register (CTUEFR) .....................................................27213.10.11 Cross triggering unit interrupt flag register (CTUIFR) ................................................27313.10.12 Cross triggering unit interrupt/DMA register (CTUIR) ...............................................27313.10.13 Control ON time register (COTR) ................................................................................27413.10.14 Cross triggering unit control register (CTUCR) ...........................................................27513.10.15 Cross triggering unit digital filter (CTUDF) ................................................................27613.10.16 Cross triggering unit expected value A (CTU_EXP_A) ..............................................27613.10.17 Cross triggering unit expected value B (CTU_EXP_B) ...............................................27713.10.18 Cross triggering unit counter range (CTU_CNTRNG) ................................................27713.10.19 FIFO DMA control register (FDCR) ............................................................................27813.10.20 FIFO control register (FCR) .........................................................................................27813.10.21 FIFO threshold (FTH) ..................................................................................................28013.10.22 FIFO status register (FST) ............................................................................................28113.10.23 FIFO Right aligned data x (x = 0,...,3) (FRx) ...............................................................28213.10.24 FIFO signed Left aligned data x (x = 0,...,3) (FLx) ......................................................283

Chapter 14Crossbar Switch (XBAR)

14.1 Information specific to this device ................................................................................................28514.1.1 Register availability ......................................................................................................28514.1.2 MPR reset value ...........................................................................................................28514.1.3 max_halt signal unavailable .........................................................................................28514.1.4 Logical master IDs .......................................................................................................28514.1.5 Master port allocation ...................................................................................................28614.1.6 Slave port allocation .....................................................................................................286

14.2 Introduction ...................................................................................................................................28714.2.1 Overview ......................................................................................................................28714.2.2 Features .........................................................................................................................28714.2.3 Limitations ....................................................................................................................28714.2.4 General Operation ........................................................................................................288

14.3 XBAR registers .............................................................................................................................28914.3.1 Register summary .........................................................................................................28914.3.2 XBAR register descriptions ..........................................................................................29014.3.3 Coherency .....................................................................................................................296

14.4 Function .........................................................................................................................................29714.4.1 Arbitration ....................................................................................................................29714.4.2 Priority Assignment ......................................................................................................29914.4.3 Master Port Functionality .............................................................................................29914.4.4 Slave Port Functionality ...............................................................................................302

14.5 Initialization/Application Information ..........................................................................................30814.6 Interface .........................................................................................................................................308

14.6.1 Overview ......................................................................................................................308



14.6.2 Master Ports ..................................................................................................................30814.6.3 Slave Ports ....................................................................................................................309

Chapter 15Cyclic Redundancy Checker (CRC) Unit

15.1 Introduction ...................................................................................................................................31115.1.1 Glossary ........................................................................................................................311

15.2 Features .........................................................................................................................................31115.3 Block diagram ...............................................................................................................................31115.4 Signal description ..........................................................................................................................31215.5 Register description .......................................................................................................................312

15.5.1 CRC Configuration Register (CRC_CFG) ...................................................................31315.5.2 CRC Input Register (CRC_INP) ..................................................................................31415.5.3 CRC Current Status Register (CRC_CSTAT) ..............................................................31515.5.4 CRC Output Register (CRC_OUTP) ............................................................................316

15.6 Functional description ...................................................................................................................31615.7 Use cases and limitations ..............................................................................................................318

Chapter 16Deserial Serial Peripheral Interface (DSPI)

16.1 Introduction ...................................................................................................................................32116.1.1 Overview ......................................................................................................................32116.1.2 Features .........................................................................................................................32216.1.3 DSPI configurations .....................................................................................................32316.1.4 Modes of operation .......................................................................................................324

16.2 External signal description ............................................................................................................32516.2.1 PCS[0]/SS Peripheral Chip Select/Slave Select ......................................................32516.2.2 PCS[1] - PCS[3] Peripheral Chip Selects 13 .........................................................32516.2.3 PCS[4] Peripheral Chip Select 4 .............................................................................32516.2.4 PCS[5]/PCSS Peripheral Chip Select 5/Peripheral Chip Select Strobe ..................32616.2.5 PCS[6] - PCS[7] Peripheral Chip Selects 6 - 7 .......................................................32616.2.6 SIN Serial Input .......................................................................................................32616.2.7 SOUT Serial Output ................................................................................................32616.2.8 SCK Serial Clock ....................................................................................................326

16.3 Memory map and register definition .............................................................................................32616.3.1 Memory map ................................................................................................................32616.3.2 Register descriptions ....................................................................................................327

16.4 Functional description ...................................................................................................................34516.4.1 Start and Stop of DSPI Transfers ..................................................................................34616.4.2 Serial Peripheral Interface (SPI) Configuration ...........................................................34616.4.3 DSPI baud rate and clock delay generation ..................................................................34916.4.4 Transfer formats ...........................................................................................................35216.4.5 Continuous Serial Communications Clock ..................................................................36016.4.6 Interrupts/DMA Requests .............................................................................................36216.4.7 Power Saving Features .................................................................................................363



16.5 Initialization/Application Information ..........................................................................................36416.5.1 How to Manage DSPI Queues ......................................................................................36416.5.2 Switching Master and Slave Mode ...............................................................................36516.5.3 Baud Rate Settings .......................................................................................................36516.5.4 Delay Settings ...............................................................................................................36616.5.5 Calculation of FIFO Pointer Addresses ........................................................................367

Chapter 17e200z4d Core Complex Overview

17.1 Overview .......................................................................................................................................37117.2 Features .........................................................................................................................................372

17.2.1 Execution Unit Features ...............................................................................................37317.2.2 L1 Cache Features ........................................................................................................37417.2.3 Memory Management Unit Features ............................................................................37517.2.4 Exernal core complex interface features ......................................................................37517.2.5 Nexus 3+ Features ........................................................................................................375

17.3 Programming model ......................................................................................................................37617.3.1 Register set ...................................................................................................................37617.3.2 Instruction set ...............................................................................................................37917.3.3 Interrupts and Exception Handling ...............................................................................380

17.4 Microarchitecture summary ..........................................................................................................38217.5 Availability of detailed documentation .........................................................................................383

Chapter 18eDMA Channel Mux (DMA_MUX)

18.1 Introduction ...................................................................................................................................38518.1.1 Overview ......................................................................................................................38518.1.2 Features .........................................................................................................................38518.1.3 Modes of operation .......................................................................................................386

18.2 External signal description ............................................................................................................38618.2.1 Overview ......................................................................................................................386

18.3 Memory map and register definition .............................................................................................38618.3.1 Register descriptions ....................................................................................................387

18.4 DMA_MUX request source slot mapping ....................................................................................38818.5 DMA_MUX trigger inputs ............................................................................................................38918.6 Functional description ...................................................................................................................389

18.6.1 DMA Channels with periodic triggering capability .....................................................38918.6.2 DMA channels with no triggering capability ...............................................................39118.6.3 "Always Enabled" DMA sources .................................................................................392

18.7 Initialization/application Information ...........................................................................................39218.7.1 Reset .............................................................................................................................39218.7.2 Enabling and configuring sources ................................................................................393



Chapter 19Enhanced Direct Memory Access (eDMA)

19.1 Introduction ...................................................................................................................................39719.1.1 Overview ......................................................................................................................39819.1.2 Features .........................................................................................................................398

19.2 Memory map/register definition ....................................................................................................39919.2.1 Register descriptions ....................................................................................................400

19.3 Functional description ...................................................................................................................42819.3.1 eDMA microarchitecture ..............................................................................................42819.3.2 eDMA basic data flow ..................................................................................................42919.3.3 eDMA performance ......................................................................................................432

19.4 Initialization/application information ............................................................................................43519.4.1 eDMA initialization ......................................................................................................43519.4.2 eDMA programming errors ..........................................................................................43619.4.3 eDMA arbitration mode considerations .......................................................................43619.4.4 eDMA transfer ..............................................................................................................43719.4.5 TCD status ....................................................................................................................43919.4.6 Channel linking ............................................................................................................44119.4.7 Dynamic programming .................................................................................................441

Chapter 20Enhanced Motor Control Timer (eTimer)

20.1 Introduction ...................................................................................................................................44320.2 Features .........................................................................................................................................44520.3 External signal descriptions ..........................................................................................................446

20.3.1 TIO[5:0] - Timer Input/Outputs ...................................................................................44620.3.2 TAI[2:0] - Timer Auxiliary Inputs ................................................................................446

20.4 Memory map and register definition .............................................................................................44720.4.1 Module memory map ...................................................................................................44720.4.2 Register descriptions ....................................................................................................44820.4.3 Timer Channel Registers ..............................................................................................44820.4.4 Watchdog Timer Registers ...........................................................................................46320.4.5 Configuration Registers ................................................................................................464

20.5 Functional description ...................................................................................................................46620.5.1 General .........................................................................................................................46620.5.2 Counting Modes ...........................................................................................................46720.5.3 Other Features ..............................................................................................................474

20.6 Interrupts .......................................................................................................................................47520.7 DMA ..............................................................................................................................................475

Chapter 21Error Correction Status Module (ECSM)

21.1 Introduction ...................................................................................................................................47721.2 Overview .......................................................................................................................................47721.3 Features .........................................................................................................................................477



21.4 Memory map and register description ...........................................................................................47721.4.1 Memory map ................................................................................................................47721.4.2 Register description ......................................................................................................478

Chapter 22Fault Collection and Control Unit (FCCU)

22.1 Introduction ...................................................................................................................................50322.1.1 Glossary and acronyms .................................................................................................504

22.2 Main features .................................................................................................................................50422.3 Block diagram ...............................................................................................................................50522.4 Signal description ..........................................................................................................................50622.5 Register interface ...........................................................................................................................50622.6 Memory map and register description ...........................................................................................506

22.6.1 FCCU Control Register (FCCU_CTRL) ......................................................................50822.6.2 FCCU CTRL Key Register (FCCU_CTRLK) .............................................................51122.6.3 FCCU Configuration Register (FCCU_CFG) ..............................................................51122.6.4 FCCU CF Configuration Register (FCCU_CF_CFG0..3) ...........................................51322.6.5 FCCU NCF Configuration Register (FCCU_NCF_CFG0..3) .....................................51422.6.6 FCCU CFS Configuration Register (FCCU_CFS_CFG0..7) .......................................51522.6.7 FCCU NCFS Configuration Register (FCCU_NCFS_CFG0..7) .................................51722.6.8 FCCU CF Status Register (FCCU_CF_S0..3) .............................................................51722.6.9 FCCU CF Key Register (FCCU_CFK) ........................................................................51922.6.10 FCCU NCF Status Register (FCCU_NCF_S0..3) ........................................................52022.6.11 FCCU NCF Key Register (FCCU_NCFK) ..................................................................52122.6.12 FCCU NCF Enable Register (FCCU_NCF_E0..3) ......................................................52222.6.13 FCCU NCF Time-out Enable Register (FCCU_NCF_TOE0..3) .................................52322.6.14 FCCU NCF Time-out Register (FCCU_NCF_TO) ......................................................52422.6.15 FCCU CFG Timeout Register (FCCU_CFG_TO) .......................................................52522.6.16 FCCU IO Control Register (FCCU_EINOUT) ............................................................52622.6.17 FCCU Status Register (FCCU_STAT) .........................................................................52722.6.18 FCCU SC Freeze Status Register (FCCU_SCFS) ........................................................52822.6.19 FCCU CF Fake Register (FCCU_CFF) .......................................................................53022.6.20 FCCU NCF Fake Register (FCCU_NCFF) ..................................................................53022.6.21 FCCU IRQ Status Register (FCCU_IRQ_STAT) ........................................................53122.6.22 FCCU IRQ Enable Register (FCCU_IRQ_EN) ...........................................................53222.6.23 FCCU XTMR Register (FCCU_XTMR) .....................................................................53322.6.24 FCCU MCS Register (FCCU_MCS) ...........................................................................534

22.7 Functional description ...................................................................................................................53522.7.1 Definitions ....................................................................................................................53522.7.2 FSM description ...........................................................................................................53522.7.3 Self-checking capabilities .............................................................................................53722.7.4 Reset interface ..............................................................................................................53822.7.5 Fault priority scheme and nesting .................................................................................53822.7.6 Fault recovery ...............................................................................................................53922.7.7 WKUP/NMI interface ..................................................................................................544



22.7.8 STCU interface .............................................................................................................54522.7.9 NVM interface ..............................................................................................................54622.7.10 FCCU_F interface ........................................................................................................54722.7.11 Fault mapping ...............................................................................................................551

Chapter 23Flash Memory

23.1 Flash memory block (C90FL) .......................................................................................................55723.1.1 C90FL block overview .................................................................................................55723.1.2 C90FL block features ...................................................................................................55823.1.3 C90FL modes of operation ...........................................................................................55923.1.4 C90FL block diagram ...................................................................................................55923.1.5 C90FL memory map and register definition ................................................................55923.1.6 C90FL flash memory functional description (user mode) ...........................................58123.1.7 User option bits .............................................................................................................59023.1.8 Test flash memory ........................................................................................................591

23.2 Dual-ported platform flash memory controller (PFLASH2P) ......................................................59223.2.1 Introduction ..................................................................................................................59223.2.2 Registers .......................................................................................................................59623.2.3 Functional description ..................................................................................................602

Chapter 24FlexCAN Module

24.1 Introduction ...................................................................................................................................60724.1.1 Overview ......................................................................................................................60824.1.2 FlexCAN module features ............................................................................................60824.1.3 Modes of operation .......................................................................................................609

24.2 External signal description ............................................................................................................61024.2.1 CAN Rx ........................................................................................................................61024.2.2 CAN Tx ........................................................................................................................610

24.3 Memory map and register definition .............................................................................................61024.3.1 FlexCAN memory mapping .........................................................................................61124.3.2 Message Buffer Structure .............................................................................................61224.3.3 Rx FIFO Structure ........................................................................................................61524.3.4 Register descriptions ....................................................................................................617

24.4 Functional Description ..................................................................................................................63424.4.1 Overview ......................................................................................................................63424.4.2 Transmit Process ...........................................................................................................63524.4.3 Arbitration process .......................................................................................................63524.4.4 Receive Process ............................................................................................................63624.4.5 Matching Process ..........................................................................................................63824.4.6 Data Coherence ............................................................................................................63924.4.7 Rx FIFO ........................................................................................................................64124.4.8 CAN Protocol Related Features ...................................................................................64324.4.9 Modes of Operation Details ..........................................................................................647



24.4.10 Interrupts .......................................................................................................................64924.4.11 Bus Interface .................................................................................................................649

24.5 Initialization/Application Information ..........................................................................................65024.5.1 FlexCAN Initialization Sequence .................................................................................65024.5.2 FlexCAN addressing and RAM size configurations ....................................................651

Chapter 25Flexible Motor Control Pulse Width Modulator Module (FlexPWM)

25.1 Introduction ...................................................................................................................................65325.1.1 Overview ......................................................................................................................65325.1.2 Features .........................................................................................................................65325.1.3 Modes of operation .......................................................................................................65425.1.4 Block diagrams .............................................................................................................655

25.2 External signal descriptions ..........................................................................................................65625.2.1 PWMA[n] and PWMB[n] External PWM Pair .......................................................65625.2.2 PWMX[n] Auxiliary PWM signal ...........................................................................65625.2.3 FAULT[n] Fault inputs ............................................................................................65625.2.4 EXT_SYNC External Synchronization Signal ........................................................65725.2.5 EXT_FORCE External Output Force Signal ..........................................................65725.2.6 EXTA[n] and EXTB[n] Alternate PWM Control Signals .......................................65725.2.7 OUT_TRIG0[n] and OUT_TRIG1[n] Output Triggers ..........................................65725.2.8 EXT_CLK External Clock Signal ...........................................................................657

25.3 Functional Description ..................................................................................................................65725.3.1 Block Diagram ..............................................................................................................65725.3.2 PWM Capabilities ........................................................................................................65725.3.3 Functional details ..........................................................................................................66725.3.4 PWM generator loading ...............................................................................................684

25.4 Memory Map and Registers ..........................................................................................................68725.4.1 Module Memory Map ...................................................................................................68725.4.2 Register Descriptions ....................................................................................................68825.4.3 Submodule Registers ....................................................................................................68825.4.4 Configuration registers .................................................................................................70625.4.5 Fault Channel Registers .............................................................................................712

25.5 Interrupts .......................................................................................................................................71525.6 DMA ..............................................................................................................................................716

Chapter 26FlexRay Communication Controller

26.1 Introduction ...................................................................................................................................71926.1.1 Reference ......................................................................................................................71926.1.2 Glossary ........................................................................................................................71926.1.3 Color coding .................................................................................................................72026.1.4 Overview ......................................................................................................................72026.1.5 Features .........................................................................................................................72226.1.6 Modes of operation .......................................................................................................723



26.2 External Signal Description ..........................................................................................................72426.2.1 Detailed Signal Descriptions ........................................................................................725

26.3 Controller Host Interface Clocking ...............................................................................................72526.4 Protocol Engine Clocking .............................................................................................................72626.5 Memory Map and Register Description ........................................................................................726

26.5.1 Memory Map ................................................................................................................72626.5.2 Register Descriptions ....................................................................................................729

26.6 Functional Description ..................................................................................................................81026.6.1 Message Buffer Concept ..............................................................................................81126.6.2 Physical Message Buffer ..............................................................................................81126.6.3 Message Buffer Types ..................................................................................................81226.6.4 FlexRay Memory Area Layout .....................................................................................81826.6.5 Physical Message Buffer Description ..........................................................................82026.6.6 Individual Message Buffer Functional Description .....................................................83026.6.7 Individual Message Buffer Search ...............................................................................85526.6.8 Individual Message Buffer Reconfiguration ................................................................85826.6.9 Receive FIFOs ..............................................................................................................85926.6.10 Channel Device Modes .................................................................................................86526.6.11 External Clock Synchronization ...................................................................................86726.6.12 Sync Frame ID and Sync Frame Deviation Tables ......................................................86826.6.13 MTS Generation ...........................................................................................................87126.6.14 Key Slot Transmission ..................................................................................................87226.6.15 Sync Frame Filtering ....................................................................................................87326.6.16 Strobe Signal Support ...................................................................................................87426.6.17 Timer Support ...............................................................................................................87526.6.18 Slot Status Monitoring ..................................................................................................87626.6.19 System Bus Access .......................................................................................................87926.6.20 Interrupt Support ..........................................................................................................88026.6.21 Lower Bit Rate Support ................................................................................................88526.6.22 PE Data Memory (PE DRAM) .....................................................................................88626.6.23 CHI Lookup-Table Memory (CHI LRAM) ..................................................................88726.6.24 Memory Content Error Detection .................................................................................88826.6.25 Memory Error Injection ................................................................................................892

26.7 Application Information ................................................................................................................89426.7.1 Initialization Sequence .................................................................................................89426.7.2 CHI LRAM Error Injection out of POC:default config ...............................................89526.7.3 PE DRAM Error Injection out of POC:default config .................................................89526.7.4 Shut Down Sequence ....................................................................................................89526.7.5 Number of Usable Message Buffers .............................................................................89626.7.6 Protocol Control Command Execution ........................................................................89726.7.7 Message Buffer Search on Simple Message Buffer Configuration ..............................898

Chapter 27Frequency-Modulated Phase-Locked Loop (FMPLL)

27.1 Introduction ...................................................................................................................................901



27.2 Overview .......................................................................................................................................90127.3 Features .........................................................................................................................................90127.4 Memory map .................................................................................................................................90227.5 Register descriptions .....................................................................................................................902

27.5.1 Control Register (CR) ...................................................................................................90227.5.2 Modulation Register (MR) ...........................................................................................905

27.6 Functional description ...................................................................................................................90627.6.1 Normal mode ................................................................................................................90627.6.2 Progressive clock switching .........................................................................................90627.6.3 Normal Mode with frequency modulation ...................................................................90727.6.4 Powerdown mode .........................................................................................................908

27.7 Requirements .................................................................................................................................90827.8 Recommendations .........................................................................................................................909

Chapter 28Interrupt Controller (INTC)

28.1 Introduction ...................................................................................................................................91128.1.1 Module overview ..........................................................................................................91128.1.2 Block diagram ..............................................................................................................91128.1.3 Features .........................................................................................................................912

28.2 Modes of Operation .......................................................................................................................91328.2.1 Normal Mode ................................................................................................................91328.2.2 Debug Mode .................................................................................................................91428.2.3 Stop Mode ....................................................................................................................91428.2.4 Factory Test Mode ........................................................................................................914

28.3 External Signal Description ..........................................................................................................91428.4 Memory map/register definition ....................................................................................................914

28.4.1 Memory map ................................................................................................................91428.4.2 Register Information .....................................................................................................91528.4.3 INTC Block Configuration Register (INTC_BCR) .....................................................91628.4.4 INTC Current Priority Register for Processor 0 (INTC_CPR_PRC0) .........................91728.4.5 INTC Interrupt Acknowledge Register for Processor 0 (INTC_IACKR_PRC0) ........91828.4.6 INTC End of Interrupt Register for Processor 0 (INTC_EOIR_PRC0) .......................91928.4.7 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3 - INTC_SSCIR4_7) .....91928.4.8 INTC Priority Select Registers (INTC_PSR0_3 - INTC_PSR252_255) .....................921

28.5 Functional Description ..................................................................................................................92228.5.1 Interrupt Request Sources .............................................................................................92228.5.2 Priority Management ....................................................................................................92328.5.3 Handshaking with processor .........................................................................................924

28.6 Initialization/application information ............................................................................................92728.6.1 Initialization flow .........................................................................................................92728.6.2 Interrupt exception handler ...........................................................................................92728.6.3 Code Compressions Impact on Vector Table ..............................................................92928.6.4 ISR, RTOS, and Task Hierarchy ...................................................................................929



28.6.5 Order of Execution .......................................................................................................93028.6.6 Priority Ceiling Protocol ...............................................................................................93128.6.7 Selecting Priorities According to Request Rates and Deadlines ..................................93228.6.8 Software settable Interrupt Requests ............................................................................93328.6.9 Lowering Priority Within an ISR .................................................................................93428.6.10 Negating an Interrupt Request Outside of its ISR ........................................................93428.6.11 Examining LIFO contents ............................................................................................935

28.7 Interrupt sources ............................................................................................................................935

Chapter 29JTAG Controller (JTAGC)

29.1 Introduction ...................................................................................................................................94529.1.1 Overview ......................................................................................................................94529.1.2 Features .........................................................................................................................94529.1.3 Modes of operation .......................................................................................................946

29.2 External signal description ............................................................................................................94729.2.1 Overview ......................................................................................................................94729.2.2 Detailed Signal Descriptions ........................................................................................947

29.3 Register Definition ........................................................................................................................94829.3.1 Register descriptions ....................................................................................................948

29.4 Functional Description ..................................................................................................................95129.4.1 JTAGC Reset Configuration .........................................................................................95129.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port ................................................................95129.4.3 TAP Controller State Machine .....................................................................................95229.4.4 JTAGC Block Instructions ............................................................................................95429.4.5 Boundary Scan ..............................................................................................................956

29.5 Initialization/Application Information ..........................................................................................956

Chapter 30LIN Controller (LINFlexD)

30.1 Introduction ...................................................................................................................................95730.2 Main features .................................................................................................................................957

30.2.1 LIN mode features ........................................................................................................95830.2.2 UART mode features ....................................................................................................958

30.3 The LIN protocol ...........................................................................................................................95930.3.1 Dominant and recessive logic levels ............................................................................95930.3.2 LIN frames ....................................................................................................................95930.3.3 LIN header ....................................................................................................................96030.3.4 Response .......................................................................................................................961

30.4 LINFlexD and software intervention ............................................................................................96230.5 Summary of operating modes .......................................................................................................96230.6 Controller-level operating modes ..................................................................................................963

30.6.1 Initialization mode ........................................................................................................96330.6.2 Normal mode ................................................................................................................96430.6.3 Sleep (low-power) mode ..............................................................................................964



30.7 LIN modes .....................................................................................................................................96430.7.1 Master mode .................................................................................................................96430.7.2 Slave mode ...................................................................................................................96630.7.3 Slave mode with identifier filtering ..............................................................................96830.7.4 Slave mode with automatic resynchronization .............................................................971

30.8 Test modes .....................................................................................................................................97330.8.1 Loop Back mode ...........................................................................................................97330.8.2 Self Test mode ..............................................................................................................973

30.9 UART mode ..................................................................................................................................97430.9.1 Data frame structure .....................................................................................................97430.9.2 Buffer ............................................................................................................................97530.9.3 UART transmitter .........................................................................................................97630.9.4 UART receiver ..............................................................................................................977

30.10 Memory map and register description ...........................................................................................97930.10.1 LIN control register 1 (LINCR1) .................................................................................98030.10.2 LIN interrupt enable register (LINIER) .......................................................................98330.10.3 LIN status register (LINSR) .........................................................................................98530.10.4 LIN error status register (LINESR) ..............................................................................98830.10.5 UART mode control register (UARTCR) .....................................................................98930.10.6 UART mode status register (UARTSR) .......................................................................99230.10.7 LIN timeout control status register (LINTCSR) ..........................................................99430.10.8 LIN output compare register (LINOCR) ......................................................................99530.10.9 LIN timeout control register (LINTOCR) ....................................................................99630.10.10 LIN fractional baud rate register (LINFBRR) ..............................................................99730.10.11 LIN integer baud rate register (LINIBRR) ...................................................................99730.10.12 LIN checksum field register (LINCFR) .......................................................................99830.10.13 LIN control register 2 (LINCR2) .................................................................................99930.10.14 Buffer identifier register (BIDR) ................................................................................100030.10.15 Buffer data register least significant (BDRL) ............................................................100130.10.16 Buffer data register most significant (BDRM) ...........................................................100230.10.17 Identifier filter enable register (IFER) ........................................................................100330.10.18 Identifier filter match index (IFMI) ............................................................................100330.10.19 Identifier filter mode register (IFMR) ........................................................................100430.10.20 Identifier filter control registers (IFCR0IFCR15) ....................................................100530.10.21 Global control register (GCR) ....................................................................................100630.10.22 UART preset timeout register (UARTPTO) ...............................................................100730.10.23 UART current timeout register (UARTCTO) .............................................................100830.10.24 DMA Tx enable register (DMATXE) .........................................................................100930.10.25 DMA Rx enable register (DMARXE) ........................................................................1009

30.11 DMA interface .............................................................................................................................101030.11.1 Master node, TX mode ...............................................................................................101030.11.2 Master node, RX mode ...............................................................................................101330.11.3 Slave node, TX mode .................................................................................................101530.11.4 Slave node, RX mode .................................................................................................101830.11.5 UART node, TX mode ...............................................................................................1021



30.11.6 UART node, RX mode ...............................................................................................102330.11.7 Use cases and limitations ............................................................................................1026

30.12 Functional description .................................................................................................................102730.12.1 8-bit timeout counter ..................................................................................................102730.12.2 Interrupts .....................................................................................................................102830.12.3 Fractional baud rate generation ..................................................................................1029

30.13 Programming considerations .......................................................................................................103130.13.1 Master node ................................................................................................................103130.13.2 Slave node ..................................................................................................................103230.13.3 Extended frames .........................................................................................................103630.13.4 Timeout .......................................................................................................................103730.13.5 UART mode ................................................................................................................1037

Chapter 31Memory Protection Unit (MPU)

31.1 Introduction .................................................................................................................................103931.2 Block diagram .............................................................................................................................103931.3 Features .......................................................................................................................................104131.4 Modes of operation ......................................................................................................................104231.5 External signal description ..........................................................................................................104231.6 Memory map and register definition ...........................................................................................1042

31.6.1 MPU Control/Error Status Register (MPU_CESR) ...................................................104431.6.2 MPU Error Address Register, Slave Port n (MPU_EARn) ........................................104531.6.3 MPU Error Detail Register, Slave Port n (MPU_EDRn) ...........................................104531.6.4 MPU Region Descriptor n (MPU_RGDn) .................................................................104631.6.5 MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn) ...............1051

31.7 Functional description .................................................................................................................105231.7.1 Access evaluation macro ............................................................................................105331.7.2 Putting it all together and AHB error terminations ....................................................1055

31.8 Initialization information .............................................................................................................105631.9 Application information ..............................................................................................................1056

Chapter 32Mode Entry Module (MC_ME)

32.1 Introduction .................................................................................................................................105932.1.1 Overview ....................................................................................................................105932.1.2 Features .......................................................................................................................10

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MPC5643L Microcontroller Reference Manual - nxp.com · MPC5643L Microcontroller Reference Manual, Rev. 10 Freescale Semiconductor 1 MPC5643L Microcontroller Reference Manual Devices