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DM814x/AM387x BASE Evaluation Module Hardware User Guide

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DM814x/AM387x BASE BOARD-REVD

Copyright 2011 Mistral Solutions Pvt. Ltd.

Hardware User Guide


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DM814x/AM387x BASE BOARD-REVD Hardware User Guide

VER 0.1 5th December 2011

MISTRAL SOLUTIONS (P) LTD

#60, Adarsh Regent, 100 Feet Ring Road

Domlur Extension, Bangalore 71, India.

Tel: 91-80-30912600. Fax: 91-80-25356440

www.mistralsolutions.com


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IMPORTANT NOTICE

Mistral Solutions reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify that the data being relied on is current before placing orders.

Mistral Solutions warrants performance of its products and related software to current specifications in accordance with Mistral Solutions standard warranty. Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty.

Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Mistral Solutions does not warrant nor is liable for the product described herein to be used in other than a development environment.

Mistral Solutions assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does Mistral Solutions warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Mistral Solutions covering or relating to any combination, machine, or process in which such DM814X/AM387X development products or services might be or are used.

FCC WARNING

This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures necessary to correct this interference.



Appendix A 5 TMDXEVM8148 EVM Base Board Schematics

Table of Contents

1. Introduction................................................................................ 11 1.1 DM814X/AM387X Processor: ............................................................. 11 1.2 Functional block diagram .................................................................... 13 1.3 Key Features ....................................................................................... 14 1.4 Functional Overview ........................................................................... 15 1.5 Memory & I/O Mapping ....................................................................... 16 1.6 GPIO Mapping ..................................................................................... 16 1.7 I2C Address Mapping .......................................................................... 17

2. Interfaces & power section of DM814x/AM387x BASE EVM ........ 18 2.1 EVM interfaces: ................................................................................... 18

2.1.1 DDR interface: ........................................................................................... 18 2.1.2 NAND interface ......................................................................................... 19 2.1.3 SD/MMC Interface ..................................................................................... 19 2.1.4 Audio Interface ......................................................................................... 19 2.1.5 EMAC Interface ......................................................................................... 20 2.1.6 EEPROM interfaces .................................................................................... 20 2.1.7 Video outputs ............................................................................................ 21 2.1.8 High Speed USB Interface ......................................................................... 21 2.1.9 SPI Flash interface .................................................................................... 22 2.1.10 UART Interface ...................................................................................... 22 2.1.11 I2C Interface ......................................................................................... 22 2.1.12 Debug Interface ..................................................................................... 23 2.1.13 PCI express Interface ............................................................................ 23 2.1.14 MSP430 Interface .................................................................................. 24

2.2 Clock ................................................................................................... 26 2.3 Power.................................................................................................. 26

2.3.1 DM814x/AM387x Power .......................................................................... 27 3. Physical Description .................................................................... 28

3.1 DM814x/AM387x EVM layout .............................................................. 28 3.1.1 DM814x/AM387x BASE EVM Top View ...................................................... 29 3.1.2 DM814x/AM387x BASE EVM Bottom View ................................................. 30

3.2 Connectors/Switches/Headers ........................................................... 31 3.2.1 SD / MMC .................................................................................................. 31 3.2.2 JTAG Header ............................................................................................. 32 3.2.3 S-VIDEO out .............................................................................................. 33 3.2.4 Composite video Connector ....................................................................... 34 3.2.5 USB-OTG Connector: ................................................................................. 34 3.2.6 HDMI OUT Connector: ............................................................................... 35 3.2.7 Ethernet Connector: .................................................................................. 37



3.2.8 PCI express Connector: ............................................................................. 38 3.2.9 UART Connector: ....................................................................................... 40 3.2.10 EEPROM Header: .................................................................................... 41 3.2.11 MSP-JTAG Header: ................................................................................. 42 3.2.12 SATA POWER & DATA: ............................................................................ 43 3.2.13 Audio connectors ................................................................................... 44 3.2.14 Power Switches: .................................................................................... 46 3.2.15 Boot mode Switches: ............................................................................. 48 3.2.16 Reset Button SW9: ................................................................................. 49 3.2.17 Power ON Reset SW10: .......................................................................... 50 3.2.18 GPIO Switch & LEDs ............................................................................... 52 3.2.19 Fuses: .................................................................................................... 52

3.3 Test Points .......................................................................................... 53 3.4 Expansion Connector ........................................................................... 55



Table of Figures

Figure 1: DM814x/AM387x Processor .............................................................. 11 Figure 2: DM814x/AM387x BASE EVM Functional Block Diagram .......................... 13 Figure 3: DM814x/AM387x BASE EVM Top View ...... Error! Bookmark not defined. Figure 4: DM814x/AM387x BASE EVM Bottom View ........................................... 30 Figure 5: SD/MMC Connector .......................................................................... 31 Figure 6: JTAG Header ................................................................................... 32 Figure 7: S Video out Connector ...................................................................... 33 Figure 8: Composite Video out Connector ......................................................... 34 Figure 9: USB-OTG Connector ........................................................................ 35 Figure 10: HDMI Connector ........................................................................... 36 Figure 11: Ethernet Connector ....................................................................... 37 Figure 12: PCIe Connector ............................................................................ 38 Figure 13: UART Connector ........................................................................... 40 Figure 14: EEPROM Header ........................................................................... 41 Figure 15: MSP-JTAG Header ......................................................................... 42 Figure 16: SATA POWER & DATA connector ..................................................... 43 Figure 17: Audio codec connectors ................................................................. 45 Figure 18: Slide Switches .............................................................................. 47 Figure 19: Boot mode Switches ...................................................................... 48 Figure 20: Reset Switches ............................................................................. 50 Figure 21: Major Test Points of EVM ............................................................... 54



List of Tables

Table 1: Document History ............................................................................ 10 Table 2: Board History .................................................................................. 10 Table 3: Memory & I/O Map .......................................................................... 16 Table 4: GPIO mapping ................................................................................ 16 Table 5: I2C Address Mapping ....................................................................... 17 Table 6: I2C Address of power monitors .......................................................... 25 Table 7: SD/MMC Connector .......................................................................... 32 Table 8: JTAG Header ................................................................................... 33 Table 9: S-Video Connector ........................................................................... 33 Table 10: Composite Video Connector .............................................................. 34 Table 11: USB-OTG Connector ........................................................................ 35 Table 12: HDMI OUT Connector ....................................................................... 37 Table 13: Ethernet Connector .......................................................................... 38 Table 14: PCIe Connector ............................................................................... 39 Table 15: UART Connector .............................................................................. 40 Table 16: EEPROM Header .............................................................................. 41 Table 17: MSP-JTAG Header ............................................................................ 42 Table 18: SATA POWER connector .................................................................... 43 Table 19: SATA DATA connector ...................................................................... 44 Table 20: LINE OUT & HP OUT connector .......................................................... 44 Table 21: LINE IN connector ........................................................................... 45 Table 22: MIC IN connector ............................................................................ 45 Table 23: Boot mode selection ........................................................................ 48 Table 24: Warm Reset Push Button .................................................................. 49 Table 25: Cold Reset Push Button .................................................................... 50 Table 26: Test points ..................................................................................... 53 Table 27: 64 pin Power Expansion Connector J16 ............................................... 55 Table 28: 64 pin video Expansion Connector J17 ................................................ 56 Table 29: 128 Pin Video Expansion Connector J18 .............................................. 58 Table 30: 128 Pin GPMC Expansion Connector J19 .............................................. 60 Table 31: 128 Pin MCASP Expansion Connector J20 ............................................ 61 Table 32: 64 Pin GPMC Expansion Connector J21 ............................................... 62



About This Manual

Developed with Mistral Solutions, the DM814x/AM387x BASE Evaluation Module (EVM) enables developers to start immediate evaluation of DM814x/AM387x processors and begin building on different video applications

This document describes the board level operations of the DM814x/AM387x BASE Evaluation Module (EVM). The EVM is based on the Texas Instruments DM814x/AM387x Applications Processor

Notational Conventions

DM814x/AM387x BASE Evaluation Module will sometimes be referred to as the DM814x EVM or BASE EVM.

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Information about Cautions

This Document may contain cautions.

This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software, or hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully.

Related Documents, Application Notes and User Guides

Information regarding the DM814x/AM387x Processor can be found at the following Texas Instruments website: http://www.ti.com



VER. No History

0.1 Draft Version

Table 1: Document History

PCB

Revision History

REV A Created

REV B REVA-Ethernet PHY section changed

REV C REVB-Current sense resistor value changed, VBACKUP connected to GND

REV D Modified as per change list MS_TI_CEN_DM814X_BB_REVD_CHNG_LIST.xls

Table 2: Board History

The Boards contains Electro-static Discharge (ESD) sensitive devices. Take proper precautions to ground yourself before handling the board.



Chapter 1

Introduction to the DM814X/AM387X BASE EVM

1. Introduction

Chapter one provides a brief description of the DM814x/AM387x Processor along with the key features and a high-level block diagram of the DM814x/AM387x BASE EVM. Also it describes about memory & I/O mapping, GPIO mapping, and I2c mapping of devices on DM814x/AM387x BASE EVM.

1.1 DM814X/AM387X Processor:

DM814X/AM387X mainly consists of ARM Cortex A8 RISC CPU with Neon extension, TI C674x VLIW floating-point DSP core, and high-definition video/imaging coprocessors.

Figure 1: DM814x/AM387x Processor



It is a highly-integrated, programmable platform that leverages TIs DaVinci

technology to meet the processing needs of the following applications: Video Conferencing, Video Broadcasting, Automotive Navigation/DTV/Media/Vision, Video Surveillance (IP NetCam, DVR), Industrial Automation HMI, Wireless Networked Projectors, Portable Data Collection, Point-of-Sale, Digital Signage, Gaming, Web Tablet, and Smart Home Controller applications. Programmability is provided by an ARM Cortex A8 RISC CPU with Neon extension, TI C674x VLIW floating-point DSP core, and high-definition video/imaging coprocessors. The ARM Cortex A8 32-bit RISC microprocessor with Neon floating-point extension includes: 32 Kbytes (KB) of Instruction cache; 32KB of Data cache; 512KB of L2 Cache; 176KB of on-chip boot ROM (128KB of Secure ROM and 48 KB of Public ROM); and 64KB of RAM.

The C674x DSP core is the new high-performance floating-point DSP generation in the TMS320C6000 DSP platform. The C674x Floating Point DSP processor uses 32KB of L1 program memory, 32KB of L1 data memory AND 256KB of L2 cache memory. Up to 32KB of L1P can be configured as program cache. The remaining is non-cacheable no-wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining is non-cacheable no-wait-state data memory

DM814x/AM387x also includes a high-definition video/imaging coprocessor 2 (HDVICP2), a Face Detect (FD) engine, and an SGX530 3D graphics engine to off-load many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms.DM814x/AM387x provides a seamless interface to data streams and other devices required to create a complete networked A/V application.

DM814x/AM387x processor is a 684-Pin Pb-Free BGA Package which has 0.8-

mm Ball Pitch with via Channel Technology to Reduce PCB Cost. The ARM cortex A8 core operates at the speed of 1 GHZ & DSP core operate at the speed of 750 MHZ.



1.2 Functional block diagram

The functional block diagram of the DM814x/AM387x BASE EVM is given below:

Figure 2: DM814x/AM387x BASE EVM Functional Block Diagram



1.3 Key Features

The key features are:

DM814x Processor is a High-Performance Digital Media System on chip Memory

It has Dual 32-bit DDR3 SDRAM interface (DDR0 & DDR1). 1GB size of memory from Micron is used on the DDR3 interface of DM814x/AM387x EVM.

A 2gbit NAND Flash memory from Micron with socket for placing the NAND is used on the DM814x/AM387x Base EVM

Power for processor is derived from integrated power management IC TPS659113.

Analog video out interface-Composite and S-Video output from TV OUT interface of processor is available on the board

Digital Video out interface-on chip HDMI Transmitter on TMS320814x supports 1080p resolution.

USB interface-It has dual High/full Speed USB OTG 2.0 port with integrated PHYs

Ethernet interface-It has two RGMII ports interfaced to the MAC having the speed of 10/100/1000Mbps.

Stereo Audio Interface Audio Line IN, Mic IN, Speaker OUT and Headset OUT

Serial Interfaces- SD/MMC connector in 4bit SD mode Supporting up to 48MHZ

A 32 Mbit SPI Flash memory available on DM814x/AM387x EVM for SPI booting.

Serial ATA (SATA) 3.0 Gbps Controller With integrated PHY on DM814x/AM387x which can directly connect to SATA HDD.

Ultra low power microcontroller MSP430 to monitor the current flow DM814x/AM387x devices with UART interfaces.

Dip switch to select different Boot mode configurations Standard 20-pin JTAG debug interface Video, GPMC, and MCASP expansion board to board connectors are

available to connect different application boards of DM814x/AM387x like video vision, video camera, video conference, and catalog application.

PCI Express 2.0 Port With Integrated PHY and 1 Lane supports up to 5.0 GT/s

The DM814x/AM387x EVM is RoHS compliant



1.4 Functional Overview The DM814x/AM387x EVM is based on TIs DM814x/AM387x application

processor. The micron memory MT41J128M8JP-125 is connected to the DM814x/AM387x processor via SSTL_15 interface. The DDR memory on the board consists eight chips (MT41J128M8JP-125) of micron memory each having the capacity of 1Gbit. MT41J128M8JP-125 has an excellent on chip ODT for better signal quality. NAND flash memory is connected to the processor through GPMC interface. The chip enable pin of the NAND device shall be connected to GPMC_nCS0 of the DM814x/AM387x processor.

Analog Video outputs of EVM support both Composite TV output and S-Video output on the main board. The Composite or S-Video Outputs are available on respective connector by default.

DM814x/AM387x BASE EVM supports multiple video input options from any of the application board through VIN0, VIN1, and camera port. Any one of the below interface shall be active at a given point of time when catalog application board is connected through expansion board to board connectors.

1. S-Video Input, digitized through Video decoder (TVP5147) 2. Composite Video Input digitized through Video decoder

(TVP5147) 3. RGB Video Input digitized through Video decoder (TVP7002) 4. VGA input digitized through Video decoder (TVP7002) 5. Camera Input-from parallel camera interface

The EVM has a SD/MMC slot connected using SD/MMC1 4 bit interface on the main board. And the SD/MMC2 interface is routed to the expansion connector for WLAN module on application board. The EVM has two RGMII Ethernet port (RGMII0, RGMII1) using a two external PHY AR8031 which is interfaced to the processor via the RGMII interface. It has PCIe2.0 x4connector with integrated PHY on DM814x processor which can be configured as Root complex or Endpoint.

The EVM supports two UART (DM814x UART, MSP430 UART) interfaces via two serial ports (DB9 connector) on the main board. Two USB mini-AB connectors on the board to support High Speed USB OTG2.0 interface. One Stereo Line IN, MIC IN, Speaker OUT and Stereo Headset OUT audio interface is supported through the audio codec TLV320AIC3106IRGZT on the EVM. The audio codec on the EVM is controlled by I2C0 & MCASP2 interface.

The EVM has 5 DIP switches for various purposes like different boot modes selection, GPIO toggling, video out enable, GPMC nWP, and Reset the GPIO. The EVM also includes 3 reset push button switches and 6 slide switches for power flow. It has standard 20-pin JTAG Header (10x2 1.27 mm pitch) for debug interface. This JTAG port can be accessed through TIs Code Composer Studio development version 4.0.The EVM is powered by a 12V, 5A external power supply. The TPS659113 power management device provides the required CPU core voltages and IO voltages for DM814x/AM387x Processor.



1.5 Memory & I/O Mapping

The Memory and I/O space mapping for the DM814x/AM387x EVM is given below.

Device

Start address

End address Size Description

GPMC 0x0000_0000 0x1FFF_FFFF 512MB GPMC On chip ROM 0x4000_0000 0x4001_FFFF 128kB Secure ROM 0x4002_0000 0x4002_BFFF 48K ROM On chip RAM 0x402F_0000 0x402F_FFFF 64KB Secure RAM 0x4030_0000 0x4031_FFFF 128KB OCMC SRAM PCIe 0x2000_0000 0x2FFF_FFFF 256MB PCIe DDR 0x8000_0000 0xFFFF_FFFF 2GB DDR I2C0 0x4802_8000 0x4802_8FFF 4kB I2C0 peripheral registers I2C1 0x4802_A000 0x4802_AFFF 4kB I2C1 peripheral registers I2C2 0x4819_C000 0x4819_CFFF 4kB I2C2 peripheral registers SPI0 0x4803_0000 0x4803_0FFF 4kB SPI0 peripheral registers SPI1 0x481A_0000 0x481A_0FFF 4kB SPI1 Peripheral registers MMC 0x481D_8000 0x481E_7FFF 64kB MMC/SD/SDIO1 Peripheral

registers

Table 3: Memory & I/O Map

1.6 GPIO Mapping The below table shows some of the GPIOs used in DM814x/AM387x BASE EVM S NO GPIO name Source Purpose

1 AIC_EXPANSION PCF8575 DEVICE MCASP 2 ENET_INTn GP1[10] ETHERNET 3 PCF8575_INT GP1[8] INTERRUPT 4 EN_1V8_LDO TPS659113GPIO 8 ENABLING 1V8 SUPPLY 5 EN_BCK2_LS TPS659113GPIO ENABLING LOAD SWITCH 6 EN_TPS62350 TPS659113-- GPIO 6 ENABLING CVDD_HDVICP 7 EN_BCK3_TPS65232 TPS659113-- GPIO 2 ENABLING PCI_3V3 8 EN_TPS51116 TPS659113-- GPIO 0 ENABLING DDR SUPPLY 9 MSP430_INT PCF8575 DEVICE INTERRUPT FOR MSP430 10 TPS_INT1 TPS659113-- INT 1 INTERRUPT FOR DM814X 11 TPS_SLEEP PCF8575 DEVICE SLEEP FOR TPS659113 12 PCI_SW_RESETn PCF8575 DEVICE PCI RESET 13 IR_REMOTE_OFF PCF8575 DEVICE IR SENSOR CONTROLLING 14 UART0_OFF PCF8575 DEVICE UART-0 CONTROLLING 15 SW_VOUT_EN TDA04H0SK1 DEVICE VIDEO SW ENABLE 16 GPMC_nWP TDA04H0SK1 DEVICE GPMC WRITE PROTECT 17 RESET_GPIO TDA04H0SK1 DEVICE ENABLING PCI POR BUFFER

Table 4: GPIO mapping



1.7 I2C Address Mapping

The address mapping for I2C interface on DM814x/AM387x BASE EVM is given below:

I2C Used Device Address I2C0 Audio codec 0x18 I2C0 TPS62353 0x48 I2C0 EEPROM 0x50 I2C0 TPS659113 0x2D I2C0 IO Expander-PCF8575 0x20 I2C0 MSP430 0x25 I2C1 HDMI interface I2C0 & I2C2 Application Board devices

Table 5: I2C Address Mapping



Chapter 2

Interfaces & power section of DM814x/AM387x BASE EVM

2. Interfaces & power section of DM814x/AM387x BASE EVM

This chapter describes the major interfaces & power section of the DM814x/AM387x BASE EVM.

2.1 EVM interfaces: The main interfaces of DM814x/AM387x base EVM are

DDR NAND flash SD/MMC USB Ethernet Audio PCI express SPI Flash SATA Composite video & S-video HDMI UART JTAG EEPROM

2.1.1 DDR interface: The DM814x/AM387x supports Dual 32-bit mDDR/DDR2/DDR3 SDRAM interface

(DDR0 and DDR1 interface).The DDR3 device on the DM814x/AM387x Base EVM is MT41J128M8JP-125 with configuration of 128 Meg x 8. Four 8bit 128Meg DDR3 devices are interfaced to each 32bit memory mDDR/DDR2/DDR3 SDRAM interface (DDR0, DDR1). Hence a total of 512MB DDR3 memory is interfaced to each (DDR0, DDR1) interface of DM814x/AM387x.

The supply voltage (1.5V) and termination voltage (0.75V) for the DDR3 chips is generated by the synchronous buck converter TPS51116. The reference voltage (0.75V) is generated by a voltage divider. For the DQ and DQS lines, series termination is 0E. For DM lines 22E series termination is provided. And all the address and control lines have a 51E resistor, 0.1uF capacitor parallel termination.

DM0 and DQS0 are the reference for Write and read to first DDR chip DDRx_0 (in each DDR interface). DM1 and DQS1 are the reference for the second DDR chip



DDRx_1, DM2 and DQS2 are the reference for the third DDR chip DDRx_2, DM3 and DQS3 are the reference for the fourth DDR chip DDRx_3.The address lines A[0:13], bank address lines BA[0:2], and the control signals are connected to each of the four DDR3 chips.

2.1.2 NAND interface

MT29F2G16AADWP:D is the NAND Flash on DM814x/AM387x EVM. The memory configuration is 2Gbit. NAND flash is interfaced to GPMC port of the DM814x/AM387x. It has 16 multiplexed I/O lines for data and address. The address lines are selected by enabling the GPMC_ADVN_ALE (address latch enable) to HIGH. The chip select of NAND flash is connected to GPMC_nCS0 of the GPMC controller. To select between on board NAND booting or NOR booting on application boards (video vision or video security) a DIP switch SW2 is provided on the DM814x/AM387x base EVM. For on board NAND booting SW2.1 should be ON. NAND IC is placed inside the 48 pin Socket on the EVM.

2.1.3 SD/MMC Interface SD/MMC CARD connector MHC-W21-601-LF is interfaced to SD1/MMC1 port of the DM814x/AM387x. Power supply to the MMC card (VMMC) is controlled by the load switch MIC94060YC6.VMMC is derived from EVM3V3 supply. The enable pin of the Load switch U41 is connected to the GP1 [2]. Load switch is enabled by default (resistor R209 connecting GP1 [2] pin to EN pin of load switch is not mounted in default configuration). Card detect pin of the SD/MMC connector is connected directly to the SD1_SDCD (Ball AE5) of DM814x/AM387x. Write protect pin of the SD/MMC connector is not connected directly to AG4 pin of DM814x/AM387x which have resistor option if write protect feature is required. Write protect is Muxed {UART0_DSRn/UART3_TXD/SPI [0] _SCS [2]n/I2C[2]_SDA/SD1_SDWP/GP1[3] } .By default SD/MMC card is not write protected (resistor R208 connects the pin to AG4 described as above).This pin is used for I2C2 data on the application boards.

2.1.4 Audio Interface The Audio codec used in DM814x/AM387x Base EVM is a TLV320AIC3106.It is a

low-power stereo audio codec with stereo headphone amplifier, as well as codec with stereo headphone amplifier, as well as single-ended or fully differential configurations. The stereo audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital filtering in the DAC path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32-kHz, 44.1-kHz, and 48-kHz rates. The stereo audio ADC supports sampling rates from 8 kHz to 96 kHz and is preceded by programmable gain amplifiers or AGC that can provide up to 59.5-dB analog gain for low-level microphone inputs. A highly programmable PLL is included for flexible clock generation and support for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz.TLV320AIC3106 is controlled by



I2C0 & MCASP2 interface. It operates at an analog supply of 3.3 V, a digital core supply of 1.8 V, and a digital I/O supply of 3.3 V.A 24.576MHZ clock is used as a master clock for the audio codec in the EVM.

2.1.5 EMAC Interface

The EMAC SW controls the flow of packet data between the device and two external Ethernet PHYs, with hardware flow control and quality-of-service (QOS) support. The EMAC SW contains a 3-port gigabit switch, where one port is internally connected and the other two ports are brought out externally. Each of the external EMAC ports supports 10Base-T (10 Mbits/second [Mbps]), and 100BaseTX (100 Mbps), in either half- or full-duplex mode, or 1000BaseT (1000 Mbps) in full-duplex mode. The EVM has two RGMII Ethernet port (RGMII0, RGMII1) using a two external PHY AR8031 which is interfaced to the processor via the RGMII interface. A single MDIO interface (MDIO clock & MDIO data) is connected out to control the PHY configuration and status monitoring of RGMII0 & RGMII1. Multiple external PHYs can be controlled by the MDIO interface. The EMAC SW I/Os operate at 3.3 V and are not compatible with 2.5-V I/O signaling. Therefore, only Ethernet PHYs with 3.3-V I/O interface should be used. The AR8031 requires only a single, 3.3V power supply. On-chip regulators provide all the other required voltages.

The AR8031 embeds CDT (Cable Diagnostics Test) technology on-chip which allows measuring cable length, detecting the cable status, and identifying remote and local PHY malfunctions, bad or marginal patch cord segments or connectors. Some of the possible problems that can be detected include opens, shorts, cable impedance mismatch, bad connectors, termination mismatch, and a bad transformer.AR8031 also Supports Wake-on-LAN (WoL) to detect magic packet and notify the sleeping system to wake up. AR8031 integrates the termination R/C circuitry & the serial resistors for the line side and no external parallel termination required between PHY & Magnetics on the board.

The EVM uses two external 25MHZ crystal (Y3 & Y8) to generate local clock for RGMII0 & RGMII1.The PHY uses three clock signals namely RX_CLK, MDIO_CLK, & GTX_CLK & four transmit\receive data lines. RX_CLK is flow from PHY to MAC. GTX_CLK is coming from MAC to PHY.

2.1.6 EEPROM interfaces The EVM uses 256-Kb I2C CMOS Serial EEPROM CAT24C256WI-GT3 to store the

board ID information .EEPROM is interfaced to DM814X processor using I2C0. The CAT24C256 is a 256-Kb Serial CMOS EEPROM, internally organized as 512 pages of 64 bytes each. It features a 64-byte page write buffer and supports Both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol.

The write protect pin WP of EEPROM has been pulled low by default, if the EEPROM memory has to be write protected pins 7 and 8 of J13 has to be short using a jumper.



2.1.7 Video outputs

The EVM has two analog video outputs namely S-Video & composite video and one digital HDMI video out interface. These interfaces are controlled by High Definition Video processing Subsystem of DM814x/AM387x Processor. S Video & composite video connectors are directly connected to the Processor. HDMI connector is connected to processor through ESD protection device TPD12S521DBTR.HDMI interface is controlled by I2C0 interface of DM814x. It has 3 differential pair of data line & one differential pair of clock line. The HDMI interface consists of a digital HDMI transmitter (1.3a-compliant transmitter) core with TMDS encoder, a core wrapper with interface logic and control registers, and a transmit PHY

HDMI interface has the following features

Hot-plug detection Supports up to 165-MHz pixel clock

->1920 x 1080p @75 Hz with 8-bit/component color depth ->1600 x 1200 @60 Hz with 8-bit/component color depth

Support for deep-color mode:

->10-bit/component color depth up to 1080p @60 Hz (Max pixel clock = 148.5 MHz) ->12-bit/component color depth up to 720p/1080i @60 Hz (Max pixel clock = 123.75 MHz)

TMDS clock to the HDMI-PHY is up to 185.625 MHz NOTE: The signal GPMC_A22 is internally muxed with CE_REMOTE_IN on pin

AB27 & signal GPMC_A23 is muxed with HDMI_HP_IN on AA26 of DM814x processor. By default HDMI lines are used in the board. To use GPMC_A22 & GPMC_A23 on application board we need to change the signal EXP_GPMC_ADD_SELn as active LOW through I2C0 IO Expander.

2.1.8 High Speed USB Interface

The USB controller provides a low-cost connectivity solution for numerous consumer portable devices by providing a mechanism for data transfer between USB devices with a line/bus speed up to 480 Mbps. The DM814x/AM387x device USB subsystem has two independent USB 2.0 Modules (USB0 & USB1) built around two OTG controllers. The OTG supplement feature, the support for a dynamic role change, is also supported. Each port has the support for a dual-role feature allowing for additional versatility enabling operation capability as a host or peripheral. Both ports have identical capabilities and operate independent of each other.



Each USB controller is built around the Mentor USB OTG controller and TI GS70 PHY. Each USB controller has user configurable 32K Bytes of Endpoint FIFO and has the support for 15 Transmit endpoints and 15 Receive endpoints in addition to Endpoint 0. The USB subsystem makes use of the CPPI 4.1 DMA for accelerating data movement via a dedicated DMA hardware. The two USB modules share the CPPI DMA controller and accompanying Queue Manager, Interrupt Pacer, Power Management module, and PHY/UTMI clock. The PHY does not have a built-in charge pump and an external power source is required to source the 5V VBUS power. The PHY has built in charge detection for device mode and control capability for host application for implementing external charge detection capability.

For an OTG controller, the usual method followed by the controller to assume

the role of a host or a device is governed by the state of the ID pin which in turn is controlled by the USB cable connector type. The DM814x device has bonded out these ID pins and allows the control to be handled directly from the connector, i.e. the USB controller would assume the role based on the cable end inserted to the mini A/B connector (J2 & J3) on the EVM. There is a jumper option available on the EVM to ground the USB_ID pin for USB0 & USB1.

2.1.9 SPI Flash interface

The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (4 to 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The DM814x/AM387x processor supports Four Serial Peripheral Interfaces. The SPI0 signal from DM814x/AM387x is used to control SPI FLASH memory device. A 32MBIT SPI FLASH memory (W25X32VSFIG) provided on the EVM to provide SPI booting.

2.1.10 UART Interface

The UART performs serial-to-parallel conversions on data received from a peripheral device and Parallel-to-serial conversion on data received from the CPU. There are two UART interface (UART0 & UART1) available for DM814x/AM387x and one UART interface available for MSP430 on the EVM.UART0 on Base EVM is selected by enabling the signal UART0_OFF to LOW.UART0 is also routed to application boards UART interface through Board-Board connectors on the EVM. At a time either the UART interface (UART0) on Base EVM or application boards can be used.UART0 supports Baud-rate up to 3.6 Mbit/s.UART1 is connected to the IR receiver on the EVM. The IR Receiver is selected by enabling the signal IR_REMOTE_OFF to LOW.

2.1.11 I2C Interface

The device includes four inter-integrated circuit (I2C) modules which provide an interface to other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1. External components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through the I2C module.



The I2C port supports the following features in DM814x/AM387x:

Standard and fast modes from 10 - 400 Kbps Noise filter to remove noise 50 ns or less Seven- and ten-bit device addressing modes Multimaster transmitter/slave receiver mode Multimaster receiver/slave transmitter mode Combined master transmit/receive and receive/transmit modes Two DMA channels, one interrupt line Built-in FIFO (32 byte) for buffered read or write.

I2C0 of DM814x/AM387x is being shared across devices like Audio codec, IO Expander, MSP430 microcontroller, TPS62353, TPS659113, EEPROM. Also I2C0 & I2C2 are routed to Board-Board expansion connector to support the interfaces on application board. HDMI interface uses I2C1 signals.

2.1.12 Debug Interface

The EVM supports two JTAG debug interfaces namely: DM814x-JTAG & MSP430-JTAG interface. Debug connectors are used for test, debug, execute, trace and download the program to target unit. There are two JTAG connectors on the board

14pin MSP430 JTAG Header 20 pin DM814x-JTAG Header

2.1.13 PCI express Interface

PCIe is a serial-based technology which uses low-voltage differential data signaling/lines (LVDS) to reduce the number of data signal lines and high-frequency clock signals in a point-to-point interconnect arrangement between two devices. It also serves to eliminate multiple host presences on the same bus.

The PCIE sub system contains the Synopsys Design Ware core (DWC) PCIe Dual

Mode core and Texas Instruments SERDES PHY. The dual mode (DM) core operates as either endpoint (EP) mode or root complex (RC) port mode. The core supports a single in-port and a single out-port. The operating mode of the device; that is, the role that the PCIe core assumes, is set to either EP or RC based on the value sampled from the BOOTMODE[4:0] pins, if used as a secondary boot loader, or by application software Configuring PCIE_CFG [PCIE_DEVTYPE] register. The DM core can be switched between modes at runtime by applying a power-on reset.

PCIE supports high-speed data transfer at rates of up to 5.0 Gbps per lane per direction. PCIe on the EVM uses PCI_3V3 and IP_EVM_12V as the supply voltages. The clock required for clocking data and PHY functional clocks are generated by the PHY through the supplied external input 100 MHz differential clock from the device U28 (CDCM61002RHBR) on the EVM.



NOTE: To enable PCIe to be compatible with a PCs spread spectrum clock, the

following modification needs to do on the Base Board as shown on the figure3. 1. Remove the PCIe clock AC decoupling capacitors on the location C199,

C201, C206, C210 2. Place an 0805 size 270pF or .1uF capacitors across the pads of C199 &

C206 for negative reference clock and across the pads of C201 & C210 for positive reference clock that are closest to each other.

Figure 3: PCIe Clock AC Decoupling caps- Host Clocking enabled

2.1.14 MSP430 Interface

All the power supplies on both the base EVM and Application Boards are provided with power measurement capability using ultra low power microcontroller MSP430.



MSP 430 based controller in combination with Current/Power Monitor with I2C Interface INA226 will be used for power monitoring. In DM814x/AM387x Base EVM Twelve INA current monitors are available for monitoring the currents of following supply

1. VDDQ_DM814x_1V5

2. CVDD_DSP

3. CORE_VDD

4. CORE_HDVICP

5. VDDA_1V8

6. PLL_1V8

7. HDMI_1V8

8. CVDD_ARM

9. DVDD_GPMC

10. DVDD

11. DVDD_C

12. VMMC

The Table gives I2C address of power monitors

S No. Supply Name Address

1 PLL_1V8 1000000 2 HDMI_1V8 1000001 3 CVDD_ARM 1000010 4 VDDQ_DM814x_1V5 1000011 5 CORE_HDVICP 1000100 6 VDDA_1V8 1000101 7 DVDD_GPMC 1000110 8 DVDD 1000111 9 CORE_VDD 1001000 10 CVDD_DSP 1001001 11 DVDD_C 1001010 12 VMMC 1001011

Table 6: I2C Address of power monitors



2.2 Clock

The EVM has the following clocks,

1. Y1-Provide 32.768 KHZ Real Time Clock (RTC) to Power Management IC (TPS659113)

2. Y2- Provide 20MHz Device (DEV) clock which is used to generate the majority of the internal Reference clocks for DM814x/AM387x

3. Y3-Provide 25MHz Clock for Ethernet PHY (RGMII0)

4. Y4- Provide 32.768 KHZ auxiliary clock to MSP430 microcontroller 5. Y5- Provide 25 MHZ clock to generate differential clock for PCI & SERDES CLK

6. Y6- provide 22.579 MHZ the Auxiliary (AUX) clock which can optionally be used as a source for the Audio and/or Video PLLs

7. Y8- Provide 25MHz Clock for Ethernet PHY (RGMII1)

8. U32- Provide 32768-Hz clock input which is optionally provided at the CLKIN32 pin to serve as a reference clock in place of the RTCDIVIDER clock for the following Modules:

o RTC o GPIO0/1/2/3 o TIMER1/2/3/4/5/6/7 o ARM Cortex-A8 o SYNCTIMER

2.3 Power

The main power input for the EVM system is provided using an external 12V universal adaptor. The other voltages required for the main board are derived using on board regulators on the main board. There are four major switching regulators used to derive power for DM814x/AM387x EVM

1. TPS65232 (U10)-Gives TPS_EVM_5V0, BCK2_3V3, PCI_3V3

2. TPS659113 (U11)-Gives power to DM814x/AM387x

3. TPS51116 (U20) - DDR Power supply

4. TPS62353 (U68)-Gives TPS_CVDD_HDVICP



2.3.1 DM814x/AM387x Power

The Power Management IC TPS65913 (U11) takes care of the generation and distribution of various power requirements of the DM814x/AM387x Processor module which are listed below.

DM814x/AM387x I/O supply:TPS_VDDA_1V8 -1.8V DM814x/AM387x core supply

o VDD1(CVDD_ARM)-1.2V o VDD2 (CVDD_DSP)-1.2V o Core_VDD-1.2V o CVDD_HDVICP-1.2V

DM814x/AM387x Auxiliary Supplies o DVDD_GPMC-3.3V o DVDD-3.3V o DVDD_c-3.3V o DVDD_SD-3.3V o VDDA_1V8-1.8V o HDMI_1V8-1.8V o VDDA_USB_1V8V-1.8V o VDDQ_1V5-1.5V

DM814x/AM387x VDAC supply VDAC_1V8-1.8V

VDAC_3V3-3.3V

PLL Supply PLL_1V8-1.8V

The input supply to power Manager is from TPS_EVM_5V0 and TPS_BCK2_3V3 to generate different voltage rails.TPS659113 is controlled by I2C0 interface of DM814x/AM387x and the address is 0X2D.



Chapter 3

Physical Description

3. Physical Description

This chapter describes the physical layout of the DM814x/AM387x Base EVM.

3.1 DM814x/AM387x EVM layout

The DM814x/AM387x Base EVM REV D has the following dimension

317.5x187.96mm 10 layer PCB Thickness of layer 2mm



3.1.1 DM814x/AM387x BASE EVM Top View

Figure 4: TMDXEVM8148 EVM Base Board Top View

+12V DC

SD/MMC card holder

DM814x-JTAG

BOOT mode SW

HP OUT

USB1-OTG

Power ON Switch

USB0-OTG

S-Video OUT

CV OUT

HDMI OUT

LINE OUT LINE IN

MIC

DM814x-UART

NAND Flash PCIe connector

GPIO LEDs

GPIO SW

RGMII0

RGMII1

Audio codec

DM814X PROCESSOR

RGMII0-PHY

RGMII1-PHY

SPI Flash

DDR3-0 DDR3-1

EEPROM HEADER

IR R

ece

iver

SATA PWR

MS

P-JT

AG

MS

P-U

AR

T



3.1.2 DM814x/AM387x BASE EVM Bottom View

Figure 5: DM814x/AM387x BASE EVM Bottom View

64 Pin Power expansion B-B connectors (J16)

128 Pin GPMC B-B Connectors (J19)

128 pin Video B-B Connectors (J18)

64 Pin GPMC B-B Connectors (J21)

128 Pin MCASP B-B Connectors (J20)

64 pin Video B-B Connectors (J17)



3.2 Connectors/Switches/Headers

The DM814x/AM387x BASEEVM has several connectors, switches, Headers and jumpers for various purposes which are listed below;

3.2.1 SD / MMC

The MMC/SD card holder is located on top side of the board and is used to provide an interface to a MMC/SD card. It is a 28 pin SD\MMC card holder.

Figure 6: SD/MMC Connector

The pin-out details of SD\MMC card holder J15 is as follows

Pin No

Signal name Pin no

Signal name

1 MMC1_DAT3 15 MMC1_SD_CD 2 MMC1_CMD 16 NC 3 GND 17 NC 4 VMMC 18 GND 5 MMC1_CLK 19 NC 6 GND 20 NC 7 MMC1_DAT0 21 GND 8 MMC1_DAT1 22 NC 9 MMC1_DAT2 23 NC 10 NC 24 NC 11 NC 25 NC

SD\MMC card Holder



12 NC 26 NC 13 NC 27 GND 14 MMC1_SD_WP 28 GND

Table 7: SD/MMC Connector

3.2.2 JTAG Header

JTAG Header is located on the top side centre of the EVM. It is a 20 pin JTAG Header (10x2, 1.27 mm pitch).

Figure 7: JTAG Header

The pin out details of JTAG Header (J11) is as below:

Pin no Signal name

1 TMS 2 TRSTN 3 TDI 4 TDIS 5 TVD 6 KEY 7 TDO 8 GND1 9 TCKRTN 10 GND2 11 TCLK

DM814x-JTAG Header



12 GND3 13 EMU0 14 EMU1 15 SRST 16 GND4 17 EMU2 18 EMU3 19 EMU4 20 GND5

Table 8: JTAG Header

3.2.3 S-VIDEO out

The figure below shows this connector as viewed from the card edge.

Figure 8: S Video out Connector

S-Video Connector JC1 is a 4-pin connector. Do NOT plug into this connector with the power on. The pin out details of the S-Video out is as below

Pin No Signal

1 GND

1 GND

3 Video Y (Luma)

4 Video C (Chroma)

Table 9: S-Video Connector

S-Video OUT



3.2.4 Composite video Connector The figure below shows this connector as viewed from the card edge.

Figure 9: Composite Video out Connector

Composite Video connector J9 is a 4 pin RCA connector. Do NOT plug into this connector with the power on. The pin out details of the CV out on RCA connector is as below

Pin No Signal

1 VIDEO OUT

2 GND

3 GND

4 GND

Table 10: Composite Video Connector

3.2.5 USB-OTG Connector: The DM814x/AM387x EVM has two USB-OTG connector (J2 & J3). It is a 9 pin mini-AB connector. The figure below shows this connector as viewed from the card edge.

CV OUT



Figure 10: USB-OTG Connector

The pin out details of the USB-OTG connector (J2 & J3) is as below

Pin No

Pin no

1 VCC 6 SH1 2 D+ 7 SH2 3 D- 8 SH3 4 ID 9 SH4 5 GND

Table 11: USB-OTG Connector

3.2.6 HDMI OUT Connector: The EVM has HDMI OUT on the top side of EVM. It is 23 pin Type A Receptacle

connector. The figure below shows this connector as viewed from the card edge.

USB0-OTG USB1-OTG



Figure 11: HDMI Connector

The pin out details of the HDMI OUT connector (J1) is as below

Signal name

1 HDMI_D2+ 2 GND 3 HDMI_D2- 4 HDMI_D1+ 5 GND 6 HDMI_D1- 7 HDMI_DO+ 8 GND 9 HDMI_DO- 10 HDMI_CLK+ 11 GND 12 HDMI_CLK- 13 CE_REMOTE_OUT 14 NC 15 DDC_CLK 16 DDC_DAT 17 GND 18 5V_OUT_HDMI

HDMI OUT (J1) HDMI ESD Protection



19 HDMI_HP_OUT 20 GND 21 GND 22 GND 23 GND

Table 12: HDMI OUT Connector

3.2.7 Ethernet Connector: It has two RJ-45 connector with magnetics for both RGMII0 & RGMII1 interface. Both are connected to the respective Ethernet PHY Transceiver through parallel termination. The figure below shows this connector as viewed from the card edge.

Figure 12: Ethernet Connector

The pin out details of the Ethernet RJ45 connector (J14 & J27) is as below

Pin no Signal name

1 GND 2 PHY_VDD_2V5 3 TRD[3]P 4 TRD[3]N

RGMII1 RGMII0



5 TRD[2]P 6 TRD[2]N 7 TRD[1]P 8 TRD[1]N 9 TRD[0]P 10 TRD[0]N D1 ENET_LED_LINK D2 GND D3 ENET_LED_RX D4 EVM_3V3 SH1 GND SH2 GND

Table 13: Ethernet Connector

3.2.8 PCI express Connector: The EVM has PCIe2.0 x4connector with integrated PHY on DM814x/AM387x. The

Figure below shows the PCIe connector

Figure 13: PCIe Connector



The pin out details of PCI express connector U38 is as follows

Pin no Pin Description Pin no Pin Description

B1 IP_EVM_12V A1 PRSNT# B2 IP_EVM_12V A2 IP_EVM_12V B3 IP_EVM_12V A3 IP_EVM_12V B4 GND A4 GND B5 NC A5 TCK B6 NC A6 TDI B7 GND A7 NC B8 PCI_3V3 A8 TMS B9 TRSTn A9 PCI_3V3 B10 NC A10 PCI_3V3 B11 NC A11 PCI_CON_PORz B12 NC A12 GND B13 GND A13 REFCLKp B14 CON.PCIE_TXP0 A14 REFCLKn B15 CON.PCIE_TXN0 A15 GND B16 GND A16 CON.PCIE_RXP0 B17 PRSNT# A17 CON.PCIE_RXN0 B18 GND A18 GND B19 NC A19 NC B20 NC A20 GND B21 GND A21 NC B22 GND A22 NC B23 NC A23 GND B24 NC A24 GND B25 GND A25 NC B26 GND A26 NC B27 NC A27 GND B28 NC A28 GND B29 GND A29 NC B30 NC A30 NC B31 PRSNT# A31 GND B32 GND A32 NC

Table 14: PCIe Connector



3.2.9 UART Connector:

The EVM has two UART DB-9 connector. One UART connector (P2) is connected to DM814x/AM387x through RS232 Transceiver. The other UART connector (P1) is connected to MSP430 Microcontroller through RS232 Transceiver. The figure below shows this connector as viewed from the card edge.

Figure 14: UART Connector

The pin out details of UART connector is as below

Pin NO. Description Pin No. Description

1 NC 7 RTS 2 RXD 8 CTS 3 TXD 9 NC 4 NC 10 UART_GND 5 GND 11 UART_GND 6 NC

Table 15: UART Connector

DM814x-UART

MSP-UART



3.2.10 EEPROM Header: It has 2X5 EEPROM Header on the EVM. Jumper should be put on the Header as

shown on figure. To get the default connection from DM814x/AM387x place the jumper between 1-2, 3-4, 5-6 and 9-10 only and do not for 7-8.The pin 7 & 8 for write Protect function of EEPROM.

Figure 15: EEPROM Header

The pin out details of EEPROM Header is as below

Pin NO. Description Pin No. Description

1 EVM_3V3 2 PROM_EVM_3V3 3 I2C0_SCL 4 PROM_I2C0_SCL 5 I2C0_SDA 6 PROM_I2C0_SDA 7 EVM_3V3 8 PROM_WP 9 GND 10 GND

Table 16: EEPROM Header



3.2.11 MSP-JTAG Header: The EVM has 2X7; 2.54mm pitch JTAG Header to access the MSP430 microcontroller on the EVM.

Figure 16: MSP-JTAG Header

The pin out details of MSP-JTAG Header is as follows

Pin No

Signal name Pin no Signal name

1 MSP430_TDO/TDI 8 NC 2 NC 9 NC 3 NC 10 NC 4 EVM_3V3 11 NC 5 NC 12 NC 6 NC 13 NC 7 MSP430_TCK 14 NC

Table 17: MSP-JTAG Header



3.2.12 SATA POWER & DATA: The SATA Power & DATA connector is shown in the figure. SATA power

connector is a 4 pin, 5.08mm pitch Molex connector. SATA DATA connector is 7X1, 1.27mm pitch male connector

Figure 17: SATA POWER & DATA connector

The pin-out details of SATA power connector J10 is as follows

Pin No

Signal name

1 IP_EVM_12V 2 GND1 3 GND2 4 EVM_5V0

Table 18: SATA POWER connector

SATA POWER

SATA DATA



The pin-out details of SATA Data connector J12 is as follows

Pin No

Signal name

1 GND 2 SATA_TXP0_CON 3 SATA_TXN0_CON 4 GND 5 SATA_RXN0_CON 6 SATA_RXP0_CON 7 GND MH1 NC MH9 NC

Table 19: SATA DATA connector

3.2.13 Audio connectors The EVM has 4 audio connectors for different function like

1. Headphone OUT (J6) 2. Speaker OUT (J5) 3. Audio LINE IN from audio source (J7) 4. Microphone Input (J8)

All the four connectors are 3.5mm, 4pin female Stereo jack which are connected to Audio codec through coupling capacitors.

Pin No

Signal name

1 GND 2 LEFT_OUT 3 RIGHT_OUT 4 NC

Table 20: LINE OUT & HP OUT connector



Audio codec connectors is shown on the figure

Figure 18: Audio codec connectors

The pin out details of audio LINE IN connector is as follows

Pin No

Signal name

1 GND 2 LEFT_IN 3 RIGHT_IN 4 GND

Table 21: LINE IN connector

The pin out details of audio MIC IN connector is as follows

Pin No

Signal name

1 GND 2 LEFT_IN 3 (Shorted to pin2) 4 GND

Table 22: MIC IN connector



3.2.14 Power Switches: The EVM has one DPDT Switch SW1 for main power (12V supply) & 6 SPST 3 pin

slide switches for various purposes like as follows 1. SW3 (TPS65232 SW)-connected to IP_EVM_12v when switch position is towards Arrow mark and OFF when it is away from arrow mark on the Board. 2. SW4 (PCI_3V3 SW)-connected to TPS_PCI_3V3 when switch position is towards arrow mark & connected to EXP_EVM_3V3 when it is away from arrow mark. 3. Sw6 (EVM_3V3 SW)-Connected to LS_EVM_3V3 when switch position is towards arrow mark & connected to EXP_EVM_3V3 when it is away from arrow mark. 4.SW7(EVM_5V0 SW)- connected to TPS_EVM_5V0 when switch position is towards Arrow mark and OFF when it is away from arrow mark on the Board. 5.SW12(EXP_EVM3V3 SW)- Connected to EVM_3V3 when switch position is away from arrow mark & OFF when it is towards arrow mark 6.SW14(EXP_EVM_5V0 SW)- Connected to EVM_5V0 when switch position is away from arrow mark & OFF when it is towards arrow mark 3.2.14.1 Default Switch Settings of the EVM: While Power ON makes sure the following switches are in correct position as follows

SW3-towards Arrow mark (right side) SW4- towards Arrow mark (left side) SW6- towards Arrow mark (left side) SW7- towards Arrow mark (Right side) SW12-Away from Arrow mark (left side) SW14--Away from Arrow mark (Right side)



The figure shows the slide switches of DM814x/AM387x EVM

Figure 19: Slide Switches

SW6

SW7

SW14 SW12

SW4 SW3



3.2.15 Boot mode Switches:

The switch positions 1 to 5 of switch S1 determine the boot mode order. The 1st boot mode listed for each S1 [5:1] configuration is executed as the primary boot mode. If the primary boot mode fails, the 2nd, 3rd, and 4th boot modes are executed in that order until a successful boot is completed. The other positions of the switch S1 [6:12] & SW13 [1:4] is reserved and is to be pulled down (OFF).

Figure 20: Boot mode Switches

The table below shows the different boot combinations S1.1 S1.2 S1.3 S1.4 S1.5 Boot mode order

0 1 0 0 1 NAND- NANDI2C- SPI- UART 1 0 0 0 0 UART-XIP/WAIT(MUX0)(1)-MMC-SPI 1 1 1 0 1 MMC-SPI UART-EMAC 0 0 1 0 0 EMAC-SPI-NAND-NANDI2C

Table 23: Boot mode selection

SW13 S1

ON MARK



3.2.16 Reset Button SW9:

This switch generates a warm reset to the Processor to reset all modules in the device, except for the Test and Emulation logic, and the EMAC Switch.

Setting Result

OPEN Normal operating condition. Open = logical 1 state

PUSH BUTTON CLOSED

Active low reset signal .Closed = logical 0 state

Table 24: Warm Reset Push Button

The following sequence must be followed during a warm reset: 1. Power supplies and input clock sources should already be stable.

2. The RESET pin must be asserted (low) for a minimum of 30 DEV Clock cycles. Within the low period of the RESET pin, the following happens:

(a) All pins, except Test and Emulation pins enter a Hi-Z mode and the associated pulls, if applicable, will be enabled.

(b) The PRCM asserts reset to all modules within the device, except for the Test and Emulation logic, EMAC Switch (optional), PLL, and Clock configuration.

3. The RESET pin may now be de-asserted (driven high). When the RESET pin is de-asserted (high):

(a) The BTMODE [15:0] pins are latched. (b) Reset to the ARM Cortex-A8 and modules without a local processor is de-asserted, with the exception of Test and Emulation logic, EMAC Switch (optional), PLL, and Clock configuration. (c) RSTOUT_WD_OUT is asserted for TBD DEV Clock cycles, if BTMODE [11] was latched as "0". (d) The clock, reset, and power-down state of each peripheral is determined by the default settings of the PRCM.

(e) The ARM Cortex-A8 begins executing from the Boot ROM.



Figure 21: Reset Switches

3.2.17 Power ON Reset SW10: This switch can be used to reset the entire chip, including the Test and

Emulation logic, and the EMAC Switch. PORn is also referred to as a cold reset since it is required to be asserted when the device goes through a power-up cycle

Setting Result

OPEN Normal operating condition. Open = logical 1 state

PUSH BUTTON CLOSED Active low Power ON Reset. Closed = logical 0 state

Table 25: Cold Reset Push Button

The following sequence must be followed during a Power-on Reset: 1. Wait for the power supplies to reach normal operating conditions while keeping the POR pin asserted.

Warm Reset Power ON Reset



2. Wait for the input clock sources DEV_CLKIN, AUX_CLKIN, and SERDES_CLKN/P to be stable (if used by the system) while keeping the POR pin asserted (low).

3. Once the power supplies and the input clock sources are stable, the POR pin must remain asserted (low) for a minimum of 2 DEV Clock cycles. Within the low period of the POR pin, the following happens:

(a) All pins except Emulation pins enter a Hi-Z mode and the associated pulls, if applicable, will be enabled.

(b) The PRCM asserts reset to all modules within the device.

(c) The PRCM begins propagating these clocks to the chip with the PLLs in BYPASS mode.

4. The POR pin may now be de-asserted (driven high). When the POR pin is de-asserted (high):

(a) The BTMODE [15:0] pins are latched. (b) Reset to the ARM Cortex-A8 and Modules without a local processor is de-asserted.

(c) RSTOUT_WD_OUT is briefly asserted if BTMODE [11] was latched as "0".

(d) The clock, reset, and power-down state of each peripheral is determined by the default settings of the PRCM. (e) The ARM Cortex-A8 begins executing from the Boot ROM.



3.2.18 GPIO Switch & LEDs

The EVM includes 4 GPIO LEDs controlled through I2CO interface & it toggle based upon the switch settings of SW8 on the EVM.

3.2.19 Fuses: The EVM has fuse F1 near the switch SW1.The one end of Fuse is connected

after Schottky Barrier Rectifier & transient voltage suppressors. The other end of Fuse is connected to Switch SW1.The current ratings of the Fuse is 4A and the voltage rating is 125VDC.

GPIO LED

GPIO SW



3.3 Test Points

The EVM has many test points. All test points are available on the top side of the board. The following figure identifies the position of each test point and the table lists the each test point signal.

Table 26: Test points

S. No Supply Reference1 IP_EVM_12V TP1 2 EVM_5V0 TP3 3 BCK2_3V3 TP32 4 LS_EVM_3V3 TP43 5 EVM_3V3 TP56 6 PCI_3V3 TP10 7 VDDQ_1V5 TP53 8 VREF TP76 9 CORE_VDD TP13 10 CVDD_ARM TP31 11 CVDD_DSP TP48 12 VDDA_1V8 TP33 13 PLL_1V8 TP15 14 VMMC TP68 15 VDDA_USB_1V8 TP28 16 VDAC_1V8 TP11 17 DVDD TP39 18 CVDD_HDVICP TP58 19 EVM_1V8 TP25 20 VAIC_1V8 TP19 21 RSTOUTn TP59 22 PORz TP75



Figure 22: Major Test Points of EVM

TP3 TP13 TP1

TP53

TP59

TP76

TP48

TP56

TP31

TP43



3.4 Expansion Connector

The pin-out details of the 64 pin Power expansion connector J16 of EVM are as below:

Pin no Pin Description Pin no Pin Description 1 EXP_CVDD_ARM 2 EXP_CORE_VDD 3 EXP_CVDD_ARM 4 EXP_CORE_VDD 5 EXP_CVDD_ARM 6 EXP_CORE_VDD 7 EXP_CVDD_ARM 8 EXP_CORE_VDD 9 GND 10 GND 11 EXP_CVDD_DSP 12 EXP_CORE_VDD 13 EXP_CVDD_DSP 14 EXP_CORE_VDD 15 EXP_CVDD_DSP 16 EXP_CORE_VDD 17 EXP_CVDD_DSP 18 EXP_VDDQ_1V5 19 GND 20 GND 21 EXP_EVM_1V8 22 EXP_VDDQ_1V5 23 EXP_EVM_1V8 24 EXP_VDDQ_1V5 25 EXP_EVM_1V8 26 EXP_VDDQ_1V5 27 EXP_EVM_1V8 28 EXP_VDDQ_1V5 29 GND 30 GND 31 EXP_EVM_1V8 32 EXP_VDDQ_1V5 33 EXP_EVM_3V3 34 EXP_VDDQ_1V5 35 EXP_EVM_3V3 36 EXP_VDDQ_1V5 37 EXP_EVM_3V3 38 EXP_VDDQ_1V5 39 GND 40 GND 41 EXP_EVM_3V3 42 EXP_EVM_3V3 43 EXP_EVM_3V3 44 EXP_EVM_3V3 45 EXP_EVM_3V3 46 EXP_EVM_3V3 47 EXP_EVM_3V3 48 EXP_EVM_3V3 49 GND 50 GND 51 NC 52 NC 53 NC 54 NC 55 NC 56 NC 57 NC 58 NC 59 NC 60 NC 61 GND 62 GND 63 GND 64 GND

Table 27: 64 pin Power Expansion Connector J16



The pin-out details of the 64 pin Board-Board video expansion connector J17 of EVM are as below:

Pin no Pin Description Pin no Pin Description 1 VIN0_DE0 2 NC 3 GND 4 GND 5 VIN0_HSYNC 6 NC 7 NC 8 NC 9 GND 10 GND 11 VIN0_VSYNC 12 NC 13 NC 14 VIN0_DE1 15 GND 16 GND 17 NC 18 NC 19 NC 20 VIN0_FLD0 21 GND 22 GND 23 NC 24 RSV14 25 NC 26 RSV15 27 GND 28 GND 29 NC 30 RSV12 31 NC 32 RSV13 33 GND 34 GND 35 SPI1_SCLK 36 RSV10 37 SPI1_MISO 38 RSV11 39 GND 40 GND 41 SPI1_MOSI 42 RSV9 43 SPI1_nCS0 44 RSV8 45 GND 46 GND 47 NC 48 RSV7 49 NC 50 RSV6 51 GND 52 GND 53 NC 54 NC 55 NC 56 NC 57 GND 58 GND 59 NC 60 NC 61 GND 62 GND 63 GND 64 GND

Table 28: 64 pin video Expansion Connector J17



The pin-out details of the 128 pin Board-Board video expansion connector J18 of EVM are as below:

Pin no Pin Description Pin no Pin Description 1 VIN0_DE0 2 VIN0_D0 3 GND 4 GND 5 VIN0_FLD0 6 VIN0_D2 7 VIN0_CLK1 8 VIN0_D9 9 GND 10 GND 11 VIN0_D1 12 VOUT0_G_Y_YC2 13 VIN0_D4 14 VOUT0_G_Y_YC6 15 GND 16 GND 17 VIN0_D11 18 VOUT0_R_CR4 19 VIN0_D5 20 VIN0_D6 21 GND 22 GND 23 VIN0_D12 24 VIN0_D8 25 VIN0_D10 26 VIN0_D3 27 GND 28 GND 29 VIN0_D14 30 VIN0_D7 31 VIN0_D13 32 VOUT0_G_Y_YC4 33 GND 34 GND 35 VIN0_D15 36 VOUT0_B_CB_C8 37 VOUT0_CLK 38 VOUT0_G_Y_YC5 39 GND 40 GND 41 VOUT0_G_Y_YC8 42 VOUT0_B_CB_C6 43 VOUT0_G_Y_YC7 44 VOUT0_B_CB_C5 45 GND 46 GND 47 EXP_EVM_3V3 48 IP_EVM_12V 49 EXP_EVM_3V3 50 IP_EVM_12V 51 GND 52 GND 53 EXP_EVM_5V0 54 IP_EVM_12V 55 EXP_EVM_5V0 56 IP_EVM_12V 57 GND 58 GND 59 VOUT0_B_CB_C9 60 VOUT0_B_CB_C3 61 VOUT0_R_CR2 62 VOUT0_B_CB_C7 63 GND 64 GND 65 VOUT0_R_CR6 66 VOUT0_G_Y_YC3 67 VOUT0_R_CR5 68 VOUT0_G_Y_YC9 69 GND 70 GND 71 VOUT0_R_CR9 72 VIN0_CLK0 73 VOUT0_HSYNC 74 VOUT0_B_CB_C4 75 GND 76 GND 77 VIN0_D16 78 VOUT0_B_CB_C2 79 VIN0_D17 80 VOUT0_R_CR3 81 GND 82 GND



Pin no Pin Description Pin no Pin Description 83 VIN0_D18 84 VIN0_D19 85 VOUT0_VSYNC 86 VIN0_D20 87 GND 88 GND 89 NC 90 NC 91 NC 92 VIN0_D21 93 GND 94 GND 95 VOUT0_AVID 96 VIN0_D22 97 NC 98 VOUT0_R_CR7 99 GND 100 GND 101 VIN0_FLD1 102 VOUT0_R_CR8 103 USB1_CE 104 VIN0_D23 105 GND 106 GND 107 NC 108 NC 109 NC 110 USB0_CE 111 GND 112 GND 113 PM_I2C_SCL 114 NC 115 PM_I2C_SDA 116 NC 117 GND 118 GND 119 NC 120 NC 121 GND 122 GND 123 GND 124 GND 125 GND 126 GND 127 GND 128 GND

Table 29: 128 Pin Video Expansion Connector J18

The pin-out details of the 128 pin Board-Board GPMC expansion connector J19 of EVM are as below:

Pin no Pin Description Pin no Pin Description 1 McA5_AXR0 2 PM_I2C_SCL 3 GND 4 GND 5 GPMC_nCS3 6 PM_I2C_SDA 7 EXP_GPMC_nCS0 8 OSC_WAKE 9 GND 10 GND 11 GPMC_nCS2 12 EXP_GPMC_A22 13 GPMC_nCS1 14 EXP_GPMC_A23 15 GND 16 GND 17 GPMC_WEN 18 GPMC_nCS4 19 McA5_AXR1 20 VOUT1_R_CR0 21 GND 22 GND 23 GPMC_OEN_REN 24 VOUT1_R_CR1 25 GPMC_nBE1 26 MMC2_DAT1 27 GND 28 GND 29 VOUT1_G_Y_YC1 30 MMC2_DAT2



Pin no Pin Description Pin no Pin Description 31 MMC2_DAT0 32 MMC2_DAT3 33 GND 34 GND 35 VOUT1_B_CB_C1 36 VOUT1_B_CB_C2 37 VOUT1_B_CB_C0 38 MMC2_CLK 39 GND 40 GND 41 VOUT1_FLD 42 GPMC_WAIT0 43 GPMC_D0 44 McA5_AFSX 45 GND 46 GND 47 EXP_EVM_3V3 48 IP_EVM_12V 49 EXP_EVM_3V3 50 IP_EVM_12V 51 GND 52 GND 53 EXP_EVM_5V0 54 IP_EVM_12V 55 EXP_EVM_5V0 56 IP_EVM_12V 57 GND 58 GND 59 GPMC_D2 60 VOUT1_G_Y_YC0 61 GPMC_D5 62 GPMC_nBE0_CLE 63 GND 64 GND 65 GPMC_D7 66 GPMC_D4 67 GPMC_D9 68 GPMC_D3 69 GND 70 GND 71 GPMC_D12 72 GPMC_D1 73 GPMC_D11 74 McA5_ACLKX 75 GND 76 GND 77 GPMC_D10 78 GPMC_nADV_ALE 79 GPMC_CLK 80 GPMC_D6 81 GND 82 GND 83 GPMC_D15 84 GPMC_D8 85 NC 86 GPMC_D13 87 GND 88 GND 89 NC 90 NC 91 AUXOSC_MXI 92 NC 93 GND 94 GND 95 NC 96 MMC0_DAT0 97 UART0_DTRn 98 MMC0_DAT1 99 GND 100 GND 101 SPI0_nCS0 102 GPMC_D14 103 SPI0_SCLK 104 MMC0_DAT2 105 GND 106 GND 107 GPMC_A21 108 SPI0_MOSI 109 SPI0_nCS1 110 SPI0_MISO 111 GND 112 GND 113 MMC0_CLK 114 DCAN0_RX 115 MMC0_CMD 116 MMC0_DAT3 117 GND 118 GND



119 EXP_UART0_RXD 120 DCAN0_TX 121 GND 122 GND 123 GND 124 GND 125 GND 126 GND 127 GND 128 GND

Table 30: 128 Pin GPMC Expansion Connector J19

The pin-out details of the 128 pin Board-Board MCASP expansion connector J20 of EVM are as below:

Pin no Pin Description Pin no Pin Description 1 PM_I2C_SCL 2 UART0_DSRn 3 GND 4 GND 5 PM_I2C_SDA 6 UART0_DCDn 7 EXP_MCA2_AXR0 8 I2C0_SDA 9 GND 10 GND 11 MCA1_AXR2 12 I2C0_SCL 13 EXP_MCA2_AXR1 14 I2C1_SDA 15 GND 16 GND 17 MCA1_AXR3 18 I2C1_SCL 19 EXP_MCA2_ACLKX 20 MCA0_AXR3 21 GND 22 GND 23 MCA2_AXR2 24 MCA0_AXR2 25 EXP_MCA2_AFSX 26 MCA0_AXR6 27 GND 28 GND 29 AUD_CLKIN2 30 AUD_CLKIN0 31 MCA2_AXR3 32 MCA0_AFSR 33 GND 34 GND 35 MCA1_AXR1 36 MCA0_ACLKX 37 MCA1_AXR0 38 MCA0_AFSX 39 GND 40 GND 41 VOUT1_G_Y_YC8 42 MCA1_AFSX 43 VOUT1_B_CB_C9 44 MCA0_AXR1 45 GND 46 GND 47 EXP_EVM_3V3 48 IP_EVM_12V 49 EXP_EVM_3V3 50 IP_EVM_12V 51 GND 52 GND 53 EXP_EVM_5V0 54 IP_EVM_12V 55 EXP_EVM_5V0 56 IP_EVM_12V 57 GND 58 GND 59 AUD_CLKIN1 60 VOUT1_G_Y_YC4 61 MDIO_MDIO 62 MCA0_AXR5 63 GND 64 GND 65 MDIO_MDCLK 66 MCA0_AXR4



Pin no Pin Description Pin no Pin Description 67 MCA1_ACLKX 68 MCA0_AXR0 69 GND 70 GND 71 VOUT1_B_CB_C3 72 MCA1_ACLKR 73 VOUT1_B_CB_C4 74 MCA0_AXR7 75 GND 76 GND 77 VOUT1_B_CB_C6 78 MCA1_AFSR 79 VOUT1_B_CB_C5 80 VOUT1_G_Y_YC7 81 GND 82 GND 83 VOUT1_B_CB_C8 84 VOUT1_R_CR7 85 VOUT1_B_CB_C7 86 VOUT1_VSYNC 87 GND 88 GND 89 VOUT1_G_Y_YC3 90 VOUT1_R_CR8 91 VOUT1_G_Y_YC5 92 MCA0_AXR8 93 GND 94 GND 95 VOUT1_G_Y_YC6 96 MCA0_AXR9 97 VOUT1_G_Y_YC9 98 VOUT1_HSYNC 99 GND 100 GND 101 VOUT1_R_CR4 102 NC 103 VOUT1_R_CR6 104 MCA0_ACLKR 105 GND 106 GND 107 VOUT1_R_CR5 108 NC 109 VOUT1_CLK 110 NC 111 GND 112 GND 113 VOUT1_R_CR9 114 VOUT1_AVID 115 NC 116 NC 117 GND 118 GND 119 NC 120 NC 121 GND 122 GND 123 GND 124 GND 125 GND 126 GND 127 GND 128 GND

Table 31: 128 Pin MCASP Expansion Connector J20



The pin-out details of the 64 pin Board-Board GPMC expansion connector J21 of EVM are as below:

Pin no Pin Description Pin no Pin Description 1 VOUT1_R_CR3 2 MCA3_ACLKX 3 GND 4 GND 5 EXP_UART0_TXD 6 GPMC_A20 7 MCA3_AXR0 8 GPMC_A18 9 GND 10 GND 11 VOUT1_R_CR2 12 GPMC_A19 13 MCA3_AXR1 14 GPMC_A17 15 GND 16 GND 17 MMC2_DAT7 18 MMC2_DAT5 19 MMC2_DAT6 20 VOUT1_G_Y_YC2 21 GND 22 GND 23 VOUT0_FLD 24 MCA3_AXR2 25 GP0_31 26 MCA3_AXR3 27 GND 28 GND 29 CLK32OUT 30 MCA3_AFSX 31 MCA4_ACLKX 32 UART0_CTSn 33 GND 34 GND 35 GP1_10 36 UART0_RTSn 37 GP1_9 38 GPMC_A16 39 GND 40 GND 41 GP1_8 42 UART0_RIN 43 GP1_7 44 RSTOUTn 45 GND 46 GND 47 RSV17 48 GP0_30 49 RSV16 50 GP0_29 51 GND 52 GND 53 MCA4_AXR0 54 MCA4_AXR1 55 EXP_WARM_RESET 56 MCA4_AFSX 57 GND 58 GND 59 APP_PORz 60 MMC2_DAT4 61 GND 62 GND 63 GND 64 GND

Table 32: 64 Pin GPMC Expansion Connector J21



Appendix A

Schematics

This appendix contains the schematics for the DM814x/AM387x REVD Base EVM.


108

Appendix B

Mechanical Information

This appendix contains the assembly diagram of the DM814x/AM387x EVM.

A-12A-1


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Acronyms

BGA Ball grid Array CCS Code Composer Studio DDR Double Data Rate EEPROM Electrically Erasable Programmable Read Only Memory ESD - Electro Static Discharge EVM Evaluation Module GPIO General Purpose Input/Output GPMC-General Purpose Memory Controller I2C Inter Integrated Circuit JTAG Joint Test Action Group LCD Liquid Crystal Display LED - Light Emitting Diode MAC Media Access Controller McBSP Multi Channel Buffered Serial Port OTG On-The-Go PCB Printed Circuit Board PHY Physical Transceiver SD/MMC Secure Digital/Multi Media Card SDRC SDRAM Controller SDRAM Synchronous Dynamic Random Access Memory SPI Serial Peripheral Interface SPDT Single Pole Double Throw UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus

B-4


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Mistral Solutions Pvt. Ltd.
