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Mixed-Signal Group
Murmann
Mixed-Signal Group
Murmann
Digitizing the Analog World:
Challenges and Opportunities
April 5, 2010
Boris Murmann
2
Murmann Mixed-Signal Group
Research Overview
Signal
Processing
A/D
D/A
Signal
Conditioning
Signal
Conditioning
Transducers,
Antennas,
Cables, ...
Digital enhancement
algorithms
High-performance and low-
power A/D and D/A
converters
Sensor
interfaces
MEMS
Spin-Valve
Biomolecule
detection
Neural
prostheticsMedical ultrasound
3
Research Examples
High-performance A/D converters
Neural prosthetics
MEMS accelerometers
Large area electronics
4
Digitally Assisted A/D Converters
Signal
Processing
A/D
D/A
Signal
Conditioning
Signal
Conditioning
Analog Media
and
Transducers
DigitalAnalog
CLK
Additional digital processing for
performance enhancement
5
ADC for a “Digital” Serial Link
No analog error accumulation and better scalability
Need efficient high-speed ADC, typically > 10GS/s
6
ADC1
ADC2
ADCN
text
X(t) Y[n]
Time-Interleaving
1
2
N
7
Popular way to increase ADC throuhgput
ADC1
ADC2
ADCN
X(t) Y[n]
G1
Voff_2
G2
Voff_N
GN
Voff_1
text
Imperfections
1
2
N
8
Mismatches result in signal distortion Gain
Offset
Timing Skew
Our Focus: Timing Skew
9
1
2
(2-channel example)
Digital Backend
ADC1
ADC2
ADCN
X(t)
ADCCal
Y[n]
Clock
Skew Calibration Using Extra ADC
Statistics-based skew measurement in digital backend
Correction through analog adjustments
10
1
2
N
Cal
1 2
Digitally
adjustable
delay cells
N
Timing of Auxiliary ADC Phase
1
2
N
Cal
1
2
N
Cal
1 2
Digital Backend
ADC1
ADC2
ADCN
X(t)
ADCCal
Y[n]
Clock
11
1
2
N
Cal
Calibration Scheme
For each channel, adjust delay cells until correlation between
calibration ADC output and each slice are maximized
ADCCal can be 1-bit and “slow”
12
ADC1
ADC2
ADCN
X(t)
ADCCal
Y[n]
ClockMax
1
2
N
Cal
1 2
R()
Removed pre-publication slides on experimental
results…
13
14
MEMS Accelerometer
Capacitance change ~10 fF/g
Desired resolution ~10 mg for airbags and ESP Must resolve capacitance changes of ~100 aF
Problem: Drift in parasitic bondwire capacitance
CMOS
15
Sigma-Delta Interface
INam
kbsms 2
1 x
xC
C
VCA V
S/HLead
Compensator
DigVmechF
Force-
Balancing
DecimatorOutV
M. Lemkin and B. E. Boser, “A three-axis micromachined accelerometer with a CMOS
position-sense interface and digital offset-trim electronics,“ IEEE J. Solid-State Circuits,
vol. 34, pp. 456-468, April 1999.
Mechanical
16
Offset
INam
kbsms 2
1 xx
C
CVCA
VS/H
Lead
Compensator
mechF
Force-
Balancing
OffsetC
Offset due to bond
wire deformation
17
Linear Feedback System with Two Inputs
1 2
1 1y x x
f af
ayx1
f
+ _ b+
x2
18
Spring Constant Modulation
The output due to Coff can be modulated to higher
frequencies by modulating the spring constant k
1Out mech Off
k kV F C
CFBFB
x
INam
kbsms 2
1 xx
C
CVCA
VS/H
Lead
Compensator
mechF
Force-
Balancing
OffsetC
19
Spring softening effect
Acceleration
Spring
Acceleration
Spring
_ _+
_ _+
_ _+
_ _+
Electrostatic
Can be used to modulate spring constant (k)
20
Modulation through Multiplexed Feedback
Time-Multiplexed
INam
kbsms 2
1 x
xC
CVCA
VS/H
PULSE
OutVmechF
Electrostatic
Force
Decimator
xkm kf
Int Com
T T
MOD MOD Force-BalancingForce-Balancing
Output Spectrum with 1-Tone Modulation
21
10-6
10-5
10-4
10-3
10-2
10-1
-160
-140
-120
-100
-80
-60
-40
-20
0
Frequency (MHz)
Po
we
r/fr
eq
ue
ncy (
dB
/Hz)
10-6
10-5
10-4
10-3
10-2
10-1
-160
-140
-120
-100
-80
-60
-40
-20
0
Frequency (MHz)
Po
we
r/fr
eq
ue
ncy (
dB
/Hz)
10-6
10-5
10-4
10-3
10-2
10-1
-160
-140
-120
-100
-80
-60
-40
-20
0
Frequency (MHz)
Po
we
r/fr
eq
ue
ncy (
dB
/Hz)
-89 dB
-32 dB
-46 dBDC
Acceleration
Offset
Capacitance
0 fF
10 fF
50 fF
9.1 m/s^2
9.1 m/s^2
9.1 m/s^2
100
102
104
106
-140
-120
-100
-80
-60
-40
-20
Frequency [Hz]
Outp
ut S
pectr
um
[dB
]
Modulating spring-constant with a pseudo-random sequence
22
Pseudo-Random Modulation
23
Parameter Convergence
0 0.5 1 1.5 2-0.2
0
0.2
0.4
0.6
0.8
1
1.2
Time [Sec]
Feedback s
ignal [x
10
-15]
Closed-loop system - Feeding back capacitance
Coff=0fF
Coff=0.01fF
Coff=0.1fF
Coff=1fF
Chip Design in Progress
24
CMOS
MEMS
C to V Integrator Compensator Quantizer
Electrostatic
Feedback
State-
Machine
VOut
Clk
VRef Gnd
FPGA
DecimatorCorrelator
DOut
k-modulation
Scan In/Out
Neural Prosthetics
Cortical motor prosthetics Neurons in the motor cortical areas of the brain encode
information about intended movement
25Courtesy K.V. Shenoy Courtesy L.R. Hochberg
Nature Magazine June ‘06
Neural Signal Acquisition
Electrode signals consist of multiple sources DC Offset, about 15mV from electrode/tissue interface
Local field potential (LFP), ≤3mV peak, 10Hz to 100Hz
Spikes from nearby neurons, 35μV – 1mV peak, 500Hz to 5kHz
26
Courtesy C.L. KlaverCourtesy M. Sahani
Specs
27
Spikes Local Field Potential
Gain 600 V/V 200 V/V
Lower Cutoff 300Hz 1Hz
Upper Cutoff 10kHz 1kHz
Input Referred Noise
(total from sampling node)2.0µVrms 1.0µVrms in 10-100Hz
Total Power (96x Array) 3mW 100µW
Separate the fast and slow signal acquisition for DR Custom front end design for each path
Spike Path Front-End
28
Input Stage
SC
Bandpass
Filter
SAR ADC
Input Cap
Output
Buffers
Sampling Phase
29
Integrate signal current on
CB and sample
High-pass for DC block
using Cac and Rbig (off-
resistance)
A1 contains a pole that
helps minimize noise
folding
A1 Implementation Details
30
ITAIL I<< ITAIL
Voutp
Voutm
VB1
VB2
M1a M1b
Flicker noise
reduction
Anti-alias for
thermal noise
from M1a,b
Static Power
31
Two-Channel Interface Pixel
32
Frontend
SAR ADC
Die Photo (96 channels, 5mm x 5mm)
33
The Future?
34
Organic Semiconductors
Mechanically flexible
Suitable for solution processing Cover large areas at low cost
Make disposable devices
35
Jellyfish Autonomous Node
36
http://muri.mse.vt.edu/
Jellyfish Bell Prototype (Virginia Tech)
37
A bio-inspired shape memory alloy composite (BISMAC) actuator
A .A .Villanueva, et al., 2010 Smart Mater. Struct. 19 025013 (17pp)
Want to Make Plastic ADCs !
38
6-bit A/D Converter Prototype
39
W. Xiong, U. Zschieschang, H. Klauk, and B.
Murmann, “A 3V, 6b Successive Approximation ADC
using Complementary Organic Thin-Film Transistors
on Glass,” ISSCC 2010.
Substrate Glass
Interconnect Ti/Au evaporation, litho, wet etch
Gate electrodes Al evaporation, shadow masking
Source/Drain Au Evaporation, shadow masking
Dielectric 5.7nm AlOx/SAM
PFET DNTT, ~0.5 cm2/Vs
NFET F16CuPc, ~0.02 cm2/Vs
Area 28mm x 22mm
Component count 74
ADC Schematic
40
VREFN
C/32 C/32C/32
...
...
Bit 0 Bit 1 Bit 5Bit 2, 3, 4
Input
SAR Logic
(off-chip)
Output
To DAC
ComparatorDAC with
Sampler
C CCC 2C 2C
VREFN VREFNVREFP VREFNVREFP VREFP VMID
VREFPVMID
VREFN
Calibration DAC
Main DAC
Calibration enables 6-bit
precision despite poorly
matched capacitors
C-2C structure
possible due
small stray
caps (glass)
Comparator
41
CS1 CS2 CS3 CS4
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Wp = 500um
Wn = 500um
Lp = Ln = 20um
CS1 = 1.1nF
A0 = -7.8
= 3.0ms
Wp = 400um
Wn = 400um
Lp = Ln = 20um
CS2 = 1.1nF
A0 = -9.8
= 4.0ms
Wp = 400um
Wn = 400um
Lp = Ln = 20um
CS3 = 1.1nF
A0 = -9.8
= 4.0ms
Wp = 100um
Wn = 300um
Lp = Ln = 20um
CS4 = 1.1nF
A0 = -19.6
= 16.4ms
Transmission Gates:
Wp = Wn = 100um
Lp = Ln = 20um
CF1 CF2 CF3 CF4
+ -
Input Output
Auto-zeroing
cancels threshold
voltage drift
Anti-parallel PFET/NFET
layout minimizes variations
if CF due to misalignment
CgdnCgdp
0 8 16 24 32 40 48 56 63-4
-2
0
2
4D
NL
(L
SB
)
Code
0 8 16 24 32 40 48 56 63-4
-2
0
2
4
Code
INL
(L
SB
)
Measured DNL/INL
42
Before calibration, 100 Hz clock rate
0 8 16 24 32 40 48 56 63-1
-0.5
0
0.5
1D
NL
(L
SB
)
Code
0 8 16 24 32 40 48 56 63-1
-0.5
0
0.5
1
Code
INL
(L
SB
)
Measured DNL/INL
43
After calibration, 100 Hz clock rate
Organic ADC Summary
44
Process3 metal complementary
organic thin-film
Minimum feature size 20 mm
Chip area 28 mm x 22 mm
Resolution 6 bits
Full-scale range 2 V
Max DNL / INL -0.6 LSB / 0.6 LSB
Clock rate / Update rate 100 Hz / 16.7 Hz
Power consumption 3.6 mW @ 3 V
45
Conclusions
Mixed-signal IC design remains a vibrant area of
research
Changing boundary conditions Ever-increasing need for higher performance, lower power
New applications
New device technologies
A recurring theme in our research Looking for new ways to overcome analog imperfections
using DSP and calibration