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NANOELECTROMECHANICAL RELAYS FOR ENERGY-EFFICIENT,
INTEGRATED SYSTEMS
A DISSERTATION
SUBMITTED TO THE DEPARTMENT OF MECHANICAL ENGINEERING
AND THE COMMITTEE ON GRADUATE STUDIES
OF STANFORD UNIVERSITY
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
Kimberly L. Harrison
August 2015
http://creativecommons.org/licenses/by-nc/3.0/us/
This dissertation is online at: http://purl.stanford.edu/kd660zc5422
© 2015 by Kimberly Lake Harrison. All Rights Reserved.
Re-distributed by Stanford University under license with the author.
This work is licensed under a Creative Commons Attribution-Noncommercial 3.0 United States License.
ii
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Roger Howe, Primary Adviser
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Mark Cutkosky, Co-Adviser
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Thomas Kenny
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
H.S.Philip Wong
Approved for the Stanford University Committee on Graduate Studies.
Patricia J. Gumport, Vice Provost for Graduate Education
This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file inUniversity Archives.
iii
iv
Abstract
As CMOS transistors scale to smaller technology nodes and gate lengths become
shorter, the passive power loss of CMOS devices becomes higher and CMOS-based
electronics waste more energy in their off-state. This leads to shorter battery life, thus
limiting the size and lifetime of untethered devices such as mobile phones, medical
implants, wireless sensors and aerospace systems. Nanoelectromechanical (NEM)
relays, which feature zero off-state leakage current and near-zero subthreshold slope,
are ideal devices for low-energy electronics. As components in integrated CMOS-NEM
systems, relays have the potential to greatly reduce overall power usage and footprint.
I will first discuss the advantages of electrostatic NEM relays over other relay
designs including low actuation voltages, hysteresis, good scaling behavior, and flexible
materials and processing choices. A review of device physics illuminates some design
requirements for better performance. Promising applications for integrated CMOS-
NEM relay systems include logic and computation, low-energy memory, energy-
efficient signal routing and energy management of power sources.
Next, I present an advanced process flow for fabrication of CMOS-compatible
NEM relays. I demonstrate back-end-of-line compatible fabrication of polysilicon
germanium NEM relays with buried aluminum interconnect layer. The buried
interconnect is protected from the release etch by a silicon nitride or alumina etchstop
layer. A titanium nitride barrier layer prevents spiking of the aluminum into the
v
structural layer. Ohmic contact performance is enhanced by using an ALD ruthenium
or ALD titanium nitride contact layer. A lifetime of 900,000 cycles with contact
resistance under 100MΩ has been observed among ruthenium-coated devices in a
nitrogen ambient. Additional design considerations, such as a compliant contact etching
and high overdrive voltage, can lead to contact resistances under 500Ω. Analysis of
thermal behavior at the contact promises to further lower resistance, prevent welding or
predict welding for use in semi-permanent latching structures. I present experimental
data which closely matches an advanced model of NEM relay thermal behavior, as well
as operation of a thermally “latching” electrostatic relay.
Finally, device characteristics are compared with prior work. Previous designs
of laterally-actuated electrostatic relays show lower resistance at higher cycles, but do
not show CMOS-compatible processing. Other prior work shows CMOS-compatible
processing with good performance, but does not demonstrate buried device layers. The
work presented in this thesis represents a step forward in the demonstration of NEM
relays for back-end-of-line compatible processing by demonstrating working relays
with buried aluminum interconnect for the first time. Suggested further work includes
scaling of devices to achieve CMOS-compatible actuation voltages and encapsulation
to prevent premature degradation of the contact.
vi
Acknowledgement
First, I would especially like to thank my adviser Prof. Roger Howe. His upbeat
attitude and expansive knowledge were tremendous assets during my graduate work. I
first realized that I wanted to specialize in nano-devices after taking ENGR240
Introduction to Micro- and Nano-Electromechanical Systems with Prof. Howe. He
made the class so fun and exciting that I became hooked. In addition to being a giant in
the field, he was an excellent teacher who was always eager to share his excitement with
anyone and everyone, no matter their background. His excitement for my work kept
me going in rough times, and I will always appreciate the pep talks and cheerleading
that helped me to overcome many challenges and set-backs.
I would like to thank my co-adviser Prof. Mark Cutkosky. When I first started
my graduate studies, Prof. Cutkosky provided invaluable mentorship and assistance.
My first years working in his lab on scansorial robotics became a solid basis for my
future work in nanofabrication, and I enjoyed the experience. I was always impressed
with his sharp insight and wide breadth of knowledge, and I appreciated his feedback
throughout my graduate career. I would also like to give my thanks to the other students
in the Biomimetics and Dextrous Manipulation Lab, including Santhi Elayuperamal,
Matt Estrada, Alan Asbeck, Samson Phan, Dan Aukes, Daniel Soto, Aaron Parness, Noe
Esparza and many others, for their friendship and words of advice.
vii
I would like to thank Prof. Tom Kenny for his mentorship and encouragement.
My work with his group as part of the Episeal run was invaluable for my understanding
of MEMS processing and exploration of MEMS switches. I was also delighted to take
ME220 Introduction to Sensors while he taught it. I was extremely grateful to be
included in his group’s activities, both at Stanford University and farther away at various
conferences. I would like to acknowledge my friends and colleagues in the
Microstructures and Sensors Lab for their hard work and inclusiveness: Eldwin Ng, Vu
Hong, Tim English, Chae Ahn, Mandy Phillipine, David Christensen, Yushi Yang and
many others.
I would like to thank Prof. Philip Wong for his mentorship and encouragement
during my doctoral work. I enjoyed working with Prof. Wong and his group during our
collaboration under the DARPA NEM relay program. I was also fortunate to attend his
class EE320 Nanoelectronics, which helped to deepend my understanding of the field.
I would like to thank my colleagues in the Nanoelectronics Lab for their support,
including Soogine Chong, Ji Cao, and many others.
I am tremendously grateful for the support of the other members of the NEMS
relay research group. I would especially like to thank Dr. J Provine for his one-on-one
mentorship. From raquetball lessons to fabrication tips, I gleaned an immense amount
of information from our weekly meetings. I would also like to thank Scott Lee and
Chen Chen, my graduate student predecessors and mentors. By passing on their
knowledge and experience in the lab, they allowed me to jump straight into my own
viii
research and to start making real advancements immediately. I want to acknowledge
Kamran Shavezipur for his wonderful ideas, friendliness and mentorship. I was
impressed with his innovative thinking, and I enjoyed working with him to generate
new research topics. I enjoyed working with all of you. We made a great team.
I would also like to thank other members of the larger NEMS group, for the
many interesting conversations and technical support: Justin Snapp, Sharon Chou, Jose
Padovani, Igor Bargatin, Shane Crippen, Sam Emaminejad, Ford Rylander, Jae Lee,
Robert Hennessy, Chaitanya Gupta, Tao Wu, Hongyuan Yuan, Lina Qiu, Charmaine
Chia, and Miles Bennett. I would especially like to thank Chu-En Chang for his sage
advice, jokes, soda and granola bars.
Over the course of my research, I have had the honor of mentoring some students
and directing their research as part of my own. I would like to thank Nick Bousse for
being an extraordinarily focused worker with admirable drive, bottomless curiosity and
tremendous skill. I would also like to thank Kevin Wang for spending his evenings in
lab testing endless number of devices with patience and good humor. I would also
acknowledge Bernardo Espinosa for doing a great job as a summer research student.
My sincere gratitude goes to Will Clary for working so hard on the NEM relay project
and contributing so much.
During my time at Stanford, I have had the privelege of studying under a truly
amazing set of faculty. I have not only learned coursework, but I have also received
wonderful advice and mentorship, and I will be forever indebted to the Stanford faculty
ix
for going above and beyond to mentor me and develop my abilities. I would especially
like to thank Paul Mitiguy, Sherri Sheppard, Mehdi Asheghi, Subhasish Mitra and
Reggie Mitchell for their guidance and for being great role models.
I am extremely thankful for the help and support of the staff at the facilities that
I used to fabricate and characterize my devices. I would like to thank all of the staff at
the Stanford Nanofabrication Facility, especially Michelle Rincon, Maurice Stevens,
Nancy Latta, Elmer Enriquez, Cesar Chavez, Mike Dickey and many others. I would
like to thank the staff at the Stanford Nano Shared Facilities, including Richard Chin,
Chuck Hitzman, Bob Jones, Cliff Knollenberg and many others. I greatly appreciate
my interactions with all the staff at the Berkeley Marvell Nanolab, and I would
especially like to thank Jeffrey Clarkson, Sia Parsa, Peter Huang, Richelieu Hemphill,
Hamed Khoojinian and Bill Flounders for many great conversations and guidance over
wafers or coffee. I am indebted to the building maintenance staff for helping me to
maintain my test station, especially Kenny Green and Jose Solorzano. I would also like
to thank the skilled machinists at the Varian machine shop.
Over the course of my time here at Stanford, I have had the great fortune to meet
many wonderful students who have become friends and close colleagues. I would like
to especially thank Chelsey Simmons, Bonita Song, Greg Pitner, MinMin Hou, Daniel
Jacobs, Hai Nguyen, Andrew Carroll, and many others who have touched my life during
my time at Stanford University.
x
I would not have been able to finish my graduate studies without the support of
the Engineering Diversity Program, Dean Noe Lozano and Dean Osgood. The
engineering diversity program has supported me both financially and emotionally
throughout my graduate studies, starting my first year with funding for a teaching
assistantship and ending with a small research grant during my final months before
graduating. I could not have completed my degree without this program, and the
wonderful support of the staff at the student affairs office.
I have also been fortunate to receive two fellowships supporting my pursuit of
my doctoral degree. I received a graduate research fellowship from the National Science
Foundation and also the Ford Foundation. I am eternally grateful for the support that I
received from these two institutions. They were always willing work with me to meet
my needs, and I will always be thankful for these opportunities. I would also like to
thank DARPA and Honeywell for their generous support of my research.
I would like to give special thanks to the administrative staff that helped me to
manage accounts, set appointments, find information, order equipment, complete
applications and many other administrative tasks! You are the ones that keep the
university running smoothly! Special thanks to Ann Guerra and Deborah Michael for
their help and patience.
I have been incredibly lucky to collect a wonderful group of friends, who have
supported me inside and outside the lab. My friends have kept me sane and well-
rounded, and I am lucky to have so many great people around me. Special thanks goes
xi
to Andrew McKay, fellow adventurer and zombie preparedness expert. I would also
like to thank Cristina Munoz for the many wonderful adventures, delicious meals and
insightful conversation. I would also like to thank my friends from gymnastics, capoiera
and kiteboarding.
Extra special thanks goes to Mike Thielvoldt for his support throughout my
doctoral degree. I will always appreciate the late night food delivery to lab and last
minute technical help. Knowing him has made me a better person, kiteboarder, dirt
biker, cook, driver, drinker, thinker and engineer.
And finally, I am extremely thankful for the support and encouragement of my
family. I have always felt surrounded by love, and I continue to treasure the support of
my family. I would like to include a special thank you to my brother Bruce and my
parents, who were my first teachers and cheerleaders. Starting in kindergarten, my Mom
and Dad taught me the value of hard work and perseverence. They made sure I had
every opportunity to succeed, while also giving me the tremendous freedom to explore
New York City on my own and explore my interests. I know that I can always depend
on their love. I would not have been able to come so far without their hard work and
support, and therefore I would like to dedicate my dissertation to my mother and father,
Barbara and Peter Harrison.
xii
Table of Contents
Abstract .......................................................................................................................... iv
Acknowledgement ......................................................................................................... vi
List of Figures .............................................................................................................. xvi
Chapter 1: Introduction ................................................................................................... 1
1.1 NEM Relay Design and Characteristics ............................................................... 1
1.2 Electrostatic Relay Design ................................................................................... 3
1.2.1 Electrostatic Relay Device Physics ............................................................... 3
1.2.2 Vertical Actuation and Lateral Actuation ...................................................... 9
1.2.3 Laterally-Actuated, Multi-Terminal Device Design ................................... 11
1.2.4 Contact Behavior ......................................................................................... 14
1.3 Promising Applications for NEM Relays ........................................................... 16
1.3.1 Motivation for Integrated Systems .............................................................. 16
1.3.2 Logic and Computing .................................................................................. 20
1.3.3 Memory ....................................................................................................... 21
1.3.4 Signal Routing in FPGAs ............................................................................ 22
1.3.5 Charging and Energy Management ............................................................. 22
xiii
1.4 Thesis Outline ..................................................................................................... 23
Chapter 2: Low Temperature Fabrication of NEM Relays with Buried Interconnect . 25
2.1 Background ......................................................................................................... 25
2.2 Insulation Layer .................................................................................................. 30
2.3 Interconnect Etch ................................................................................................ 30
2.4 Aluminum Deposition and Planarization ........................................................... 31
2.5 Sacrificial Layer Deposition ............................................................................... 32
2.6 Via Etch .............................................................................................................. 34
2.7 Structural Layer Deposition ............................................................................... 36
2.8 Structural Layer Etch .......................................................................................... 37
2.9 Contact Layer Deposition ................................................................................... 38
2.10 Contact Layer and Barrier Layer Etch .............................................................. 39
2.11 Device Release ................................................................................................. 41
2.12 NEM Relays without Interconnect ................................................................... 42
2.13 Alumina Sacrificial Etch Stop .......................................................................... 43
2.14 Chapter Summary ............................................................................................. 45
Chapter 3: Device Characterization .............................................................................. 46
3.1 Test Set-Up ......................................................................................................... 46
3.1.1 Nitrogen Glovebox ...................................................................................... 47
xiv
3.1.2 Vacuum Station ........................................................................................... 48
3.2 Performance Metrics .......................................................................................... 49
3.2.1 Gate-Source Voltage (VGS) Sweep .............................................................. 51
3.2.2 Cycling Test ................................................................................................. 53
3.3 Overdrive Voltage (VOV) .................................................................................... 55
3.4 Contact Time (τC) ............................................................................................... 57
3.5 Drain-Source Voltage ......................................................................................... 58
3.6 Ambient .............................................................................................................. 60
3.6 Chapter Summary ............................................................................................... 61
Chapter 4: Device Design ............................................................................................. 63
4.1 Partitioned Beam for Increased Contact Force ................................................... 64
4.2 Hollow Tip .......................................................................................................... 66
4.3 Contact Material ................................................................................................. 69
4.3.1 Effect of Contact Material on VPI and VPO .................................................. 73
4.3.2 Thermal Modeling of Thin Film at Contact ................................................ 74
4.4 Three Terminal Device with Buried Interconnect .............................................. 85
4.5 Chapter Summary ............................................................................................... 88
Chapter 5: Conclusion .................................................................................................. 90
Appendix A: Fabrication of Poly-SiGe NEM Relays with Buried Interconnect ......... 94
xv
A.1 Buried Interconnect ........................................................................................... 94
A.2 Release Layer Deposition and Via Etch ............................................................ 96
A.3 Structural Layer Deposition and Etch ............................................................... 98
A.4 Contact Layer Deposition and Etch ................................................................. 100
A.4.1 Titanium nitride Deposition ...................................................................... 100
A.4.2 Ruthenium Deposition .............................................................................. 100
A.4.3 Contact Layer Etch ................................................................................... 100
A.5 Sacrificial Layer Etch and Release .................................................................. 102
A.5.1 Liquid HF Release .................................................................................... 102
A.5.2 Vapor-HF Release .................................................................................... 103
A.6 Polycrystalline Germanium Release Layer ..................................................... 103
A.7 Alumina Sacrificial Etch Stop ......................................................................... 104
Appendix B: Vacuum Probe Station Details .............................................................. 105
B.1 Physical Description ........................................................................................ 105
B.2 Electrical Measurements .................................................................................. 108
Bibliography ............................................................................................................... 109
xvi
List of Tables
3.1Relay performance requirements for integrated CMOS-NEM relay systems
according to application………………………………………………………………50
xvii
List of Figures
1.1 Diagram of a parallel plate electrostatic device......................................................4
1.2 Diagrams illustrating pull-in sequence of three terminal device.............................6
1.3 Diagrams illustrating secondary pull-in to gate .....................................................7
1.4 Diagrams illustrating pull-out sequence of three terminal device.............................8
1.5 Diagram of vertical versus lateral relay actuation................................................9
1.6 Diagram of relay designs with multiple terminals................................................13
1.7 IDS-VGS curves of a MOSFET and NEM Relay....................................................17
1.8 Power density versus technology node of CMOS transistor ..................................18
1.9 SEM image of fabricate device and IDS-VGS curve of similar device………………19
2.1 Top-down and Cross-sectional view after release………………………..……...25
2.2 Top-down and Cross-sectional view after insulation oxide deposition…………30
2.3 Top-down and Cross-sectional view after interconnect etch…………………….31
2.4 Top-down and Cross-sectional view after Al deposition and planarization……….32
2.5 Top-down and Cross-sectional view after sacrificial layer deposition……………33
2.6 Top-down and Cross-sectional view after via etch………………………………35
2.7 SEM image of cross-section of via etch………………………………………….35
2.8 Top-down and Cross-sectional view after barrier and structural layer deposition…36
2.9 Top-down and Cross-sectional view after structural layer etch…………………..37
2.10 SEM image of cross-section of structural etch………………………………….38
xviii
2.11 Top-down and Cross-sectional view after contact layer deposition……………39
2.12 Top-down and Cross-sectional view after contact layer etch……………………40
2.13 SEM image of sidewall after contact layer and XeF2 etch……………………40
2.15 Top-down and Cross-sectional view after release……………………………41
2.16 SEM image of cross-section of device with interconnect after release………….42
2.17 Top-down and Cross-sectional view of released device without interconnect…...43
2.18 SEM image of cross-section of device with alumina etch stop after release…….44
3.1 Images of nitrogen glovebox test-station………………………………………..47
3.2 Images of vacuum probe station test station………………………………………48
3.3 Diagrams of VGS sweep data and example of experimental data ………………..52
3.4 Diagram example of contact resistance versus cycle data………………………..54
3.5 Results of VGS sweep: minimum RCON versus cycle and VOV…………….……54
3.6 Results of cycling test with varying VOV………………………………………..55
3.7 Results of VGS sweep: VPI / VPO versus VOV…………………………………....56
3.8 Results of cycling test with varying contact time…………………………………57
3.9 Results of cycling test with varying VDS…………………………………………58
3.10 Results of cycling test with hot switching versus cold switching………………..59
3.11 Results of cycling test comparing nitrogen and vacuum ambient ……………...60
4.1 SEM and diagram of partitioned beam design……………..…………..……….64
4.2 Results of VGS sweeps of multiple partitioned beam devices with varying LS…...65
4.5 SEM image of contact region with close-up showing sidewall roughness………..66
4.6 SEM image of device after hollow tip etch……………………………………...67
xix
4.7 Results of cycling tests comparing devices with and without hollow tip etch……68
4.8 SEM image showing devices with hollow tip etch after different etch times……..69
4.9 Results of cycling tests comparing devices with TiN, Ru and no contact layer…..70
4.10 Results of Auger analysis comparing oxide levels inside and near contact area…71
4.11 Results of cycling data with 900,000 cycles under 100MΩ…………………….72
4.12 Results of VGS sweep showing VPI/VPO for devices with TiN and Ru contact….73
4.13 Diagram of relay with contacting asperities illustrating contact temperatures…..75
4.14 Diagram of thermal model of joule heating in relay with thin film………………77
4.15 Simulated results of thermal model: welding voltage and power versus contact
resistance ………………………………………………….……………………….80
4.16 Results of VGS sweep before and after welding………………………………….81
4.17 Resulting contact resistance during weld and unweld cycles for a single device…82
4.18 Resulting welding power versus contact resistance for devices with varying
stiffnesses……..………………………………………………………………………84
4.19 Layout of a three-terminal device with interconnect…………………………....85
4.20 Results of multiple VGS sweep for a single device with interconnect and SiN
etchstop………………………………………………………………….……………86
4.21 Results of cycling test of device with interconnect compared to 12 devices without
interconnect and SiN etch stop………………………………………………………..87
4.22 Results of multiple VGS sweeps of single device with interconnect and alumina etch
stop ………………………….……………………………………………………..88
B.1 Image of open door of vacuum probe station…………………………………….106
xx
B.2 Layout of probe tips of 50-pin probe card………………………………………106
B.3 Image of vacuum probe station…………………………………………………..107
Chapter 1: Introduction ········································································ 1
Chapter 1: Introduction
Nanoelectromechanical (NEM) relays and hybrid CMOS-NEM relay designs are a topic
of growing interest for circuit design because NEM relays are not constrained by the
same physical limitations as CMOS devices. NEM relays offer advantages such as zero
off-state current leakage and high on-off current ratio. However, performance and size
limitations prevent the complete replacement of CMOS devices by NEM relays.
Therefore, hybrid CMOS-NEM relay systems prove optimal for performance, size and
energy usage in many applications. We present some applications that are especially
noteworthy. We also present some of the challenges associated with CMOS-compatible
NEM relay fabrication and design. The solutions to these issues are essential for
lowering the cost and complexity of manufacture and enabling hybrid-system designs.
1.1 NEM Relay Design and Characteristics
A relay is defined as a switch that opens and closes a circuit due to an electrical
input while maintaining isolation between the drive and the load circuits.
Electromechanical relays are characterized by physical actuation of a moving member
to open and close the load circuit due to an electrical signal in the drive circuit. Methods
of actuation in electromechanical relays include electromagnetic, piezoelectric, thermal,
and electrostatic.
Chapter 1: Introduction ········································································ 2
The first electromechanical relay was invented by either Edward Davy or
Joseph Henry in the mid-1830’s, and contributed directly to the invention of the first
telegraphs[1],[2]. Those early relays were electromagnetic: current passing through a
coil causes a magnetic needle to move until it physically contacts a droplet of liquid
mercury. Since then, advancements in design, materials and fabrication technology
have led to magnetic micro-relay technology. The microfabrication of a fully integrated
magnetically actuated relay has been previously demonstrated.[3] While
electromagnetic microrelays can offer current control of a load circuit, which may be
advantageous for some designs, it nevertheless requires complex process flows and
large footprint to accommodate the drive coils. Furthermore, switching speeds tend to
be very slow due to inductive damping.
Piezoelectric relays take advantage of the piezoelectric effect which, in some
materials, leads to deformation in the presence of an electric field. Piezeoelectric relays
are capable of achieving high contact forces, fast switching and large displacements.
They are capable of bi-directional deflection depending on the direction of the electric
field. Actuation speeds as low as 200ns have been achieved, and actuation voltages that
are “nearly 0V” can be achieved through body biasing.[4] However, piezoelectric
systems require processing with piezoelectric materials such as PZT or AlN, which can
present manufacturing challenges.
Thermal relays use heat-induced expansion of a material to cause mechanical
movement which leads to physical contact between electrodes. Thermal relays can
Chapter 1: Introduction ········································································ 3
achieve larger displacements than allowed by other actuation methods while
maintaining high contact force, and fabrication can be very simple since conventional
materials can be used.[5] However, thermally actuated relays are difficult to adopt for
computing applications because of the high electrical power needed to actuate the
devices, large footprint which is difficult to scale down easily and slow switching speed.
Electrostatic relays transform an electrical signal into physical motion by
placing a bias across two electrodes, of which at least one must be compliant, and thus
creating an attractive force between the electrodes that causes them to close an electrical
contact. Compared to electromechanical relays that use other actuation mechanisms,
electrostatic relays can offer low actuation power, fast switching speeds, hysteresis and
good scaling behavior [4]. Furthermore, electrostatic relays can be fabricated using a
wide variety of materials (semiconductor, metal, or polymer) for both the structural and
contact layers, allowing for great flexibility in processing techniques. For these reasons,
we have chosen to focus on advancing CMOS-compatible processing technologies for
electrostatic nanoelectromechanical (NEM) relays.
1.2 Electrostatic Relay Design
1.2.1 Electrostatic Relay Device Physics
The attractive electrostatic force between two conductive plates depends on the
dielectric constant of the fluid between the plates, the area of the plates, the distance
Chapter 1: Introduction ········································································ 4
between the plates and the voltage bias between the plates. When modelled as parallel
plates (one stationary and the other mounted on a spring), we can express the
electrostatic force Fe between the plates as:
Fe=εAV2
2d2 (1.1)
where the physical constants are area A, separation distance d, and a fluid with dielectric
constant Ɛ, as shown in Figure 1.1. The electrostatic force is always attractive, and is
opposed by the restorative spring force of the moveable structure. As the electrostatic
force increases, the plates move closer together. Eventually, the electrostatic force will
be greater than any possible spring force, causing an instability in the force balance and
allowing the plates to snap together suddenly. This sudden contact between the plates
is called the “pull-in”, and occurs when the distance between the plates approaches 1/3
Figure 1.1: Diagram of a parallel-plate electrostatic device.
Chapter 1: Introduction ········································································ 5
of the initial distance d0. Given a spring constant K, the pull-in voltage for the parallel
plate system, the pull-in voltage Vpi can be expressed as:
𝑉𝑝𝑖 = √8 𝐾𝑑03
27𝜀𝐴. (1.2)
Relays with more than two terminals can be designed to pull-in before reaching the
instability point (i.e. – a separate contact electrode can be placed less than d0/3 from the
moveable electrode). Regardless, equation 1.2 illustrates the requirements for low-
voltage actuation: low spring constant K, small gap width d0, large dielectric constant
Ɛ, and large actuation area A.
A three terminal relay, represented by the device shown in Figure 1.2, illustrates
the basic operation of an electrostatic switch. The three terminal relay is comprised of
three electrodes that are electrically isolated initially: a source (beam), a gate and a drain.
The drive voltage is represented by the gate-source voltage (VGS) and the load signal is
represented as the current across the drain-source contact (IDS). The amount of current
across the contact is determined both by physical and chemical characteristics of the
contact between the drain and beam, and by a voltage bias across the contact (VDS).
The pull-in behavior of the beam can be observed by measuring the change in
IDS as VGS gradually increases from 0V to above the pull-in threshold voltage VPI. When
the voltage bias between the gate and the source is zero (VGS = 0), the beam is in the
neutral position, no contact is made between the beam and drain and no current flows
(IDS = 0), as shown in Figure 1.2A. As the VGS increases, the beam deflects farther
Chapter 1: Introduction ········································································ 6
toward the gate. Since no physical contact exists between the beam and drain, as shown
in Figure 1.2B, the drain-source current remains zero. The gate-source voltage
continues to increase until it reaches the pull-in voltage VPI, at which point the
electrostatic force on the beam surpasses the restoring spring force, creating an unstable
Figure 1.2: Diagrams illustrating the pull-in sequence of a three terminal electrostatic
relay: (A) The beam is in the neutral position (VGS = 0), (B) The beam deflects toward
the gate as the gate-source voltage increases (0< VGS <VPI), (C) As the gate-source
voltage surpasses the pull-in threshold VPI, the beam snaps to the drain and current
passes across the contact (VGS > VPI).
Chapter 1: Introduction ········································································ 7
aggregate force that causes the beam to snap into the drain. Once contact between the
beam and drain is made, a sharp increase in current is observed between the source and
drain electrodes as illustrated in Figure 1.2C. The pressure at the contact grows as the
gate-source voltage rises past VPI, thus increasing the real contact area and reducing the
contact resistance, leading to higher current.
As the gate-source voltage continues to increase, the center of the beam will
deflect toward the gate until it eventually makes physical contact with the gate, as shown
in Figure 1.3. The contact between the beam and gate is known as the “secondary pull-
in”, and usually leads to catastrophic failure of the device due to the high voltage bias
between the beam and the gate. The risk of secondary pull-in can be minimized with
thoughtful relay design, for example by stiffening the beam.[6],[7]
After the beam has experienced pull-in to the drain, we can observe the pull-out
behavior by gradually reducing the source-gate voltage VGS back to 0V. As the source-
gate voltage decreases, the pressure on the contact diminishes due to the reduced
Figure 1.3: Diagrams illustrating the secondary pull-in of the beam to the gate
after contact with the drain.
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electrostatic force and the restorative spring force of the compliant beam member. As
the contact pressure decreases, the contact resistance increases and IDS decreases.
However, the beam-drain contact will remain intact, even after the gate-source voltage
decreases past VPI.as shown in Figure 1.4A. The current will continue to decrease as
the gate-source voltage decreases until the restorative spring force causes the beam to
disconnect suddenly from the drain. This abrupt separation of the beam and drain is
called the “pull-off” and occurs at the pull-off voltage VPO, as shown in Figure 1.4B.
Figure 1.4: Diagrams illustrating the pull-out sequence of a three terminal
device. (A) The beam remains in contact with the drain as VGS decreases (VGS
> VPO). (B) The beam suddenly snaps away from the drain, causing an abrupt
cutoff in current across the contact (0 < VGS < VPO).
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The value of VPO depends not only on the beam stiffness and electrode positions, but
also on surface forces such as van der Waals, Casimir or capillary forces. These surface
forces are difficult to model, thus making accurate prediction of VPO nearly impossible.
The difference between VPI and VPO is called the “hysteresis window”. It is
worth noting that even in the absence of surface forces, the relay will exhibit a hysteresis
window. This hysteresis window is a unique advantage of relay technology, and can be
used for low-energy programming and memory applications, as discussed in section 1.3.
1.2.2 Vertical Actuation and Lateral Actuation
The design of electrostatic actuators can take two forms: vertically-actuated and
laterally-actuated. As shown in Figure 1.5, a vertically-actuated relay moves out of the
plane of the wafer surface, and a laterally-actuated relay moves in the plane of the wafer
Figure 1.5: Diagrams showing vertically-actuated and laterally-actuated three-
terminal electrostatic relays. Vertically-actuated relays move normal to the wafer
surface, and laterally-actuated relays move within the wafer plane.
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surface. The chosen form for the relays presented in this work is lateral actuation,
although it is useful to discuss the advantages and disadvantages of this choice.
Vertically-actuated relay design is attractive because it offers versatility in
fabrication and material selection. A wide range of materials and deposition techniques
can be used to create the structural layers and contact surfaces, thus allowing good
control of contact roughness and composition. Furthermore, since the drain electrode
and beam are deposited at separate stages of the fabrication process, different materials
can be deposited on either side of the contact. The sacrificial layer is deposited directly
between the beam and other electrodes, allowing direct control of the actuation gap size
through the sacrificial layer thickness. By using extremely thin sacrificial layers, very
small gap sizes (and thus low actuation voltages) can be achieved. There are several
disadvantages of vertically actuated designs. Separate photomasks for the beam and
actuation/contact electrodes are required, which increases cost and fabrication
complexity. The contact material must survive subsequent processing steps, thus
limiting choices of contact material. Another disadvantage is that the actuation and
contact areas scale with the overall footprint, leading to poor performance at smaller
sizes and limitations on device density. Notable vertically-actuated relay designs
include torsional (see-saw) actuation[8] and four-terminal relay.[9]
An advantage of laterally-actuated relay design is the decoupling of actuation
and contact area from footprint, since the actuation and contact areas depend on the
height of the structure instead of the width. Therefore, scaling of lateral relays is more
Chapter 1: Introduction ······································································ 11
attractive than that of vertical relays. Also, the relay structure can be defined in a single
lithography step, eliminating the need for multiple lithography masks and alignment of
critical features. Laterally-actuated relays also allow more complex electrode
configurations, such as symmetric two, three or four terminal devices (see section 1.2.3).
Disadvantages of lateral actuation design include high beam stiffness and large gap
widths, both of which are limited by lithography resolution and place an upper limit on
contact force. However, this limitation can be overcome by adding a “thinning” process
for either the sacrificial layer[10] or structural layer.[11] Because the contact area is
located in the trenches between the beam and drain electrode, contact materials can only
be added to the contact surface using very conformal techniques such as atomic layer
deposition (ALD), which limits the choice of contact material. Furthermore, achieving
very smooth, vertical surfaces on the trench sidewalls can be very difficult due to
footing, re-deposition of material on the sidewalls and limited etch selectivity between
the mask and structural materials. Noteworthy laterally-actuated NEM relay designs
include curved beams[12], partitioned beams[13], comb-drive actuation[14], and
energy-recoverable actuation symmetry.[15]
1.2.3 Laterally-Actuated, Multi-Terminal Device Design
Because the position and shape of the beam and electrodes are determined
lithographically in laterally actuated relays, many designs are possible for various
numbers of electrodes. We will discuss some of the more popular designs here.
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It is possible to design a two-terminal electrostatic switch in which the actuation
and load pathways are the same, such as the design shown in Figure 1.6A.[16] In this
design, the voltage bias between the gate/drain and source electrodes causes the
compliant beam to deflect toward the gate/drain until the beam makes contact with the
gate/drain. This two-terminal design, and its symmetric version shown in Figure 1.6B,
would be simple to manufacture but would not meet the criteria for many relay
applications, since the actuation and drive circuits are not isolated. A two-terminal
switch would be more akin to a diode in behavior than a switch. Furthermore, the
voltages needed to actuate a relay are usually significantly higher than the optimal
voltage bias across the contact. Therefore, a two-terminal relay would be susceptible to
high currents across the contact, leading to accelerated degradation and welding. To
achieve isolation of the actuation and drive pathways, the design of an electrostatic relay
must include three or more terminals.
A three-terminal relay, as described previously in section 1.2.1, is comprised of
three electrically isolated elements: the source, the gate and the drain. A typical layout
for a three terminal device is shown in Figure 1.6C. In a three terminal design, a voltage
bias between the source and gate causes the beam to deflect toward the gate until the
beam makes contact with the drain. Its corresponding symmetric design, shown in
Chapter 1: Introduction ······································································ 13
Figure 1.6D, allows a single beam to make contact with either of two drain electrodes
under the influence of two corresponding gate electrodes.[17]
Designs that incorporate more than three electrodes have the added advantage
of completely separating the drive and load circuits. The six-terminal relay shown in
Figure 1.6E illustrates the actuation of the gate (beam) by the body electrodes, which
causes an electrically isolated portion of the beam to make contact simultaneously with
the drain and source electrodes.[18] In practice, designing the beam to make contact
with two rigid electrodes simultaneously is very difficult. Slight asymmetries in the
Figure 1.6: Diagram of electrostatic relays with various number of terminals: (A)
two-terminal relay, (B) .symmetric two-terminal relay, (C) three-terminal relay,
(D) symmetric three terminal relay, (e) six terminal relay (ie – symmetric four-
terminal relay) with rigid drain, (F) six terminal relay with compliant drain.
Chapter 1: Introduction ······································································ 14
electrode placement or beam shape may cause the beam to make contact with one
electrode before the other, thus requiring very high actuation voltages to contact the
second electrode or completely preventing contact altogether. To avoid this, we have
proposed an alternative design with a flexible drain electrode, as shown in Figure
1.6F.[19]
1.2.4 Contact Behavior
Arguably, the most daunting obstacle to good relay performance is instability of
contact behavior. Because the physical shape and chemical composition of the contact
transform throughout the lifetime of the device, the contact behavior is always changing.
In some cases, the contact begins to “age” immediately after fabrication. The change in
contact behavior includes shifts in contact resistance, pull-in voltage, pull-out voltages,
hysteresis window, and welding. Many factors, both chemical and physical, contribute
to the transformation of the contact.
Chemical reactions between surface and ambient can lead to compositional
changes of the material at the contact surface. For example, the build-up of a non-
conductive oxide at the surface of the deposited material can lead to lower contact
resistances. This effect can be mitigated by encapsulating the devices in an inert
environment, coating the contact with inert materials, using high contact voltage bias to
electrically break down the oxide or using contact coatings that have conductive oxides.
Chapter 1: Introduction ······································································ 15
Absorption of water onto the surface of the contact can lead to capillary forces
at the contact interface, causing changes in both actuation voltages and contact
resistances. Absorption of water can be prevented through encapsulation in a clean, dry
environment, and may be reversed by baking the device in a clean, dry vacuum
environment at high temperatures (>300˚C).
Mechanical wear at the interface can cause the contact profile to change
dramatically from cycle to cycle. Nano-scale relays are especially susceptible because
the contact area is comprised of only a few contacting asperities, leading to extremely
high localized pressures. The mechanical wear may improve the relay performance by
flattening the asperities and increasing the overall contact area. However, the relay
behavior may deteriorate over time due to the collection of debris or the removal of
contact material.
Build up of tribopolymer - a non-conductive deposit created through
polymerization of adsorbed carbon under mechanical pressure - has been shown to cause
increased contact resistance. Tribopolymers have been detected even in high vacuum
testing ambients, although the rate of polymer build-up is much slower in vacuum than
in uncontrolled ambients for some materials. The presence of this carbon film can lead
high and unstable contact resistance in nano-scale relays due to localized build-up and
break-down of the polymer film.[20]
The testing ambient is an important factor that affects contact lifetime and
behavior. Tribopolymers have been detected even in high vacuum testing ambients,
Chapter 1: Introduction ······································································ 16
although the rate of polymer build-up is much slower in vacuum than in uncontrolled
ambients. The ambient can also accelerate or retard the growth of oxides.
Transfer of material has been shown to occur in the direction of electrical
polarity across the contact.[21] For contacts with thin film coatings, this could lead to
localized removal of the contact material from one side of the interface.
Joule heating due to the high current across the contact interface can lead to
softening and melting of the contact material, resulting in a constantly shifting contact
profile or permanent welding. Welding of the contact can be catastrophic, preventing
pull-out of the beam, but can also result in a low-resistance latching design if welding
can be controlled and reversed.[22] Joule heating can be used to improve the contact
behavior by burning away contaminants and evaporating adsorbed water.
1.3 Promising Applications for NEM Relays
1.3.1 Motivation for Integrated Systems
The behavior of a CMOS transistor is often evaluated using two metrics: off-
state drain-source current (IOFF) and subthreshold slope (STH). Representative drawings
of the IDS-VGS curves for a MOSFET and an electrostatic relay are shown in Figure 1.7,
and illustrate the physical meanings behind IOFF and STH.[23] The value of IOFF indicates
the leakage current between the source and drain in the absence of a gate-source signal.
Ideally, IDS is zero because any leakage current wastes power through the device. This
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power loss is especially troublesome in battery-powered systems because of the finite
amount of power available. Solid-state transistors feature a finite off-current which
increases as the device scales to smaller sizes, leading to higher power consumption in
the off-state. The correlation between power leakage and size in CMOS devices is
illustrated in Figure 1.8.[24] The graph shows that as CMOS devices scale with lower
technology nodes, the subthreshold leakage (i.e. – off-state current) and power loss
through the gate increase. In contrast, IOFF of an electrostatic relay is limited to zero
because there is no physical current pathway between the source and drain in the off-
state, and electrostatic relays should not pass current through the gate electrode in any
Figure 1.7: Image of IDS-VGS curve of a MOSFET (left) and electrostatic relay
(right). An image of a 3-D tri-gate MOSFET is shown as an example of a
device with the IDS-VGS curve shown on the left. (Tri-gate transistor image
adapted from [23])
Chapter 1: Introduction ······································································ 18
state. Furthermore, unlike CMOS devices, IOFF and gate current remain zero as the relay
scales to very small sizes. The lower limit of this scaling model is determined by the
breakdown voltage of the ambient material.
The second important metric, the subthreshold slope, describes the strength of
the transistor response to an input (i.e. – the change in IDS for a given change in VGS).
The subthreshold slope is defined as the inverse of the slope of the subthreshold region
of the IDS-VGS curve. Ideally, this subthreshold slope would be near zero. However,
physical limitations prevent the subthreshold slope of a MOSFET from falling below
60 mV/dec, and scaling to smaller gate channel length leads to even higher subthreshold
slopes. Lower subthreshold slope near 57 mV/dec has been achieved using tunnel-FET
Figure 1.8: Power density versus technology node of a CMOS transistor due
to gate leakage, sub-threshold leakage (i.e. – off-state power loss) and active
power usage.(reprinted from [24] © IET 2009)
Chapter 1: Introduction ······································································ 19
designs[25], however the ratio of on-current to IOFF is too low to make the tunnel-FET
a true alternative. In contrast, an electrostatic relay has near-zero subthreshold slope
because of the sudden formation of the contact when the beam snaps to the drain.
Furthermore, this subthreshold slope will remain near zero as the device scales to
smaller sizes, potentially until the size the drain-source gap allows arcing between the
electrodes.
Fabricated relays exhibit zero off-current and near-zero subthreshold slope,
identical to the representative curve in Figure 1.7. An SEM image of a real three-
terminal device and the results of an IDS-VGS curve of that device are shown in Figure
1.9. The relay is fabricated using the process flow presented in Chapter 2 and tested in
a nitrogen glovebox as described in section 3.1.1 of this work. The data presented in
Figure 1.9 features IOFF below the 200pA noise floor of the measurement system and
subthreshold slope lower than the 5 mV/dec, resolution of the measurement system.
Figure 1.9: SEM image of a fabricated three-terminal device (left) and the
resulting IDS-VGS curve of a similar device (right). The fabrication and testing
of the device are described in chapters 2, 3 and 4.
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The zero off-current, near-zero subthreshold slope and VPI/VPO hysteresis
exhibited by electrostatic relays make them attractive components for low-power
systems. However, many obstacles prevent the wider adoption of NEM relays in
industry. As discussed in section 1.2.4, the electrical and mechanical behavior of the
electrostatic relay are unstable due to degradation of the contact. Although relay
performance and lifetime can be improved with encapsulation technology, contact
resistance of nano-scale relays tends to be higher than CMOS on-resistance values
because of the small contact area. Furthermore, slow switching speed makes relays
unattractive for high-speed processing. However, in certain applications, thoughtful
integration of NEM relays and CMOS technology can yield a hybrid system with better
energy efficiency than a CMOS-only design while maintaining good performance.
Additionally, monolithic fabrication of NEM relays and CMOS devices can yield a
smaller overall footprint. In the following sub-sections, we will explore some
applications that are especially attractive for integrated CMOS-NEM relay design.
1.3.2 Logic and Computing
The first programmable, fully automated digital computer ever built has been
attributed to Konrad Zuse, the inventor of the Z3. Built in 1941, it was composed of
entirely of electromagnetic relays. It could perform floating point arithmetic, and was
used to perform statistical analyses of airplane wing behavior.[26] Relay technology
has advanced considerably since then, becoming smaller, more durable and more
efficient than the early relay designs. Prior work has shown that a compact 2-to-1
Chapter 1: Introduction ······································································ 21
multiplexer can be implemented using a single six-terminal relay (as illustrated in Figure
1.6E), and then any combinational logic function can be implemented with the
multiplexer. The use of these six-terminal relay designs can result in smaller footprint
and lower energy usage compared to implementations using four-terminal relays.[27]
Also, relays allow implementation of designs that cannot be realized with CMOS
devices. For example, relays can be used to implement single-stage inverting and non-
inverting logic gates without a performance penalty.[28] Various designs have been
shown to yield better energy-performance with the replacement of CMOS circuits by
relay-based circuits with the same functionality.[29]
1.3.3 Memory
Non-volatile memory (NVM) is an attractive technology for low-power
applications because it does not require a constant energy source. Many forms of NVM
have been developed, and performance metrics include retention time, speed and energy
consumption. Some designs have already incorporated mechanical relays. An
integrated NVM which uses an electrostatic MEM relay to charge the floating gate of a
carbon nanotube based FET has demonstrated faster operation speed and lower power
consumption than conventional flash memory.[30] In another work, a model of an
alternative SRAM cell design is proposed wherein a NEM relay replaces two transistors
in a conventional six transistor SRAM cell, leading to improvements in hold and read
static noise margins, reduction in static power dissipation and decreases in write and
read delays.[31]
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1.3.4 Signal Routing in FPGAs
Field programmable gate arrays (FPGA) are a popular digital integrated circuit
design platform because they can be reprogrammed after fabrication, producing a more
flexible design than application specific ICs (ASIC). However, FPGAs are slower,
larger and consume more power than ASICs. The poor energy-performance seen in
FPGAs is largely due to the large routing arrays that enable the desired design
flexibility. Detailed simulations have shown that the replacement of CMOS routing
cells with NEM relay based routing cells can lead to smaller footprint, lower off-state
leakage power and delay reduction.[32]
1.3.5 Charging and Energy Management
Battery-powered systems must carefully manage energy usage. Off-state power
leakage in CMOS devices lead to unnecessary waste of stored energy. Because NEM
relays feature zero IOFF, they can be used to connect or completely disconnect CMOS
devices and other subsystems from a battery during standby conditions. One instance
of such an application is Given Imaging’s Pillcam, an ingestible camera that allows less
invasive imaging of the gastrointestinal tract. Because of the limited battery life, the
pill includes a magnetic reed relay which allows it to be turned on directly before or
during use.[33] Another candidate for NEM relay integration is charge-biased
actuation. Integrated systems that require high voltages for some devices often generate
these voltages using a charge pump, which drains power. Instead of a charge pump, a
Chapter 1: Introduction ······································································ 23
floating charge can be used to bias an actuation electrode. Charge retention is often
difficult because of parasitic resistances, therefore a relay can be used to momentarily
charge a floating electrode which is otherwise electrically isolated.[34]
1.4 Thesis Outline
Many challenges must be overcome before CMOS-NEM relay designs can
become more feasible for wider use. In the following chapters, I will present novel
developments in NEM relay modeling, fabrication and design that have the potential to
accelerate wider adoption of this promising technology.
In chapter 2, we will discuss CMOS-compatible fabrication of NEM relays with
buried aluminum interconnect layers. This processing technology allows monolithic
fabrication of CMOS and NEM relay devices in order to meet cost, size and
performance expectations, and will address thermal budget and chemical compatibility
issues that have not been addressed in prior work. The NEM relays presented in this
work include a buried aluminum interconnect layer, silicon nitride and alumina release
etchstop layers to protect the buried aluminum, and a polysilicon germanium structural
layer deposited at 425˚C.
In chapter 3, we will discuss device performance using several metrics including
actuation voltage, lifetime contact resistance, hysteresis and contact voltage bias. We
will discuss some of the applications on which these metrics are based, and best
Chapter 1: Introduction ······································································ 24
practices for testing relay performance in terms of these metrics. We then present data
from fabricated devices concerning each set of performance criteria.
In chapter 4, we will discuss innovative relay designs to improve the device
performance according to the metrics discussed in chapter 3. These design
improvements include selective stiffening of the relay beam to improve maximum
contact force, selective etching of the contact area to improve contact area and careful
selection of contact materials. Thermal modeling of the contact behavior is also
presented which can reduce contact degradation and enable new relay applications.
Finally, chapter 5 will include final thoughts on the performance of the relays
presented in this work. The performance of these relays are compared the performance
seen in prior work. This chapter also includes an analysis of the technical contributions
made by the work presented in this thesis, as well as suggestions for future work and
improvements.
Details of the relay processing test apparatus are presented in the chapters 2 and
3.
Chapter 2: NEM Relay Fabrication ························································ 25
Chapter 2: Low Temperature
Fabrication of NEM Relays
with Buried Interconnect
In this chapter, we will discuss low-temperature fabrication of nanoelectromechanical
relays with aluminum interconnect. Although these devices do not include underlying
CMOS structures, the inclusion of the interconnect layer is essential to show a CMOS
compatible process. A top view and cross-section view of a completed device is shown
in Figure 2.1.
2.1 Background
Figure 2.1: (Left) Top down view and (Right) cross-sectional view of representative
three terminal device with buried interconnect fully fabricated and released.
Chapter 2: NEM Relay Fabrication ························································ 26
Monolithic fabrication of hybrid CMOS-NEM relay systems offer many
advantages over processes that require separate CMOS and NEM relay processing.
These advantages include: smaller footprint, lower fabrication cost, and smaller
parasitic capacitances and resistances. However, NEM relay design must meet many
requirements to prevent damage to CMOS and interconnect structures during
processing, including:
NEM Relay fabrication thermal budget must remain below 450˚C.[35] This
processing temperature limitation is determined primarily by dopant migration
in the CMOS layers and increasing sheet resistance in the interconnect
materials.
Due to the thermal budget limitation, the NEM relay structural material must
feature low residual stress in the absence of a high-temperature anneal step and
low electrical resistivity in the absence of a high-temperature dopant activation
step.
Underlying CMOS, interconnect and interlayer dielectric materials must be
protected from chemical damage during NEM relay processing. The process
flow must prevent protect underlying devices from chemical damage.
For CMOS-driven devices, actuation voltages are limited to 5V or less.
These requirements impose limitations on the NEM relay structural and sacrificial layer
materials. Prior work has shown low temperature deposition of various relay structural
Chapter 2: NEM Relay Fabrication ························································ 27
materials including silicon[36], polycrystalline silicon germanium [[37],[38]]
amorphous silicon carbide[39], ruthenium[40], tungsten[41], and platinum[42].
Along with the constraints imposed by the requirements of post-CMOS
processing, NEM relay behavior must meet high performance standards. Although the
performance requirements vary by application, desired performance metrics for all
relays include:
Low contact resistance (<10 kΩ for logic applications)[43]
Low mechanical wear and chemical corrosion at the contact
Prevention of contact welding
Long cycle lifetime
To meet both the constraints of fabrication and performance, many designs use separate
structural and contact materials. Investigated contact materials include tungsten[44],
ruthenium[45], titanium nitride[46] and platinum[47].
Monolithic fabrication of MEMS and CMOS devices is a popular focus of
research. Monolithic fabrication involves combining the manufacture of all mechanical
and electrical components of an integrated system onto one substrate with a single
process flow. The advantages of such an integrated fabrication process include:
Better performance due to minimized parasitics from MEMS-CMOS
interconnections
Chapter 2: NEM Relay Fabrication ························································ 28
The elimination of one substrate in the MEMS-CMOS system leads to lower
cost
Smaller footprint
Monolithic integration can be achieved in one of three ways:
1) front-end-of-line (FEOL) MEMS processing: MEMS devices are fabricated first,
followed by CMOS devices.[48] This allows flexibility of MEMS processing but
requires unconventional CMOS processing techniques, making adaptation of
existing CMOS systems difficult or impossible.
2) back-end-of-line (BEOL) MEMS processing: CMOS devices are fabricated first,
followed by MEMS devices. This technique allows fabrication of CMOS devices
using conventional processing techniques, but limits the thermal budget for
processing of MEMS devices.
3) Combined MEMS and CMOS processing, whereby both types of devices are
fabricated at the same time. This method limits the materials, geometry and
processing techniques of both the CMOS and NEM relay devices. Furthermore,
side-by-side processing precludes the space-saving and performance advantages
of CMOS-NEM relay integration.
Given the existing limitations on CMOS processing and the great flexibility of
electrostatic relay design, it makes sense to preserve existing fabrication methods for
CMOS structures and adapt MEMS structures to be fabricated using BEOL-compatible
processing.
Chapter 2: NEM Relay Fabrication ························································ 29
Prior research has shown great promise in developing BEOL-compatible
processing methods for MEMS. Lund et al. have demonstrated fabrication of
encapsulated RF MEMS devices over metal interconnect layers.[49] Franke et al. have
developed poly-SiGe resonators with underlying CMOS structures and aluminum
interconnect, with an additional amorphous silicon passivation layer or polycrystalline
germanium release layer for protection of underlying layers.[50] Ruiz et al. have
developed piezoresistive pressure sensors made of polysilicon germanium which have
been successfully manufactured on CMOS devices in a monolithic fabrication
process.[51] Witvrouw et al. have demonstrated an encapsulated MEMS gyroscope on
top of CMOS amplifier and buffer circuits.[52] Digital RF MEMS capacitors have
been fabricated monolithically with an integrated CMOS charge pump by WiSpry and
IBM.[53]An electrostatically-actuated plate has been successfully fabricated using a
sputtered silicon process on top of a CMOS capacitance measurement circuit.[54] Of
the most interest to the current work, platinum NEM relays driven directly by CMOS
driver circuits have been previously demonstrated by Chong et al.(2001).[55]
In this chapter, we describe a novel fabrication process for laterally-actuated,
electrostatic poly-SiGe NEM relays with silicon oxide release layer and an aluminum
interconnect layer which is protected during the release etch by a PECVD SiN layer.
All fabrication steps occur below 425˚C, and are compatible with standard CMOS
process techniques. Further fabrication details are available in Appendix A.
Chapter 2: NEM Relay Fabrication ························································ 30
2.2 Insulation Layer
After cleaning the silicon substrate using a standard RCA clean, we deposit a 2
μm thick LPCVD silicon oxide layer. This layer will insulate the fabricated structures
from the silicon substrate, and will also form the mold for the interconnect pattern. A
diagram of the deposited silicon oxide insulation layer is shown in Figure 2.2.
2.3 Interconnect Etch
We use a damascene process to form the interconnect layer. This requires
etching the pattern of the interconnect layer into an insulating material, then filling the
trenches with a conductive material (in this case, aluminum) and polishing down to the
top of the channels.
Figure 2.2: (Left) Top down view and (Right) cross-sectional view of sample
after insulation oxide deposition.
Chapter 2: NEM Relay Fabrication ························································ 31
We use standard lithography processes to etch the interconnect pattern into the
insulation layer. We first create a resist mask using standard lithography procedures,
then transfer the pattern to the silicon oxide using a timed RIE process. The target etch
depth is 1μm.
After clearing the resist, we deposit a PECVD silicon nitride (SiN) layer, which
will provide an etch stop during a subsequent planarization step. A diagram of the
interconnect trenches with silicon nitride planarization stop is shown in Figure 2.3.
2.4 Aluminum Deposition and Planarization
The aluminum for the interconnect is deposited using a sputter recipe. After
deposition, we polish the aluminum to the top of the trench using a chemical mechanical
polishing system. It is important for subsequent processing steps that the surface
Figure 2.3: (Left) Top down view and (Right) cross-sectional view of
representative three terminal device with interconnect trenches etched in the
insulation oxide and coated in silicon nitride.
Chapter 2: NEM Relay Fabrication ························································ 32
remains smooth and flat. A diagram of the aluminum interconnects after the
planarization step is shown in Figure 2.4.
After thoroughly cleaning the slurry from the wafers, we encase the aluminum
in 1μm PECVD silicon oxide. This layer protects the aluminum during subsequent
processing steps, and electrically isolates the aluminum from upper structures.
2.5 Sacrificial Layer Deposition
For NEM relays with buried interconnect, the sacrificial layer serves four
purposes: 1) it electrically isolates the devices from the substrate and underlying
structures, 2) in areas where the sacrificial layer underneath an electrode has not been
removed during the release process, it anchors the structural elements, 3) it acts as a
sacrificial layer which supports delicate sections of the device until it is removed during
Figure 2.4: (Left) Top down view and (Right) cross-sectional view of
representative three terminal device after deposition and planarization of the
aluminum interconnect layer.
Chapter 2: NEM Relay Fabrication ························································ 33
the release process and 4) it determines the spacing of the devices above the substrate,
which determines susceptibility to vertical stiction. In order to meet the criteria for an
effective sacrificial layer, a material must be non-conductive, exhibit good adhesion to
both the substrate and structural layer, and feature high etch selectivity to the structural
material. We use silicon oxide as a sacrificial layer because it is non-conductive and
features high etch selectivity to both aluminum and silicon in a hydrofluoric acid-based
etch. However, because silicon oxide is also used to encase the aluminum interconnect
structures, we must use a release etch stop to prevent accidental exposure of the buried
aluminum. Therefore we include a 250 nm layer of PECVD silicon nitride between the
buried silicon oxide, which encases the interconnect structures, and the sacrificial oxide,
which will be etched away during the release process. The SiN is deposited at 300˚C.
Figure 2.5: (Left) Top down view and (Right) cross-sectional view of
representative three terminal device after deposition of the silicon nitride
release stop and silicon oxide sacrificial layer.
Chapter 2: NEM Relay Fabrication ························································ 34
The silicon oxide sacrificial layer is then deposited on top of the silicon nitride
layer. A diagram of a device after deposition of the sacrificial oxide layer is shown in
Figure 2.5. We have investigated silicon oxide deposited using both LPCVD and
PECVD methods. Silicon oxide deposited using LPCVD features lower etch rate in
hydrofluoric acid compared to PECVD silicon oxide, which leads to longer release etch
time and less potential damage to the oxide anchors. However, LPCVD methods feature
a lower deposition rate than PECVD methods (15nm/min and 80nm/min, respectively),
which can add expense and inconvenience to the fabrication process. Furthermore,
PECVD tools can deposit silicon oxide at a lower temperature (300˚C) compared to
LPCVD tools (400˚C). For both deposition methods, we aim to deposit 1.5 μm silicon
oxide layer.
2.6 Via Etch
In order to connect the device structural layer to the buried interconnect layer,
we must etch through the sacrificial layer to create vias between the relays and
interconnect structures. A diagram of the via etch is shown in Figure 2.6. We use a
Chapter 2: NEM Relay Fabrication ························································ 35
resist mask to etch the via pattern into the silicon oxide and silicon nitride layers,
stopping on the aluminum. We transfer the pattern to the silicon oxide/silicon nitride
Figure 2.6: (Left) Top down view and (Right) cross-sectional view of
representative three terminal device after the via etch through to the aluminum
interconnect.
Figure 2.7: SEM cross-section image of a via etched through the sacrificial
silicon oxide, silicon nitride release etch stop and buried oxide.
Chapter 2: NEM Relay Fabrication ························································ 36
layers using RIE, followed by a brief soak in dilute liquid hydrofluoric acid. An SEM
cross section showing a via etch to the aluminum layer is shown in Figure 2.7.
2.7 Structural Layer Deposition
To prevent spiking of the aluminum into the structural silicon germanium layer,
we deposit a 20nm titanium nitride (TiN) barrier layer directly after the via etch. We
use the Cambridge Nanotech Fiji F202 ALD system to ensure conformal coverage
within the via trenches without pinholes. We use a plasma enhanced deposition recipe
at 250˚C.
After deposition of the barrier layer, we deposit the structural polycrystalline
silicon germanium (poly-SiGe) layer. A diagram of a device after deposition of the
silicon germanium is shown in Figure 2.8. We use poly-SiGe as the structural layer
Figure 2.8: (Left) Top down view and (Right) cross-sectional view of
representative three terminal device after deposition of the titanium nitride
barrier layer and silicon germanium structural layer.
Chapter 2: NEM Relay Fabrication ························································ 37
because it features mechanical and chemical properties similar to polycrystalline silicon,
it is conductive when doped, it can be deposited at low temperatures, it features low
internal stresses and therefore does not require a post-deposition anneal step. We
deposit the boron-doped SiGe using LPCVD system at 425C over a deposition time of
8 hours. The resulting film is 1.8μm thick, and features a film resistivity of 1030μΩ-
cm.
2.8 Structural Layer Etch
After deposition of the SiGe structural layer, we use reactive ion etching to
create NEM relays, routing and probe pad structures. It is essential that we achieve
smooth, vertical sidewalls because the sidewalls will eventually form the relay contact,
therefore we use an oxide hard mask to achieve better etch selectivity. After clearing
the resist, we then transfer the pattern to the structural layer using a very directional RIE
Figure 2.9: (Left) Top down view and (Right) cross-sectional view of
representative three terminal device after deposition of the titanium nitride
barrier layer and silicon germanium structural layer.
Chapter 2: NEM Relay Fabrication ························································ 38
process. A diagram of a device after the structural layer etch is shown in Figure 2.9,
and an SEM image of a cross-section after the silicon germanium etch is shown in
Figure 2.10.
2.9 Contact Layer Deposition
The contact surface of the NEM relays will be located on the newly etched
sidewalls of the SiGe. In order to improve the wear behavior and conductivity of the
contact, we can deposit a thin layer of a different material on the sidewall. This new
materials will largely determine the behavior of the contact, and is therefore called the
contact material. Because we want the contact surface to remain as smooth and vertical
as possible, we require a very conformal deposition process. Atomic layer deposition
is an ideal method for creating the contact layer because it is both conformal and self-
limiting. A diagram of a device after ALD ruthenium contact layer deposition is shown
in Figure 2.11.
Figure 2.10: Cross-Section Images of etched polycrystalline silicon germanium
structural layer on silicon oxide and on polycrystalline germanium.
Chapter 2: NEM Relay Fabrication ························································ 39
We have investigated two contact layer materials: Titanium Nitride and
Ruthenium. Both films are deposited using atomic layer deposition (ALD). The ALD
titanium nitride (TiN) is deposited at 250˚C, measures 25nm thick, and yields a sheet
resistance 1300 μΩ-cm. The ALD ruthenium is deposited at 270˚C, measures 50nm
thick and yields a sheet resistance of 120 μΩ-cm.
2.10 Contact Layer and Barrier Layer Etch
The contact layer material must be removed from between the device electrodes
to prevent shorting and to expose the underlying release layer to the release etchant. At
this time, we must also remove the titanium nitride barrier layer. A diagram of a device
after the contact and barrier layer etch is shown in Figure 2.12
To preserve the contact material on the sidewalls, we use a highly directional
dry etch to remove the contact material only on the horizontal surfaces between the
Figure 2.11: (Left) Top down view and (Right) cross-sectional view of
representative three terminal device after deposition of the ruthenium contact
layer.
Chapter 2: NEM Relay Fabrication ························································ 40
electrodes. Although resist is not necessary to etch the contact layer, we nevertheless
include a lithography step in order to protect the material on the probe pads. We also
include a silicon oxide hard mask to provide better selectivity and protect the sidewall
Figure 2.13: SEM image of a device with the structural layer etched away with
XeF2 after the contact layer etch
Figure 2.12: (Left) Top down view and (Right) cross-sectional view of
representative three terminal device after etch of the ruthenium contact layer.
Chapter 2: NEM Relay Fabrication ························································ 41
surfaces from contaminants from the photoresist. After patterning the oxide, we
perform a highly directional metal etch using an ICP RIE etcher to remove the contact
layer material from between the poly-SiGe structural components. Figure 2.13 shows
the exposed sidewalls of a device with the poly-SiGe structural layer removed using
XeF2.
2.11 Device Release
After the contact layer etch, the devices are ready to be released. Before the
release etch, the devices are cleaned again using the Matrix plasma asher. We use a
hydrofluoric acid-based etchant (HF) to etch the silicon oxide sacrificial layer from
under the poly-SiGe structures, as shown in Figure 2.15. We use two forms of HF
etchant: liquid-phase etchant followed by a critical point dry step and vapor-phase
etchant. The liquid-phase etchant is attractive because it is fast and also carries away
Figure 2.15: (Left) Top down view and (Right) cross-sectional view of
representative three terminal device after sacrificial layer etch.
Chapter 2: NEM Relay Fabrication ························································ 42
contaminants, leaving a clean surface after the etch. However, it requires a critical point
dry step in order to prevent damage due to capillary forces. The vapor-phase etchant
does not require an additional drying step, but may leave residue on the surface of the
devices. An SEM image of the cross-section of a released device is shown in Figure
2.16.
2.12 NEM Relays without Interconnect
Three terminal NEM relays that do not require an interconnect layer to
electrically connect to other structures can be fabricated using the same sacrificial,
structural and contact materials as the devices with interconnect. We begin by
depositing a 1.5μm PECVD silicon oxide film, which functions as both the sacrificial
and insulation layer, as described in section 3.5. We then deposit the silicon germanium
structural layer structural layer at 425˚C over 8 hours as described in section 2.7. We
Figure 2.16: SEM cross-section of a three terminal relay with interconnect
after liquid-phase HF release. The image shows that the sacrificial layer etch
is prevented from damaging the buried oxide layers by the silicon nitride layer
etchstop layer.
Chapter 2: NEM Relay Fabrication ························································ 43
deposit and pattern a silicon oxide hard mask, then transfer the pattern and etch the
structural layer, as described in section 2.8. Note that the titanium nitride barrier layer
is not necessary in this design because there is no aluminum interconnect layer. We
deposit and etch the contact material, as described in section 2.9 and 2.10. We then
release and dry the devices, as described section 2.11. A diagram of a fully fabricated
and released three terminal device is shown in Figure 2.17.
2.13 Alumina Sacrificial Etch Stop
We can replace the silicon nitride sacrificial etch stopping layer, which was
described in section 2.5, with a layer of aluminum oxide (alumina). The alumina can
be deposited using an ALD process, and therefore can create a very thin, pinhole-free
layer that is also highly conformal. The alumina stopping layer could enable more
complex designs with buried layers that are not necessarily planar[56]. Furthermore,
alumina has shown very high etch selectivity to silicon oxide for anhydrous vapor-phase
Figure 2.17: (Left) Top down view and (Right) cross-sectional view of
representative three terminal device without interconnect after fabrication and
release.
Chapter 2: NEM Relay Fabrication ························································ 44
hydrofluoric acid. A vapor-based sacrificial etch would eliminate the need for a critical
dry step after exposure to liquid hydrofluoric acid etchant. A disadvantage of including
an alumina stopping layer might be that etching the alumina during the via etch would
require a significantly different etch chemistry from the surrounding silicon oxide
layers, possibly introducing complexity to the fabrication process.
The alumina replaces the silicon nitride layer described in section 3.5. After
depositing the buried silicon oxide layer, the ALD alumina stopping layer is deposited
using a thermal recipe. The target film thickness is 25nm. Then we continue with the
via etch, SiGe deposition and etch, and contact layer deposition and etch as previously
described.
Figure 2.18: SEM image of released device using alumina stopping layer to
prevent the sacrificial layer etch from damaging the interconnect layer.
Chapter 2: NEM Relay Fabrication ························································ 45
To release the devices, the samples are exposed to vapor-phase HF. Once the
vapor-phase HF etch is complete, the devices are ready to test. An SEM image of a
released device with alumina stopping layer as shown in Figure 2.18.
2.14 Chapter Summary
We have developed a wafer-scale, processing technique for back-end-of-line-
compatible NEM relays. We have demonstrated successful fabrication of silicon
germanium based NEM relays with buried aluminum interconnect. In the next chapter,
we will present data from devices created using this process flow.
Chapter 3: Device Characterization ························································ 46
Chapter 3: Device
Characterization
In this chapter, we will discuss the characterization of NEM relays fabricated using the
processes described in Chapter 2. The devices are tested in a nitrogen ambient using a
custom-built glovebox with positive pressure ambient. Important metrics include cycle
lifetime, contact resistance over lifetime and actuation voltages. Desired numbers for
each metric are described according to each design application. Achieved performance
for each metric is described, as well as performance trends seen over ranges of various
testing variables.
3.1 Test Set-Up
The characteristics of the testing apparatus can have a pronounced effect on
device lifetime and performance. Electrical requirements for the testing set up include
the ability to measure resistances between 1Ω and 1GΩ, generation of voltages between
10mV (lowest VDS) and 50V (highest VGS), and generation of triangle and square waves
with signal frequencies up to 1kHz. In addition, control of ambient can have noticeable
impact on performance. Prior work has shown improved contact behavior in nitrogen
environments, even compared to vacuum ambient, due to formation of insulating carbon
films at the contact.[57] The ability to drive off contamination and moisture is also
Chapter 3: Device Characterization ························································ 47
highly desireable, and can often be implemented using a heater installed in the chip
holder. Two testing platforms have been developed to test the fabricated devices: a
positive-pressure nitrogen glovebox and vacuum station with nitrogen backfill.
3.1.1 Nitrogen Glovebox
Devices with up to five terminals can be tested in a positive-pressure nitrogen
glovebox, as shown in Figure 3.1, which was custom built for testing of laterally-
actuated NEM relays.[58] The glovebox includes a vacuum loadlock for introducing
samples without allowing room air to enter. Inside the glovebox are five probes which
are connected to a Keithley 4200-SCS Parameter Analyzer. In order to better diagnose
the issues seen during testing, I added a 5000x Keyence Digital Microscope which
allows real-time, optical observation of the devices as they switch. I was also involved
Figure 3.1: Images of nitrogen glovebox test set-up. (Left) View of glovebox
next to Keithley Parameter Analayzer and Keyence microscope screen. (Right)
Close-up view inside the glovebox showing the probes, microscope and chip
holder.
Chapter 3: Device Characterization ························································ 48
in the design and installation of a custom-built, vacuum chip holder that also contains a
heating elecement which can generate temperatures up to 300˚C.
3.1.2 Vacuum Station
I was involved in the design and installation of a custom-built vacuum probe
station, shown in Figure 3.2, which allows testing of designs with multiple relays and
three-terminal relays with buried interconnect. The vacuum station is equiped with both
a dry roughing pump and turbo pump which can reach pressures below 1e-4 Torr. The
vacuum station includes a probe card that can make contact with 50 probe pads
simultaneously. The chip holder also contains a heating element and thermocouple
Figure 3.2: Images of vacuum probe station. (Left) Outside view of vacuum
chamber, computer station and heater controller. (Right) Inside view of vacuum
chamber with probe card and chip holder.
Chapter 3: Device Characterization ························································ 49
which allows controlled heating of the sample. Once a vacuum is achieved, the chamber
can be backfilled with nitrogen or room air. Actuation signals and electrical
measurements can be controlled in several ways: 1) the Keithley parameter analyzer
described in the previous section (however, only 5 probes can be controlled or measured
in this way), 2) oscilloscopes and waveform generators or power supplies, 3) a custom-
made controller using a DAQ card or microcontroller. More details can be found in
Appendix B.
3.2 Performance Metrics
Desired performance metrics for relay devices depend on the application.
Several applications that are attractive candidates for integrated CMOS-NEM relay
design are presented in section 1.3. Performance metrics for relays for integrated system
applications include:
Actuation voltage (ie – gate-source voltage, VGS)
Contact voltage bias (ie - drain-source voltage, VDS)
Lifetime Contact Resistance
Hysteresis Window (difference between VPI and VPO)
Each application has specific requirements for each metric of relay performance, some
of which are summarized in Table 3.1. Optimal lifetime behavior yields resistances
below 10kΩ for most applications. Number of cycles required before failure depends
on whether the device is used to re-route signals intermittently (as in memory or routing
Chapter 3: Device Characterization ························································ 50
applications, which require under 106 cycles), or to continuously perform computation
tasks (as in logic applications, which require 1015 cycles). Devices that are actuated by
CMOS-based circuits must feature actuation voltages less than VDD , which ideally
yields VPI < 1V although higher voltages may be allowed using charge pumps if
necessary. The hysteresis window must either be minimized to reduce noise margins
(for logic applications) or maximized to enable programming of large arrays of devices
(for FPGA routing applications). In both cases, consistent VPI and VPO over many cycles
and across devices is desired.
Routing for FPGA applications imposes a unique set of restrictions on the
hysteresis. FPGA routing applications can take advantage of the hysteresis to establish
a built-in programming technique for arrays of relays called “half-select
programming”[32]. The relay arrays are formed by arranging the relays in a grid
pattern, then connecting the source electrodes in each column, and the gate electrodes
in each row. Using half-select programming, an individual relay in the array can be
addressed by sending a combination of three voltages (0V, VSELECT and VHOLD) to its
Table 3.1: Relay performance requirements for integrated CMOS-NEM relay
systems according to application.
Performance
Requirement Logic Memory FPGA Routing
Lifetime Resistance 10kΩ[1] 10kΩ[1] 1kΩ[1]
Lifetime (cycles) 1015 [1] 1000001 1000[1]
Actuation Voltage 1 V1 1 V1 1 V1
Hysteresis minimized1 consistent maximized,
consistent
Chapter 3: Device Characterization ························································ 51
corresponding source and gate lines. The values of VSELECT and VHOLD depend not only
on the value of VPI and VPO, but also on the variation in VPI and VPO between cycles and
across devices. Ideally, a large window exists between the maximum VPO and minimum
VPI, and the variation in VPI is very small.
All described performance metrics can be measured using two testing
procedures: gate-source voltage sweep and cycling test:
3.2.1 Gate-Source Voltage (VGS) Sweep
The gate-source voltage (VGS) sweep involves ramping VGS up and down with a
constant drain-source voltage bias (VDS). The VGS sweep is used to measure actuation
voltage (VPI), hysteresis (VPI - VPO), and also the minimum attainable resistance (RMIN)
which usually occurs at VGS values higher than VPI. A diagram of results from multiple
VGS sweeps of a single three terminal relay is shown in Figure 3.3A. and an example of
experimental results from a fabricated device is shown in Figure 3.3C. The results
demonstrate a small variation in VPI sand a larger variation in VPO (due to highly
variable surface forces). The hysteresis window represents the difference between the
Chapter 3: Device Characterization ························································ 52
minimum VPI and maximum VPO. The ideal minimum contact resistance is very low
for all applications. Because increasing VGS after pull-in leads to increasing contact
force, the drain-source current (and therefore contact resistance) depends heavily on the
Figure 3.3: Diagrams of VGS sweeps for three-terminal devices. (A) Overlaid
IDS-VGS curves of a single device over several VGS sweep cycles. This graph
shows the variation in VPI and VPOT, the hysteresis window and relationship
between overdrive voltage and IDS. (B) For several devices or cycles, the ranges
of VPI and VPO are plotted as bars with a marker denoting the average
measurement. This graph allows comparison of actuation voltages and
hysteresis window for different devices or the same device over many cycles.
(C) Experimental data from a single relay over several VGS sweep cycles.
Chapter 3: Device Characterization ························································ 53
maximum VGS attained during the sweep. The maximum VGS after pull-in is expressed
as overdrive voltage (VOV), which is a function of the average pull-in voltage:
𝑉𝑂𝑉 =(𝑀𝑎𝑥𝑖𝑚𝑢𝑚 𝑉𝐺𝑆)−(𝐴𝑣𝑒𝑟𝑎𝑔𝑒 𝑉𝑃𝐼)
(𝐴𝑣𝑒𝑟𝑎𝑔𝑒 𝑉𝑃𝐼)× 100 [%]...........................................(3.1)
Higher VOV tends to yield lower contact resistance. However, many CMOS-compatible
applications require a low actuation voltage to avoid breakdown of the CMOS
transistors, limiting the device operation to small VOV. Furthermore, very high VOV can
lead to failure due to secondary pull-in to the gate (as discussed in section 1.2.1).
Although drain-source voltage (VDS) is held constant throughout the sweep, it can
significantly affect the resistance and lifetime of the devices. Some applications, such
as relay routing, require a consistent hysteresis window between devices, which can be
illustrated by plotting VPI and VPO in the format shown in Figure 3.3B.
3.2.2 Cycling Test
The second testing procedure is a cycling test, and involves the application of a
square wave VGS signal to the actuation electrode of the relay, thus repeatedly opening
and closing the relay contact. During the cycling test, the resistances are recorded both
in the open and closed state. The open state resistance measurement should be infinity,
unless the device has failed by welding in the closed state. The closed-state resistance
evolves over time depending on the rate of degradation of the contact surface, as
Chapter 3: Device Characterization ························································ 54
illustrated in Figure 3.4. The cycling test can be conducted in “hot” or “cold” switching
mode: hot-switching maintains a constant VDS regardless of the state of the contact, and
cold switching maintains VDS at 0V unless the relay is already closed. Hot switching
usually leads to more damage at the contact due to arcing across the contact gap. Other
important variables for cycling tests are VOV, VDS, and contact time.
Figure 3.4: Diagram of contact resistance versus cycle data for two devices
Figure 3.5: Results of a series of VGS sweep tests on a single three-terminal device (VDS =
100mV, LS = 3μm, poly-SiGe with ruthenium contact, N2 glovebox). (A) Minimum RCON
and gate overdrive versus sweep cycle. (B) Minimum RCON versus gate overdrive for the
same data.
Chapter 3: Device Characterization ························································ 55
3.3 Overdrive Voltage (VOV)
The relationship between minimum contact resistance, cycle number and gate
overdrive voltage is shown in Figure 3.5, in which a single three-terminal device with
ALD ruthenium contact material and partitioned beam design (LS = 3μm, as described
in section 4.1) is subjected to consecutive VGS sweeps with varying Vov. The device
was tested in the nitrogen glovebox at room temperature, with VDS = 100mV. Gate
overdrive is cycled between 3% and 82% of VPI (average VPI =27.5V). The results show
that the minimum contact resistance is reduced to less than 500Ω by high gate overdrive.
Figure 3.6: Results of a cycling test on a three-terminal device with ruthenium
contact material with varying overdrive voltage (τC = 300ms, VDS = 100mV,
cold-switching, LS = 3μm, Le = 18μm, poly-SiGe with ruthenium contact, N2
glovebox)
Chapter 3: Device Characterization ························································ 56
Over many cycles, high contact force can maintain low resistance. However, as shown
in Figure 3.6, the higher contact forces will degrade the contact interface until the
contact resistance approaches levels associated with lower contact force.
The overdrive voltage also affects the hysteresis window. The VPI and VPO of a
three-terminal device with ALD ruthenium contact are plotted with respect to Vov in
Figure 3.7. As the overdrive voltage increases, the pull-out voltage decreases. This
may be due to increased surface area at the contact, which would increase the effect of
surface forces thus lowering VPO.
Figure 3.7: Results of a VGS sweep on a three-terminal device with varying
overdrive voltage (VDS = 100mV, LS = 3μm, Le = 18μm, poly-SiGe with
ruthenium contact, N2 glovebox)
Chapter 3: Device Characterization ························································ 57
3.4 Contact Time (τC)
The time during which the contact is closed (τC) can affect the total contact
resistance. We cycled three devices (ruthenium contact with LS = 3μm, as described in
section 4.1) over 10,000 cycles, each device with a different τC. The results shown in
Figure 3.8 are plotted as contact resistance versus total contact time. They indicate that
longer τC initially yield lower contact resistance, but eventually the differences between
the device resistances become negligible. This could be due to joule heating at the
Figure 3.8: Results of a cycling test on three three-terminal devices with varying
contact times over 10,000 cycles. The results are plotted as contact resistance
versus total contact time, although all devices experienced the same number of
cycles. (VOV = 10%, VDS = 100mV, cold-switching, LS = 3μm, Le = 18μm, Poly-
SiGe with ruthenium contact, N2 glovebox).
Chapter 3: Device Characterization ························································ 58
contact, which can help to remove contamination from the contact interface but also
degrades the contact faster.
3.5 Drain-Source Voltage
Proper selection of the drain-source voltage is important for the overall
performance of the device to prevent (or induce) welding, although it does not
significantly affect the device resistance, as shown in Figure 3.9. Three devices with
ALD ruthenium contact coating and LS = 3μm (as described in section 4.1) are cycled
Figure 3.9: Results of cycling test for three different three-terminal
devices, each with different VDS levels (VOV =10%, cold-switching, τC
= 300ms, LS = 3μm, Le = 18μm, poly-SiGe with ruthenium contact, N2
glovebox)
Chapter 3: Device Characterization ························································ 59
at different VDS, with 10% VOV and the results show no discernible trends over 10,000
cycles. However VDS that is too high can quickly lead to welding.
Device cycling can be performed in either hot-switching or cold-switching mode
as previously described in section 3.2.2. Two identical three-terminal devices with ALD
ruthenium contact were cycled under either hot-switching or cold-switching conditions.
The results are shown in Figure 3.10. As shown, hot-switching leads to more unstable
resistance and faster increase in contact resistance than cold-switching.
Figure 3.10: Results of cycling test for two identical three-terminal devices,
tested under either hot-switching or cold-switching conditions. (VOV =10%,
τC = 300ms, VDS = 100mV, LS = 3μm, Le = 18μm, poly-SiGe with ruthenium
contact, N2 glovebox)
Chapter 3: Device Characterization ························································ 60
3.6 Ambient
Ideally, the composition and contamination levels of the operating ambient are
tightly controlled during testing. Prior work has suggested that ruthenium oxide/gold
contacts demonstrate better performance in a nitrogen ambient compared to a vacuum
environment.[59] Further investigation has revealed that ruthenium oxide/gold contacts
maintain lower resistance levels in a gaseous mixture of nitrogen and oxygen compared
to a pure nitrogen gas ambient when hydrocarbon contamination is introduced [20].
This work suggests that the ruthenium oxide must wear away contaminants to maintain
Figure 3.11: Results of cycling test for two identical three-terminal devices,
tested in either the nitrogen glovebox or vacuum station. (VOV =10%, τC =
200ms, VDS = 100mV, LS = 3μm, Le = 18μm, cold switching, poly-SiGe with
ruthenium contact)
Chapter 3: Device Characterization ························································ 61
a low resistance, even in conditions with low levels of contamination. The ideal
operating environment would be a stable, clean, dry, inert environment inside an
encapsulated shell. Although the devices in this work are unencapsulated, the two
testing stations offer a method for testing the effect of ambient. Figure 3.11 shows the
results of cycling tests on two identical devices: one tested in the nitrogen glovebox and
the other tested in the vacuum probe station at a 1e-4 Torr chamber pressure. The results
indicate that the nitrogen glovebox ambient yields lower resistance initially compared
to the vacuum ambient. However, the device tested in vacuum shows a two order of
magnitude decrease in resistance after 1000 cycles, indicating that the ambient is very
clean and allows the device to mechanically remove existing contamination from the
contact without generating more layers of tribopolymer. The results also suggest that
the difference in performance between devices tested in either ambient is minimal after
1000 cycles.
3.7 Chapter Summary
We use a positive pressure nitrogen glovebox to test the fabricated devices. We
focus on a few performance metrics (actuation voltage, hysteresis, contact resistance,
cycle lifetime) based on the needs of a few especially promising applications. These
metrics are measured primarily using two tests: gate-source voltage (VGS) sweep and
cycling with step in puts. Using these two tests, we examine the effect of overdrive
voltage, contact time and drain-source voltage. We see that higher overdrive voltage
(VOV) leads to lower contact resistance and lower VPO. We also see that longer contact
Chapter 3: Device Characterization ························································ 62
time leads to lower contact resistance. Drain-source voltage (VDS) does not directly
affect resistance or lifetime as long as VDS remains low enough to avoid premature
welding. Testing in nitrogen and vacuum ambient shows higher initial resistance in
vacuum but similar resistance levels after 1000 cycles. Further testing could involve
backfilling the vacuum chamber with pure nitrogen or clean, dry air (CDA) which is
80% nitrogen and 20% oxygen.
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Chapter 4: Device Design
In this chapter, we will discuss some advancements in the design and modeling
of relays for improved performance. As demonstrated in the previous chapter, contact
resistance is limited by the size and quality of the contact area. In this chapter, we will
discuss methods for increasing the contact area and improving the quality of the contact.
In the previous chapter, we used gate overdrive voltage to squeeze the contact and
increase the surface area. Destructive contact between the beam and the gate can be
avoided by using a partitioned beam design, which selectively stiffens parts of the beam
thus allowing higher overdrive voltages. The contact area can also be increased by using
a hollow tip etch, which makes the contact more compliant by selective etching of the
structural material at the contact. Careful selection of the contact material and
intelligent control of thermal behavior through thermal modeling can prevent contact
degradation and welding. Finally, we demonstrate equivalent behavior for devices with
and without interconnect.
Chapter 4: Device Design ···································································· 64
4.1 Partitioned Beam for Increased Contact
Force
Higher VOV tends to yield lower contact resistance, as previously discussed. We
have developed a “partitioned” beam design that allows for high contact force without
catastrophic pull-in to the actuation electrode. [60] The partitioned beam design allows
separation of the actuation (electrode) and spring portions of the cantilever beam, as
shown in Figure 4.1A. By making the electrode portion of the beam thicker, we can
reduce deflection of the beam near the gate electrode. We can adjust the stiffness of the
entire beam by changing the length of the spring portion. Given the partitioned beam
proportions as shown in Figure 4.1B, and assuming the electrode portion of the beam is
perfectly stiff and behaves like parallel plate actuation, the pull-in voltage of the beam
can be derived from equation 1.2 with the beam dimensions as:
Figure 4.1: Partitioned electrode design. (A) SEM image of a partitioned beam
demonstrating the electrode and spring portion (LS = 3μm, Le = 18μm). (B)
Diagram showing the important dimensions of a partitioned beam design.
Chapter 4: Device Design ···································································· 65
𝑉𝑃𝐼 = √2
27
𝐸𝑡3𝑑03
𝜀𝐿𝑒𝐿𝑆3 (3.2)
where t is the thickness of the beam spring (usually set to the minimum lithography
resolution), d0 is the initial gap distance between the beam and gate, Ɛ is the dielectric
constant of the ambient, LS is the length of the beam spring, Le is the length of the
electrode portion and E is the Young’s Modulus of the material. The relationship
between VPI and VPO is shown in Figure 4.2, in which multiple three-terminal devices
Figure 4.2: Multiple three-terminal relays with partitioned electrode design and
varying beam spring lengths (LS) showing trends in VPI, VPO and yield (Polysilicon
with titanium nitride contact, and VDS = 1V, N2 glovebox)
Chapter 4: Device Design ···································································· 66
with varying beam spring length LS (Le is also varied to maintain constant total beam
length) and titanium nitride contact material are tested using a VGS sweep. Each device
undergoes VGS sweep 10 times. Although average VPI tends to decrease with increasing
beam length (and decreasing stiffness), the restoring force is also reduced, leading to
stiction failure, as can be seen prominently at beam spring length 10μm.
4.2 Hollow Tip
All fabricated devices show very high contact resistance (>1kΩ). The main
reason for this high resistance is the small contact area. The contact area is limited by
the angle of the vertical structural layer etch, footing during the structural layer etch,
surface roughness on the sidewalls due to redeposition of etched material, and the
inherent limitation of a cantilever beam contacting the drain electrode only at the tip. A
close-up image of the contact area is shown in Figure 4.5. The small contact area creates
Figure 4.5: SEM image of three-terminal device (Left) with close-up of contact
area (Right). The device shown consists of a polysilicon structural layer with
titanium nitride contact layer.
Chapter 4: Device Design ···································································· 67
a restriction for current that is difficult to overcome with other design parameters such
as contact material and encapsulation.
To improve the contact area, we have developed a hollow tip design which
involves removing the structural material near the end of the beam, leaving only the thin
contact layer as shown in Figure 4.6.[61] The hollow etch is achieved by masking the
unreleased devices except for a small opening near the cantilever tip, then exposing the
devices to XeF2 gas, thus performing an isotropic etch of the structural material. The
amount of structural layer that is removed depends on the length of time that the devices
are exposed to XeF2. After the hollowing of the tip, the devices are released.
The resulting hollow tip has a more compliant surface than the solid tip devices,
leading to larger actual contact area and lower contact resistance as shown in Figure
4.7.[60] As shown in Figure 4.8A, devices with a longer XeF2 etch time, and therefore
larger hollow area, are prone to breaking and warping during testing. The best results,
Figure 4.6: SEM image of three-terminal device with hollow tip etch, leaving
a thin, compliant film from the contact material. The device shown consists
of a polysilicon structural layer with titanium nitride contact layer.
Chapter 4: Device Design ···································································· 68
such as those shown in Figure 4.7, are seen in devices with a very short XeF2 etch time
and therefore smaller hollow area, as demonstrated in Figure 4.8B. Although the more
compliant contact can lead to lower contact resistance, even a short XeF2 etch can
weaken the contact and limit the lifetime of the device. The sharp increase in contact
resistance seen in Figure 4.7 may indicate a broken contact membrane like the one seen
in Figure 4.8A.
Figure 4.7: Results of cycling tests for two poly-Si relays with titanium
nitride contact layer comparing contact resistance with and without hollow
tip (VOV =10%, τC = 500ms, VDS = 1V, LS = 3μm, Le = 18μm, N2 glovebox).
Adapted from [60]
© IEEE 2013
Chapter 4: Device Design ···································································· 69
4.3 Contact Material
Because of the high forces and temperatures at the contact, the material used to
form the structural layer does not perform well as a contact material. Therefore, it is
advantageous to deposit more durable materials at the contact. We have fabricated
three-terminal relays with two contact materials: ALD Ruthenium and ALD Titanium
nitride. The ruthenium film demonstrated a sheet resistance of 120 μΩ-cm with 50nm
Figure 4.8: SEM images of devices with hollow etch after testing. (A)
Device with hollow etch in beam and drain electrode. A broken contact
membrane is evident, as well as deformation in the hollowed area of the
beam. (B) Device with minimal hollow etch, only in the beam. (Polysilicon
structural layer with titanium nitride contact layer)
Chapter 4: Device Design ···································································· 70
film thickness, and the titanium nitride demonstrated sheet resistance of 1300 μΩ-cm
with 25nm film thickness. The sheet resistance of the silicon germanium is 1030 μΩ-
cm. The ALD ruthenium is an attractive contact coating because it has very low contact
resistance and it has a conductive oxide. Although the ALD titanium nitride has a
relatively high sheet resistance and non-conductive oxide, it is nevertheless an attractive
coating because of its hardness and high melting temperature. The results of the cycling
testing of three-terminal devices without any contact material and devices with either
ALD ruthenium or titanium nitride are shown in Figure 4.9. For all devices, testing was
Figure 4.9: Results of a cycling test on three three-terminal with no contact material,
ruthenium and titanium nitride contact layers (VOV = 10%, τC = 300ms, VDS =
100mV, hot-switching, LS = 3μm, Le = 18μm poly-SiGe, N2 glovebox).
Chapter 4: Device Design ···································································· 71
performed in the nitrogen glovebox. The results show that ruthenium and titanium
nitride coated devices have similar initial contact resistance near 10kΩ, and bare devices
have high resistance near 1GΩ. However, the titanium nitride devices immediately
begin to degrade and show increasing contact resistance. The ALD ruthenium coated
devices maintain a nearly constant resistance, sometimes dropping below 10kΩ, until
the resistance starts to slowly increase after 50,000 cycles. Using ALD ruthenium
contact layers, we have achieved contact resistances as low as 400Ω with high overdrive
voltage in the first few cycles.
Figure 4.10: Auger analysis shows higher oxygen content inside the contact area
than outside (poly-SiGe relay with ruthenium contact after cycling).
Chapter 4: Device Design ···································································· 72
Several techniques exist which allow compositional analysis of a surface.
Because of the extremely small size of the contact area, an analysis technique with very
small spot size and shallow depth of analysis is required. Auger analysis meets these
requirements. The results of Auger analysis of the contact region and a nearby area
outside the contact region are shown in Figure 4.10 for a device cycled 10,000 times.
The results suggest an increase in oxygen content at the contact, indicating that the
formation of the ruthenium oxide does hinder conduction across the interface. The
higher resistances seen after 50,000 cycles may also be due to buildup of tribopolymer
or mechanical displacement of the ALD ruthenium from the contact, as discussed in
section 1.2.4.
Devices with ALD ruthenium contact layer have been tested up to 900,000
cycles, as shown in Figure 4.11. The results show that the contact gradually degrades,
Figure 4.11: Results of a cycling test on a three-terminal poly-SiGe relay with
ruthenium contact layer which survived for 900,000 cycles. (VOV = 10%, τC =
300ms, VDS = 100mV, cold-switching, LS = 3μm, Le = 18μm).
Chapter 4: Device Design ···································································· 73
eventually surpassing 1MΩ after 10,000 cycles. The device failed by welding of the
beam to the drain, at which point the resistance dropped dramatically to under 1kΩ.
4.3.1 Effect of Contact Material on VPI and VPO
The contact material has an effect on the hysteresis window. In addition to
adding thickness to the beam and reducing the initial gap size, the contact material also
affects the surface energy at the contact. The results of 10 VGS sweeps of three terminal
Figure 4.12: Results of VGS sweep testing on two devices with titanium
nitride and three with ruthenium. Each device was tested 10 times (VDS =
100mV, LS = 3μm, Le = 18μm, poly-SiGe with ruthenium contact, N2
glovebox). The markers show the average actuation voltage and the errorbars
show the minimum and maximum measured results.
Chapter 4: Device Design ···································································· 74
poly-SiGe relays with ALD ruthenium and titanium nitride contact layers are shown in
Figure 4.12. Each relay was tested at least 5 times. The results show that the ALD
ruthenium contact material yields higher VPI and VPO, smaller hysteresis window and
smaller variation in VPO than the titanium nitride coated devices.
4.3.2 Thermal Modeling of Thin Film at Contact
Because of the high current density at the contact, joule heating can accelerate
degradation of the relay contact and lead to welding. Proper thermal analysis can lead
to relay designs that avoid unnecessary contact deterioration. Furthermore, if properly
understood, heating at the contact can be utilized to burn away contaminants, resurrect
a welded device or to create a weld on purpose for low-power latching applications.
Previous work has developed models of joule heating generated due to the
constriction resistance at the interface of asperity based contacts. The relationship
between the electrical and thermal properties and the temperature of the material is
given by the Wiedemann-Franz-Lorenz law: LT = ρκ, where L is the Lorenz number, T
Chapter 4: Device Design ···································································· 75
is the temperature of the material, ρ is the electrical resistivity and κ is the thermal
conductivity.[62] Previous work has extended this model to describe asperity-based
contacts with asymmetric thermal gradients on either side of the contact[63]:
2
2
2
1
22
2
1
4TTV
LR
RT C
C
M
C
4.1)
where TC is the temperature at the contacting interface, VC is the voltage across the
contact, T1 and T2 are the temperatures at either side of the asperities, γ is a scaling
function, RM is the Maxwell spreading resistance due to lattice scattering of electrons,
and RC is the total electrical contact resistance. In Figure 4.13, a diagram of a relay
beam with asperity contact illustrates the location of the temperatures at the contact (TC)
and near the contact (T1 and T2). The total contact resistance Rc can be expressed
as[64]:
2
a
a
SMCa3
4
a233.01
83.01RRR
, (4.2)
Figure 4.13: Diagram of relay with asperity based contact, illustrating
contact temperature τC and surrounding temperatures T1 and T2.
Chapter 4: Device Design ···································································· 76
where the scaling function γ is determined by the ratio a
, λ is the mean free path of
electrons, a is the contact radius, RS is the Sharvin resistance due to boundary scattering
of electrons and ρ is the electrical resistivity. The Sharvin resistance does not contribute
to joule heating of the contact, therefore the joule heating is dominated by the Maxwell
Resistance. The model presented in [63] works well for relay designs formed of a single
material, but does not accurately represent current designs that incorporate a thin film
of a different material at the contact, which is often included to decrease lifetime contact
resistance and improve wear properties. Furthermore, this model assumes that the
temperatures on either side of the contact (T1 and T2) are known.
A new, advanced thermal model is presented here for analyzing welding of an
ohmic contact with a thin contact film by assuming that TC is known and can be
determined by the melting or softening temperature of the contact material. This
advanced thermal model also incorporates joule heating in the beam, which would raise
Figure 4.14: Diagram of thermal model of relay with thin film at contact and heat
generation in the beam.
Chapter 4: Device Design ···································································· 77
the temperature at the base of the asperity at the beam (T1), thus raising the contact
temperature TC. Using this model enables calculation of welding voltage (VC) given
the contact material, device geometry and structural material, and initial resistance of
the contact. Conversely, this model can assist in identifying the contact material by its
melting point (TC) if the welding voltage and other parameters are known. A diagram
of the new thermal model which incorporates heat generation in the beam and a thin
film at the contact is shown in Figure 4.14.
A resistive model of the contact represents joule heating as an injection of
thermal power (qCON) which is equivalent to the electrical power generation across the
contact 𝑉𝐶
2
𝑅𝐶, where VC is the applied voltage across the contact and RC is the measured
contact resistance. The contact resistance is either measured before welding or
calculated using the geometry and composition of the contact via equation 4.2.
Assuming the contact film is very thin compared to the size of the asperity and the
contacting asperity is small compared to the overall size of the beam, the thermal
resistance of the asperity can be modeled as a thin disk on a semi-infinite solid, thus
giving a thermal resistance RASP that is equivalent to 1
𝑆𝜅 where S (the shape factor) is
given by 2a and κ is the thermal conductivity.[65] The contact radius a can be calculated
from equation 4.2, assuming the measured contact resistance RC is significantly higher
than other electrical device resistances such as the resistance through the beam or probe
contacts.
Chapter 4: Device Design ···································································· 78
The heat generated at the contact qCON is dissipated through the asperities as
qSOURCE and qDRAIN. The temperature at the drain can be assumed to be held at ambient
temperature T∞ since the drain electrode is large and anchored to the substrate which
acts as a heat sink. Therefore, we can express the heat dissipation at the contact using
the following set of equations:
ASP
C
C
2
C
source
ASP
C
drain
drain
C
2
C
source
C
2
C
drainsourcecon
R
TT
R
Vq
R
TTq
qR
Vq
R
Vqqq
(4.3)
An expression for heat flow between the contact and beam is essential for calculating
T1, which can be used in equation 4.1 to find VC, the voltage at which the contact film
is expected to melt and weld. If the current density through the beam is high enough,
then T1 will be significantly greater than T∞. Therefore, a model of the heat generation
in the beam must be included.
The beam can be represented by a heat generating fin. Although joule heating
injects thermal power (Qbeam) into the beam, heat is dissipated mainly through the anchor
and gate electrodes. The 1-D energy balance of the beam yields[66]:
'''Qm
dx
d beam2
2
2
(4.4)
where θ = T(x) - T∞, x is the distance along the beam, Qbeam’’’ is the volumetric heat
generation in the beam and 1/m is the characteristic length scale of a fin (i.e. – the
Chapter 4: Device Design ···································································· 79
healing length). The volumetric heat generation in the beam is given by the
electrical power input (I2R) divided by beam volume:
tLW
twLRV
Volume
RIQ
beam
beamCCbeambeam
22
''' (4.5)
where ρ is the electrical resistivity (of the structural material, in this case), and
Lbeam, W and t are the length, width and thickness of the beam, respectively. The
electrical current in the beam is equal to the current across the contact (VC/RC).
The healing length Lh of the beam due to conductive heat loss to the surrounding
air is given by [67]:
air
beamh
k
ktdL
m
01 (4.6)
where t is the thickness of the source beam, d0 is the distance between the beam and the
gate electrode, kair and kbeam are the heat conductivities of the air and beam, respectively.
The solution to equation 4.4 is given by:
2
beam
21m
'''Q)mxsinh(C)mxcosh(C
(4.7)
where C1 and C2 are coefficients based on the boundary conditions which are described
by:
1. 00x
2.tW
q
dx
d source
Wx
(4.8)
where qSOURCE is given by equation 4.3. The solution to equation 4.7 yields an
expression for T1 which can be inserted into equation 4.1 to find the voltage needed to
melt the material at the contact VC. A graphical representation of the welding voltage
VC and welding power calculated using this model as a function of measured device
Chapter 4: Device Design ···································································· 80
resistance is shown in Figure 4.15 for several different contact temperatures TC (i.e.-
different contact materials). These results correspond to a polysilicon device (ρ = 4.5e-
5 Ω-m) with Lbeam = 30μm, w = 1.5 μm, and t = 0.5 μm. The graphs indicate that
materials with higher melting points require both higher voltage and electrical power to
cause welding. They also illustrate the effect of initial contact resistance, which
correlates to higher welding voltage but lower welding power when current is not
otherwise limited.
Several devices were experimentally welded by performing consecutive VGS
sweeps with increasing VDS until welding was detected. Welding can be detected either
Figure 4.15: Simulated results of thermal model with thin film at contact and
heat generation in beam. (Top) Welding voltage versus contact resistance for
various contact materials. (Bottom) Welding Power (VC2/RC) versus contact
resistance for various contact materials.
Chapter 4: Device Design ···································································· 81
visually using the microscope or electrically by detecting non-zero IDS when VGS < VPO.
A device which has undergone one normal VGS sweep followed by a VGS sweep in which
welding occurs is shown in Figure 4.16. Although IDS is not limited, the device
nevertheless reaches a maximum IDS. In the second cycle, it can be seen that IDS remains
high, although the current drops slightly near the pull-out voltage as the restoring force
of the beam stretches the weld.
Figure 4.16: Experimental data from a three-terminal poly-SiGe relay with
ruthenium contact material during two VGS sweeps. The first sweep shows normal
pull-in and pull-out (blue). The second sweep shows normal pull-in but remains
pulled-in due to welding.
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In some cases, a welded device can be resurrected (i.e.- un-welded) by raising
VDS higher than the weld voltage while keeping VGS at zero. This allows the restoring
spring force of the beam to break the softened weld. In practice, resurrecting a welded
device is usually impossible. The weld usually creates a very low-resistance joint
between the beam and drain because the heat removes contaminants and the contact
material flows to create a larger contact area. Depending on the size of the weld, the
earlier assumption made for the thermal model – that the contacting asperity is much
Figure 4.17: Experimental data from a single fabricated relay during multiple weld
and unweld cycles, showing contact resistances in the welded and unwelded state,
with errorbars showing the minimum and maximum measured resistances over 10
cycles. The relay data show significantly lower resistances when welded compared
to the unwelded state. (poly-Si device with TiN contact coating, VDS = 10mV, VOV
= 10%, LS = 3μm, Le = 18μm)
Chapter 4: Device Design ···································································· 83
smaller than the beam thickness – will no longer be correct, thus preventing the model
from accurately predicting voltages needed to melt the contact material. As the
resistance of the weld approaches the resistance of the beam, the heat generation in the
beam effectively anneals the beam and reduces the restoring force of the deflected beam,
making pull-out impossible. Experimentally, we were able to show repeated weld and
resurrection of a device by applying the minimum VDS needed to weld the devices under
very low VOV. In these cases, the weld remains small and can be melted without causing
excessive heating in the beam. Data from a relay which has shown several cycles of
welding and resurrection are shown in Figure 4.17.
In order to compare experimental data with the improved thermal model, we
fabricated three devices with varying stiffnesses (as determined by beam length) and
subjected them to 10 cycles of welding and release. The devices feature a polysilicon
structural layer and titanium nitride contact layer. Because stiffer devices require larger
welds to prevent the beam from pulling out, the stiffer devices are expected to display
smaller contact resistances. The results of the weld/release cycles are shown in Figure
4.18. The measured resistances for the three devices (1, 2, 3) show that the stiffest
device (1) has the lowest resistance while the most compliant device (3) has the highest
stiffness, as shown in Figure 4.18B. The lower resistance device (1) also requires the
highest thermal power generation to weld, while the most compliant device (3) requires
the least, as shown in Figure 4.18A. The errorbars show the minimum and maximum
values of electrical power generation. This result matches the predicted trends shown in
Figure 4.15. For comparison, in Figure 4.18C the data from the weld/release tests are
Chapter 4: Device Design ···································································· 84
plotted over the predictive model for titanium nitride (TiN) welding. The electrical
power required to weld the devices more closely matches the predicted values while the
electrical power required to release the welded devices varied considerably and poorly
matches the predictive model, as expected.
Figure 4.18: Experimental data from a single fabricated relay during multiple weld
and unweld cycles, showing contact resistances in the welded and unwelded state.
The relay data show significantly lower resistances when welded compared to the
unwelded state. (poly-Si device with TiN contact coating, VDS = 10mV, VOV = 10%)
Chapter 4: Device Design ···································································· 85
4.4 Three Terminal Device with Buried Interconnect
Although the interconnect layer is not necessary for a three-terminal device, we
nevertheless include a three-terminal design with an interconnect layer as proof of the
interconnect fabrication process. As seen in the device layout shown in Figure 4.19, the
interconnect links the anchor of the beam to a nearby probe pad. Devices which were
constructed and tested follow the fabrication process detailed in sections 2.1-2.11, with
a protective silicon nitride release etch stop layer. Results of VGS sweep tests from
representative devices are shown in Figure 4.20. The data show sharp pull-in and pull-
out of the device. Contact resistances over six VGS sweep cycles average 30kΩ. A
Figure 4.19: Layout of three-terminal relay with buried interconnect. The
aluminum interconnect links the anchor of the beam to a nearby probe pad. A
magnified view of the beam is shown on the right.
Chapter 4: Device Design ···································································· 86
current compliance is imposed on IDS to avoid damage to the devices. The device is still
functional after 6 cycles. Cycling data from a similar device with buried interconnect
is shown in Figure 4.21 overlaid on data from twelve relays without interconnect. The
initial resistance is approximately 200 kΩ, and varies over many cycles but stays within
the same range as devices without interconnect. After reaching contact resistances over
1 MΩ, the device fails after 20,000 cycles by welding. These results indicate that the
addition of the buried interconnect feature did not degrade the performance of the
device. The lifetime of the device is within the required specifications for FPGA
routing, although the contact resistances and actuation voltages are above acceptable
levels.
Figure 4.20: Results of VGS sweep of three-terminal poly-SiGe relay with ALD
ruthenium contact layer, silicon nitride etch stop and buried aluminum interconnect.
The device performed 6 VGS sweep cycles.. (VDS = 100mV, LS = 3μm, Le = 18μm)
Chapter 4: Device Design ···································································· 87
As described in section 2.14, some devices with buried interconnect are
fabricated with an alumina release etch stop instead of silicon nitride, and released using
vapor-phase hydrofluoric acid instead of liquid-phase hydrofluoric acid. The VGS sweep
results of a three-terminal relay with interconnect protected by an alumina etch stop
layer are shown in Figure 4.22. The results show sharp pull-in and pull-out over five
VGS sweep cycles, and the device is still functional after those cycles. The average
resistance approximately 500MΩ. The resistance of the devices with alumina etch stop
is high compared to devices with the silicon nitride etchstop, which may be due to slight
variations in the fabrication processes. Because of contamination differences between
the silicon nitride and alumina depositions, the two process flows required different
tools even though most subsequent process steps were identical (the via etches required
Figure 4.21: Results of cycling of three-terminal poly-SiGe relay with ALD
ruthenium contact layer and buried aluminum interconnect. The device
performed 20,000 cycles and is still functional. (VDS = 100mV, VOV = 10%, cold
switching, τC = 300ms, LS = 3μm, Le = 18μm)
Chapter 4: Device Design ···································································· 88
different chemistries and therefore different tools). Nevertheless, the alumina etchstop
shows promise as an etchstop that can accommodate complex geometries, as described
in section 2.14.
4.5 Chapter Summary
Further control of device performance can be acquired through device design.
We have developed a “partitioned beam” design which selectively stiffens the beam
Figure 4.22: Results of five VGS sweeps on a three-terminal poly-SiGe relay
with ALD ruthenium contact, buried aluminum interconnect and alumina etch
stop. The relay is still functional. (VDS = 100mV, LS = 3μm, Le = 18μm)
Chapter 4: Device Design ···································································· 89
near the gate, thus allowing higher overdrive voltages. Published work has shown
higher contact force can be achieved through higher overdrive force, while avoiding
catastrophic pull-in to the gate. We further show that smaller beam spring length (LS)
leads to larger hysteresis window and better yield. By etching the structural material
near the contact, we can create a thin contact membrane using the contact layer. This
“hollow” contact is more compliant than the solid contact, leading to larger total contact
area and lower contact resistance. We investigate two contact materials (ALD
ruthenium and ALD titanium nitride), and testing shows that ALD ruthenium can yield
much lower contact resistance over a longer lifetime (>100MΩ over 900,000 cycles).
Thermal modeling of the contact behavior can help to avoid welding by predicting the
voltage needed to melt the contact material. Finally, we show results from three-
terminal devices with buried aluminum interconnect, with either silicon nitride or
alumina etch stop. These devices show no significant degradation in performance
compared to devices without interconnect.
Chapter 5: Conclusion ········································································ 90
Chapter 5: Conclusion
Nanoelectromechanical relays show great promise for improving current circuit
design. Integrated CMOS-NEM relay systems can show improved performance over
CMOS-only designs for many applications, including logic, memory, signal routing and
charging. After a review of existing designs, we have discussed reasons for selecting
electrostatic, laterally-actuated, back-end-of-line compatible relays.
We then presented a CMOS-compatible process for fabricating relays. As a
proof of concept, we included a buried aluminum interconnect layer which was
protected by a silicon nitride or alumina etch stop layer. We then described the
fabrication of polysilicon germanium relays with ALD ruthenium or titanium nitride
contact layer. All processing steps ocurred under 425˚C which is an established thermal
limit for CMOS-compatible processing.
The fabricated relays are tested using a nitrogen glovebox with built-in heater.
We described important performance metrics for certain applications: contact
resistance, actuation voltages and hysteresis. By adjusting overdrive voltage, contact
time and drain-source voltages, we can observe some improvement in performance.
Higher overdrive voltages and wider hysteresis windows can be achieved using
partitioned beam design. Contact resistances below 500Ω have been achieved with
overdrive voltages near 80% with an ALD ruthenium contact layer, as shown in Figure
3.5. By etching the structural material near the contact area of the beam, we can increase
Chapter 5: Conclusion ········································································ 91
the contact area and reduce the contact resistance. For titanium nitride contact material
we have achieved contact resistance near 1.5kΩ with a hollow tip etch, compared to
contact resistances of several MΩ before the etch. We have seen cycling lifetime up to
9×105 cycles for deviecs with an ALD ruthenium contact layer, where the contact
resistance stays below 100MΩ, as shown in Figure 4.10, yielding an ION/IOFF ratio 100x
over its lifetime. Prior work has demonstrated electrostatic, laterally-actuated relays
with a lifetime of 108 cycles with greater than 1000x ION/IOFF ratio.[68] The relays
presented in [58] featured a polysilicon structural layer and platinum contact material,
and were tested in room air. However, this device is not composed of CMOS-
compatible materials and therefore would not be suitable for an integrated design.
Vertically actuated relays with poly-SiGe structural layer and tungsten contact material
with a thin titanium oxide coating have shown over 60 billion cycles with contact
resistance less than 100kΩ when tested in vacuum.[69]
Devices with high cylce lifetime such as these vertically-actuated relays are
promising for future work, and suggest that laterally actuated relays could achieve better
performance with further development. The tungsten contact material cannot be used
for laterally actuated switches because an extremely conformal deposition process is
required to coat the sidewall contact and no such process exists for tungsten material.
However, existing conformal coatings may be improved with the use of a titanium oxide
coating. Furthermore, the devices described in [69] have comparatively large footprint,
yielding a 10x larger actuation area compared to the lateral relays presented in this work.
From equation 1.1, we can see that leads to 10x larger contact force. Although this
Chapter 5: Conclusion ········································································ 92
larger footprint leads to lower contact resistance, it also lowers the device density
therefore cost of the design. Advanced modeling techniques, such as the thermal model
discussed in section 4.3, could lead to better performance without increase in size. By
softening the thin film at the contact, contaminants may be removed and total contact
area increased.
For the first time, we have demonstrated laterally-actuated, BEOL-compatible
NEM relays with a buried aluminum interconnect layer. The relays, which feature a
polysilicon germanium structural layer and ALD ruthenium contact layer, show promise
for future integrated CMOS-NEM relay designs. However, before the relays can be
fully integrated with CMOS systems, further improvements are required. The actuation
voltages of the NEM relays demonstrated here ranged from 15V-30V whereas most
integrated applications require actuation voltages less than 1V. Although the
dimensions of the devices presented here are limited by the lithographic resolution of
the available exposure tools, advanced lithography methods such as immersion
lithography or e-beam lithography can be used to scale the devices and achieve lower
actuation voltages. The process flow presented in section 2 are otherwise scalable to
any feature size. Another challenge that must be overcome is the high contact resistance
seen in many devices. Although we have shown resistances <1kΩ using high overdrive
voltages, this solution is not feasible for applications that require low actuation voltages.
Improved contact performance can be achieved by using protective contact coatings
(such as the titanium oxide coating used in [68]), or encapsulation in a clean, dry, non-
reactive environment.
Chapter 5: Conclusion ········································································ 93
As CMOS transistors scale to smaller dimensions, leakage current in the off-
state will become a bigger issue. A solution to the poor energy efficiency of CMOS-
based circuits will be especially troublesome for wireless technologies, as exemplified
by the “Internet of Things” movement.[70] Designers will not be willing to implant
large numbers of sensors in a wide variety of objects if the sensors are contantly draining
their power source. NEM relays offer a solution to the looming energy efficiency crisis
in modern electronics. With continued development, including the advancements
presented in this thesis, NEM relays offer exciting opportunities for the future of
integrated circuit design.
Appendix A: Fabrication Details ··························································· 94
Appendix A: Fabrication of Poly-
SiGe NEM Relays with Buried
Interconnect
A.1 Buried Interconnect
To form the insulation layer, we deposit a 2 μm silicon oxide using an LPCVD
system (tylanBPSG) at 400˚C over 2.5 hours (SiH4 = 85 sccm, O2 = 120 sccm, Pressure
= 200 mTorr). The thickness of the silicon oxide layer is measured using the
Nanometrics Nanospec 210XP spectro-reflectometry tool. . A diagram of the deposited
silicon oxide insulation layer is shown in Figure 3.2.
To etch the interconnect pattern into the silicon oxide insulation layer, we first
create a resist mask using photolithography. We coat the silicon oxide in
hexamethyldisilazane (HMDS) to improve adhesion of the resist to the silicon oxide,
then coat the wafer in 1.6μm of Shipley 3612 resist and bake for 120 seconds at 90˚C.
We use an ASML PAS 5500/60 i-Line 5:1 reducing stepper to expose the resist using
the first lithography mask. After exposure, we bake at 110 ˚C for 90 seconds, develop
and bake at 110 ˚C for 120. We then UV bake the resist for 15 minutes, followed by a
60 minute bake at 110 ˚C.
Appendix A: Fabrication Details ··························································· 95
To etch the silicon oxide, we use Applied Materials Technologies 8100 Hexode
plasma RIE system to directionally etch the trenches. We use the standard oxide etch
recipe (O2 = 6sccm, CHF3 = 85 sccm, DC Bias = -530V DC, Max RF = 1600W,
Pressure = 40mTorr) for 30 minutes to achieve a trench depth of 1 μm. Special care
must be taken to ensure that the etch depth does not approach the thickness of the silicon
oxide, otherwise shorting may occur between the interconnect structures and silicon
substrate. Lastly, we remove the photoresist using the Gasonics Aura Plasma Asher and
clean the wafer by soaking in heated piranha solution for 20 minutes and performing a
standard RCA clean.
Before depositing the aluminum, we must deposit a thin layer of silicon
nitride, which will act as a stopping layer during the planarization step. We use the
PlasmaTherm Shuttlelock SLR-730-PECVD tool (CCP) to deposit 250nm of silicon
nitride at 300˚C over 17 minutes (RF Power = 100W, Pressure =950mTorr, SiH4 = 200
sccm, NH3 = 6 sccm, He = 1000 sccm, N2 = 400 sccm). A diagram showing the etched
silicon oxide with SiN planarization stopping layer is shown in Figure 3.3.
The aluminum is then sputtered using the Intlvac Nanochrome I Sputter System
in Dual AC mode. We deposit 1.5μm of Al-2%Si on top of the silicon nitride layer (Ar
= 7.5 sccm, AC Setpoint = 250W, Warm Up = 5 minutes, Deposition Time = 2.5 hours).
We then perform a planarization process to remove excess aluminum from
above the trenches. We use the POLI 400L CMP system, which includes a torque sensor
in the spindle which allows us to sense when the polish has reached the silicon nitride.
Appendix A: Fabrication Details ··························································· 96
We polish for 75seconds, rotate the wafer in the chuck, then polish for another 55
seconds using Ultra-Sol S-10 slurry with a polishing pressure of 250g/cm. We must
find the optimal polish time that not only clears the aluminum from outside of the
trenches but also does not over polish the aluminum, which could cause dishing and
create an uneven surface. After rinsing the wafer, we confirm isolation of the
interconnect structures both visually and electrically using a multimeter. A diagram of
the aluminum interconnects after the planarization step is shown in Figure 3.4.
Before any subsequent processing, we must clean the slurry completely from the
wafer. We soak the wafers for 5 minutes in a hydrochloric acid solution (5:1:1
H2O:H2O2:HCl) and rinse, followed by 5 minutes in an ammonium hydroxide solution
(5:1:1 H2O:H2O2:NH4OH) and rinse. After thoroughly drying the samples, we soak
them for 20 minutes in PRS-1000, followed by a rinse and dry step. Finally, we encase
the aluminum in 1μm of silicon oxide, which forms a buried silicon oxide layer, using
the PlasmaTherm PECVD tool at 300˚C over 13 minutes (RF Power = 200W, Pressure
=1100mTorr,SiH4 = 250 sccm, He = 800 sccm, N2O = 1700 sccm) ..
A.2 Release Layer Deposition and Via Etch
After encasing the aluminum interconnect in oxide, we deposit the SiN release
stop using the PlasmaTherm PECVD. The silicon nitride film is deposited at 300˚C
over 17 minutes to achieve a 250nm film, using the same recipe as described previously
for the silicon nitride planarization stopping layer in section A.1 .
Appendix A: Fabrication Details ··························································· 97
We deposit the silicon oxide release layer using either PECVD or LPCVD. The
PECVD silicon oxide sacrificial layer is deposited at 300˚C over 20 minutes to achieve
a 1.5μm film, using the same recipe previously described in section A.1 to deposit the
buried silicon oxide layer. The LPCVD silicon oxide is deposited at 400˚C over 2.5
hours to achieve a 1.5μm film, using the same recipe previously described in section
A.1 to deposit the insulation layer. It is important that the etch selectivity between the
silicon oxide and silicon nitride in hydrofluoric acid is high. We have measured an etch
rate of 15nm/min for silicon nitride and 450nm/min for the PECVD silicon oxide,
yielding a 30:1 etch selectivity. For the LPCVD oxide, the etch rate is approximately
300 nm/min, yielding a 20:1 etch selectivity.
Next, we create a resist mask for the via etch. We begin by coating the sacrificial
oxide with HMDS, followed by 1.6μm 3612 Shipley photoresist and a post exposure
bake at 90˚C for 120 seconds. We then use the second lithography mask to expose the
resist with the via pattern using the ASML stepper. After exposure, we bake at 110 ˚C
for 90 seconds, develop and bake at 110 ˚C for 120. We then UV bake the resist for 15
minutes, followed by a 60 minute bake at 110 ˚C.
We etch the vias through the silicon oxide and silicon nitride using the Applied
Materials Technologies RIE etcher. We achieve a through etch to the aluminum using
the standard oxide recipe (described previously in section A.1) over 55 minutes. We
clean any residual oxide on the aluminum using a brief (~5 second) soak in 50:1 buffered
Appendix A: Fabrication Details ··························································· 98
oxide etch (BOE). We then clear the resist using the Gasonics Aura Plasma Asher,
followed by a 10 minute soak in heated PRS-1000.
A.3 Structural Layer Deposition and Etch
We deposit a TiN barrier layer to prevent spiking of the aluminum into the
silicon germanium. We use the Cambridge Nanotech Fiji F202 ALD with a plasma-
enhanced deposition recipe at 250˚C. The precursors for the recipe are
Tetrakis(dimethylamido)-titanium(IV) and nitrogen plasma. The pulse time is 0.25
seconds. The nitrogen plasma is turned on for 20 seconds at 300W. The flow rates for
the carrier gases are 50 sccm of Nitrogen and 200 sccm of argon. A 20nm thick TiN
film is deposited over 400 cycles. Importantly, after the TiN is deposition the samples
are allowed to reach room temperature in the load lock in vacuum over one hour. The
deposited film features a film resistivity of approximately 1500 μΩ-cm. All vias are a
uniform size 5μm × 5μm, which yields a total resistance of 0.015Ω for each via. We do
not expect the vias to contribute substantially to the overall resistance of the device.
We then deposit the polycrystalline silicon germanium (SiGe) layer using the
Tystar20 tool at Berkeley’s Marvell Nanolab with recipe “SigeNUCF”: temperature =
425˚C, pressure = 400mTorr, SiH4 = 190 sccm, GeH4 = 17 sccm, BCl3 = 50 sccm). No
seed layer was required. A deposition time of 8 hours yields a 1.8μm thick film.
We choose to use a silicon oxide hard mask in order to achieve better etch
selectivity. After deposition of the structural layer, we deposit a 220nm layer of silicon
Appendix A: Fabrication Details ··························································· 99
oxide using the PlasmaTherm Shuttlelock SLR-730-PECVD tool (CCP). The silicon
oxide is deposited at 350˚C over 3 minutes (RF Power = 200W, Pressure
=1100mTorr,SiH4 = 250 sccm, He = 800 sccm, N2O = 1700 sccm) .
After deposition of the silicon oxide layer, we coat the wafers with HMDS to
promote adhesion of the photoresist to the oxide hard mask. Next, we spin 0.7 μm SPR
955 CM-.7 I-Line photoresist and pre-bake at 90˚C for 120 seconds. We use an ASML
PAS 5500/60 i-Line 5:1 reducing stepper exposure tool to pattern the photoresist using
the third lithography mask. After performing a post-exposure bake at 110˚C for 90
seconds, we develop the resist and perform a hard bake at 100˚C for 120 seconds,
followed by a 15 minute UV bake and 60 minute bake at 90 ˚C. We transfer the pattern
to the silicon oxide hard mask using a AMT 8100 RIE etcher. We then transfer the
pattern to the SiGe using a Lam Research 9400 TCP Poly RIE etcher, which has been
selected because of its ability to perform very vertical etches in silicon. We use a custom
etch recipe with Cl2, HBr, O2 chemistry (Pressure = 10mTorr, TCP RF = 250W, Bias
RF = 60W, Cl2 = 40 sccm, HBr = 100 sccm, O2 = 5 sccm). The etch time for 1.8 μm
SiGe layer using this etch recipe was 290 seconds. A diagram of a device after the
structural layer etch is shown in Figure Y7, and an SEM image of a cross-section after
the silicon germanium etch is shown in Figure Y8..
We then clean the sample by first ashing the resist using the Gasonics plasma
asher. We then soak the sample in heated PRS-1000 for 10 minutes to remove any
organic residue, followed by a rinse in water.
Appendix A: Fabrication Details ·························································· 100
A.4 Contact Layer Deposition and Etch
A.4.1 Titanium nitride Deposition
Titanium nitride is a ceramic with excellent wear properties. We deposit
titanium nitride with the Cambridge Nanotech Fiji F202 ALD system. We use the
plasma enhanced deposition recipe at 250˚C, as previously described in section Y.6. A
25nm thick film is deposited over 500 cycles. As before, the sample is allowed to
stabilize to room temperature in the load lock under vacuum before it is removed from
the tool.
A.4.2 Ruthenium Deposition
Ruthenium is a metallic material that is attractive because it has a conductive
oxide. We deposit ruthenium with the Cambridge Fiji atomic layer deposition system.
We use a thermal deposition recipe at 270˚C. The precursors for the recipe are
Bis(ethylcyclopentadienyl)ruthenium(II), oxygen and hydrogen. The pulse time is 5
seconds, and the flow rates for the plumbed gases are: Ar = 30 sccm and O2 = 200 sccm.
The A 50nm thick film is deposited over 800 cycles. Like the TiN film, the samples are
allowed to reach room temperature in the load lock in vacuum after the deposition. The
deposited film featured a film resistivity of 120 μΩ-cm.
A.4.3 Contact Layer Etch
Appendix A: Fabrication Details ·························································· 101
We deposit a 220nm PECVD silicon oxide hard mask in order to provide better
etch selectivity and also to protect the sidewall contact surfaces from contaminants from
the photoresist. We use the same recipe for PECVD silicon oxide as the structural layer
hard mask described in section Y.7. After deposition of the silicon oxide hard mask,
we coat the wafer with HMDS to promote adhesion of the photoresist. We then coat
the wafer with 1.6μm Shipley 3612 photoresist and pre-exposure bake for 120 seconds
at 90C. The fourth lithography mask is used to pattern the photoresist, again using the
ASML stepper exposure tool. After exposure, we bake at 110 ˚C for 90 seconds,
develop and bake at 110 ˚C for 120. We then UV bake the resist for 15 minutes,
followed by a 60 minute bake at 110 ˚C.
The pattern is transferred to the silicon oxide layer using the Plasmatherm
Versaline LL-ICP Oxide etcher. We use a custom recipe Ar, CF4 and CHF3 chemistry
to etch through to the underlying contact layer (Pressure = 20 mTorr, Ar = 80 sccm,
CF4 = 50 sccm, CHF3 = 20 sccm, Bias RF Forward Power = 150W, ICP RF Forward
Power = 400W). We can confirm that the oxide etch is completed using a multimeter
to probe the open areas: conductivity indicates that the metal is exposed. We then strip
the resist using the matrix plasma asher and soaking in heated PRS-1000 for 10 minutes.
We then perform the directional etch of the contact material using the
Plasmatherm Versaline LL-ICP Metal Etcher. We have created custom recipes to etch
both ALD titanium nitride and ruthenium contact materials. The titanium nitride etch
recipe uses Cl3, BCl3 and N2 etch chemistry (Pressure = 10 mTorr, Cl2 = 50 sccm,
Appendix A: Fabrication Details ·························································· 102
BCl3 = 50 sccm, N2 = 10 sccm, Bias RF Power = 150W, ICP RF Forward Power =
1000). The etch time was 20 seconds. The ruthenium etch recipe features Cl2, O2 and
Ar chemistry (Pressure = 7mTorr, Cl2 = 20 sccm, O2 = 80 sccm, Ar = 20 sccm, Bias
RF Power = 100W, ICP RF Forward Power = 500W). The etch time was approximately
100s. After etching the ALD ruthenium, we must also etch the ALD titanium nitride
barrier layer underneath the structural layer. We use the same recipe as previously
described to etch the titanium nitride contact layer, with an etch time of 50 seconds.
Using a multimeter, we can confirm that the contact layer has been successfully
removed in the open areas of the pattern. We can also use a XeF2-based etch to remove
the structural layer in the open areas in order to view the sidewall. Figure X shows an
SEM image of a device which has undergone a XeF2 etch using the Xactix e-1 etcher
system.
A.5 Sacrificial Layer Etch and Release
A.5.1 Liquid HF Release
To remove the silicon oxide and release the compliant structures, the devices are
soaked in a solution of 49% hydrofluoric acid and 51% water for approximately 30
seconds. The devices are then rinsed in 3 separate beakers of water, then transferred to
a bath of isopropanol in preparation for the critical point dry step.
After the etch step, we must remove the fluid from around the structures. A
critical point dry step prevents capillary forces from damaging the devices as they dry.
Appendix A: Fabrication Details ·························································· 103
After the soak in liquid HF, the devices are allowed to soak in isopropanol for 1 hour to
remove any remaining acid residue. Then the devices are dried using a critical point
dryer (Tousimis Automegasamdri 915B). After the critical point dry step, the devices
are ready for testing. A diagram of a fully released device is shown in Figure 3.15, and
an SEM cross-section of a released device with interconnect is shown in Figure 3.16. If
the devices cannot be tested immediately after release, they are stored in a low vacuum
environment.
A.5.2 Vapor-HF Release
To etch the silicon oxide sacrificial layer usin vapor-phase HF, we use the SPTS
Primaxx μEtch system. We use an existing recipe developed by the tool manufacturer
(Pressure = 125 Torr, Temperature = 45˚C, N2 = 1425 sccm, EtOH = 210 sccm, HF =
190 sccm). An etch time of 150 seconds over 1 cycle resulted in working, released
devices.
A.6 Polycrystalline Germanium Release Layer
After deposition of the silicon oxide sacrificial layer, a polycrystalline
germanium (Ge) film is deposited using LPCVD (thermcopoly1 “PGE” recipe:
Temperature = 400˚C, Pressure = 400 mTorr, GeH4 = 50 sccm). A deposition time of
2 hours yields a film thickness 1.3 μm. The thickness of the film is measured after it is
etched using an Alphastep 500 Profilometer to measure the step height.
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A.7 Alumina Sacrificial Etch Stop
After deposition of the buried oxide layer, the alumina film is deposited using
the Cambridge Nanotech Fiji F202 ALD system with a thermal ALD process. The
recipe precursors are Trimethylaluminum (CH3)3Al (ie – TMA) and H2O. The pulse
time is 0.06 seconds of TMA and 0.06 seconds of H2O, and the flow rate of Ar is 30
sccm. A 25nm thick alumina film is deposited over 250 cycles at 250˚C.
After deposition of the sacrificial silicon oxide layer, we must etch through the
alumina as part of the via etch, which is described in section A.2. After etching through
the silicon oxide sacrificial layer, we then etch the alumina using a Plasmatherm
Versaline LL-ICP Metal Etcher. The alumina etch recipe uses BCl3 etch chemistry
(Pressure = 4 mTorr, BCl3 = 15 sccm, Bias RF Forward Power = 50W, ICP RF Forward
Power = 600W), with an etch time of 60 seconds. After the alumina etch, buried silicon
oxide can be accessed and etched to finish the via opening, as before. Subsequent
processing steps (structural layer deposition and etch, contact layer deposition and etch)
can be performed as previously described.
Appendix B: Vacuum Probe Station Details ············································· 105
Appendix B: Vacuum Probe
Station Details
Control of ambient testing conditions is essential to long lifetime and good
performance of NEM relays. Although encapsulated devices are not presented in this
work, other methods of ambient control are presented. In addition to a nitrogen
glovebox, a vacuum station is used to test devices.
B.1 Physical Description
The vacuum chamber includes a 4 axis positioner (VG Scienta) with a custom-
designed chip holder which allows translation of the chip in 3 axes plus rotation in the
plane of the chip. The chip holder also incorporates a resistive heating element and
thermocouple, which is controlled with a VG Scienta RHS temperature controller. A
50-pin probe card is rigidly affixed to the underside of the chamber door. Vacuum
compatible cables connect to two 25-pin electrical feedthrough connectors set in the
walls of the chamber. Once the vacuum chamber door is closed, the chip can be
repositioned until the probe card pins make contact with the device probe pads. A
Scienscope camera provides real-time magnification for alignment of the chip to the
probe card. A desktop computer displays the camera view and controls the turbo pump.
Appendix B: Vacuum Probe Station Details ············································· 106
Figure B.1: Image of open vacuum chamber door. The 50-pin probe card and
chip holder are visible.
Figure B.2: Probe card pin layout. The probe pads are assumed to be
100μm with 50μm spacing between each pad.
Appendix B: Vacuum Probe Station Details ············································· 107
The vacuum chamber can reach 1e-5 Torr vacuum pressure. An Agilent IDP-3
dry scroll pump can attain pressures near 1e-2 Torr. After reaching roughing pressure,
an Agilent Turbo-V 81-M turbo pump can reach pressures below 1e-5 Torr. Two
pressure sensors are used: An Instrutech convection vacuum gauge (CVG101GF) senses
pressures between atmospheric and 1e-4 Torr, and a Duniway cold cathode vacuum
gauge (CCG-525-CFF) senses pressures down to 1e-8 Torr. The Terranova Model 960
vacuum gauge controller manages the pressure measurement between the two sensors,
and provides a readout display of the pressure.
Figure B.3: Image of vacuum probe station. The vacuum chamber,
temperature controller and desktop PC are visible.
Appendix B: Vacuum Probe Station Details ············································· 108
Once vacuum pressure is achieved, the chamber can be backfilled with any
desired gas. Currently, the station is set up to backfill with pure nitrogen or room air.
B.2 Electrical Measurements
Many methods may be used to test devices inside the vacuum chamber. Using
the electrical feedthroughs, any connector can be adapted to manage the signals to or
from the inividual probes in the probe card.
In this work, we use the Keithley 4200-SCS parameter analyzer to test the
devices inside the chamber. However, this test-set up will not be adequate for multi-
relay circuits that require simultaneous connection to more than 5 pins of the probe card.
Future work involves testing multi-relay circuits using a custom built controller.
Bibliography ·················································································· 109
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