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© Semiconductor Components Industries, LLC, 2010
August, 2020− Rev. 61 Publication Order Number:
NCP1529/D
Buck Converter - DC-DC,High Efficiency, AdjustableOutput Voltage, Low Ripple1.7 MHz, 1 A
NCP1529The NCP1529 step−down DC−DC converter is a monolithic
integrated circuit for portable applications powered from one cellLi−ion or three cell Alkaline/NiCd/NiMH batteries. The device is ableto deliver up to 1.0 A on an output voltage range externally adjustablefrom 0.9 V to 3.9 V or fixed at 1.2 V or 1.35 V. It uses synchronousrectification to increase efficiency and reduce external part count. Thedevice also has a built−in 1.7 MHz (nominal) oscillator which reducescomponent size by allowing a small inductor and capacitors. Automaticswitching PWM/PFM mode offers improved system efficiency.
Additional features include integrated soft−start, cycle−by−cyclecurrent limiting and thermal shutdown protection.
The NCP1529 is available in a space saving, low profile2x2x0.5 mm UDFN6 package and TSOP−5 package.
Features• Up to 96% Efficiency
• Best In Class Ripple, including PFM mode
• Source up 1.0 A
• 1.7 MHz Switching Frequency
• Adjustable from 0.9 V to 3.9 V or Fixed at 1.2 V or 1.35 V
• Synchronous rectification for higher efficiency
• 2.7 V to 5.5 V Input Voltage Range
• Low Quiescent Current 28 �A
• Shutdown Current Consumption of 0.3 �A
• Thermal Limit Protection
• Short Circuit Protection
• All Pins are Fully ESD Protected
• These are Pb−Free Devices
Typical Applications• Cellular Phones, Smart Phones and PDAs
• Digital Still Cameras
• MP3 Players and Portable Audio Systems
• Wireless and DSL Modems
• USB Powered Devices
• Portable Equipment
GND
VIN
EN
SW
FBOFF ON
VIN
CIN COUT
R1
R2
Cff
Figure 1. Typical Application for Adjustable Version
L VOUT
GND
VIN
EN
SW
FBOFF ON
VIN
CIN COUT
Figure 2. Typical Application for Fixed Version
LVOUT
TSOP−5SN SUFFIXCASE 483
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MARKINGDIAGRAM
15
DXJ = Specific Device CodeA = Assembly LocationY = YearW = Work Week� = Pb−Free Package(Note: Microdot may be in either location)
1
5
DXJAYW�
�
XXM�
�
123
654
UDFN6MU SUFFIX
CASE 517AB
XX = Specific Device CodeM = Date Code� = Pb−Free Package(Note: Microdot may be in either location)
See detailed ordering and shipping information in the packagedimensions section on page 14 of this data sheet.
ORDERING INFORMATION
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PIN FUNCTION DESCRIPTION
PinTSOP−5
PinUDFN6 Pin Name Type Description
1 6 EN Analog Input Enable for switching regulators. This pin is active HIGH and is turned off bylogic LOW on this pin.
2 2,4,7(Note 1)
GND Analog /Power Ground
This pin is the GND reference for the NFET power stage and the analogsection of the IC. The pin must be connected to the system ground.
3 5 SW Analog Output Connection from power MOSFETs to the Inductor.
4 3 VIN Analog /Power Input
Power supply input for the PFET power stage, analog and digital blocks. Thepin must be decoupled to ground by a 4.7 �F ceramic capacitor.
5 1 FB Analog Input Feedback voltage from the output of the power supply. This is the input to theerror amplifier.
1. Exposed pad for UDFN6 package, named Pin 7, must be connected to system ground.
Figure 3. Pin Connections − TSOP−5 Figure 4. Pin Connections − UDFN6
(Top View)
1
2
3
5
4
EN
GND
SW
FB
VIN
1
2
3
6
4
FB
GND
VIN
EN
GND
PIN CONNECTIONS
5 SW7
(Top View)
PERFORMANCES
Figure 5. Efficiency vs Output CurrentVIN = 3.6 V, VOUT = 3.3 V
100
90
80
70
60
50
40
30
20
10
00 500 1000
IOUT (mA)
EF
FIC
IEN
CY
(%
)
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FUNCTIONAL BLOCK DIAGRAM
GND
VINVbattery
4.7 �F
ENEnable
LOGICCONTROL
& THERMALSHUTDOWN
PWM/PFMCONTROL
ILIMIT
REFERENCEVOLTAGE
FB
SW
Q1
10 �F
18 pFR1
R2
2.2 �HQ2
Figure 6. Simplified Block Diagram
NCP1529
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MAXIMUM RATINGS
Rating Symbol Value Unit
Minimum Voltage All Pins Vmin −0.3 V
Maximum Voltage All Pins (Note 2) Vmax 7.0 V
Maximum Voltage EN Vmax VIN + 0.3 V
Thermal Resistance, Junction−to−Air (TSOP−5 Package)Thermal Resistance using TSOP−5 Recommended Board Layout (Note 9)
R�JA 300110
°C/W
Thermal Resistance, Junction−to−Air (UDFN6 Package)Thermal Resistance using UDFN6 Recommended Board Layout (Note 9)
R�JA 22040
°C/W
Operating Ambient Temperature Range (Notes 7 and 8) TA −40 to 85 °C
Storage Temperature Range Tstg −55 to 150 °C
Junction Operating Temperature (Notes 7 and 8) Tj −40 to 150 °C
Latchup Current Maximum Rating (TA = 85°C) (Note 5) Other Pins Lu �100 mA
ESD Withstand Voltage (Note 4)Human Body ModelMachine Model
Vesd2.0200
kVV
Moisture Sensitivity Level (Note 6) MSL 1 per IPC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.2. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25°C.3. According to JEDEC standard JESD22−A108B.4. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) per JEDEC standard: JESD22−A114.Machine Model (MM) per JEDEC standard: JESD22−A115.
5. Latchup current maximum rating per JEDEC standard: JESD78.6. JEDEC Standard: J−STD−020A.7. In applications with high power dissipation (low VIN, high IOUT), special care must be paid to thermal dissipation issues. Board design
considerations − thermal dissipation vias, traces or planes and PCB material − can significantly improve junction to air thermal resistanceR�JA (for more information, see design and layout consideration section). Environmental conditions such as ambient temperature TA bringsthermal limitation on maximum power dissipation allowed.The following formula gives calculation of maximum ambient temperature allowed by the application:TA MAX = TJ MAX − (R�JA x Pd)Where: TJ is the junction temperature,
Pd is the maximum power dissipated by the device (worst case of the application),and R�JA is the junction−to−ambient thermal resistance.
8. To prevent permanent thermal damages, this device include a thermal shutdown which engages at 180°C (typ).9. Board recommended TSOP−5 and UDFN6 layouts are described on Layout Considerations section.
Figure 7. Maximum Output Current, TA = 45�C
0
200
400
600
800
1000
1200
−40 −20 0 20 40 60 80TA, AMBIENT TEMPERATURE (°C)
PD
, PO
WE
R D
ISS
IPA
TIO
N (
mW
)
Figure 8. Power Derating
TSOP−5
UDFN6
0
200
400
600
800
1000
1200
2.7 3.2 3.7 4.2 4.7 5.2
VIN, INPUT VOLTAGE (V)
I OU
Tm
ax, M
AX
IMU
M O
UT
PU
T C
UR
-R
EN
T (
mA
)
TSOP−5
UDFN6
NCP1529
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ELECTRICAL CHARACTERISTICS (Typical values are referenced to TA = +25°C, Min and Max values are referenced −40°C to+85°C ambient temperature, unless otherwise noted, operating conditions VIN = 3.6 V, VOUT = 1.2 V, unless otherwise noted.)
Rating Conditions Symbol Min Typ Max Unit
INPUT VOLTAGE
Input Voltage Range Vin 2.7 − 5.5 V
Quiescent Current No Switching, No load IQ − 28 39 �A
Standby Current EN Low ISTB − 0.3 1.0 �A
Under Voltage Lockout VIN Falling VUVLO 2.2 2.4 2.55 V
Under Voltage Hysteretis VUVLOH − 100 − mV
ANALOG AND DIGITAL PIN
Positive going Input High Voltage Threshold VIH 1.2 − − V
Negative going Input High Voltage Threshold VIL − − 0.4 V
EN Threshold Hysteresis VENH − 100 − mV
EN High Input Current EN = 3.6 V IENH − 1.5 − �A
OUTPUT
Feedback Voltage Level Adjustable VersionFixed Version at 1.2 VFixed Version at 1.35 V
VFB −−−
0.61.21.35
−−−
V
Output Voltage Range (Notes 10, 11)USB or 5 V Rail Powered Applications(VIN from 4.3 V to 5.5 V) (Note 12)
VOUT 0.90.9
−−
3.33.9
V
Output Voltage Accuracy Room Temperature (Note 13)Overtemperature Range
�VOUT −−3
�1�2
−+3
%
Maximum Output Current (Note 10) IOUTMAX 1 − − A
Output Voltage Load RegulationOvertemperature
Load = 100 mA to 1000 mA (PWM Mode)Load = 0 mA to 100 mA (PFM Mode)
VLOADR −−
−0.91.1
−−
%
Load Transient ResponseRise/Fall Time 1 �s
10 mA to 100 mA Load Step(PFM to PWM Mode)200 mA to 600 mA Load Step(PWM to PWM Mode)
VLOADT −
−
40
85
−
−
mV
Output Voltage Line Regulation Load = 100 mA VIN = 2.7 V to 5.5 V VLINER − 0.05 − %
Line Transient Response Load = 100 mA 3.6 V to 3.2 V Line Step (Fall Time = 50 �s) VLINET − 6.0 − mVPP
Output Voltage Ripple IOUT = 0 mAIOUT = 300 mA
VRIPPLE −−
8.03.0
−−
mVPP
Switching Frequency FSW 1.2 1.7 2.2 MHz
Duty Cycle D − − 100 %
Soft−Start Time Time from EN to 90% of Output Voltage tSTART − 310 500 �s
POWER SWITCHES
High−Side MOSFET On−Resistance RONHS − 400 − m�
Low−Side MOSFET On−Resistance RONLS − 300 − m�
High−Side MOSFET Leakage Current ILEAKHS − 0.05 − �A
Low−Side MOSFET Leakage Current ILEAKLS − 0.01 − �A
PROTECTION
DC−DC Short Circuit Protection Peak Inductor Current IPK − 1.6 − A
Thermal Shutdown Threshold TSD − 180 − °C
Thermal Shutdown Hysteresis TSDH − 40 − °C
10.Functionality guaranteed per design and characterization.11. Whole output voltage range is available for adjustable versions only. By topology, the maximum output voltage will be equal or lower than
the input voltage.12.See chapter ”USB or 5 V Rail Powered Applications”.13.For adjustable versions only, the overall output voltage tolerance depends upon the accuracy of the external resistor (R1 and R2). Specified
value assumes that external resistor have 0.1% tolerance.
NCP1529
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TABLE OF GRAPHS
Typical Characteristics for Step−down Converter Figure
� Efficiency vs. Output Current 10, 11, 12
Iq ON Quiescent Current, PFM no load vs. Input Voltage 9
Iq OFF Standby Current, EN Low vs. Input Voltage 8
FSW Switching Frequency vs. Ambient Temperature 13
VLOADR Load Regulation vs. Load Current 14
VLOADT Load Transient Response 16, 17
VLINER Line Regulation vs. Output Current 15
VLINET Line Transient Response 18, 19
tSTART Soft Start 20
IPK Short Circuit Protection 21
VUVLO Under Voltage Lockout Threshold vs. Ambient Temperature 22
VIL, VIH Enable Threshold vs. Ambient Temperature 23
P, G Phase & Gain Performance 24
NCP1529
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I stb
, STA
ND
BY
CU
RR
EN
T (�A
)
2.5 3.0 3.5 4.0 4.5 5.0 5.50
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VIN, INPUT VOLTAGE (V)
Figure 9. Standby Current vs. Input Voltage(Enable = 0, Temperature = 25�C)
27
28
29
30
31
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VIN, INPUT VOLTAGE (V)
Figure 10. Quiescent Current vs. Input Voltage(Open Loop, Feedback = 1,
Temperature = 25�C)
I q, Q
UIE
SC
EN
T C
UR
RE
NT
(�A
)
0
10
20
30
40
50
60
70
80
90
100
0 200 400 600 800 1000
EF
FIC
IEN
CY
(%
)
IOUT, OUTPUT CURRENT (mA)
Figure 11. Efficiency vs. Output Current(VIN = 3.3 V, VOUT = 1.2 V)
25°C
85°C
−40°C
0
10
20
30
40
50
60
70
80
90
100
0 200 400 600 800 1000
EF
FIC
IEN
CY
(%
)
IOUT, OUTPUT CURRENT (mA)
Figure 12. Efficiency vs. Output Current(Vout = 1.2 V, Temperature = 25�C)
5.5 V
VBAT = 2.7 V3.3 V
EF
FIC
IEN
CY
(%
)
IOUT, OUTPUT CURRENT (mA)
Figure 13. Efficiency vs. Output Current(VIN = 3.6 V, Temperature = 25�C)
VOUT = 0.9 V
3.3 V
1.2 V
0
10
20
30
40
50
60
70
80
90
100
0 200 400 600 800 10001.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
−60 −20 20 60 100TA, AMBIENT TEMPERATURE (°C)
Figure 14. Switching Frequency vs. AmbientTemperature (Vout = 1.2 V, Iout = 200 mA)
SW
ITC
HIN
G F
RE
QU
EN
CY
(M
Hz)
VIN = 2.7 V
3.6 V5.5 V
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−3.0
−2.0
−1.0
0.0
1.0
2.0
3.0
0 200 400 600 800 1000
LOA
D R
EG
ULA
TIO
N (
%)
IOUT, OUTPUT CURRENT (mA)
Figure 15. Load Regulation vs. Output Current(VIN = 5.5 V, VOUT = 1.2 V)
25°C85°C
−40°C
−3.0
−2.0
−1.0
0
1.0
2.0
3.0
2.7 3.2 3.7 4.2 4.7 5.2
IOUT = 800 mA
100 mA
1 mA
VIN, INPUT VOLTAGE (V)
Figure 16. Line Regulation vs. Input Voltage(VOUT = 1.2 V, Temperature = 25�C)
LIN
E R
EG
ULA
TIO
N (
%)
Figure 17. 10 mA to 100 mA Load Transient in 1 �s(VIN = 3.6 V, VOUT = 1.2 V, Temperature = 25�C)
Figure 18. 200 mA to 600 mA Load Transient in 1 �s(VIN = 3.6 V, VOUT = 1.2 V, Temperature = 25�C)
Figure 19. 3.0 V to 3.6 V Line Transient, Rise = 50 �s(VIN = 1.2 V, IOUT = 100 mA, Temperature = 25�C)
Figure 20. 3.6 V to 3.0 V Line Transient, Fall = 50 �s(VIN = 1.2 V, IOUT = 100 mA, Temperature = 25�C)
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Figure 21. Typical Soft−Start (VIN = 3.6 V, VOUT = 1.2 V,IOUT = 100 mA, Temperature = 25�C)
Figure 22. Short−Circuit Protection (VIN = 3.6 V,VOUT = 1.2 V, IOUT = CC, Temperature = 25�C)
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
−50 −25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
Figure 23. Undervoltage Lockout Thresholdvs. Ambient Temperature
UN
DE
RV
OLT
AG
E L
OC
KO
UT
TH
RE
SH
OLD
(V
)
UVLOfall
UVLOrise
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
−40 −15 10 35 60 85
VIL
VIH
TA, AMBIENT TEMPERATURE (°C)
Figure 24. Enable Threshold Voltages vs.Ambient Temperature
EN
AB
LE T
HR
ES
HO
LD V
OLT
AG
ES
(V
)
−50
−30
−10
10
30
50
70
10 100 1000 10000 100000 1000000−160
−120
−80
−40
0
40
80
120
160
200
Phase
Gain
FREQUENCY (Hz)
Figure 25. Phase and Gain Performance(VIN = 3.6 V, VOUT = 1.2 V, IOUT = 200 mA, Temperature = 25�C)
GA
IN (
dB)
PH
AS
E (
°)
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DC/DC OPERATION DESCRIPTION
Detailed DescriptionThe NCP1529 uses a constant frequency, current mode
step−down architecture. Both the main (P−channelMOSFET) and synchronous (N−channel MOSFET)switches are internal.
The output voltage is set by an external resistor divider inthe range of 0.9 V to 3.9 V and can source at least 1A.
The NCP1529 works with two modes of operation;PWM/PFM depending on the current required. In PWMmode, the device can supply voltage with a tolerance of�3% and 90% efficiency or better. Lighter load currentscause the device to automatically switch into PFM mode toreduce current consumption and extended battery life.
Additional features include soft−start, undervoltageprotection, current overload protection and thermalshutdown protection. As shown on Figure 1, only sixexternal components are required. The part uses an internalreference voltage of 0.6 V. It is recommended to keepNCP1529 in shutdown mode until the input voltage is 2.7 Vor higher.
PWM Operating ModeIn this mode, the output voltage of the device is regulated
by modulating the on−time pulse width of the main switchQ1 at a fixed 1.7 MHz frequency.
The switching of the PMOS Q1 is controlled by a flip−flopdriven by the internal oscillator and a comparator thatcompares the error signal from an error amplifier with thesum of the sensed current signal and compensation ramp.
The driver switches ON and OFF the upper side transistor(Q1) while the lower side transistor is switched OFF thenON.
At the beginning of each cycle, the main switch Q1 isturned ON by the rising edge of the internal oscillator clock.The inductor current ramps up until the sum of the currentsense signal and compensation ramp becomes higher thanthe error amplifier’s voltage. Once this has occurred, thePWM comparator resets the flip−flop, Q1 is turned OFFwhile the synchronous switch Q2 is turned ON. Q2 replacesthe external Schottky diode to reduce the conduction lossand improve the efficiency. To avoid overall power loss, acertain amount of dead time is introduced to ensure Q1 iscompletely turned OFF before Q2 is being turned ON.
VOUT
ISW
Figure 26. PWM Switching Waveforms(VIN = 3.6 V, VOUT = 1.2 V, IOUT = 600 mA,
Temperature = 25�C)
VSW
PFM Operating ModeUnder light load conditions, the NCP1529 enters in low
current PFM mode of operation to reduce powerconsumption. The output regulation is implemented bypulse frequency modulation. If the output voltage dropsbelow the threshold of PFM comparator a new cycle will beinitiated by the PFM comparator to turn on the switch Q1.Q1 remains ON during the minimum on time of the structurewhile Q2 is in its current source mode. The peak inductorcurrent depends upon the drop between input and outputvoltage. After a short dead time delay where Q1 is switchedOFF, Q2 is turned in its ON state. The negative currentdetector will detect when the inductor current drops belowzero and sends a signal to turn Q2 to current source mode toprevent a too large deregulation of the output voltage. Whenthe output voltage falls below the threshold of the PFMcomparator, a new cycle starts immediately.
VOUT
ISW
Figure 27. PFM Switching Waveforms(VIN = 3.6 V, VOUT = 1.2 V, IOUT = 0 mA,
Temperature = 25�C)
VSW
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Soft−StartThe NCP1529 uses soft−start to limit the inrush current
when the device is initially powered up or enabled. Soft startis implemented by gradually increasing the referencevoltage until it reaches the full reference voltage. Duringstartup, a pulsed current source charges the internalsoft−start capacitor to provide gradually increasingreference voltage. When the voltage across the capacitorramps up to the nominal reference voltage, the pulsedcurrent source will be switched off and the reference voltagewill switch to the regular reference voltage.
Cycle−by−cycle Current LimitationFrom the block diagram, an ILIM comparator is used to
realize cycle−by−cycle current limit protection. Thecomparator compares the SW pin voltage with the referencevoltage, which is biased by a constant current. If the inductorcurrent reaches the limit, the ILIM comparator detects theSW voltage falling below the reference voltage and releasesthe signal to turn off the switch Q1. The cycle−by−cyclecurrent limit is set at 1600 mA (nom).
Low Dropout OperationThe NCP1529 offers a low input to output voltage
difference. The NCP1529 can operate at 100% duty cycle.In this mode the PMOS (Q1) remains completely ON. The
minimum input voltage to maintain regulation can becalculated as:
Vout � VOUT(max) � �IOUT�RDS(on)_RINDUCTOR
�� (eq. 1)
• VOUT: Output Voltage (V)
• IOUT: Max Output Current
• RDS(on): P−Channel Switch RDS(on)
• RINDUCTOR: Inductor Resistance (DCR)
Undervoltage LockoutThe Input voltage VIN must reach 2.4 V (typ) before the
NCP1529 enables the DC/DC converter output to begin thestart up sequence (see soft−start section). The UVLOthreshold hysteresis is typically 100 mV.
Shutdown ModeForcing this pin to a voltage below 0.4 V will shut down
the IC. In shutdown mode, the internal reference, oscillatorand most of the control circuitries are turned off. Therefore,the typical current consumption will be 0.3 �A (typicalvalue). Applying a voltage above 1.2 V to EN pin will enablethe DC/DC converter for normal operation. The device willgo through soft−start to normal operation.
Thermal ShutdownInternal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event that the maximumjunction Temperature is exceeded. If the junction
temperature exceeds 180°C, the device shuts down. In thismode all power transistors and control circuits are turnedoff. The device restarts in soft−start after the temperaturedrops below 140°C. This feature is provided to preventcatastrophic failures from accidental device overheating.
Short Circuit ProtectionWhen the output is shorted to ground, the device limits the
inductor current. The duty−cycle is minimum and theconsumption on the input line is 550 mA (typ). When theshort circuit condition is removed, the device returns to thenormal mode of operation.
USB or 5 V Rail Powered ApplicationsFor USB or 5 V rail powered applications, NCP1529 is
able to supply voltages up to 3.9 V, 600 mA, operating inPWM mode only, with high efficiency (Figure 28), lowoutput voltage ripple and good load regulation results overall current range (Figure 29).
40
45
50
55
60
65
70
75
80
85
90
95
100
0 200 400 600 800 1000
EF
FIC
IEN
CY
(%
)
IOUT, OUTPUT CURRENT (mA)
Figure 28. Efficiency vs. Output Current(VIN = 5.0 V, VOUT = 3.9 V)
25°C85°C
−40°C
−3.0
−2.5
−2.0
−1.5
−1.0
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 200 400 600 800 1000
LOA
D R
EG
ULA
TIO
N (
%)
IOUT, OUTPUT CURRENT (mA)
Figure 29. Load Regulation vs. Output Current(VIN = 5.0 V, VOUT = 3.9 V)
25°C85°C
−40°C
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APPLICATION INFORMATION
Output Voltage SelectionIn case of adjustable versions, the output voltage is
programmed through an external resistor divider connectedfrom VOUT to FB then to GND.
For low power consumption and noise immunity, theresistor from FB to GND (R2) should be in the [100k−600k]range. If R2 is 200 k given the VFB is 0.6 V, the currentthrough the divider will be 3.0 �A.
The formula below gives the value of VOUT, given thedesired R1 and the R1 value:
Vout � VFB � (1 � R1�R2) (eq. 2)
• VOUT: Output Voltage (V)
• VFB: Feedback Voltage = 0.6 V
• R1: Feedback Resistor from VOUT to FB
• R2: Feedback Resistor from FB to GND
Input Capacitor SelectionIn PWM operating mode, the input current is pulsating
with large switching noise. Using an input bypass capacitorcan reduce the peak current transients drawn from the inputsupply source, thereby reducing switching noisesignificantly. The capacitance needed for the input bypasscapacitor depends on the source impedance of the inputsupply.
The maximum RMS current occurs at 50% duty cyclewith maximum output current, which is IO, max/2.
For NCP1529, a low profile ceramic capacitor of 4.7 �Fshould be used for most of the cases. For effective bypassresults, the input capacitor should be placed as close aspossible to the VIN Pin
Table 1. LIST OF INPUT CAPACITORS
Manufacturer Part Number Case Size Value(�F)
DC Bias(V)
Technology
MURATA GRM15 series 0402 4.7 6.3 X5R
MURATA GRM18 series 0603 4.7 10 X5R
TDK C1608 series 0603 4.7 6.3 X5R
TDK C1608 series 0603 4.7 10 X5R
Output L−C Filter Design ConsiderationsThe NCP1529 operates at 1.7 MHz frequency and uses
current mode architecture. The correct selection of theoutput filter ensures good stability and fast transientresponse.
Due to the nature of the buck converter, the output L−Cfilter must be selected to work with internal compensation.For NCP1529, the internal compensation is internally fixedand it is optimized for an output filter of L = 2.2 �H andCOUT = 10 �F.
The corner frequency is given by:
f �1
2� L � COUT
�1
2� 2.2 �H � 10 �F� 34 kHz
(eq. 3)
The device operates with inductance value of 2.2 �H. Ifthe corner frequency is moved, it is recommended to checkthe loop stability depending of the accepted output ripplevoltage and the required output current. Take care to checkthe loop stability. The phase margin is usually higher than45°.
Table 2. L−C FILTER EXAMPLE
Inductance (L) Output Capacitor (COUT)
2.2 �H 10 �F
4.7 �H 4.7 �F
Inductor SelectionThe inductor parameters directly related to device
performances are saturation current and DC resistance andinductance value. The inductor ripple current (�IL)decreases with higher inductance:
�IL �VOUT
L � fSW
�1 VOUT
VIN
� (eq. 4)
• �IL: Peak to peak inductor ripple current
• L: Inductor value
• fSW: Switching frequencyThe saturation current of the inductor should be rated
higher than the maximum load current plus half the ripplecurrent:
IL(max) � IO(max) ��IL
2(eq. 5)
• IL(max): Maximum inductor current
• IO(max): Maximum Output currentThe inductor’s resistance will factor into the overall
efficiency of the converter. For best performances, the DCresistance should be less than 0.3 � for good efficiency.
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Table 3. LIST OF INDUCTORS
Manufacturer Part Number CaseSize(mm)
HeightMax(mm)
L(�H)
DCRTyp(�)
DCRMax(�)
Rated Current (mA)Inductance
Drop
Rated Current (mA)Temperature
Drop
Structure
COILCRAFT DO1605T-222 5.5 x 4.2 1.8 2.2 NA 0.070 1800 (-10%) 1700 (+40°C) Wire Wound
COILCRAFT EPL3015-222 3.0 x 3.0 1.5 2.2 0.082 0.094 1600 (-30%) 2000 (+40°C) Wire Wound
COILCRAFT EPL2014-222 2.0 x 2.0 1.4 2.2 0.120 0.132 1300 (-30%) 1810 (+40°C) Wire Wound
MURATA LQM2HPN2R2 2.5 x 2.0 1.0 2.2 0.080 0.100 NA 1300 (+40°C) Multilayer
MURATA LQH3NPN2R2 3.0 x 3.0 1.2 2.2 0.065 0.085 1150 (-30%) 1460 (+40°C) Wire Wound
MURATA LQH44PN2R2 4.0 x 4.0 1.8 2.2 0.049 0.059 2500 (-30%) 1800 (+40°C) Wire Wound
TDK MLP2520S2R2L 2.5 x 2.0 1.0 2.2 0.080 0.104 1300 (-30%) NA Multilayer
TDK VLS252010T2R2 2.0 x 1.6 1.2 2.2 0.158 0.190 1400 (-30%) 1100 (+40°C) Wire Wound
WURTH ELEC 744 029 002 2.8 x 2.8 1.35 2.2 0.088 0.105 1150 (-35%) 1700 (+40°C) Wire Wound
Output Capacitor SelectionSelecting the proper output capacitor is based on the
desired output ripple voltage. Ceramic capacitors with lowESR values will have the lowest output ripple voltage andare strongly recommended. The output capacitor requireseither an X7R or X5R dielectric.
The output ripple voltage in PWM mode is given by:
�VOUT � �IL �� 1
4 � fSW � COUT
� ESR� (eq. 6)
Table 4. LIST OF OUTPUT CAPACITORS
Manufacturer Part Number Case Size Value(�F)
DC Bias(V)
Technology
MURATA GRM15 series 0402 4.7 6.3 X5R
MURATA GRM18 series 0603 4.7 10 X5R
MURATA GRM18 series 0603 10 6.3 X5R
TDK C1608 series 0603 4.7 6.3 X5R
TDK C1608 series 0603 4.7 10 X5R
TDK C1608 series 0603 10 6.3 X5R
Feed−Forward Capacitor Selection (Adjustable Only)The feed-forward capacitor sets the feedback loop
response and acts on soft-start time. A minimum 18 pFfeed-forward capacitor is needed to ensure loop stability.
Having feed-forward capacitor of 1 nF or higher canincrease soft−start time and reduce inrush current. Choose asmall ceramic capacitor X7R or X5R or COG dielectric.
NCP1529
www.onsemi.com14
LAYOUT CONSIDERATIONS
Electrical Layout ConsiderationsImplementing a high frequency DC−DC converter
requires respect of some rules to get a powerful portableapplication. Good layout is key to prevent switchingregulators to generate noise to application and tothemselves.
Electrical layout guide lines are:• Use short and large traces when large amount of current
is flowing.• Keep the same ground reference for input and output
capacitors to minimize the loop formed by high currentpath from the battery to the ground plane.
• Isolate feedback pin from the switching pin and thecurrent loop to protect against any external parasiticsignal coupling. Add a feed−forward capacitor betweenVOUT and FB which adds a zero to the loop andparticipates to the good loop stability. A 18 pF
capacitor is recommended to meet compensationrequirements.A four layer PCB with a ground plane and a power plane
will help NCP1529 noise immunity and loop stability.
Thermal Layout ConsiderationsHigh power dissipation in small package leads to thermal
consideration such as:• Enlarge VIN trace and added several vias connected to
power plane.• Connect GND pin to top plane.
• Join top, bottom and each ground plane together usingseveral free vias in order to increase radiator size.
For high ambient temperature and high power dissipationrequirements, UDFN6 package using exposed padconnected to main radiator is recommended. Refer toNotes 7, 8, and 9.
Figure 30. TSOP−5 Recommended Board Layout Figure 31. UDFN6 Recommended Board Layout
VOUTTrace
FB Trace
SWTrace
VIN Trace
GND PlaneEN Trace
SWTrace
VOUTTrace
FB Trace
VIN Trace
GND Plane
EN Trace
ORDERING INFORMATION
DeviceNominal
Output Voltage Marking Package Shipping†
NCP1529ASNT1G* Adj DXJ TSOP−5 3000 / Tape & Reel
NCP1529MUTBG* Adj TL
UDFN6 3000 / Tape & ReelNCP1529MU12TBG** 1.2 V TC
NCP1529MU135TBG 1.35 V RC
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.
*Not recommended for new designs.**This device is End of Life. Please contact sales for additional information and assistance with replacement devices.
The product described herein (NCP1529), may be covered by the following U.S. patents: TBD. There may be other patents pending.
TSOP−5CASE 483ISSUE N
DATE 12 AUG 2020SCALE 2:1
1
5
XXX M�
�
GENERICMARKING DIAGRAM*
15
0.70.028
1.00.039
� mminches
�SCALE 10:1
0.950.037
2.40.094
1.90.074
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.
XXX = Specific Device CodeA = Assembly LocationY = YearW = Work Week� = Pb−Free Package
1
5
XXXAYW�
�
Discrete/LogicAnalog
(Note: Microdot may be in either location)
XXX = Specific Device CodeM = Date Code� = Pb−Free Package
NOTES:1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THEMINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLDFLASH, PROTRUSIONS, OR GATE BURRS. MOLDFLASH, PROTRUSIONS, OR GATE BURRS SHALL NOTEXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONALTRIMMED LEAD IS ALLOWED IN THIS LOCATION.TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2FROM BODY.
DIM MIN MAXMILLIMETERS
ABC 0.90 1.10D 0.25 0.50G 0.95 BSCH 0.01 0.10J 0.10 0.26K 0.20 0.60M 0 10 S 2.50 3.00
1 2 3
5 4S
AG
B
D
H
CJ
� �
0.20
5X
C A BT0.102X
2X T0.20
NOTE 5
C SEATINGPLANE
0.05
K
M
DETAIL Z
DETAIL Z
TOP VIEW
SIDE VIEW
A
B
END VIEW
1.35 1.652.85 3.15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ARB18753CDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1TSOP−5
© Semiconductor Components Industries, LLC, 2018 www.onsemi.com
ÍÍÍÍÍÍ
NOTES:1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP.4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE
TERMINALS.5. TIE BARS MAY BE VISIBLE IN THIS VIEW AND ARE CONNECTED TO
THE THERMAL PAD.
SEATINGPLANE
0.10 C
A3
A
A1
0.10 C
UDFN6 2x2, 0.65PCASE 517AB
ISSUE CDATE 10 APR 2013SCALE 4:1
DIMA
MIN MAXMILLIMETERS
0.45 0.55A1 0.00 0.05A3 0.127 REFb 0.25 0.35D 2.00 BSCD2 1.50 1.70
0.80 1.00E 2.00 BSCE2e 0.65 BSCL
--- 0.15L1
PIN ONEREFERENCE
0.08 C
0.10 C
6X
L
e
E2
b
3
6 6X
1
4
D2
GENERICMARKING DIAGRAM*
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.
XX = Specific Device CodeM = Date Code� = Pb−Free Package
XXM�
�
BOTTOM VIEW
0.25 0.35
L1
DETAIL A
L
ALTERNATE TERMINALCONSTRUCTIONS
L
ÉÉÉÉÉÉÇÇÇ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATECONSTRUCTIONS
ÉÉÉÉÇÇ
A1
A3
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.30
0.65
0.476X
DIMENSIONS: MILLIMETERS
0.40
1.70
PITCH
0.95
6X
1
PACKAGEOUTLINE
RECOMMENDED
TOP VIEW
SIDE VIEW
DETAIL B
NOTE 4
DETAIL A
END VIEW
AM0.10 BC
M0.05 C
D
E
A BNOTE 5
C
(Note: Microdot may be in either location)
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98AON22162DDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1UDFN6 2X2, 0.65P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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