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New LUMAT board. Fabio Giannuzzi - Filippo Giorgi – Mauro Villa Bologna Lucid meeting – 10th December 2013. Key points. Main goals Build new system on solid ground Same algorithms, same functionalities Basic idea: Duplicate ROD data and send them to a new LUMAT - PowerPoint PPT Presentation
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New LUMAT board
Fabio Giannuzzi - Filippo Giorgi – Mauro Villa
Bologna
Lucid meeting – 10th December 2013
Key points• Main goals
– Build new system on solid ground– Same algorithms, same functionalities
• Basic idea:– Duplicate ROD data and send them to a new
LUMAT– Same LUMAT main board– Update only the input mezzanines
• From mezzanine with 24+24 LVDs inputs to optical link mezzanines
• Provide ROD – Mezzanine protocols for lumi measurement 2
New LUMAT Board
• “Minimal changes”• (V2 Edro - ZDC)• “FTK“ input mezzanine
• HW tests to be done systematically
Rod A
Rod C
• New Lumat board• FTK mezzanines• LUCROD prototype– In sharing with other
activities.
Hardware under test in lab
Development plan• Ensure fixed latency serial communication over fibers
– Decide protocol to use Done– FTK mezzanine to FTK communication (Xilinx-Xilinx) Done– LUCROD to FTK communication (Altera-Xilinx)
Ongoing– FTK-to-FTK beam simulation Ongoing
• Development of FTK algo firmware Planned• Update of Stratix firmware to be started• Software integration to be started
• Need fixed requirement:– If you would like to add/change something, please say/write it
down now!
LUCROD-LUMAT Communication
LUCROD to LUMAT:•16 (PMT)+4(fibers) hit bits/BCID (clock tick)•Orbit Signal (marks the BCID=0 in the stream)•Data Valid/Live info•2 spare signals (handshake, lumi block transition)•Control words (parity and others) in the S-link protocol
LUMAT to ROD•Nothing (in principle); could be something like handshake, live info…
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Total: 24 bits
FTK-to-FTK serial tests
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Tests done using the same FPGA or 2 different FPGA with the same reference clock (40 MHz) but different transmission clocks
Full realistic chain on TX and RX side:TX: 32 bit @ 40 MHz -> dual clock FIFO-> 50 MHz rd clk
-> 16 bit data sent at 100 MHz with alignment wordsRX: received data at 100MHz, removed alignment words ->
32 bit data at 50 MHz -> dual clock FIFO 32 bit @ 40 MHz
No loss of sync; no loss of data.
• The SFP oscillator is not programmable yet– Minor issue: we can change the oscillator, but it will take
some time deferred– LUCROD prototype receives data on the optical link but it
does not send them out investigating
• Manpower is short and over-committed- for many reasons: so do not ask too many changes!
Known problems at the moment
Summary
• New LUMAT Card and LUCROD prototype already in our hands– Hardware tests yet to be done systematically– Firmware in the writing phase
• LUCROD-LUMAT serial protocol: – Protocol decided; in the implementation phase
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