Noise Canceling in 1-D Data: Presentation #7

Seri Rahayu Abd RaufFatima BoujarwahJuan ChenLiyana Mohd SharippArti Thumar

M2

Feb 28th, 2005Functional Block Layout/Floorplan

Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware

Project Manager: Bobby Colyer

Status

• Design proposal (Done)

• Architecture proposal (Done)

• Size Estimates and Floorplan (Done)

• Gate Level Design

- Schematics (Done)

• To be done:– Layout (35%)– Spice simulation

Design Decisions

• Successfully implemented Wallace + Booth

• Changed register design

Last week...

Updated Floorplan

Floating Point Adder (Vertical)

Floating Point Adder (Horizontal)

Wallace Tree (Before)

Wallace Tree + Booth Encoding

Barrel Shifter

Comparator

Add/Sub (FP Adder)

Register (16 bit)

Counter

Timing (FPA)

• Rise Time:• 65 picoseconds(10%-90%)

• Fall Time:• 56 ps

Updated Transistor Count

PartLast Week’s Transistors

New Transistors

16-bit FPA 3x 4154 = 12462 3x 2746 = 8238

16-bit FPM 3x 3858 = 11574 3x 4456 = 13368

Registers 7x16x14 = 1568 7x 272 = 1904

ROM 800 783

Converter 2x312 = 624 2x 108 = 216

MUX 384 402

Adder 248 248

Counter 214 222

Alternator 64 0

Total≈ 27938 + Misc ≈ 30000

≈ 25381 + Misc ≈ 27000

Challenges…

• Finishing up layout

• Make sure that the signal strength is sufficient

• Need to decide (multiplier) – symmetry vs. trans count

Questions?