NS9750 - Training Hardware. System Controller Module

NS9750 - Training

Hardware

System Controller Module

SCM: System Controller Module

The following features are contained in the SCM:• System clock generation• System level address decoding• AHB arbiter• AHB bus monitoring• Vectored interrupt controller• 16 Timer/Counter modules• Software watchdog timer• Bootstrap initialization• System power save sleep and wake up control

System Clock GenerationBlock Diagram

PLL

FN

FBM

FS[1:0]

ND[4:0]

CKOUT = 796.2624 MHzFBM = 398.1312 MHz

divider = FS = 2multiplier = ND + 1 = 27

CN

set bystrapping

OSC20MHz -

40MHz

BPNote, to use an external

oscillator, place a 100 ohmresistor in series between

the oscillator and x1

29.4

912

MH

z

x1_sys_osc

x2_sys_osc

div by2

fixed

div by4

fixed

div by 8fixed

cpu_clock (199.0656 MHz)

ahb_clock (99.5328 MHz)

bbus_clock (49.7664 MHz)

div by14, 12, 10 or 8

fixed by strapping

div by4, 8, 16, or 32configurable

lcd_clock(internal or external source)

lcd_clock_control (configurable)

pci_clk_control (configurable)

pci_clock_out

main clocksto modules

pci_clock (28.4379 MHz)

lcdclock

pci_clock_inpci_clk

CKOUT

MUL byND (27)

DIV byFS (2)

System Clock Generation

• The oscillator reference clock must be kept in the 20MHz to 40MHz range.

• The PLL frequency ( CKOUT) must be kept in the 400MHz to 800MHz range.

• The PLL can be bypassed via a hardware strapping option.

• The PLL settings can be modified by system software. A full chip reset will occur after the PLL settings have been modified.

System Level Address Decoding

External Chip Select• There are 8 external memory chip selects, 4 for

static type memories and 4 for dynamic type memories.

• The address space from 0x0000_0000 to 0x7FFF_FFFF is reserved for the 8 external memory chip selects.

• The specific address space for the 8 external chip selects can be rearranged via configuration registers in the SCM.


AHB Peripheral Address Decoding0x0000 0000 – 0x7FFF FFFF 2048 MB 8 External Chip Selects0x8000 0000 – 0x8FFF FFFF 256 MB PCI Memory0x9000 0000 – 0x9FFF FFFF 256 MB BBus Peripherals1

0xA000 0000 – 0xA00F FFFF 1 MB PCI IO0xA010 0000 – 0xA01F FFFF 1 MB PCI CONFIG_ADDR0xA020 0000 – 0xA02F FFFF 1 MB PCI CONFIG_DATA0xA030 0000 – 0xA03F FFFF 1 MB PCI Arbiter0xA040 0000 – 0xA04F FFFF 1 MB BBUS-to-AHB Bridge 0xA050 0000 – 0xA05F FFFF 1 MB Reserved0xA060 0000 – 0xA06F FFFF 1 MB Ethernet0xA070 0000 – 0xA07F FFFF 1 MB Memory Controller0xA080 0000 – 0xA08F FFFF 1 MB LCD Controller0xA090 0000 – 0xA09F FFFF 1 MB System Control Module 0xA0A0 0000 – 0xFFFF FFFF Reserved


BBus Peripheral Address Decoding0x9000 0000 – 0x900F FFFF 1MB BBUS DMA

0x9010 0000 – 0x901F FFFF 1MB USB

0x9020 0000 – 0x9020 003F 1MB SER Port #1

0x9020 0040 – 0x9020 007F 1MB SER Port #2

0x9030 0000 – 0x9030 003F 1MB SER Port #3

0x9030 0040 – 0x9030 007F 1MB SER Port #4

0x9040 0000 – 0x904F FFFF 1MB IEEE-1284

0x9050 0000 – 0x905F FFFF 1MB I2C

0x9060 0000 – 0x906F FFFF 1MB BBUS Utility

0x9070 0000 – 0x9FFF FFFF Reserved

AHB ArbiterBlock Diagram

ARM926I

D

EthernetMAC

Slv

PCI

Slv

Bbus

Slv

LCD

Slv

MemoryController

RegSlv

Slv1

EthernetMAC

Tx Rx

PCI

Mst

Bbus

Mst

LCD

Mst

Master Write Mux

Slave Read Mux

PCIArbSlv

SCM

SlvSlv0

Memory Controller: One port is for the CPU and the other port is for all other masters.Two ports are used to maximize the overall performance to the external memory.

AHB ArbiterExample Bandwidth Calculation

The bandwidth for the masters on the AHB arbiter is configurable via control registers in the SCM. The following example shows a typical

configuration.

Assumptions• 5 AHB masters – Ethernet Rx, Ethernet Tx, PCI, BBus, and LCD.• Memory clock frequency – 100MHz (max AHB clock frequency).• Average access time per 32-byte memory access – 16 clock cycles.• The ARM926 is guaranteed one half the total memory bandwidth (this

is accounted for in the “100MHz/2” part of the formula below).

Per Master Bandwidth Calculation[(100MHz/2) / (16clock cycles per access x 5masters)] x 32bytes

= 20 Mbytes/master

AHB Arbiter Example Bandwidth Calculation

Arbiter Configuration

If 20Mbytes per second meets the requirements of all of the masters, then the AHB arbiter will be programmed as follows.

BRC0[31:24] ARM926 BRC0[23:16] Ethernet RxBRC0[15:8] ARM926 BRC0[7:0] Ethernet TxBRC1[31:24] ARM926 BRC1[23:16] PCIBRC1[15:8] ARM926 BRC1[7:0] BBusBRC2[31:24] ARM926 BRC2[23:16] LCDBRC2[15:8] disabled BRC2[7:0] disabledBRC3[31:24] disabled BRC3[23:16] disabledBRC3[15:8] disabled BRC3[7:0] disabled


Now assume that the LCD master needs more than 20Mbytes, and the other masters need less than 20Mbytes. The new requirements are:

• Ethernet Rx - 12.5Mbytes

• Ethernet Tx - 12.5Mbytes

• PCI - 16Mbytes

• BBus - 4Mbytes

• LCD - 25Mbytes

• Total - 70Mbytes

New Per Master Bandwidth Calculation

[(100MHz/2) / (16clock cycles per access x 6masters)] x 32bytes

= 16.667 Mbytes/master


New Arbiter Configuration

The AHB arbiter will now be programmed as follows with the LCD module assigned 2 arbiter channel slots.

BRC0[31:24] ARM926 BRC0[23:16] Ethernet RxBRC0[15:8] ARM926 BRC0[7:0] Ethernet TxBRC1[31:24] ARM926 BRC1[23:16] LCD (first slot)BRC1[15:8] ARM926 BRC1[7:0] PCIBRC2[31:24] ARM926 BRC2[23:16] BBusBRC2[15:8] ARM926 BRC2[7:0] LCD (second

slot)BRC3[31:24] disabled BRC3[23:16] disabledBRC3[15:8] disabled BRC3[7:0] disabled

AHB Bus Monitoring

The following events can be programmed to cause a chip reset, interrupt, or save status only.

• AHB Bus Arbiter Timeout – triggers when the AHB bus is granted to a new master and the bus continues to be in the IDLE state for longer than the AHB Bus Arbiter Timeout Period configuration register.

• AHB Bus Monitor Timeout - triggers when a bus master starts a slave access and no slave acknowledges the bus access within the AHB Bus Monitor Timeout Period configuration register.

• AHB Slave Error Response Detect – triggers when a slave ERROR response type is received.

• AHB Max Burst Detect – triggered when burst transfers greater than the value programmed in the AHB Max Burst Detect Length configuration register.

Vectored Interrupt ControllerBlock Diagram

Interrupt Source 0Interrupt Source 1

Interrupt Source 31

Priority Level 1

Interrupt Assign ID Reg 1


Interrupt Source 31

Priority Level 0 (highest)



Interrupt Source 31

Priority Level 31 (lowest)


PriorityEncoder

IRQ

FIQ

Interrupt Vector Address Reg Level 1



Winning Priority Level

ISADDR Reg

Active Interrupt Level Reg

Vectored Interrupt Controller

SourcesInterrupt 0 – Watchdog TimerInterrupt 1 – AHB Bus ErrorInterrupt 2 – BBus Aggregate1

Interrupt 3 – reservedInterrupt 4 – Ethernet RxInterrupt 5 – Ethernet TxInterrupt 6 – Ethernet PhyInterrupt 7 – LCD Interrupt 8 – PCI Interrupt 9 – PCI Arbiter Interrupt 10 – PCI Ext Int 0Interrupt 11 – PCI Ext Int 1Interrupt 12 – PCI Ext Int 2Interrupt 13 – PCI Ext Int 3Interrupt 14 – I2CInterrupt 15 – BBus DMA

Interrupt 16 – Timer 0Interrupt 17 – Timer 1Interrupt 18 – Timer 2Interrupt 19 – Timer 3Interrupt 20 – Timer 4Interrupt 21 – Timer 5Interrupt 22 – Timer 6Interrupt 23 – Timer 7Interrupt 24 – Timer 8 and 9Interrupt 25 – Timer 10 and 11Interrupt 26 – Timer 12 and 13Interrupt 27 – Timer 14 and 15Interrupt 28 – Ext Int 0Interrupt 29 – Ext Int 1Interrupt 30 – Ext Int 2Interrupt 31 – Ext Int 3


Configuration Sequence• Configure the Interrupt Vector Address register for each level, 31-0.

• Assign a source Interrupt Assign ID, IRQ or FIQ, and enable each level by writing to the Config registers. Disable any levels that are not used.

• Configure the operation of the external interrupts by writing to the External Interrupt Control registers (3-0). The external interrupts can be negative or positive edge, or negative or positive level triggered.

• Wait for an interrupt to occur.

• Read the Active Interrupt Level Status register to determine the interrupt level. This step is optional.


Configuration Sequence• Read the Interrupt Service Routine Address register (ISRADDR) to

determine the address to jump to. This read operation masks out this and all lower interrupt levels until the interrupt service routine has finished.

• Jump to ISRADDR and service the interrupt. The routine should clear the interrupt at the source.

• After the interrupt service routine is finished, perform a write (any value) to the ISRADDR register. This write operation will unmask this and all lower interrupt levels.

Timer/Counter Modules

• The Timer/Counters are 32-bits wide.

• The clock for each Timer/Counter is configurable to be the ARM926 clock rate divided by 1, 2, 4, 8, 16, 32 or 64, or an external event via GPIO.

• The Timer/Counters can be concatenated together to form larger counters.

• 8 of the Timer/Counters have dedicated inputs to the Vectored Interrupt Controller. The other 8 Timer/Counters share 4 inputs.

• A status register is available to read the current value of each Timer/Counter, (Timer 0-15 Read register).

• The Timer/Counter registers can be configured to rollover or stop on terminal count.

Software Watchdog Timer

• Provided to detect gross system failures and configuration errors.

• The clock rate can be configured to be the ARM926 clock divided by 2, 4, 8, 16, 32, or 64.

• The timeout range can be configured from microseconds to minutes.

• When enabled the system software must write to the Software Watch Dog Timer register before it expires.

• When the Software Watch Dog Timer does time out, the system can be configured to generate an IRQ, a FIRQ, or a RESET to restart the whole system.

Bootstrap InitializationPin Name Description

rtck PCI arbiter configuration

0 – External PCI Arbiter

1 – Internal PCI Arbiter (default)

boot_strap[0] Chip select 1 byte lane signals configuration0 – active high for reads and low for writes (default)1 – active low for reads and writes

boot_strap[1] CardBus mode select

0 – CardBus mode

1 – PCI mode (default)

Internal pull-up resistors on the pins provide a default configuration by either inverting or not inverting the signal from the pin. To change the default configuration, use a pull-down resistor in the 2.2k-2.4k range.

Bootstrap Initialization

Pin Name Description

boot_strap[2] Memory interface dynamic memory read mode

0 – Command delayed mode (MUST BE USED)

1 – Clock delayed mode (default)

boot_strap[4:3] Chip select 1 data width

00 – 8 bits

01 – 16 bits

10 – 32 bits (default)

gpio[49] Chip select 1 polarity

0 – active low (default)

1 – active high

gpio[44] Endian mode

0 – little endian (default)

1 – big endian

Bootstrap Initialization

Pin Name Description

reset_done Bootup mode

0 – boot from SDRAM using serial SPI EEPROM

1 – boot from FLASH/ROM (default)

gpio[19] PLL bypass

0 – PLL not bypassed (default)

1 – PLL bypassed

gpio[17], gpio[12], gpio[10], gpio[8], gpio[4],

PLL ND[4:0] (PLL multiplier is ND+1)

Bits gpio[10] and gpio[4] are inverted to produce a default configuration of 11010 or 26. This gives a default PLL multiplier value of 27.

Bootstrap InitializationPin Name Description

gpio[2], gpio[0] PLL FS[1:0] (PLL frequency select)

FS Divide by

00 1

01 2 (default)

10 4

11 8

Documents

NS9750 - Training Hardware. System Controller Module