If you can't read please download the document
Upload
buikhuong
View
223
Download
2
Embed Size (px)
Citation preview
Fraunhofer IZM
Opportunities and Challenges for FOWLP and FOPLP
T. Braun, K.-F. Becker, M. Tpper, R. Aschenbrenner, K.-D. Lang
Dr. Tanja Braun, Fraunhofer IZMGustav-Meyer-Allee 25, 13355 Berlin, Germany
Email: [email protected]
mailto:[email protected]
Fraunhofer IZM - confidential
2
Roadmap Fan-Out Wafer & Panel Level Packaging
Source: Yole
Fraunhofer IZM - confidential
3
Roadmap Fan-Out Wafer & Panel Level Packaging
Source: Yole
Fraunhofer IZM - confidential
4
PCB via element vertical interconnect element
through s ilicon v ia die
laser drilled through via
laser drilled blind v ia
Through Mold Via (TMV) TechnologiesDie
Mold
DieMold
Substrate
TMV
Fraunhofer IZM - confidential
5
TMV with Vertical Interconnect Element (VIE)
VIE interconnection stacked packages with VIE
vertical interconnect element (VIE)
Planar structured Si or mold wafer with Cu-Lines (single or double sided)
VIE singulation by wafer dicing
90 rotated placement on carrier with all other components
Planar structured Cu-Lines form z-connection
Wafer grinding opens back side contact of VIE after molding and carrier release
Fraunhofer IZM - confidential
6
TMV with Through Silicon Via Die
FOWLP electrical 3D routing with through silicon via die
2D X-Ray image, 3D routing with silicon via die
Placement of Si dies with Through Silicon Vias (TSV) on carrier with all other components
TSV form z-connection
Electrical connection of overmolded backside TSV contact e.g. by laser drilled blind or wafer grinding into TSV contact
Fraunhofer IZM - confidential
7
TMV with Laser Drilled Through Via
Package with laser drilled through via
sensor stack with laser drilled vias
laser drilled through via
Laser drilling of through mold vias, via formation (diameter, pitch, roughness) depends on filler sizes of the epoxy molding compound
Metallization of vias by Cu plating
High aspect ration (> 8:1) feasible
Via plugging possibly needed
Fraunhofer IZM - confidential
8
Foldable FOWLP *
wafer dicing layout with cuts for bending (orange) and package singulation (white)
foldable fan-out wafer level packages
* patent pending
Two-step dicing process enables bending/folding of packages
1st step: bending cuts by dicing only through the molding compound
2nd step: package singulation by standard dicing through the entire package
Fraunhofer IZM - confidential
9
Foldable FOWLP (FFOLWP)
FFOWLP with two dies and straight cuts FFOWLP with multiple dies and straight cuts
FFOWLP with two dies and V-cuts FFOWLP with multiple dies and straight and V-cuts -> endless folding
Fraunhofer IZM - confidential
10
Bendable FOWLP
bended FOWLP
Two-step dicing process enables also bending of packages
Bending in two directions possible
3D conformal surface adaptation
Fraunhofer IZM - confidential
11
Demonstrator Layout
Two die package, die size: 5x5 mm
Daisy chain layout for electrical testing
Redistribution layer based on polyimide film (25 m) lamination
Adaptive RDL patterning based on real die position
-via formation by laser ablation and Cu-line structuring by laser direct imaging (LDI)
Bending cuts and package separation with standard wafer dicing equipment
PI adhesive layer (25 m Pyralux) acts as dicing buffer layer)
Fraunhofer IZM - confidential
12
Demonstrator Manufacturing
100 m
Fraunhofer IZM - confidential
13
Demonstrator Results
X-ray CT image of folded FOWLPEMC
adhesive
PI
adhesive
EMC
Cross section folded edge
Foldable FOWLP Packages could be successfully manufactured
Overall process flow was proven including 2-step dicing approach
Folding of packages by 180 is feasible without damaging package or Cu lines
Fraunhofer IZM - confidential
14
Demonstrator Results
Cross section folded edge
Dicing through Epoxy Molding Compound and stopping in the adhesive layer worked well
No damage or cracks in the PI and Cu layer
Fraunhofer IZM - confidential
15
Roadmap Fan-Out Wafer & Panel Level Packaging
Source: Yole
Fraunhofer IZM - confidential
16
Panel Packaging Process Step Tasks To Solve
assemblycompress ion
moldingcarrier
preparationdebonding
redistri-bution
handling, thinning & s ingulation
Eq
uip
me
nt
Ma
teri
al Carrier
steel, glass,..? Thermo
release tape Alternatives?
EMC liquid,
granular, sheet?
Dielectric polymers
liquid or film? photosensitive
or not? Sputter targets Plating
Handling carrier
Tape or other material
Temporary adhesives
Tape laminator
Available automatic equipment?
Pick and Place Accuracy on
panel size?
Material application
Dispensing, sprinkle,
Molding Uniformity,
thickness control,
Debonder Available
automatic equipment?
Lithography Stepper, laser
ablation, LDI Sputtering,
plating Thickness
variation, lines & spaces
Thinning & Dicing
Available automatic equipment?
Fraunhofer IZM - confidential
17
Panel Packaging Process Step Tasks To Solve
assemblycompress ion
moldingcarrier
preparationdebonding
redistri-bution
handling, thinning & s ingulation
Eq
uip
me
nt
Ma
teri
al Carrier
steel, glass ,..?
Thermorelease tape
Alternatives?
EMC liquid,
granular, sheet?
Dielectric polymers
liquid or film? photosensitive
or not? Sputter targets Plating
Handling carrier
Tape or other material
Temporary adhesives
Tape laminator
Available automatic equipment?
Pick and Place Accuracy on
panel size?
Material application
Dispensing, sprinkle,
Molding Uniformity,
thickness control,
Debonder Available
automatic equipment?
Lithography Stepper, laser
ablation, LDI Sputtering,
plating Thickness
variation, lines & spaces
Thinning & Dicing
Available automatic equipment?
Fraunhofer IZM - confidential
18
Panel Assembly Infrastructure - Carrier Selection
CarrierX Direction
[mm/mm]standard error
Y Direction [mm/mm]
standard error
steel 8,04 1004 0,261 1004 7,20 1004 0,200 1004
glass 0,87 1004 0,213 1004 0,65 1004 0,167 1004
Die Shift Factor Comparison on Waferbetween Glass (6,75 ppm/K by AGC) and Steel (12 ppm/K)
Die Shift Factor:Linear displacement of dies after molding (CTE EMC = ~7 ppm/K)-> mainly due CTE mismatches and chemical shrinkage of EMC. Die shift on the glass carrier is much lower than on the steel carrier.
But: Robustness of glass carriers needs improvement
-100 -80 -60 -40 -20 0 20 40 60 80 100
-0,10
-0,08
-0,06
-0,04
-0,02
0,00
0,02
0,04
0,06
0,08
0,10
X
[m
m]
X [mm]-100 -80 -60 -40 -20 0 20 40 60 80 100
-0,10
-0,08
-0,06
-0,04
-0,02
0,00
0,02
0,04
0,06
0,08
0,10
X
[m
m]
X [mm]
glass steel
Fraunhofer IZM - confidential
19
Panel Packaging Process Step Tasks To Solve
assemblycompress ion
moldingcarrier
preparationdebonding
redistri-bution
handling, thinning & s ingulation
Eq
uip
me
nt
Ma
teri
al Carrier
steel, glass,..? Thermo
release tape Alternatives?
EMC liquid,
granular, sheet?
Dielectric polymers
liquid or film? photosensitive
or not? Sputter targets Plating
Handling carrier
Tape or other material
Temporary adhesives
Tape laminator
Available automatic equipment?
Pick and Place Accuracy on
panel size?
Material application
Dispensing, sprinkle,
Molding Uniformity,
thickness control,
Debonder Available
automatic equipment?
Lithography Stepper, laser
ablation, LDI Sputtering,
plating Thickness
variation, lines & spaces
Thinning & Dicing
Available automatic equipment?
Fraunhofer IZM - confidential
20
Cu- Compatibility Low T cure High Breakdown V Low Cost Avoid dry ice for
shipping and storage
Si- , Glass -, Organic Interposers and
FOWLP Low CTE Low stress Low k/loss Panel Level Dry Film
FC of ULK Young`s
Modulus
BoP WLP Tensile
strength Elongation to
break
Next Generation Thin Film Polymers & Processing
0
1000
2000
3000
4000
5000
6000
7000
8000
2015 2016 2017 2018 2019 2020
Si Interposer 300mm (thousands ofwafers)
FO-WLP equiv. 300mm (thousands ofwafers)
0
1000
2000
3000
4000
5000
6000
7000
8000
2015 2016 2017