Optimality Study of Logic Synthesis for LUT-Based FPGAs

Jason Cong and Kirill Minkovich

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Outline

TermsPurposeHow the Examples were constructedCompare their structure to existing

benchmarksLook at the results

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Terms

LEKO – Logic Synthesis examples with Known Optimal

LEKU – Logic Synthesis examples with Known Upper bounds

MCNC – Microelectronics Center of North Carolina

MFFC – Maximum Fanout Free Cone (a method of measuring the structure of the circuit)

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Purpose

To develop an algorithm for generating synthetic benchmarks (LEKO and LEKU) with known optimal technology mapping solutions

Allow us to construct arbitrarily large test circuits for Synthesis software

To show that these benchmarks are structurally similar the MCNC benchmark

Show results

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LEKO Construction

Basic Building Block – Core Graph (Cn):◦It has n inputs and n outputs◦Every output is a function of all n inputs◦Each internal node of Cn has exactly 2 inputs◦There exists an optimal mapping (area/depth) of Cn

into a 4-LUT mapping solutionThese *same* building blocks are put

together on several layers so that there exist a path from every Basic block on the bottom layer to the top layer.

65 input core Graph – C5

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Additional Notes

To construct a core graph from a pre-existing benchmark, all you have to do is extract a piece of logic from that has an equal number of inputs and outputs

LEKU circuits are derived from the LEKO circuits by collapsing and gate decomposition

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Structure Comparison

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Important notes about the results

Only performed the logic synthesis step of the tools and did not go through the final placement and routing

The actual depths are not report because Xilinx uses two 4-LUTS in their logic blocks

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Examples Used

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Results

Mapping Results (LEKO) Synthesis Results (LEKU)

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Results (2)

This suggests that there may be significant opportunity for improvement in the logic-synthesis algorithms.

They must have a more global view of synthesis including duplication removal.

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Conclusions

The problems with the MCNC is that almost every logic-synthesis tool is specifically tuned to perform well on these benchmarks.

LEKO allows the designer to combine multiple ‘hard to map’ cares into one design with a known optimal

Knowing the optimal solution, the designer can see exactly where the algorithm made the mistake and why

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Conclusions (2)

LEKU circuits are meant to test how the existing algorithms perform and how much room is left for improvement when handling each type of inefficiency and/or redundancy.

This is basically a platform to create new benchmarks that can test every part of a synthesis tool