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OVP and EMI Protected, Precision, Low Noise and Bias Current Op Amps
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES Low offset voltage: 60 µV maximum at 25°C (8-lead and
14-lead SOIC) Low offset voltage drift: 1 µV/°C maximum (8-lead and
14-lead SOIC) Low input bias current: 1 nA maximum at 25°C Low voltage noise density: 8 nV/√Hz typical at 1 kHz Large signal voltage gain (AVO): 100 dB minimum over full
supply voltage and operating temperature Input overvoltage protection to 32 V above and below the
supply voltage rail Integrated EMI filter
70 dB typical rejection at 1000 MHz 90 dB typical rejection at 2400 MHz
Rail-to-rail output swing Low supply current: 500 µA typical per amplifier Wide bandwidth
Gain bandwidth product (AV = 100): 3.5 MHz typical Unity-gain crossover (AV = 1): 3.5 MHz typical −3 dB bandwidth (AV = 1): 6 MHz typical
Dual-supply operation Specified at ±5 V to ±15 V, operates over ±2.5 V to ±18 V
Unity-gain stable No phase reversal Long-term offset voltage drift (10,000 hours): 2 µV typical Temperature hysteresis: 2 µV typical
APPLICATIONS Wireless base station control circuits Optical network control circuits Instrumentation Sensors and controls
Thermocouples, RTDs, strain gages, shunt current measurements
GENERAL DESCRIPTION The ADA4177-1 single-channel, ADA4177-2 dual-channel, and ADA4177-4 quad-channel amplifiers feature low offset voltage (2 µV typical) and drift (1 µV/°C maximum), low input bias current, low noise, and low current consumption (500 µA typical). Outputs are stable with capacitive loads of more than 1000 pF with no external compensation.
The inputs of the ADA4177-1/ADA4177-2/ADA4177-4 feature outstanding precision amplifier robustness, providing input protection against signal excursions 32 V beyond either supply, as well as 70 dB of rejection for electromagnetic interference (EMI) at 1000 MHz.
PIN CONNECTION DIAGRAM OUT A 1
–IN A 2
+IN A 3
V– 4
V+8
OUT B7
–IN B6
+IN B5
ADA4177-2TOP VIEW
(Not to Scale)
1228
2-00
1
Figure 1. ADA4177-2, for Additional Packages and Models, See the Pin
Configurations and Function Descriptions Section
Applications for these amplifiers include sensor signal conditioning (such as thermocouples, resistor thermal detectors (RTDs), and strain gages), process control front-end amplifiers, and precision diode power measurement in optical and wireless transmission systems.
The ADA4177-1/ADA4177-2/ADA4177-4 operate over the −40°C to +125°C industrial temperature range. The ADA4177-1/ ADA4177-2 are available in an 8-lead SOIC package and an 8-lead MSOP package. The ADA4177-4 is available in a 14-lead TSSOP and a 14-lead SOIC package.
12
–10
–8
–6
–4
–2
0
2
4
6
8
10
INPU
T B
IAS
CU
RR
ENT
(mA
)
VIN (V)–50 503010–10–30
1228
2-44
6
VSY = ±15V
Figure 2. Overvoltage Current Limiting, Voltage Follower Configuration
Table 1. Evolution of Protected Input Op Amps by Generation1 Gen. 1, OVP (10 V)
Gen. 2, OVP (25 V)
Gen. 3, OVP (32 V)
Gen. 4 EMI Filters
Gen. 5, OVP (32 V) + EMI
OP191 ADA4091-2 ADA4096-2 AD8657 ADA4177-1 OP291 ADA4091-4 ADA4096-4 AD8659 ADA4177-2 OP491 ADA4092-4 AD8546 ADA4177-4 AD8548 ADA4661-2 ADA4666-2
1 Gen. means generation.
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 2 of 33
TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Pin Connection Diagram ................................................................ 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4
Electrical Characteristics, ±5 V .................................................. 4 Electrical Characteristics, ±15 V ................................................ 6 Absolute Maximum Ratings ....................................................... 8 Maximum Power Dissipation ..................................................... 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 12 Theory of Operation ...................................................................... 25
Applications Information .............................................................. 26 Active Overvoltage Protection ................................................. 26 Limiting Overvoltage Current Out of the Positive Supply Pin....................................................................................................... 27 EMI Protection ........................................................................... 28 Self Heating ................................................................................. 28 Using the ADA4177-1/ADA4177-2/ADA4177-4 as a Comparator ................................................................................. 28 Output Phase Reversal ............................................................... 29 Proper Printed Circuit Board (PCB) Layout .......................... 29 Long-Term Drift ......................................................................... 29 Temperature Hysteresis ............................................................. 30
Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 33
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 3 of 33
REVISION HISTORY 8/2018—Rev. D to Rev. E Change to Input Capacitance (CINCM) Parameter, Table 2............ 4 Change to Input Capacitance (CINCM) Parameter, Table 3............ 6 Changes to Ordering Guide ........................................................... 33 5/2017—Rev. C to Rev. D Changes to Features Section, Applications Section, and General Description Section ........................................................................... 1 Changes to Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, and Figure 14 ................................................................................... 12 Changes to Figure 15 and Figure 16 ............................................. 13 Changes to Add an External Series Input Resistor Section and Figure 85 ........................................................................................... 26 Changes to Self Heating Section ................................................... 28 Added Long-Term Drift Section ................................................... 29 Added Temperature Hysteresis Section, Figure 97, Figure 98, and Figure 99; Renumbered Sequentially ............................................... 30 4/2015—Rev. B to Rev. C Added ADA4177-1 ............................................................ Universal Deleted Figure 2; Renumbered Sequentially ................................. 1 Change to Table 1 .............................................................................. 1 Added Figure 5, Figure 6, and Table 7; Renumbered Sequentially ........................................................................................ 9 Changes to Figure 16, Figure 17, Figure 19, and Figure 20 ....... 12 Changes to Figure 26 ...................................................................... 14 Changes to Figure 34, Figure 35, Figure 37, and Figure 39 ....... 16 Changes to Figure 46, Figure 47, Figure 49, and Figure 50 ....... 17 Changes to Figure 59 and Figure 62 ............................................. 19 Changes to Figure 63, Figure 65, Figure 66, and Figure 68 ....... 20 Changes to Figure 69 and Figure 72 ............................................. 21 Changes to Figure 75 and Figure 78 ............................................. 22 Added Figure 77 and Figure 80 ..................................................... 22 Added Figure 81 to Figure 83 ........................................................ 23 Changes to Theory of Operation Section .................................... 24
Changes to Input Protection Circuit Section and Limiting Overvoltage Current Out of the Positive Supply Pin Section ... 26 Changes to Using the ADA4177-1/ADA4177-2/ADA4177-4 as a Comparator Section ..................................................................... 27 Changes to Ordering Guide ........................................................... 31 1/2015—Rev. A to Rev. B Added ADA4177-4 ............................................................ Universal Reorganized Layout ........................................................... Universal Added Figure 2; Renumbered Sequentially ................................... 1 Changes to Features and General Description Section ................ 1 Changes to Table 2 ............................................................................ 3 Changes to Table 3 ............................................................................ 5 Changes to Table 5 ............................................................................ 7 Added Figure 6, Figure 7, and Table 7; Renumbered Sequentially ........................................................................................ 9 Added Figure 10 and Figure 13 ..................................................... 10 Replaced Figure 15 and Figure 18 ................................................. 11 Added Figure 14, Figure 16, Figure 17, and Figure 19 ............... 11 Changes to Figure 20, Figure 21, Figure 23, and Figure 24 ....... 12 Changes to Figure 32 and Figure 33 ............................................. 14 Changes to Figure 38 and Figure 41 ............................................. 15 Changes to Figure 58 and Figure 61 ............................................. 18 Changes to Figure 62, Figure 65, and Figure 66 .......................... 19 Changes to Figure 69 and Figure 72 ............................................. 20 Change to Figure 87 Caption ......................................................... 25 Updated Outline Dimensions ........................................................ 27 Added Figure 93 and Figure 94 ..................................................... 28 Changes to Ordering Guide ........................................................... 29 10/2014—Rev. 0 to Rev. A Changes to Large Signal Voltage Gain Parameter, Test Conditions/Comments Column, Table 3 ....................................... 5 10/2014—Revision 0: Initial Version
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 4 of 33
SPECIFICATIONS ELECTRICAL CHARACTERISTICS, ±5 V VSY = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS
Offset Voltage VOS 8-Lead SOIC and 14-Lead SOIC 2 60 µV −40°C < TA < +125°C 120 µV 8-Lead MSOP 3 120 µV −40°C < TA < +125°C 200 µV 14-Lead TSSOP 3 150 µV −40°C < TA < +125°C 300 µV
Offset Voltage Matching 8-Lead SOIC 40 µV 8-Lead MSOP 110 µV
Offset Voltage Drift ΔVOS/ΔT −40°C < TA < +125°C 8-Lead SOIC and 14-Lead SOIC 1 µV/°C 8-Lead MSOP and 14-Lead TSSOP 1.6 µV/°C
Input Bias Current IB −1 −0.4 +1 nA −40°C < TA < +125°C −2 +2 nA Input Offset Current IOS −0.75 +0.1 +0.75 nA −40°C < TA < +125°C −1.5 +1.5 nA Input Voltage Range IVR −3.5 +3.5 V Overvoltage Current Limit1 IOVP 5 V < VCM < 37 V 12 mA −37 V < VCM < −5 V 10 mA Common-Mode Rejection Ratio CMRR VCM = −3.5 V to +3.5 V 122 130 dB −40°C < TA < +125°C 120 dB Large Signal Voltage Gain AVO RL = 2 kΩ, VOUT = −4.5 V to +4.5 V 108 110 dB −40°C < TA < +125°C 100 dB RL = 10 kΩ, VOUT = −4.5 V to +4.5 V 115 120 dB −40°C < TA < +125°C 110 dB Input Capacitance CINDM Differential mode 1 pF CINCM Common mode 8 pF Input Resistance RDIFF Differential mode 4 MΩ RCM Common mode 100 GΩ
OUTPUT CHARACTERISTICS Output Voltage
High VOH ILOAD = 1 mA 4.95 V −40°C < TA < +125°C 4.90 V ILOAD = 7 mA 4.80 V −40°C < TA < +125°C 4.75 V Low VOL ILOAD = 1 mA −4.95 V −40°C < TA < +125°C −4.90 V ILOAD = 7 mA −4.80 V −40°C < TA < +125°C −4.75 V
Output Current IOUT VDROPOUT < 1 V 25 mA Short-Circuit Current ISC TA = 25°C
Sourcing 36 mA Sinking 48 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = 1 0.11 Ω
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 5 of 33
Parameter Symbol Test Conditions/Comments Min Typ Max Unit POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±2.5 V to ±18 V 125 145 dB −40°C < TA < +125°C 120 dB
Supply Current per Amplifier ISY VOUT = 0 V 500 560 µA −40°C < TA < +125°C 600 µA DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 1.5 V/µs Settling Time tS
To 0.1% VIN = 1 V step, RL = 2 kΩ, AV = −1 1.8 µs To 0.01% VIN = 1 V step, RL = 2 kΩ, AV = −1 3.5 µs
Gain Bandwidth Product GBP VIN = 10 mV p-p, RL = 2 kΩ, AV = 100 3.5 MHz Unity-Gain Crossover UGC VIN = 10 mV p-p, RL = 2 kΩ, AV = 1 3.5 MHz −3 dB Closed-Loop Bandwidth f−3 dB VIN = 10 mV p-p, RL = 2 kΩ, AV = 1 6 MHz Total Harmonic Distortion Plus Noise THD + N VIN = 1 V rms, RL = 2 kΩ, AV = +1, f = 1 kHz 0.003 % EMI Rejection of +INx EMIRR VIN = 200 mV p-p
f = 1000 MHz 70 dB f = 2400 MHz 90 dB
NOISE PERFORMANCE Voltage Noise en p-p 0.1 Hz to 10 Hz 175 nV p-p Voltage Noise Density en f = 10 Hz 10 nV/√Hz f = 1 kHz 8 nV/√Hz Current Noise Density in f = 1 kHz 0.2 pA/√Hz
1 All inputs are stressed to 32 V beyond supplies for 500 ms. See Figure 71 for the typical input bias current vs. the input voltage over the overvoltage protected input range.
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 6 of 33
ELECTRICAL CHARACTERISTICS, ±15 V VSY = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS
Offset Voltage VOS 8-Lead SOIC and 14-Lead SOIC 2 60 µV
−40°C < TA < +125°C 120 µV 8-Lead MSOP 3 120 µV
−40°C < TA < +125°C 200 µV 14-Lead TSSOP 3 150 µV
−40°C < TA < +125°C 300 µV Offset Voltage Matching
8-Lead SOIC 40 µV 8-Lead MSOP 110 µV
Offset Voltage Drift ΔVOS/ΔT −40°C < TA < +125°C 8-Lead SOIC and 14-Lead SOIC 1 µV/°C 8-Lead MSOP and 14-Lead TSSOP 1.6 µV/°C
Input Bias Current IB −1 −0.3 +1 nA −40°C < TA < +125°C −2 +2 nA Input Offset Current IOS −0.75 +0.1 +0.75 nA −40°C < TA < +125°C −1.5 +1.5 nA Input Voltage Range IVR −13.5 +13.5 V Overvoltage Current Limit1 IOVP 15 V < VCM < 47 V 12 mA −47 V < VCM < −15 V 10 mA Common-Mode Rejection Ratio CMRR VCM = −13.5 V to +13.5 V 128 130 dB −40°C < TA < +125°C 125 dB Large Signal Voltage Gain AVO RL = 2 kΩ, VOUT = −14.2 V to +14.2 V 110 114 dB −40°C < TA < +125°C 103 dB RL = 10 kΩ, VOUT = −14.5 V to +14.5 V 118 120 dB −40°C < TA < +125°C 110 dB Input Capacitance CINDM Differential mode 1 pF CINCM Common mode 8 pF Input Resistance RDIFF Differential mode 4 MΩ
RCM Common mode 130 GΩ OUTPUT CHARACTERISTICS
Output Voltage High VOH ILOAD = 1 mA 14.95 V −40°C < TA < +125°C 14.90 V ILOAD = 7 mA 14.80 V −40°C < TA < +125°C 14.75 V Low VOL ILOAD = 1 mA −14.95 V −40°C < TA < +125°C −14.90 V ILOAD = 7 mA −14.80 V −40°C < TA < +125°C −14.75 V
Output Current IOUT VDROPOUT < 1 V 25 mA Short-Circuit Current ISC TA = 25°C
Sourcing 53 mA Sinking 65 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = 1 0.08 Ω
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 7 of 33
Parameter Symbol Test Conditions/Comments Min Typ Max Unit POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±2.5 V to ±18 V 125 145 dB −40°C < TA < +125°C 120 dB Supply Current per Amplifier ISY VOUT = 0 V 500 580 µA
−40°C < TA < +125°C 620 µA DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 1.5 V/µs Settling Time tS
To 0.1% VIN = 10 V p-p, RL = 2 kΩ, AV = −1 5.5 µs To 0.01% VIN = 10 V p-p, RL = 2 kΩ, AV = −1 7.5 µs
Gain Bandwidth Product GBP VIN = 10 mV p-p, RL = 2 kΩ, AV = 100 3.5 MHz Unity-Gain Crossover UGC VIN = 10 mV p-p, RL = 2 kΩ, AV = 1 3.5 MHz −3 dB Closed-Loop Bandwidth f−3 dB VIN = 10 mV p-p, RL = 2 kΩ, AV = 1 6 MHz Total Harmonic Distortion Plus Noise THD + N VIN = 1 V rms, AV = +1, RL = 2 kΩ, f = 1 kHz 0.002 % EMI Rejection of +INx EMIRR VIN = 200 mV p-p
f = 1000 MHz 70 dB f = 2400 MHz 90 dB
NOISE PERFORMANCE Voltage Noise en p-p 0.1 Hz to 10 Hz 175 nV p-p Voltage Noise Density en f = 10 Hz 10 nV/√Hz f = 1 kHz 8 nV/√Hz Current Noise Density in f = 1 kHz 0.2 pA/√Hz
MULTIPLE AMPLIFIERS CHANNEL SEPARATION CS f = 1 kHz 127 dB 1 All inputs are stressed to 32 V beyond supplies for 500 ms. See Figure 74 for the typical input bias current vs. the input voltage over the overvoltage protected input range.
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 8 of 33
ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating Supply Voltage 36 V Input Voltage VSY ± 32 V Differential Input Voltage ±VSY Output Short-Circuit Duration to GND See the Maximum Power
Dissipation section Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +125°C Junction Temperature Range −65°C to +150°C Lead Temperature, Soldering (10 sec)1 300°C Electrostatic Discharge (ESD)
Human Body Model (HBM)2 4 kV Field Induced Charged Device
Model (FICDM)3 1250 V
Machine Model (MM) 200 V 1 IPC/JEDEC J-STS-020D applicable standard. 2 ESDA/JEDEC JS-001-2011 applicable standard. 3 JESD22-C101 (ESD FICDM standard of JEDEC) applicable standard.
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
MAXIMUM POWER DISSIPATION The ADA4177-1/ADA4177-2/ADA4177-4 can drive a short-circuit output current of up to 65 mA. However, the usable output load current drive is limited by the maximum power dissipation allowed by the device package. The absolute maximum junction temperature is 150°C (see Table 4). The junction temperature can be estimated as follows:
TJ = PD × θJA + TA
where: TJ is the die junction temperature. PD is the power dissipated in the package. θJA is the thermal resistance of the package. TA is the ambient temperature.
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated by the output stage transistor. It is calculated as follows:
PD = (VSY × ISY) + (VSY − VOUT) × ILOAD
where: VSY is the power supply rail. ISY is the quiescent current. VOUT is the output of the amplifier. ILOAD is the output load.
Do not exceed the 150°C maximum junction temperature for the device. Exceeding the junction temperature limit can cause degradation in the parametric performance or even destroy the device. Refer to Technical Article MS-2251, Data Sheet Intricacies—Absolute Maximum Ratings and Thermal Resistances, for more information.
THERMAL RESISTANCE Thermal resistance between junction and ambient (θJA) is specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance Package Type θJA θJC Unit 8-Lead MSOP 190 44 °C/W 8-Lead SOIC 158 43 °C/W 14-Lead TSSOP 240 43 °C/W 14-Lead SOIC 115 36 °C/W
ESD CAUTION
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 9 of 33
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NOTES1. NIC = NOT INTERNALLY CONNECTED.
NIC–IN+INV–
NICV+OUTNIC
ADA4177-1TOP VIEW
(Not to Scale)
1228
2-20
5
1
2
3
4
8
7
6
5
Figure 3. ADA4177-1 8-Lead MSOP Pin Configuration
NOTES1. NIC = NOT INTERNALLY CONNECTED.
NIC 1
–IN 2
+IN 3
V– 4
NIC8
V+7
OUT6
NIC5
ADA4177-1TOP VIEW
(Not to Scale)
1228
2-10
5
Figure 4. ADA4177-1 8-Lead SOIC Pin Configuration
Table 6. ADA4177-1 Pin Function Descriptions Pin No. Mnemonic Description 1, 5, 8 NIC Not Internally Connected. 2 −IN Inverting Input Channel. 3 +IN Noninverting Input Channel. 4 V− Negative Supply Voltage. 6 OUT Output Channel. 7 V+ Positive Supply Voltage.
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 10 of 33
OUT A 1
–IN A 2
+IN A 3
V– 4
V+8
OUT B7
–IN B6
+IN B5
ADA4177-2TOP VIEW
(Not to Scale)
1228
2-00
4
Figure 5. ADA4177-2 8-Lead MSOP Pin Configuration
OUT A 1
–IN A 2
+IN A 3
V– 4
V+8
OUT B7
–IN B6
+IN B5
ADA4177-2TOP VIEW
(Not to Scale)
1228
2-00
5
Figure 6. ADA4177-2 8-Lead SOIC Pin Configuration
Table 7. ADA4177-2 Pin Function Descriptions Pin No. Mnemonic Description 1 OUT A Output Channel A. 2 −IN A Inverting Input Channel A. 3 +IN A Noninverting Input Channel A. 4 V− Negative Supply Voltage. 5 +IN B Noninverting Input Channel B. 6 −IN B Inverting Input Channel B. 7 OUT B Output Channel B. 8 V+ Positive Supply Voltage.
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 11 of 33
ADA4177-4
1
2
3
4
5
6
7
–IN A
+IN A
V+
OUT B
–IN B
+IN B
OUT A 14
13
12
11
10
9
8
–IN D
+IN D
V–
OUT C
–IN C
+IN C
OUT D
TOP VIEW(Not to Scale)
1228
2-20
6
Figure 7. ADA4177-4 14-Lead TSSOP Pin Configuration
OUT A 1
–IN A 2
+IN A 3
V+ 4
OUT D14
–IN D13
+IN D12
V–11
+IN B 5 +IN C10
–IN B 6 –IN C9
OUT B 7 OUT C8
ADA4177-4TOP VIEW
(Not to Scale)
1228
2-20
7
Figure 8. ADA4177-4 14-Lead SOIC Pin Configuration
Table 8. ADA4177-4 Pin Function Descriptions Pin No. Mnemonic Description 1 OUT A Output Channel A. 2 −IN A Inverting Input Channel A. 3 +IN A Noninverting Input Channel A. 4 V+ Positive Supply Voltage. 5 +IN B Noninverting Input Channel B. 6 −IN B Inverting Input Channel B. 7 OUT B Output Channel B. 8 OUT C Output Channel C. 9 −IN C Inverting Input Channel C. 10 +IN C Noninverting Input Channel C. 11 V− Negative Supply Voltage. 12 +IN D Noninverting Input Channel D. 13 −IN D Inverting Input Channel D. 14 OUT D Output Channel D.
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 12 of 33
TYPICAL PERFORMANCE CHARACTERISTICS Ambient temperature (TA) = 25°C unless otherwise noted.
80
70
60
0
10
20
30
40
50
NU
MB
ER O
F A
MPL
IFIE
RS
VOS (µV)
VSY = ±5V8-LEAD SOIC
–50
–45
–40
–35
–30
–25
–20
–15
–10 –5 0 5 10 15 20 25 30 35 40 45 50
1228
2-40
2
Figure 9. Input Offset Voltage (VOS) Distribution, VSY = ±5 V, 8-Lead SOIC
60
0
10
20
30
40
50
NU
MB
ER O
F A
MPL
IFIE
RS
VOS (µV)
–100 –90
–80
–70
–60
–50
–40
–30
–20
–10 0 10 20 30 40 50 60 70 80 90 100
VSY = ±5V8-LEAD MSOP
1228
2-40
0
Figure 10. Input Offset Voltage (VOS) Distribution, VSY = ±5 V, 8-Lead MSOP
300
0
50
100
150
200
250
NU
MB
ER O
F A
MPL
IFIE
RS
VOS (µV)
VSY = ±5V14-LEAD SOIC
–50
–45
–40
–35
–30
–25
–20
–15
–10 –5 0 5 10 15 20 25 30 35 40 45 50
1228
2-50
3
Figure 11. Input Offset Voltage (VOS) Distribution, VSY = ±5 V,
14-Lead SOIC
90
80
70
60
0
10
20
30
40
50
NU
MB
ER O
F A
MPL
IFIE
RS
VOS (µV)
VSY = ±15V8-LEAD SOIC
–50
–45
–40
–35
–30
–25
–20
–15
–10 –5 0 5 10 15 20 25 30 35 40 45 50
1228
2-40
3
Figure 12. Input Offset Voltage (VOS) Distribution, VSY = ±15 V,
8-Lead SOIC
60
0
10
20
30
40
50
NU
MB
ER O
F A
MPL
IFIE
RS
VOS (µV)
–100 –90
–80
–70
–60
–50
–40
–30
–20
–10 0 10 20 30 40 50 60 70 80 90 100
VSY = ±15V8-LEAD MSOP
1228
2-40
1
Figure 13. Input Offset Voltage (VOS) Distribution, VSY = ±15 V,
8-Lead MSOP
300
0
50
100
150
200
250
NU
MB
ER O
F A
MPL
IFIE
RS
VOS (µV)
VSY = ±15V14-LEAD SOIC
–50
–45
–40
–35
–30
–25
–20
–15
–10 –5 0 5 10 15 20 25 30 35 40 45 50
1228
2-50
4
Figure 14. Input Offset Voltage (VOS) Distribution, VSY = ±15 V,
14-Lead SOIC
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 13 of 33
90
80
70
60
0
10
20
30
40
50
NU
MB
ER O
F A
MPL
IFIE
RS
VOS (µV)
–100 –90
–80
–70
–60
–50
–40
–30
–20
–10 0 10 20 30 40 50 60 70 80 90 100
VSY = ±5V14-LEAD TSSOP
1228
2-50
1
Figure 15. Input Offset Voltage (VOS) Distribution, VSY = ±5 V,
14-Lead TSSOP
160
–40
V OS
(µV)
TEMPERATURE (°C)
–160
–120
–80
–40
0
40
80
120
–25 –10 5 20 35 50 65 80 95 110 125
VSY = ±5V8-LEAD SOIC, 14-LEAD SOIC
1228
2-50
8
Figure 16. Input Offset Voltage (VOS) vs. Temperature, VSY = ±5 V,
8-Lead SOIC and 14-Lead SOIC
300
–40
V OS
(µV)
TEMPERATURE (°C)
–300
–200
–100
0
100
200
–25 –10 5 20 35 50 65 80 95 110 125
VSY = ±5V8-LEAD MSOP, 14-LEAD TSSOP
1228
2-51
2
Figure 17. Input Offset Voltage (VOS) vs. Temperature, VSY = ±5 V,
8-Lead MSOP and 14-Lead TSSOP
90
80
70
60
0
10
20
30
40
50
NU
MB
ER O
F A
MPL
IFIE
RS
VOS (µV)
–100 –90
–80
–70
–60
–50
–40
–30
–20
–10 0 10 20 30 40 50 60 70 80 90 100
VSY = ±15V14-LEAD TSSOP
1228
2-50
2
Figure 18. Input Offset Voltage (VOS) Distribution, VSY = ±15 V,
14-Lead TSSOP
160
–40
V OS
(µV)
TEMPERATURE (°C)
–160
–120
–80
–40
0
40
80
120
–25 –10 5 20 35 50 65 80 95 110 125
VSY = ±15V8-LEAD SOIC, 14-LEAD SOIC
1228
2-51
1
Figure 19. Input Offset Voltage (VOS) vs. Temperature, VSY = ±15 V,
8-Lead SOIC and 14-Lead SOIC
300
–40
V OS
(µV)
TEMPERATURE (°C)
–300
–200
–100
0
100
200
–25 –10 5 20 35 50 65 80 95 110 125
VSY = ±15V8-LEAD MSOP, 14-LEAD TSSOP
1228
2-51
5
Figure 20. Input Offset Voltage (VOS) vs. Temperature, VSY = ±15 V,
8-Lead MSOP and 14-Lead TSSOP
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 14 of 33
80
70
60
50
40
30
20
10
NU
MB
ER O
F A
MPL
IFIE
RS
TCVOS (µV/°C)
0
VSY = ±5V8-LEAD SOIC, 14-LEAD SOIC
–0.55 –0.30 –0.05 0.20 0.45 0.70 0.95
1228
2-51
3
Figure 21. Temperature Coefficient of Offset Voltage (TCVOS), VSY = ±5 V,
8-Lead SOIC and 14-Lead SOIC
40
35
30
25
20
15
10
5
NU
MB
ER O
F A
MPL
IFIE
RS
TCVOS (µV/°C)
0
VSY = ±5V8-LEAD MSOP, 14-LEAD TSSOP
–0.55 –0.30 –0.05 0.20 0.45 0.70 0.95
1228
2-51
4
Figure 22. Temperature Coefficient of Offset Voltage (TCVOS), VSY = ±5 V,
8-Lead MSOP and 14-Lead TSSOP
100
–100
–80
–60
–40
–20
0
20
40
60
80
V OS
(µV)
VCM (V)–5 –4 –3 –2 –1 0 1 2 3 4 5
AVERAGE – 3σ
AVERAGE
AVERAGE + 3σ
VSY = ±5V
1228
2-40
7
Figure 23. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
VSY = ±5 V
80
70
60
50
40
30
20
10
NU
MB
ER O
F A
MPL
IFIE
RS
TCVOS (µV/°C)
0
VSY = ±15V8-LEAD SOIC, 14-LEAD SOIC
–0.55 –0.30 –0.05 0.20 0.45 0.70 0.95
1228
2-51
6
Figure 24. Temperature Coefficient of Offset Voltage (TCVOS), VSY = ±15 V,
8-Lead SOIC and 14-Lead SOIC
35
30
25
20
15
10
5
NU
MB
ER O
F A
MPL
IFIE
RS
TCVOS (µV/°C)
0
VSY = ±15V8-LEAD MSOP, 14-LEAD TSSOP
–0.55 –0.30 –0.05 0.20 0.45 0.70 0.95
1228
2-51
7
Figure 25. Temperature Coefficient of Offset Voltage (TCVOS), VSY = ±15 V,
8-Lead MSOP and 14-Lead TSSOP
100
–100
–80
–60
–40
–20
0
20
40
60
80
V OS
(µV)
VCM (V)–15 –10 –5 50 10 15
AVERAGE – 3σ
AVERAGE
AVERAGE + 3σ
VSY = ±15V
1228
2-40
8
Figure 26. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
VS = ±15 V
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 15 of 33
5.00
4.80
4.82
4.84
4.86
4.88
4.90
4.92
4.94
4.96
4.98
OU
TPU
T VO
LTA
GE
SWIN
G (V
)
TEMPERATURE (°C)–50 –25 7550250 100 125
VSY = ±5V
VOH AT ILOAD = 7mA
VOH AT ILOAD = 1mA
VOL AT ILOAD = 7mA
VOL AT ILOAD = 1mA
1228
2-40
9
Figure 27. Output Voltage Swing vs. Temperature, VSY = ±5 V
300
0
50
100
150
200
250
NU
MB
ER O
F A
MPL
IFIE
RS
INPUT BIAS CURRENT (nA)
–1.0
–0.8
–0.6
–0.4
–0.2 0
0.2
0.4
0.6
0.8
1.0
VSY = ±5V12
282-
411
Figure 28. Input Bias Current Distribution, VSY = ±5 V
0.2
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
INPU
T B
IAS
CU
RR
ENT
(nA
)
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
VSY = ±5VVCM = 0V
IB–IB+
1228
2-41
3
Figure 29. Input Bias Current (IB) vs. Temperature, VSY = ±5 V
15.00
14.80
14.82
14.84
14.86
14.88
14.90
14.92
14.94
14.96
14.98
OU
TPU
T VO
LTA
GE
SWIN
G (V
)
TEMPERATURE (°C)–50 –25 7550250 100 125
VSY = ±15V
VOH AT ILOAD = 7mA
VOH AT ILOAD = 1mA
VOL AT ILOAD = 7mA
VOL AT ILOAD = 1mA
1228
2-41
0
Figure 30. Output Voltage Swing vs. Temperature, VSY = ±15 V
450
400
0
50
100
150
200
300
350
250N
UM
BER
OF
AM
PLIF
IER
S
INPUT BIAS CURRENT (nA)
–1.0
–0.8
–0.6
–0.4
–0.2 0
0.2
0.4
0.6
0.8
1.0
VSY = ±15V
1228
2-41
2
Figure 31. Input Bias Current Distribution, VSY = ±15 V
0.2
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
INPU
T B
IAS
CU
RR
ENT
(nA
)
TEMPERATURE (°C)
–50 –25 0 25 50 75 100 125
VSY = ±15VVCM = 0V
IB–
IB+
1228
2-41
4
Figure 32. Input Bias Current (IB) vs. Temperature, VSY = ±15 V
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 16 of 33
0.6
0.5
0.4
0.3
0.2
0.1
0
I SY
(mA
)
VSY (V)0 403430252015105
1228
2-40
6
–40°C+25°C+85°C+125°C
Figure 33. Supply Current per Amplifier (ISY) vs. Power Supply Voltage (VSY)
10k
1k
1
10
100
OU
TPU
T D
RO
POU
T VO
LTA
GE
(mV)
SINK CURRENT (mA)0.001 0.01 1001010.1
VSY = ±5V
–40°C+25°C+85°C+125°C
1228
2-42
1
Figure 34. Output Dropout Voltage vs. Sink Current, VSY = ±5 V
OU
TPU
T D
RO
POU
T VO
LTA
GE
(mV)
SOURCE CURRENT (mA) 1228
2-42
3
10k
1k
1
10
100
0.001 0.01 1001010.1
VSY = ±5V
–40°C+25°C+85°C+125°C
Figure 35. Output Dropout Voltage vs. Source Current, VSY = ±5 V
10
–10
–5
0
5
OFF
SET
VOLT
AG
E (µ
V)
VSY (V)0 2015105 25 30 35
1228
2-41
9
Figure 36. Offset Voltage (VOS) vs. Power Supply Voltage (VSY)
10k
1k
1
10
100
OU
TPU
T D
RO
POU
T VO
LTA
GE
(mV)
SINK CURRENT (mA)0.001 0.01 1001010.1
VSY = ±15V
–40°C+25°C+85°C+125°C
1228
2-42
2
Figure 37. Output Dropout Voltage vs. Sink Current, VSY = ±15 V
OU
TPU
T D
RO
POU
T VO
LTA
GE
(mV)
SOURCE CURRENT (mA) 1228
2-42
4
10k
1k
10
1
100
0.001 0.01 1001010.1
VSY = ±15V
–40°C+25°C+85°C+125°C
Figure 38. Output Dropout Voltage vs. Source Current, VSY = ±15 V
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 17 of 33
120
–80
–60
–40
–20
0
20
40
60
80
100
120
–80
–60
–40
–20
0
20
40
60
80
100
OPE
N-L
OO
P G
AIN
(dB
)
PHA
SE (D
egre
es)
FREQUENCY (Hz)1k 10k 100k 1M 10M 100M
VSY = ±5VAV = –10RL = 2kΩTA = 25°C
PHASE WITH CL = 0pFPHASE WITH CL = 100pFPHASE WITH CL = 200pF
GAIN WITH CL = 0pFGAIN WITH CL = 100pFGAIN WITH CL = 200pF
1228
2-42
5
Figure 39. Open-Loop Gain and Phase vs. Frequency, VSY = ±5 V
60
–40
–20
0
20
40
CLO
SED
-LO
OP
GA
IN (d
B)
FREQUENCY (Hz)1k 10M1M100k10k
VSY = ±5V
G = +1
G = +10
G = +100
1228
2-42
7
Figure 40. Closed-Loop Gain vs. Frequency, VSY = ±5 V
146
130
134
138
142
132
136
140
144
CM
RR
(dB
)
TEMPERATURE (°C)–50 50250–25 75 100 125
VSY = ±5V
1228
2-42
9
Figure 41. Common-Mode Rejection Ratio (CMRR) vs. Temperature, VSY = ±5 V
120
–80
–60
–40
–20
0
20
40
60
80
100
120
–80
–60
–40
–20
0
20
40
60
80
100
OPE
N-L
OO
P G
AIN
(dB
)
PHA
SE (D
egre
es)
FREQUENCY (Hz)1k 10k 100k 1M 10M 100M
VSY = ±15VAV = –10RL = 2kΩTA = 25°C
PHASE WITH CL = 0pFPHASE WITH CL = 100pFPHASE WITH CL = 200pF
GAIN WITH CL = 0pFGAIN WITH CL = 100pFGAIN WITH CL = 200pF
1228
2-42
6
Figure 42. Open-Loop Gain and Phase vs. Frequency, VSY = ±15 V
60
–40
–20
0
20
40
CLO
SED
-LO
OP
GA
IN (d
B)
FREQUENCY (Hz)1k 10M1M100k10k
VSY = ±15V
G = +1
G = +10
G = +100
1228
2-42
8
Figure 43. Closed-Loop Gain vs. Frequency, VSY = ±15 V
146
130
134
138
142
132
136
140
144
CM
RR
(dB
)
TEMPERATURE (°C)–50 50250–25 75 100 125
VSY = ±15V
1228
2-43
0
Figure 44. Common-Mode Rejection Ratio (CMRR) vs. Temperature, VSY = ±15 V
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 18 of 33
1000
0.001
100
10
1
0.1
0.01
Z OU
T (Ω
)
FREQUENCY (MHz)0.0001 10.10.010.001 10
VSY = ±5V
AV = +100
AV = +10AV = +1
1228
2-43
1
Figure 45. Output Impedance (ZOUT) vs. Frequency, VSY = ±5 V
3
–3
2
1
0
–1
–2
V OU
T (1
V/D
IV)
TIME (100µs/DIV)
VSY = ±5VVIN = 4V p-pAV = +1RL = 2kΩCL = 300pF
1228
2-43
3
Figure 46. Large Signal Transient Response, VSY = ±5 V
0.10
–0.10
0.05
0
–0.05
V OU
T (V
)
TIME (100µs/DIV)
VSY = ±5VVIN = 100mV p-pAV = +1RL = 2kΩCL = 1000pF
1228
2-43
5
Figure 47. Small Signal Transient Response, VSY = ±5 V
1000
0.001
100
10
1
0.1
0.01
Z OU
T (Ω
)
FREQUENCY (MHz)0.0001 10.10.010.001 10
VSY = ±15V
AV = +100
AV = +10AV = +1
1228
2-43
2
Figure 48. Output Impedance (ZOUT) vs. Frequency, VSY = ±15 V
12.5
–12.5
–10.0
–7.5
–5.0
–2.5
0
2.5
5.0
7.5
10.0
V OU
T (2
.5V/
DIV
)
TIME (100µs/DIV)
VSY = ±15VVIN = 20V p-pAV = +1RL = 2kΩCL = 300pF
1228
2-43
4
Figure 49. Large Signal Transient Response, VSY = ±15 V
0.10
–0.10
0.05
0
–0.05
V OU
T (V
)
TIME (100µs/DIV)
VSY = ±15VVIN = 100mV p-pAV = +1RL = 2kΩCL = 1000pF
1228
2-43
6
Figure 50. Small Signal Transient Response, VSY = ±15 V
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 19 of 33
0.25
0.20
0.15
–0.10
0.10
0.05
0
–0.05
6
5
4
–1
3
2
1
0
INPU
T VO
LTA
GE
(V)
OU
TPU
T VO
LTA
GE
(V)
TIME (10µs/DIV)
VSY = ±5VVIN = 75mVAV = –100RL = 10kΩCL = 35pF
1228
2-43
7
INPUT
OUTPUT
Figure 51. Positive Overload Recovery, VSY = ±5 V
–6
–5
–4
–3
–2
–1
0
1
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
–5 0 5 10 15 20 25
OU
TPU
T VO
LTA
GE
(V)
INPU
T VO
LTA
GE
(V)
TIME (5µs/DIV)
VSY = ±5VVIN = 75mVAV = –100RL = 10kΩCL = 35pF
1228
2-43
9
INPUT
OUTPUT
Figure 52. Negative Overload Recovery, VSY = ±5 V
145
125
130
135
140
PSR
R (d
B)
TEMPERATURE (°C)–50 50250–25 75 100 125
VSY = ±5V TO ±15V
1228
2-42
0
Figure 53. Power Supply Rejection Ratio (PSRR) vs. Temperature, VSY = ±5 V to ±15 V
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
16
14
12
10
–2
8
6
2
4
0
INPU
T VO
LTA
GE
(V)
OU
TPU
T VO
LTA
GE
(V)
TIME (10µs/DIV)
VSY = ±15VVIN = 225mVAV = –100RL = 10kΩCL = 35pF
1228
2-43
8
INPUT
OUTPUT
Figure 54. Positive Overload Recovery, VSY = ±15 V
1228
2-44
0O
UTP
UT
VOLT
AG
E (V
)
TIME (5µs/DIV)
–16
–14
–12
–10
–8
–6
–4
–2
0
2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
–5 0 5 10 15 20 25
INPU
T VO
LTA
GE
(V)
VSY = ±15VVIN = 225mVAV = –100RL = 10kΩCL = 35pF
INPUT
OUTPUT
Figure 55. Negative Overload Recovery, VSY = ±15 V
140
120
100
80
60
40
20
0
CM
RR
(dB
)
FREQUENCY (kHz)0.1 10k1k100101
VSY = ±5VVSY = ±15V
1228
2-45
5
Figure 56. Common-Mode Rejection Ratio (CMRR) vs. Frequency,
VSY = ±5 V and VSY = ±15 V
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 20 of 33
120
100
80
60
40
20
–20
0
PSR
R (d
B)
FREQUENCY (kHz)0.1 10k1k100101
VSY = ±5V
PSRR+
PSRR–
1228
2-45
6
Figure 57. Power Supply Rejection Ratio (PSRR) vs. Frequency, VSY = ±5 V
50
40
30
20
10
0
OVE
RSH
OO
T (%
)
LOAD CAPACITANCE (nF)0.01 0.1 101
VSY = ±5VAV = +1RL = 2kΩVIN = 100mV p-p
OS–
OS+
1228
2-45
8
Figure 58. Small Signal Overshoot vs. Load Capacitance, VSY = ±5 V
–0.003
–0.002
–0.001
0
0.001
0.002
0.003
0.004
0.005
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
–0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
OU
TPU
T (V
)
INPU
T (V
)
TIME (µs)
VSY = ±5VVIN = 1V p-pRL = 2kΩ
INPUT
OUTPUT
1228
2-54
8
Figure 59. Positive Settling Time to 0.1%, VSY = ±5 V
120
100
80
60
40
20
–20
0
PSR
R (d
B)
FREQUENCY (kHz)0.1 10k1k100101
VSY = ±15V
PSRR+
PSRR–
1228
2-45
7
Figure 60. Power Supply Rejection Ratio (PSRR) vs. Frequency, VSY = ±15 V
50
40
30
20
10
0
OVE
RSH
OO
T (%
)
LOAD CAPACITANCE (nF)0.01 0.1 101
VSY = ±15VAV = +1RL = 2kΩVIN = 100mV p-p
OS–
OS+
1228
2-45
9
Figure 61. Small Signal Overshoot vs. Load Capacitance, VSY = ±15 V
–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
0.020
–30
–25
–20
–15
–10
–5
0
5
10
–2 –1 0 1 2 3 4 5 6 7 8
OU
TPU
T (V
)
INPU
T (V
)
TIME (µs)
VSY = ±15VVIN = 10V p-pRL = 2kΩ
INPUT
OUTPUT12
282-
551
Figure 62. Positive Settling Time to 0.1%, VSY = ±15 V
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 21 of 33
–0.003
–0.002
–0.001
0
0.001
0.002
0.003
0.004
0.005
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
–0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
OU
TPU
T (V
)
INPU
T (V
)
TIME (µs)
VSY = ±5VVIN = 1V p-pRL = 2kΩ
INPUT
OUTPUT
1228
2-55
2
Figure 63. Negative Settling Time to 0.1%, VSY = ±5 V
FREQUENCY (Hz)100 10M1M100k10k1k
1k
100
1
10
VOLT
AG
E N
OIS
E D
ENSI
TY (n
V/√H
z)
AV = +1 VSY = ±15VVSY = ±5V
1228
2-46
8
Figure 64. Voltage Noise Density vs. Frequency, VSY = ±5 V and VSY = ±15 V
FREQUENCY (kHz)0.01 1001 100.1
1
0.1
0.00001
0.001
0.0001
0.01
THD
+ N
(%)
80kHz>500kHz
VSY = ±5VRL = 2kΩVIN = 1V rms
1228
2-47
0
Figure 65. THD + N vs. Frequency, VSY = ±5 V
1228
2-55
5–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
0.020
–30
–25
–20
–15
–10
–5
0
5
10
–2 –1 0 1 2 3 4 5 6 7 8
OU
TPU
T (V
)
INPU
T (V
)
TIME (µs)
VSY = ±15VVIN = 10V p-pRL = 2kΩ
INPUT
OUTPUT
Figure 66. Negative Settling Time 0.1%, VSY = ±15 V
0
20
16
12
8
4
0 1.0 2.0 3.00.5 1.5 2.5
VOLT
AG
E N
OIS
E C
OR
NER
(nV/
√Hz)
FREQUENCY (Hz)
VSY = ±5VVSY = ±15V
1228
2-48
3
Figure 67. Voltage Noise Corner vs. Frequency, VSY = ±5 V and VSY = ±15 V
1228
2-47
1
FREQUENCY (kHz)0.01 1001 100.1
1
0.1
0.00001
0.001
0.0001
0.01
THD
+ N
(%)
80kHz>500kHz
VSY = ±15VRL = 2kΩVIN = 1V rms
Figure 68. THD + N vs. Frequency, VSY = ±15 V
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 22 of 33
AMPLITUDE (V rms)0.001 0.01 1010.1
1
0.1
0.0001
0.001
0.01
THD
+ N
(%)
VSY = ±5VRL = 2kΩfIN = 1kHz
1228
2-47
2
Figure 69. THD + N vs. Amplitude, VSY = ±5 V
TIME (1s/DIV)
INPU
T VO
LTA
GE
(50n
V/D
IV)
VSY = ±5V
1228
2-46
4
Figure 70. 0.1 Hz to 10 Hz Noise, VSY = ±5 V
VIN (V)–40 40205–10–25–35 2510–5–20–30 30 35150–15
15.0
–15.0
–12.5
–10.0
–7.5
–5.0
–2.5
0
2.5
5.0
7.5
10.0
12.5
INPU
T B
IAS
CU
RR
ENT
(mA
)
VSY = ±5V
1228
2-46
6
Figure 71. Input Bias Current vs. Input Voltage (VIN) Including
Input Overvoltage Range (Beyond VSY = ±5 V )
1228
2-47
3
AMPLITUDE (V rms)0.001 0.01 1010.1
1
0.1
0.0001
0.001
0.01
THD
+ N
(%)
VSY = ±15VRL = 2kΩfIN = 1kHz
Figure 72. THD + N vs. Amplitude, VSY = ±15 V
TIME (1s/DIV)
INPU
T VO
LTA
GE
(50n
V/D
IV)
VSY = ±15V
1228
2-46
5
Figure 73. 0.1 Hz to 10 Hz Noise, VSY = ±15 V
VIN (V)–50 500–40 10–30 20–20 30–10 40
12.5
–15.0
–12.5
–10.0
–7.5
–5.0
–2.5
0
2.5
5.0
7.5
10.0
INPU
T B
IAS
CU
RR
ENT
(mA
)
VSY = ±15V
1228
2-46
7
Figure 74. Input Bias Current vs. Input Voltage (VIN) Including
Input Overvoltage Range (Beyond VSY = ±15 V)
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 23 of 33
COMMON-MODE VOLTAGE (V)–5 –4 –3 –2 –1 0 1 2 3 4 5
1000
–1000
–800
–600
–400
–200
0
200
400
600
800
INPU
T B
IAS
CU
RR
ENT
(pA
)
VSY = ±5V
1228
2-48
0
+85°C+125°C
+25°C–40°C
Figure 75. Input Bias Current vs. Common-Mode Voltage (VCM) and
Temperature, VSY = ±5 V
FREQUENCY (kHz)0.001 0.01 1001010.1
10
0.1
1
CU
RR
ENT
NO
ISE
DEN
SITY
(pA
/√H
z)
VSY = ±15VVSY = ±5V
1228
2-47
5
Figure 76. Current Noise Density vs. Frequency, VSY = ±5 V and VSY = ±15 V
45
20
25
30
35
40
–50 –25 0 25 50 75 100 125
SOU
RC
ING
CU
RR
ENT
(mA
)
TEMPERATURE (°C) 1228
2-60
0
VSY = ±5V
Figure 77. Output Short-Circuit Sourcing Current vs. Temperature, VSY = ±5 V
COMMON-MODE VOLTAGE (V)–15 –10 –5 0 5 10 15
3000
–2000
–1000
–1000
0
1000
2000
INPU
T B
IAS
CU
RR
ENT
(pA
)
VSY = ±15V
1228
2-48
1
+85°C+125°C
+25°C–40°C
Figure 78. Input Bias Current vs. Common-Mode Voltage (VCM) and
Temperature, VSY = ±15 V
FREQUENCY (kHz)0.01 1001010.1
–90
–150
–140
–130
–120
–110
–100
CH
AN
NEL
SEP
AR
ATI
ON
(dB
)
VSY = ±15VVIN = 10V p-pAV = +1000RL = 2kΩ
1228
2-47
4
Figure 79. Channel Separation vs. Frequency, VSY = ±15 V
60
30
35
40
45
50
55
–50 –25 0 25 50 75 100 125
SOU
RC
ING
CU
RR
ENT
(mA
)
TEMPERATURE (°C) 1228
2-60
1
VSY = ±15V
Figure 80. Output Short-Circuit Sourcing Current vs. Temperature, VSY = ±15 V
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 24 of 33
–20
–50
–45
–40
–35
–30
–25
–50 –25 0 25 50 75 100 125
SIN
KIN
G C
UR
REN
T (m
A)
TEMPERATURE (°C) 1228
2-60
2
VSY = ±5V
Figure 81. Output Short-Circuit Sinking Current vs. Temperature, VSY = ±5 V
3
–3
–2
–1
0
1
2
0 50 100 150 200 250 300 350
CH
AN
GE
IN V
OS
(µV)
TIME (Seconds) 1228
2-60
4
Figure 82. Offset Voltage Short-Term Drift
–30
–80
–70
–60
–50
–40
–50 –25 0 25 50 75 100 125
SIN
KIN
G C
UR
REN
T (m
A)
TEMPERATURE (°C) 1228
2-60
3
VSY = ±15V
Figure 83. Output Short-Circuit Sinking Current vs. Temperature, VSY = ±15 V
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 25 of 33
THEORY OF OPERATION The ADA4177-1/ADA4177-2/ADA4177-4 are precision, bipolar op amps that integrate both input overvoltage protection (OVP) and input EMI filtering while maintaining a low 2 nA maximum bias current and a rail-to-rail output operation. Figure 84 shows a conceptual schematic of the main amplifier that uses super beta, bipolar input transistors and bias current cancellation to minimize the input bias current. The inputs are cascoded to protect the super beta input devices from damage during overvoltage conditions. The cascoded inputs feed into an active load that makes up the primary gain stage. A buffered transconductance (gm) stage converts a differential voltage to a differential current to drive the output stage. The rail-to-rail output can swing to 50 mV maximum (for example, the guaranteed room temperature limit for VOH is 14.95 V when the positive supply is 15 V) with a 1 mA load at 25°C.
1228
2-44
9
gm
P B
IAS
N B
IAS
OVP
OVP
Figure 84. Conceptual Schematic
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 26 of 33
APPLICATIONS INFORMATION ACTIVE OVERVOLTAGE PROTECTION The ADA4177-1/ADA4177-2/ADA4177-4 use active overvoltage protection to protect the devices from damage when the inputs are driven to a voltage up to 32 V above the positive supply voltage or 32 V below the negative supply voltage. The ADA4177-1/ADA4177-2/ADA4177-4 not only protect the input from damage, but they also reduce the input noise.
Common Protection Methods
Add an External Series Input Resistor
When an op amp does not have input overvoltage protection, moving the input voltage above or below the supply voltage can cause excessive input current, which can damage the op amp. To avoid this, add a series resistor at the input. To protect the op amp from a 30 V transient beyond either rail, limit the input current to 5 mA, and add a 6 kΩ series resistor to the input. However, a trade-off of adding the series resister is its added thermal noise. The 6 kΩ series resistor exhibits 10 nV/√Hz of thermal noise, which adds quadrature thermal noise from the resistor with the op amp noise.
22RESISTORAMPOPTOTAL NNN +=
where: NTOTAL is the total noise. NOP AMP is the op amp noise. NRESISTOR is the thermal noise generated by the resistor.
When the additional thermal noise from the series resistor is added to the thermal noise (8 nV/√Hz) of the ADA4177-1/ADA4177-2/ ADA4177-4, the 6 kΩ series resistor brings the total thermal noise to 12 nV/√Hz, which is a 70% increase in thermal noise. Figure 85 shows how noise from the additional source resistance adds to the total noise at the amplifier input; the higher the source resistance, the higher the total noise. Because the ADA4177-1/ ADA4177-2/ADA4177-4 have integrated input protection for overvoltage conditions, the noise trade-off is avoided.
20
0
2
4
6
8
10
12
14
16
18
EQU
IVA
LEN
T TH
ERM
AL
NO
ISE
(nV/
√Hz)
TOTAL SOURCE RESISTANCE0 30000250002000015000100005000
TOTAL NOISE
RESISTOR NOISE
1228
2-44
5
ADA4177-1/ADA4177-2/ADA4177-4 NOISE
Figure 85. Equivalent Thermal Noise vs. Total Source Resistance
Add External Clamping Diodes
Precision op amps have a low VOS and a high common-mode rejection ratio (CMRR). Both of these characteristics simplify system calibration and minimize dynamic error. To maintain these specifications in the presence of ESD events, bipolar op amps often have internal clamp diodes and small limiting resistors in series with their inputs; however, these do not address fault conditions where the inputs exceed the rails. In these cases, the system designer commonly adds clamping diodes (D1 and D2) along with a series resistor (ROVP), shown in Figure 86.
1228
2-44
1
ROVP
RF
VINVOUTD2
D1
V–
V+
Figure 86. Common Scheme for Protecting Precision Amplifier Inputs from
Overvoltage Conditions
If the signal source at VIN is driven to one diode voltage beyond the op amp supplies, the fault current is limited by ROVP. Schottky diodes have a low forward knee voltage of 200 mV less than a typical small signal diode. Therefore, all overvoltage currents are shunted through the external diodes (D1 and D2). The reverse leakage current for a typical Schottky diode is extremely variable with the reverse voltage level. Therefore, as the noninverting input of the op amp swings, the D1 and D2 leakage currents do not match, and the differences pass through ROVP, creating a voltage drop. The voltage drop on ROVP appears as a variation in VOS, which can drastically reduce the CMRR performance. Because the ADA4177-1/ADA4177-2/ADA4177-4 have integrated input protection during overvoltage conditions, the degradation in performance is avoided.
Input Protection Circuit
The ADA4177-1/ADA4177-2/ADA4177-4 inputs provide overvoltage protection without the trade-offs encountered in the common design methods. The conceptual schematic of the input is shown in Figure 87.
1228
2-44
2
J1B
J1AVIN1
J2B
J2AVIN2
V+
V– Figure 87. Conceptual Schematic of the Inputs of the
ADA4177-1/ADA4177-2/ADA4177-4
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 27 of 33
J1A, J1B, J2A, and J2B are depletion mode junction field effect transistors (JFETs) that replace the series resistance in the conventional protection scheme. Under normal operation, the input bias current of the ADA4177-1/ADA4177-2/ADA4177-4 flows through the J1A and J2A transistors without pinching off the channel. To achieve excellent noise performance, J1A and J2A must have a low on resistance (RDSON) of approximately 300 Ω.
When either input exceeds the rail by more than a diode, large currents flow through either J1A or J2A, which causes the channels to pinch off and effectively raises their resistance. Figure 88 shows the positive overvoltage and negative overvoltage characteristics as the FET channel pinches.
12
–10
–8
–6
–4
–2
0
2
4
6
8
10
INPU
T B
IAS
CU
RR
ENT
(mA
)
VIN (V)–50 503010–10–30
1228
2-50
0
VSY = ±15V
Figure 88. Input Bias Current During Positive and Negative Overvoltage,
VSY = ±15 V, Voltage Follower Configuration
Figure 89 shows how the JFET effective resistance increases exponentially as shown by the measurements at 2 V, 20 V, and 40 V overvoltage. As the overvoltage increases from 2 V to 40 V, the resistance increases from 300 Ω to 3.5 kΩ (a factor of 11).
10
–2
0
2
4
6
8
OVE
RVO
LTA
GE
(mV)
VIN (V)2.5 42.532.5 37.527.522.517.512.57.5
1228
2-45
4
300Ω AT 2V
2.2kΩAT 20V 3.5kΩ AT 40V
Figure 89. Overvoltage vs. Input Voltage (VIN), Voltage Follower
Configuration
LIMITING OVERVOLTAGE CURRENT OUT OF THE POSITIVE SUPPLY PIN Because the positive power supply of the system can be incapable of sinking the large overvoltage current of 8 mA (see Figure 88), care was taken to divide down this current into the positive rail during an overvoltage event. As shown in Figure 90, Q1L is a lateral PNP transistor that serves two purposes. First, the emitter base acts as a clamping diode to route the overvoltage current away from the V+ pin and to the V− pin. Second, it divides down this current via the beta of Q1L. At an emitter current of 8 mA, the beta of Q1L is approximately 8, which reduces the current injected into the positive supply by a factor of 8.
1228
2-44
3
J1B
J1A+IN
V+
Q1L
V–
Figure 90. Overvoltage Protection Circuitry
Figure 91 shows the positive and negative supply currents when the input voltage exceeds the supply voltages (and overvoltage condition). The current at the V+ terminal does not reverse direction during an overvoltage event because the current is directed to V− via the collector of Q1L.
8
–12
–10
–8
–6
–4
–2
0
4
6
2
SUPP
LY C
UR
REN
T (m
A)
INPUT DIFFERENTIAL (V)–40 403020100–10–20–30
1228
2-45
2
POSITIVE SUPPLY CURRENT
NEGATIVE SUPPLY CURRENT
Figure 91. Supply Current vs. Input Differential, Circuit Configured at
Unity Gain with V+ = +15 V and V− = −15 V
If negative overvoltage transients are expected, ensure that the negative voltage source driving V− can handle sourcing current without forcing current into the device and causing the supply voltage to change.
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 28 of 33
EMI PROTECTION The ADA4177-1/ADA4177-2/ADA4177-4 inputs are also protected from high frequency EMI. In an op amp with no EMI protection, signals not within the bandwidth of the op amp couple into sensitive amplifier inputs and become rectified as they travel through the amplifier, eventually appearing as ac feedthrough on top of a dc offset. When an input filter is not provided, these offsets can be quite large. These offsets are referred to as the electromagnetic interference rejection ratio (EMIRR). The amplifier EMIRR is defined as
×=
OSΔVEMIRR
mV100log20
where: 100 mV is generally the peak-to-peak input used for the test. ΔVOS is the change in the op amp offset as a result of the input signal.
Figure 92 shows the input EMI protection of the ADA4177-1/ ADA4177-2/ADA4177-4.
120
100
80
60
40
20
0
EMI R
EJEC
TIO
N R
ATI
O P
EAK
VO
LTA
GE
(dB
)
FREQUENCY (MHz)10 1000100
1228
2-45
3
INPUT +INVSY = ±15VRF POWER = –16dBm (50mV p-p)
Figure 92. EMI Rejection Ratio Peak Voltage vs. Frequency
SELF HEATING During an overvoltage condition, the ADA4177-1/ADA4177-2/ ADA4177-4 dissipate heat according to the thermal resistance (θJA) of the package it is in, which, in turn, heats up the die. Ensure that the specified operating junction temperature does not exceed 150°C for device protection. Extended overtemperature exposure can cause some operating specifications to shift outside of their guaranteed limits.
As shown in Figure 88, the ADA4177-1/ADA4177-2/ADA4177-4 inputs sink by approximately 8 mA at 15 V overvoltage. In that condition, the ADA4177-1/ADA4177-2/ADA4177-4 dissipate 120 mW of power. If the package has a θJA of 100°C/W, the junction temperature rises by approximately 12°C over the ambient temperature of the package and junction. In such a case, derate the ambient operating temperature by 12°C (125°C minus 12°C) for an absolute maximum operating temperature of 113°C.
When the junction temperature exceeds the absolute maximum junction temperature of 150°C, add an additional series resistance to the inputs to further decrease the overvoltage current. Figure 93 shows the maximum operating temperature vs. the continuous overvoltage at θJA = 150°C/W.
140
120
100
80
60
40
20
0
MA
XIM
UM
OPE
RA
TIN
G T
EMPE
RA
TUR
E (°
C)
CONTINUOUS OVERVOLTAGE (V)0 403510 15 20 25 305
1228
2-44
7
WITH TWO INPUTS IN OVERVOLTAGE
WITH ONE INPUT IN OVERVOLTAGE
Figure 93. Maximum Operating Temperature vs. Continuous Overvoltage for
One Input and Two Inputs (θJA = 150°C/W)
USING THE ADA4177-1/ADA4177-2/ADA4177-4 AS A COMPARATOR The ADA4177-1/ADA4177-2/ADA4177-4 can be used as a comparator as long as relatively small input impedance can be tolerated. That is, the input differential pair is diode clamped but the overvoltage protection circuitry limits the differential. Figure 94 shows the input current vs. the input differential voltage with ±15 V supplies.
8
–8
–6
–4
–2
0
2
4
6
INPU
T C
UR
REN
T (m
A)
INPUT DIFFERENTIAL (V)–20 20151050–5–10–15
1228
2-45
1
Figure 94. Input Current vs. Input Differential with ±15 V Supplies
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 29 of 33
Figure 95 shows the input and output of a comparator circuit referenced to ground using the ADA4177-1/ADA4177-2/ ADA4177-4. The supply voltages are ±5 V. The −INx input is grounded and a positive input is stepped to ±1 V. Both the positive and negative recovery is approximately 4 µs.
1228
2-44
8
VIN
VOUT
Figure 95. ADA4177-1/ADA4177-2/ADA4177-4 Used as a Comparator with
±5 V Supplies and a ±1 V Input Step, Voltage Follower Configuration
OUTPUT PHASE REVERSAL Phase reversal is defined as a change in polarity in the amplifier transfer function. Many op amps exhibit phase reversal when the voltage applied to the input is greater than the maximum common-mode voltage. In some instances, this phase reversal can cause permanent damage to the amplifier. In feedback loops, it can result in system lockups or equipment damage. The ADA4177-1/ADA4177-2/ADA4177-4 are immune to phase reversal problems even at input voltages beyond the power supply settings.
1228
2-48
2
Figure 96. Output Showing No Phase Reversal in Overvoltage Condition
PROPER PRINTED CIRCUIT BOARD (PCB) LAYOUT The ADA4177-1/ADA4177-2/ADA4177-4 are high precision devices. To ensure optimum performance at the PCB level, take care in the design of the board layout.
To avoid leakage currents, maintain a clean and moisture free board surface. Coating the surface creates a barrier to moisture accumulation and reduces parasitic resistance on the board.
Keeping supply traces short and properly bypassing the power supplies minimizes the power supply disturbances caused by the output current variation, such as when driving an ac signal into a heavy load. Connect bypass capacitors as closely as possible to the device supply pins. Stray capacitances are a concern at the outputs and the inputs of the amplifier. Keep the signal traces at least 5 mm from supply lines to minimize coupling.
A variation in temperature across the PCB can cause a mismatch in the Seebeck voltages at solder joints and other points where dissimilar metals are in contact, resulting in thermal voltage errors. To minimize these thermocouple effects, orient resistors so that heat sources warm both ends equally. Ensure, where possible, that input signal paths contain matching numbers and types of components, to match the number and type of thermocouple junctions. For example, dummy components such as zero value resistors can be used to match real resistors in the opposite input path. Place matching components in close proximity to each other, and orient them in the same manner. Ensure that leads are of equal length so that thermal conduction is in equilibrium. Keep heat sources on the PCB as far away from amplifier input circuitry as is practical.
The use of a ground plane is highly recommended. A ground plane reduces EMI noise and maintains a constant temperature across the circuit board.
LONG-TERM DRIFT The stability of a precision signal path over its lifetime or between calibration procedures is dependent on the long-term stability of the analog components in the path, such as op amps, references, and data converters. To help system designers predict the long-term drift of circuits that use the ADA4177-1/ ADA4177-2/ADA4177-4, Analog Devices measured the offset voltage of multiple units for 10,000 hours (more than 13 months) using a high precision measurement system, including an ultrastable oil bath. To replicate real-world system performance, the devices under test (DUTs) were soldered onto an FR4 PCB using a standard reflow profile (as defined in the JEDEC J-STD-020D standard), as opposed to testing them in sockets. This manner of testing is important because expansion and contraction of the PCB can apply stress to the integrated circuit (IC) package and contribute to shifts in the offset voltage.
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 30 of 33
The ADA4177-1/ADA4177-2/ADA4177-4 have extremely low long-term drift, as shown in Figure 97. The red, blue, and green traces show sample units. Note that the ADA4177-1/ADA4177-2/ ADA4177-4 have a mean drift over 10,000 hours of less than 2 µV, or 2% of their maximum specified offset voltage of 60 µV at room temperature.
TIME (Hours)
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10,0
00
CH
AN
GE
IN O
FFSE
T VO
LTA
GE
(µV)
–8
–6
–4
–2
0
2
4
6
8
1228
2-19
7
MEANMEAN PLUS ONE STANDARD DEVIATIONMEAN MINUS ONE STANDARD DEVIATION
VSY = 10V27 UNITSTA = 25°C
SAMPLE 1SAMPLE 2SAMPLE 3
Figure 97. Measured Long-Term Drift of the ADA4177-1/ADA4177-2/ ADA4177-4 Offset Voltage over 10,000 Hours
TEMPERATURE HYSTERESIS In addition to stability over time as described in the Long-Term Drift section, it is useful to know the temperature hysteresis, that is, the stability vs. cycling of temperature. Hysteresis is an important parameter because it tells the system designer how closely the signal returns to its starting amplitude after the ambient temperature changes and subsequent return to room temperature. Figure 98 shows the change in input offset voltage as the temperature cycles three times from room temperature to +125°C to −40°C and back to room temperature. The dotted line is an initial preconditioning cycle to eliminate the original temperature induced offset shift from exposure to production solder reflow temperatures.
In the three full cycles, the offset hysteresis is typically only 2 µV, or less than 2% of its 120 µV maximum offset voltage over the full operating temperature range. The histogram in Figure 99 shows that the hysteresis is larger when the device is cycled through only a half cycle, from room temperature to hot 125°C and back to room temperature.
TEMPERATURE (°C)–40 –20 0 20 40 60 80 100 120
CH
AN
GE
IN O
FFSE
T VO
LTA
GE
(µV)
–80
–60
–20
–40
0
20
40
60
80VSY = 10V
1228
2-19
8
PRECONDITIONCYCLE 1CYCLE 2CYCLE 3
Figure 98. Change in Offset Voltage over Three Full Temperature Cycles
OFFSET VOLTAGE HYSTERESIS (µV)
NU
MB
ER O
F D
EVIC
ES
1228
2-19
9
0
40
30
50
35
45
252015105
0
40
30
50
35
45
252015105
–18 –15 –12 –9 –6 –3 0 3 6 9 12 15 18
VSY = 10V27 UNITS × 3 CYCLESHALF CYCLE = +26°C, +125°C, +26°CFULL CYCLE = +26°C, +125°C, +26°C, –40°C, +26°C
HALF CYCLEFULL CYCLE
Figure 99. Histogram Showing the Temperature Hysteresis of the Offset Voltage over Three Full Cycles and over Three Half Cycles
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 31 of 33
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°0°
0.800.550.40
4
8
1
5
0.65 BSC
0.400.25
1.10 MAX
3.203.002.80
COPLANARITY0.10
0.230.09
3.203.002.80
5.154.904.65
PIN 1IDENTIFIER
15° MAX0.950.850.75
0.150.05
10-0
7-20
09-B
Figure 100. 8-Lead Mini Small Outline Package [MSOP]
(RM-8) Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
0124
07-A
0.25 (0.0098)0.17 (0.0067)
1.27 (0.0500)0.40 (0.0157)
0.50 (0.0196)0.25 (0.0099) 45°
8°0°
1.75 (0.0688)1.35 (0.0532)
SEATINGPLANE
0.25 (0.0098)0.10 (0.0040)
41
8 5
5.00 (0.1968)4.80 (0.1890)
4.00 (0.1574)3.80 (0.1497)
1.27 (0.0500)BSC
6.20 (0.2441)5.80 (0.2284)
0.51 (0.0201)0.31 (0.0122)
COPLANARITY0.10
Figure 101. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
ADA4177-1/ADA4177-2/ADA4177-4 Data Sheet
Rev. E | Page 32 of 33
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 0619
08-A
8°0°
4.504.404.30
14 8
71
6.40BSC
PIN 1
5.105.004.90
0.65 BSC
0.150.05 0.30
0.19
1.20MAX
1.051.000.80
0.200.09 0.75
0.600.45
COPLANARITY0.10
SEATINGPLANE
Figure 102. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14) Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AB
0606
06-A
14 8
71
6.20 (0.2441)5.80 (0.2283)
4.00 (0.1575)3.80 (0.1496)
8.75 (0.3445)8.55 (0.3366)
1.27 (0.0500)BSC
SEATINGPLANE
0.25 (0.0098)0.10 (0.0039)
0.51 (0.0201)0.31 (0.0122)
1.75 (0.0689)1.35 (0.0531)
0.50 (0.0197)0.25 (0.0098)
1.27 (0.0500)0.40 (0.0157)
0.25 (0.0098)0.17 (0.0067)
COPLANARITY0.10
8°0°
45°
Figure 103. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
Data Sheet ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 33 of 33
ORDERING GUIDE Model1 Temperature Range Package Description Package Option Marking Code ADA4177-1ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A3E ADA4177-1ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A3E ADA4177-1ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A3E ADA4177-1ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4177-1ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4177-1ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4177-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A36 ADA4177-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A36 ADA4177-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A36 ADA4177-2ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4177-2ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4177-2ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ADA4177-4ARUZ −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 ADA4177-4ARUZ-R7 −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 ADA4177-4ARUZ-RL −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14 ADA4177-4ARZ −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 ADA4177-4ARZ-R7 −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 ADA4177-4ARZ-RL −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14 1 Z = RoHS Compliant Part.
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