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VHDL Design Units

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VHDL Design Units

Entity

Package

Configuration

Architecture

Package body

Primary Design Units

Secondary Design units

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VHDL Terms

Entity :

All designs are expressed in terms of entities. An

entity is the most basic building block in a design.If the design is hierarchical, then the top-leveldescription will have lower-level descriptionscontained in it. These lower-level descriptions will

be lower-level entities contained in the top-levelentity description

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VHDL Terms

Architecture :

All entities that can be simulated have an

architecture description. The architecture describesthe behaviour of the entity. A single entity canhave multiple architectures. One architecture mightbe behavioural while another might be structural

description of the design.

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VHDL Terms

Configuration :

A Configuration statement is used to bind a

component instance to an entity-architecture pair.

Package :

A package is a collection of commonly used datatypes and subprograms in a design. (like a toolboxthat contains tools used to build designs)

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An Entity and its Model

Hardware

Abstraction

of a

Digital System

Entity Declaration

Entity

Model

Architecture Bodies

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Components

Entity

(Interface)

Architecture

(Function)

Package

Declaration

Configuration

Package

Body

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A VHDL File

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Design Entity

Functional Definition

Entity Declaration

Architecture Body

Entity

Interface Declaration

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Entity

Declares the design name.

Provides the port information

Describes the interface of the design entity.

The interface includes all inputs, outputs and bi-directional

signals and generics.

A declarative part to declare Subprograms, types and

constants .

Declarations are visible to all the architectures assigned

to the entity An entity may contain its own passive statements.

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Entity Syntax

Entity entity-nameis

[generic (list-of-generics-and-their-types);]

[port (list-of-interface-port-names-and-their-types);]

[entity-item-declarations]

[begin

entity-statements]

End [entity][entity_name];

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PORTS

Each I/O signal in an entity declaration is a port.

Must have a name, a direction (mode) and a data type.

A port is a data object (signal).

It can be assigned values and used in expressions.

port (

portname : [mode] subtype_indication [:= init_value]

{; portname : [mode] subtype_indication [:= init_value]}

);

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Port Data Types

Pre defined

BooleanBoolean

bitbit

bit_vectorbit_vector

integerinteger

IEEE std_logic_1164

std_ulogic , std_logicstd_ulogic , std_logic std_logic_vectorsstd_logic_vectors

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Modes

In - input port, read only

out - output port , write only

inout - bi-directional port, read/write,

multiple drivers

buffer - read and update, single driver

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VHDL Entity

entity- name of a function and itsinterfaces

Full adderb_in

a_in

cy_ in

sum_out

cy_out

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Entity

entity

fulladder

is

port a_in,b_in,cy_in :

end

;

sum_out,cy_out : ;

(

)

in

bitout

bit

;

fulladder

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Entity Declarations

add4

a

b

ci

4

4Sum

co

4

EntityEntity add4

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Entity Declaration

ExampleExample

EntityEntity add4 isis

portport

( a : inin std_logic_vectorstd_logic_vector(3 downto 0);b : inin std_logic_vectorstd_logic_vector(3 downto 0);

ci : inin std_logicstd_logic;

sum : outout std_logic_vectorstd_logic_vector(3 downto 0);

co : outout std_logicstd_logic);

endend add4;

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Example

entity and2is --and gate

port (a,b : in bit;

y : out bit);

endand2;

architecture dataflowof and2is

Begin

y