PA-002 ESD_EOS rev_g

8/12/2019 PA-002 ESD_EOS rev_g

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Understanding and Protecting Against Electrical

Overstress (EOS) of Operational-Amplifiers

By Thomas KuehlSenior Applications Engineer

Precision AnalogLinear Applications Engineering


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This is your IC


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This could be your IC after an

electrical overstress event!


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Presentation Subjects

ESD and EOS definitions

Amplifier input range

ESD models

Internal ESD and consequently EOS protection circuits

Amplifier EOS operating situations

External EOS protection


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ESD and EOS: Whats the difference?

Electrostatic Discharge (ESD)The transfer of electrostatic charge

between bodies or surfaces at different electrostatic potential.

Electrical Over Stress (EOS)The exposure of an item to current or

voltage beyond its maximum ratings.

EOS

Low voltage >VsLonger duration event

Low power

In-circuit event

ESD

High voltage (kVs)Short duration event (1-100ns)

Fast edges

Low power

Out of circuit event


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-

++

OP2 !OPAMP

L1 50n C1 100n

L2 50n

C2 100n

V1 5

V2 5

R2 10kR1 1k

+

VG1

R4 1kR3 1k

Vout-

++

OP1 !OPAMP

-5V bus

+5V bus

PC BoardHandling and assembly

environments

Two very different environments

ESD EOS

10V

0V


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The TI data sheet Absolute Maximum Ratings is a good

place to check and assure EOS problems are avoided


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Safe with Rs

Safe with Rs

CMV input range

Non-linear input

Input voltage range of an op-amp

+3.5V

0V

-0.1V

-0.5V

+5.5V

+5.0V Pos rail

Neg railNeg safe

Pos Safe

-5.0V

ESD protect region

ESD protect region

+2kV

+100V

-100V

-2kV

Input

voltage

*Selected to limit input current to 10mA max.

In-circuit max

positive

In-circuit max

negative

+

-

+

U1 OPA735

V1 5

C1 100n

Vo

+

Vi 2.5

Rs 1k

OPA735 low

Drift CMOS

Op-amp

*

+

_


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ESD Stress Models

L1 7.5uR1 1.5k

C1

100p+

VG1

0*1

*)(

2

2

iLCdt

di

L

Ri

dt

d

ESD model R L C V

Human Body Model HBM 1.5 k 7500 nH 100 pF 2kV

Machine Model MM 20 750 nH 200 pF 100 - 200V

Charged Device Model CDM 20 5 nH 2-10pF 200V - 1kV


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L1 7.5u R1 1.5k

C2 2p Rdut 10

VF1

A+

AM1

t

SW1

C1 100p

IC

IC1

Human Body ESD Model

modeled in TINA Spice

DUT

2kV

T

Time (s)

0 50n 100n 150n 200n

AM1 (Amps)

0.0

500.0m

1.0

1.5

VF1 (Volts)

0.0

5.0

10.0

15.0

Rdut = 10 Ohms

Human Body model

Rdut is the on

resistance of an ESD

protection circuit


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L1 500n R1 10

C2 2p Rdut 10

VF1

A+

AM1

t

SW1

C1 200p

IC

IC1

Machine ESD Model


DUT

200V

Machine Model

Rdut is the on

resistance of an ESD

protection circuit

T

Time (s)

0 50n 100n 150n 200n

AM1 (Amps)

-2.0

0.0

2.0

4.0

VF1 (Volts)

-20.0

0.0

20.0

40.0

Rdut = 10 Ohms


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CDM - ESD by induction

T

Cp: 2p[F]

Cp: 4p[F]

Cp: 6p[F]

Time (s)

0.0 1.0n 2.0n 3.0n 4.0n

Current(A)

-5.0

-2.5

0.0

2.5

5.0

Cp: 2p[F]

Cp: 4p[F]

Cp: 6p[F]

TCp: 2p[F]

Cp: 4p[F]

Cp: 6p[F]

VG1

Time (s)

0.0 1.0n 2.0n 3.0n 4.0n

Voltage(V)

-200

0

200

400

VG1

Cp: 6p[F]

Cp: 4p[F]

Cp: 2p[F]

L1 5n R1 20

C1 10p

SW1

Rdut 10

Cp 2p

A+

AM1

VF1IC

IC1

250V

2 - 10pF

Charge Device Model


Rdut is the onresistance of an ESD

protection circuit


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T4!NPN

D31N914

R11k

Pad

Vee

Rb

Common input/output ESD protection circuits

Input steering diodes

Vcer input clamp

CMOS input/output protection

D1 1N914D2 1N914

Vdd / Vcc bus

input or

output

circuit

-Vdd / Vee bus

PadAbsoption

circuit

T1 NonameD1 PMLL4448

Pad/Pin

C1 20f

D2 PMLL4448

R1 190

R2 74

R3 74

T1 Noname

C1 20f

Input Pad

V+

V-

R

419.5

R49.4

R49.4

R49.4

R49.4

R49.4

R49.4

R410.2

Ouput Pad

C1 20f

V-

SCR

OR

input

pad

output

pad

IC level SCR model

is more complex


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Supply clamp circuits

NPN bipolaron high-speed process

ON

OFF

V+

V-

V+

V-

V+

V-

T1 !NPN

RB 500

IS1 1u

T2 Noname T3 !NPN

Rsub 500RB 500

Avala nche generat ing

current - internal or

external source

RB set by design

and process

Bipolar BVcer Clamp

NMOS ClampNMOS parasitic

NPN transistor


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NMOS parasitic bipolar transistor

IC

n n

Drain

(collector)

Source

(emitter)

Gate

IDS

Rsub

Isub

Sub (base) P-sub/epi

p


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A commonly applied ESD protection method

for analog integrated circuits

V+

V-

Vo

In+

In- -

+

IOP1

D11N41

48

D

21N4148

D31N41

48

D

41N4148 T1 !NPN

Rb 2k

Rs 1k

Rs 1k

D51N4148

D61N4148

Input protection Output protection

Power supply

absorption device

ultra

low leakage

diodes


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INA168 ESD cell layouts

Input pin

ESD2 N-sinkerBL

ESD1 NPN B-E

Supply clamp

NPN transistor /

resistor

Output pin

ESD7 NPN B-E

ESD8 N-sinkerBL


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V-

V+

V-V+

V2 2.5

R3 10k

+

-

+

U1 OPA364

V1 2.5

C1 100n C2 100n

+

VG1

Vo

+

VG2

Vin+

TL1

VG1 intended

l inear range signal

Vp = 2.25V, f = 100Hz

VG2 unintended

transients, noise

impulses, etc.

Input overdrive may activate

ESD protection circuits

T

Time (s)

0.00 5.00m 10.00m 15.00m 20.00m

VG1

-2.25

0.00

2.25

VG2

0.00

500.00m

1.00

Vin+

-2.25

500.00m

3.25

Vo

-2.50

0.00

2.50

VG1 + VG2 sum may activate

ESD circuit on peaks


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f


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Vcer clamp

transistor

V+

V-

TERM

GRN IN

GRN OUT OUT

-

+ +

OP1 !OPAMP+ -C1 10u

+-

C2 10u

R1 500 R2 500

R3 75

T1 !NPN

R4 75

R5 2k

TL1

+

VG1

One channel of RGB

amplifier application

V+/V- wall-wart power supply

without on/off switch

A supply clamp transistor failure during

resulting from an input EOS/ESD event


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EOS-related CMOS operational-amplifier field failures

TI quad CMOS operational amplifier failing unexpectedly in air conditioner application TI FA report indicated the operational amplifier die had carbonized material on die and

pin 4 (V+) to pin 11 (V-) short

EOS analysis of the customer application input and output ESD circuits did not reveal

any likely candidates


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EOS-related CMOS operational-amplifier field failures

A request for the Field Applications Engineers to observe and monitor the amplifier pinsduring the various operational cycles was made and provided

They found that a 20 Vpk pulse was appearing on the V+ line during operation of the airconditioner. The nominal supply voltage was +5 V

The EOS was causing either the supply-to-supply ESD clamp to break down, or voltagebreakdown of the amplifier transistor structures

A higher voltage operational amplifier and a transient voltage suppressor on the V+ line

were recommended

20 Vpk EOS

on V+ line


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Where does the 10mA

IOVERLOAD

maximum

originate?

Input current limiting by external series-R


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The continuous input overload current is set to < 1/10th

the JEDEC maximum latch test current (t 10ms)

Parasitic circuit latch testing

A+

AM1

+

-

+

U1 OPA348

+VS1 5

+

VS2 0

SW1

+

VG1 -

+

VCCS1

I/O high

I/O low

Compliance

Range +/-7.5V

I max 150mA

Input pins connected together

during output pin test

Pin under

test

Ouput f loats

during input

pin tests

Current injectionlatch test


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T

Time (s)

0 10m 20m 30m 40m 50m

AM1

0.0

15.0m

30.0m

VG1

0.00

1.75

3.50

VG2

0.00

2.50

5.00

VM1

0.00

1.75

3.50

Iinexcessively high

while supply ramps

Watch Vin during power up!


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A3 +in

A3 -in

+

Vcm 0

+

Vd/2 1

+

Vd/2 1

T1 !NPN

IS1 10u

Ib Comp 1n

+

-

+

IOP2

R1 25kRG 25k

C1 6p

Vin+

Vin-

Over-Voltage

Protection

A1 A2 +

Mirror of

A1circuit

Ext

Vbias

Vo

Ref

Vin-

Vin+

V+

V-

-

+

IOP1

-

+

IOP2

-

+

IOP3

R1 25k

R2 25k

R3 60k

R4 60k

R5 60k

R6 60k

RG 25k

Over-Voltage

Protection

Over-Voltage

Protection

EXT

Instrumentation amplifier input protection


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T

VG1

Vo

Time (s)

0.0 1.0u 2.0u 3.0u 4.0u 5.0u

Voltage(V)

0

2

4

6

8

10

VG1

Vo

V-

V+

V-V+

+

-

+

U1 OPA227

R1 500

R2 1k

+

VG1 R3 1k

Vo

V1 15 V2 15

C1 100n C2 100n

Input-outputvoltage difference

10%

90%

SR = 2.3V/us

Excessive differential input over-voltage

Possible occurrences

When operating an operational amplifieras a comparator

During slewing

Bipolar input operational amplifier

Plot for illustrative purposes only!


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T28 !NPN T23 !NPN

+

VG1

T41 !NPN

R1 500

V1 15

V2 15

RL 1k

Vo

T44 !NPN

Gain stages and bias circui ts

Pulse

Source

Vin-

Vin+

Iin20mA

max

VG1= 2VD+ (IinR1) + Vo

If VO= 0V, then:

Iin= (VG12VD) R1

OPA277 input-to-input differential

over-voltage protection

modern bipolar op-amps have input clamps

Input overdrive of CMOS rail to rail IO


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Input overdrive of CMOS rail-to-rail IO

chopper amplifiers

When Vin exceeds a Vcm maximum Vo is forced to an

output rail level

The op-amp is forced outside of its linear operating range

The feedback loop collapses and an input differentialvoltage develops

One clamp diode or the other becomes forward biased and

the input bias current can increase tremendously

This may limit the use of this type of operational amplifier

as a comparator

Back-to-back clamp diodes are inherent and internal to the chopper switch structures


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Vin Vs / Gain

+50mV

0mV

0V

-2.5V

Positive

input

Negative

output

0mV

-50mV

2.5V

0V

Negative

input

Positive

output

V-

V-

R1 2k R2 100k

+

VG1

-

+ VM1

V1 2.5C1 100n

V2 2.5

C2 100n

+

-

+

U1 OPA335

Stepped from

50mV to 0mV

OPA335

Av = -50V/V

Overload Recovery

Auto-zero CMOS

Operational-amplifiers


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+

-

+

U1 OPA234

V1 5

-

+VM1

C1 10nR1 50

+

VG1

Vin 5Vp-p

+ 2.0Vdc

+4.5V

VG1

-0.5V

+4.5V

VM1

0V

Output inversion

Output inversion during input overdrive


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Smoothing a transient

with an RLC filter

Transient amplitude

effectively reduced

Ringing dependent on

RLC values and load R

Amplifier PSRR becomes

important

T

VG1

VM1

Time (s)

0 20u 40u 60u 80u 100u

VG1

5.0

7.5

10.0

VM1

4.5

5.0

5.5

1us transient riding

on 5V supply voltage

VG1

VM1

+

VG1

C1 1u

-

+ VM1

L1 100u

RL 1k

Rs 5LOAD

5V Power

supply

Supply pin over-voltage protection


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Transient voltage suppression (TVS)

diode

6.8V- 550V reverse standoff voltage

Unidirectional & bidirectional models

Ppk = 1.5kW (10 x 1000us) @ 25C

Cj 1nF @ 20V

Littlefuse no. 1.5KE6.8, etc.

+

VG1

C1 10n

-

+ VM1RL 1k

Rs 10

LOAD

5V Power

supply

Vz = 6.8V

T

VG1

VM1

Time (s)

0 20u 40u 60u 80u 100u

VG1

5.0

7.5

10.0

VM1

4.5

5.8

7.0

zener diode used in simulation

no TVS model availableVM1

VG1 5V 1us transient riding

on +5V supply line

Supply pin over-voltage protection


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Features

Multilayer ceramic construction

Operating voltage range VM(DC)= 5.5 to 120V

Non-repetitive surge current (8/ 20us)

Non-repetitive energy (10/ 1000us)

response time


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Transient voltage suppressors

For CMOS, bipolar and SiGe

Features:

Available from 5.6 to 18V

DC working voltage 18VAC working voltage 14V

Turn-on-time


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Externally connected input protection

devices



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SD1 BAS40

SD2 BAS40

+

-

+

U1 OPA374

R1 5kR2 5k

+

VG1

C1 100n

-

+ VM1

V1 5

Schottky diodes provide

enhanced input protection

Features:

Forward voltage VF 380mV, IF= 1mA

Forward current IF= 200mA max (cont.)

Leakage current * IR 100nA, VR= 30V

Diode capacitance Ctot 5pF, VR= 0V


devices

* A small-signal silicon diode (IN4148) will likely turn on at lower voltage than the internal

ESD silicon diode and may exhibit lower leakage current than a Schottky diode.



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devices

An important point about added protection devices


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An important point about added protection devices

in the signal circuit

Protection components such as transient voltage suppressors (TVS), diodesand zener diodes all exhibit capacitance even when biased off

The capacitance will vary to some extent with the voltage applied across the

protection device

Most often the capacitance does not have a linear capacitance to voltagerelationship (voltage coefficient)

This non-linear capacitance to voltage relationship may increase distortion in

the protected circuit

It will be most evident in a very low THD circuits, but may not degrade

performance significantly

Power Line Communications (PLC)


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Power Line Communications (PLC)

EOS environmentIEC61000-4-5

Open-circuit surge pulse test

4kV, 1.2us tfront, 50us thalf-value

PLC EOS protection


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PLCEOS protectionActual protection scheme will vary with application and layout

High voltage MOVand low-voltage TVS

clamping

Fast rectifier andSchottky clamps

The internal output ESDcell is unlikely to withstand

the open-circuit HV pulse

- latching is probable


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In Summary

EOS and ESD events may activate ESD protection but resultin different outcomes

Internal ESD circuits may sufficiently handle EOS

Be aware of unique EOS situations such as power up and

input slewing

External EOS protection circuits will be required if device

damage is likely to occur without it

Documents

PA-002 ESD_EOS rev_g