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Kumar C Keshavan Designcon 2009 February 3, 2009
Panel Session TP-TU3 High-speed Channel Designs IBIS AMI Solution
2 © 2012 Cadence Design Systems, Inc. All rights reserved.
• Modeling of Equalization schemes including FFE, DFE • Representing Clock and Data Recovery • Computing Bit Error Rates == High Simulation Performance • Architectural Exploration
Challenges
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• Addressed device modeling challenges • Enables pre Architectural level Exploration and post layout • Already prevalent in IC design houses • IBIS Version 5(Aug 2008) includes AMI Modeling support • IBIS AMI Models are interoperable
Algorithm Level Modeling
4 © 2012 Cadence Design Systems, Inc. All rights reserved.
AMI – key concepts
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• EDA tools leverage/build on existing infrastructure • Tx/Rx will still require an analog I/O front end model
IBIS AMI Analog Channel
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• AMI Models are Executable “blackbox” • Platform dependent • One AMI model/device • Accompanied by Parameter Definition File
AMI Model Section
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IBIS AMI Data Flow API
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IBIS AMI-What it does and does not
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• AMI Models being developed and delivered by various ic vendors
• EDA tools need to support ami • Models are available so far through nda
AMI Status
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AMI in action
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AMI FFE
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FFE + DFE
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AMI Models enable practical design space exploration
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Design Space
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AMI optimizes tap coefficient
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• AMI Modeling is here – Essential for serial link analysis
• Pre and post layout • Increasing model availability • EDA tools support AMI
Final Thoughts
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