Part II

HARDWARE DESIGN

PART II HARDWARE

. INTRODUCTION

2.1 DESIGN PRECONDITIONS

A. Digital signals . The CPU module shown in fig clearly illustrates the three-bus

architecture of the typical processor. The 16 lines of the address bus are labeled A0

(least significant bit) through A15 (most significant bit). Similarly, the 8 lines of the

data bus are loaded D0 through D7. The 4 lines of the control bus are defined to be

consistent with the four types of machine cycles introduced in section 1.1 (I/O read and

write and memory read and write).

Most microprocessors and digital circuits provide signal levels that are

transistor-transistor-logic (TTL) compatible. In this system, any voltage level less than

or equal to 0.4V is considered a logic 0. Logic 1 is defined as a voltage level greater or

equal to 2.4V. Typical values are 0.2V and 3.4V. Note that a TTL receiver is designed

to accept voltages as high as 0.8V for logic 0 and as low as 2.0V for logic 1.

Another popular logic family is complemetary metal oxide semiconductor

(CMOS), devices that produce typical logic levels of 0V and 5V. In most cases, TTL

devices can drive a nearly unlimited number of CMOS devices (provided that pull up

resistors are used to bring TTL’s logic 1 level closer to 5.0V), but CMOS devices are

limited to one standard TTL load. The idealized square waves usually drawn (with 0

rise and fall times and perfectly squared edges) are not realized in practice.

B. Interfacing ‘slower’ devices . Usually, the speed of a I/O device is measured by

considering its address access time (or simply, access time). The 8088 processor

gives slow access time before it latches or gates the value on data bus, meaning

that it will not have enough time to decode the memory address and gate the

proper data byte onto the data bus.

Since nothing can be done to speed up the I/O device The only option left is

to slow down the processor. This can be done using two Popular methods, which are: -

1. Using a slower system clock to accommodate the slowest device in the circuit

Implementing a wait state generator to request a wait period until the device is ready.

2. The later method is a more efficient approach, especially for systems that

require Speed such as complex mathematical operation performing equipment, since

the System slows down only when it accesses the slower devices rather than throughout

its operation.

.2.2. SERIAL INTERFACING

2.2.1 THE EIA RS-232 SERIAL INTERFACE

First published in 1969, it was intended to describe the interface between a

computer terminal and a modem. In RS-232 terms the word DTE (data terminal

equipment) means the terminal computer and DCE (data communications equipment)

refers to the modem.

The RS-232 specifications limit the data rate to 19,200 bps with a 50-foot cable.

In practice, much longer cables can be accommodated, but at lower data rates. RS-232

is a voltage standard with typical logic levels of -12V for a logic 1 and +12V for a logic

0.

Standard TTL uses positive logic and provides 0.4V of noise immunity. RS-232 is quite

different: it uses negative logic with typical output levels of +12V. The higher voltages

are necessary to ensure reliable operation with long cables. A 2V noise immunity

specification allows the cables to be routed through noisy environments that would be a

problem for TTL.

In order to interface RS-232 with TTL, special line drivers and receivers are

required. The MC1488 (or equivalent) accepts TTL-level inputs and provides RS-232

output levels. The MC1489 does the opposite, converting the RS-232 levels on the

transmission line to TTL levels for the receiving device (in the case of this project the

8088 USART).

2.4.2 SIGNAL DESCRIPTION OF THE RS-232

When RS-232 was developed, six active-low (+12V) signals were defined to

control the transfer of data between a terminal (DTE) and a modem (DCE). The

definitions of each signal are as follows:

DCD: (data carrier detect) output by the DCE and indicates that the

Modem has detected a valid carrier from a remote site.

DTR: (data terminal ready) output by the DTE to indicate that it is

Present and ready for communications.

DSR: (data set ready) output by the DCE in response to DTE.

RTS: (request to send): output by the DTE to indicate that it is ready to

Transmit data.

CTS: (clear to send): this signal is output by the DCE and acknowledges

RTS. It indicates that the DCE is ready for transmission.

RI: (RING) output by the DCE (modem) and is active in synchronism

With the telephone line signal

2.4.3 MECHANICAL INTERFACE OF THE RS-232 (DB 9 CABLE)

Fig2.1 pin out of RS-232 cable

IMPORTANT TERMS

2.3.1 The 8088 microprocessor. The processor in the design (intel8088) is an 8-bit

CPU available in three clock rates that is 5MHZ, 8MHZ, 10MHZ packaged in a 40

pins CERDIP or plastic package. 8088 operate in a single processor or multi-processor

to achieve a high performance.

Some of the pins serve a particular function in a minimum mode (or single

processor mode) and others function in maximum mode (multiprocessor mode)

configuration.

The terms we have found new from that of our knowledge of 8085 processor are listed

below.

TEST: this input is examined by a “WAIT” instruction if it goes LOW execution will

continue else the processor remains in idle state

MN/MX: the logic level at this pin decides whether the processor is to operate in either

minimum (single processor) or maximum (multiprocessor) mode.

LOCK: this output pin indicates that other system bus masters will be prevented from

gaining the system bus, while the LOCK signal is low.

2.3 CIRCUIT DESCRIPTIONS

2.3.1 CLOCK GENERATOR

In every microprocessor based device the operations done by the CPU

need common system timing in order to harmonize the various external and internal

processes. A clock generator device usually employing a crystal oscillator provides this

system-timing signal. The 8088 CPU module shown in fig.2.1 also demonstrates a

commonly used clock generator circuit using a crystal, a single 74HC04 inverter IC

and some passive components to start the crystal to oscillate.

The crystal type square wave generator is most of the time employed for

systems that require higher clock speeds (in the MHZ range), since only crystal based

oscillators can generate frequencies up to this range. The project design, however, is

based on system clock frequency in the higher MHZ range (about 6MHZ). Hence a

crystal based clock generator was not found a necessity in the design.

A disadvantage of the crystal based oscillator is that it does not output a

fairly shaped square waveform most of the time. This specially is a problem in high

frequency operations because of the stray and junction capacitances created. Another

shortcoming of the crystal oscillator is that it requires a crystal, which is most of the

time found with values of common needs. Thus we cannot modify the clock rate to our

needs but rather the design itself might need modification to adjust for the available

clock rate determined by the crystal.

Thus it was desired to design the system with another type of square wave

generator, which was decided on a 555 timer IC. The device setup and output

waveforms are shown below: -

Fig.2.2. the 555 timer connected for a stable operation to generate

the necessary main system clock.

Thus the 555 timer was found to provide a good result in terms of

wave shape and stable operation which are necessary parameters for reliable system

performance. The output frequency can be easily calculated using the following

derived formula: -

Thus for a system clock speed of 6MHZ, with the values of Ra and Rb

chosen as 5000 and 1000 respectively, the value of the capacitor C can be

found easily with : -

Thus a 0.001 F capacitor should give a good approximate result.

Apart from the main system clock there also exists another clock generator in the

design with a much lower clock speed (about 19,600 Hz) and having a purpose of

supplying the baud rate clock for the serial communication device (8251A USART).

The component selection and frequency results will be discussed in later sections

dealing with the device.

2.4 SERIAL INPUT /OUTPUT INTERFACING 2.4.1 OVERVIEW

All microcomputer input /output fall under one of two broad categories: serial or

parallel. In parallel port at least 11-condctor cables are required. The parallel port also

tends to be hardware specific, with the result that a parallel port on computer may not

be compatible with a parallel port on an other computer.

A serial I/O port transmits each data byte bit by bit. The immediate advantage of

this technique is that only two conductors are used: the signal wire and ground unless

and otherwise it is full duplex in which case three wires is allowed. Of course, we

decide how long each bit will persist and what order of the bits will be. These “rules”

are referred to as the serial communication protocols. As you might imagine, several

different protocols have been developed over the years.

The obvious penalty with a serial I/O port is a significant reduction in the data

transfer rate. The most popular serial standard, EIA RS-232, restricts the data rate to

less than 2000 bytes per second and cable length to less than 50 ft. newer (and faster)

standards have been proposed, but have not gained the RS-232 popularity.

Despite this disadvantage, serial communication and RS-232 standards in

particular have become widely accepted. One of the reasons is the definition by the EIA

committee of a “standard” serial port. By defining the protocol, users can be sure of

compatibility between their equipments and an RS-232 serial port.

Another powerful feature of serialized data is that such data can easily be converted to

audio tones and transmitted over the switched telephone network. This is done with a

modem and allows communication between computer equipment thousand of miles

apart.

ASYNCHRONOUS SERIAL COMMUNICATIONS

One of the most common applications of serial I/O port is the interface of a

keyboard on a video display terminal. In this circuit, each keystroke generates the

seven bits ASCII code that is converted to bit by bit serial form and then transmitted to

a computer over a two or three conductor cable.

Note an important characteristics of this interface: at some times the serial ports will be

required to transfer data at 10 to 20 characters per second, but at other times a data

rate may be 1 or 2 characters per second. Indeed, most of the time the keyboard is not

in use and the data rate is zero. Because of this erratic data rate, an asynchronous

communication protocol must be established.

The accepted technique for asynchronous serial communication is to hold the serial

output line at logic 1 level (called mark) until data is to be transmitted. Each character

is required to begin with logic 0(called space). This character is called the start bit and

is used to synchronize the transmitter and receiver. The data is sent least significant bit

first and framed between the start bit (always a 0) and one or two stop bits (always a 1).

The start and stoop bit carry no information, but are required because of the

asynchronous nature of the data. The data rate can be expressed as bits per second or

characters per second. The term “bits per second” is also called as baud rate. This

value in our project is about 600.

2.4.2 STANDARD ASYNCHRONOUS SERIAL COMMUNICATIION PROTOCOL

As we have mentioned previously, protocols define certain rules that should be

followed to help standardize the communication technique. An example is the adoption

of a 0 start bit and logic 1 stop bits. In setting up serial port, several parameter must be

specified, the most common of which are as follows.

Data bits per character, usually 5to 8

Stop bits, one or two

Parity bits, used to detect single bit error

Baud rat

Intel 8251A is a universal synchronous asynchronous receiver transmitter

compatible with Intel processors. This may be programmed to operate in any of the

serial communication mode built in to it. This chip converts the parallel data into serial

stream of bits and converts it into parallel data bytes to be read by microprocessor.

2.4.3 Architecture and signal description of 8251 The architectural block diagram of 8251 followed by functional description of

each block is shown below.

Figure2.3

The data buffer interfaces the internal bus of the circuit with the system bus.

The read write controller logic controls the operation of the peripheral depending on

operations initiated by the CPU. This unit also selects one of the two internal

addresses. Those are control addresses and data addresses at the behest of the C/D

signal. The modem control unit handles the modem handshake signal to coordinate the

communication between modem and USART.

The transmit control unit transmit the data byte received by the data bus

buffer from the CPU for further serial communication. This decides the transmission

rate which is controlled by TXC input frequency. This unit also derives two transmitted

status signal namely TXRDY and TXEMPT. These may be used by the CPU for

handshaking. The transmit buffer is parallel to serial converter that receives a parallel

byte for conversion into a serial signal and further transmission on the communication

channel. The receive control unit decides the receiver frequency as controlled by the

RXC input frequency. This unit generates receiver ready (RXRDY) signal that may be

used by the CPU for handshaking and also detects a break in the data string while

8251 is in asynchronous Mode. In synchronous mode the 8251 detects SYNC character

using SYNDET/BD pin.

2.4.4 OPERATING MODES OF 8251A

The 8251A can be programmed to operate in its various modes using its mode

control words. A set of control words is written into the internal registers of 8251A to

make it operate in desired mode.

Once the 8251 is programmed as required, the TXRDY output is raised high to signal

the CPU that 8251A is ready to receive a data byte from it that is to be further

converted to serial format and transmitted. This automatically goes low when CPU

writes a data byte into 8251A.

In receiver mode the 8251A receives a serial data byte from the modem or I/O device.

After receiving the entire data byte, the RXRDY signal raised high to inform the CPU

that the 8251A has a character ready for it.

The RXRDY signal is automatically reset after the CPU reads the received byte

from8251A. The signal is received from the modem/receiving input/output device.

The control words of 8251A are of two functional types.

mode instruction control word

command instruction control word

1. Mode instruction control word

This defines the general operational characteristics of 8251A. After internal (reset

command) or external (reset input pin) reset, this must be written to configure the 8251

as per the required operation. Once this has been written into 8251A, SYNC character

or command instructions may be programmed further as per requirements.

Fig.2.4 (pp.283)

2. Command instruction control word

The command instruction controls the actual operation of the selected format like

enable transmit/receive, error reset and modem control.

Fig.2.5 (pp.286)

STATUS READ DEFINITION

This definition is used by the CPU to read the status of the active 8251 to confirm

if any error condition like the requirement of processor service has been defected,

during the operation.

A read command is issued by processor with C/D=1 to accomplish this

function. Some of the bits in the definition have the same significance as those of the

pins of 8251A. These are used to interface the 8251A in a polled configuration, besides

the interrupt controlled mode. The pin TXRDY is an exception. The status ‘read

format’ is shown below.

D7 D6 D5 D4 D3 D2 D1 D0

DSR SYNDET FE* OE* PE* TXEMPTY RXRDY TXRDY

2.5 The 8088 microprocessor.

The INTEL 8088 is ahigh performance microprocessor implemented in N-

channel, depletion load, silicon gate technology (HMOS-2),and packaged in a40-pin

CERDIP package. The processor has attributes of both 8- and 16-bit microprocessors.

It is directly compatible with 8086 software and 8080/8085 hardware and peripherals.

The processor in the design (intel8088) is an 8-bit CPU available in three clock

rates that is 5MHZ, 8MHZ, 10MHZ packaged in a 40 pins CERDIP or plastic package.

8088 operate in a single processor or multi-processor to achieve a high performance.

Fig2.6 pin diagram pf 8088

TABLE1.

The pin configuration is shown in fig2.6. Some of the pins serve a particular

function in a minimum mode (or single processor mode) and others function in

maximum mode (multiprocessor mode) configuration.

2.5.1 Architecture of 8088 The complete architecture of 8088 can be divided into two parts (a) bus

interface unit (BIU) and (b) execution unit (EU). The bus interface unit contains the

circuit for physical address calculation and a predecoding instruction byte queue (4

bytes long). The bus interface unit makes the system’s bus signals available for

external interfacing of the devices.

Fig.2.7functional block diagram

Fig.2.8 waveforms of minimum mode

FIG2.9.waveforms of maximum mode

2.6 Interrupt and interrupt service routines Whenever the numbers of devices interrupt a CPU at time and if the processor is

able to handle them properly it is said to have multiple interrupt processing capability.

In case of 8088 there are two interrupt pins, viz. NMI and INTR. The NMI is a

nonmaskable interrupt input pin. This means that any interrupt request at NMI input

cannot be masked or disabled at any means. The INTR interrupt, however, may be

masked using interrupt flag (IF).

Interrupt service routines (ISRs) are the programs to be executed by interrupting the

main program execution of the CPU, after an interrupt request appears. After the

execution of ISR, the main program continues its execution further from the point at

which it was interrupted.

2.6.1 Programmable interrupt controller 8259A While the CPU is executing a program ,an interrupt breaks the normal

sequence of execution of instructions ,diverts its execution to some other program

called interrupt service routines(ISR) .after executing ISR , the control is transferred

back again to the main program which was being executed at the time of interruption .

A programmable interrupt controller 8259A is able to handle a number of interrupt

at a time. This controller takes care of a number of simultaneously appearing interrupt

requests along with their type and priority. This relives the processor from all these

tasks

2.6.2 Architecture and signal description of 8259A The architectural block diagram of 8259A is shown in figure below. The

functional explanation of each block is given in the following text.Interrupt request

registers (IRR): the interrupt at IR0 inpute line are handled by interrupt request

registers internally. IRR stors all the interrupt requests in it in order to serve them one

by one on the priority basis.

.

Fig.2.10 The architecture and signal description of 8259A

In-service register (ISR): this stores all the interrupt those are being served i.e. ISR

keeps a track of the requests being served.

Priority resolver: this unit determines the priorities of interrupt requests appearing

simultaneously. The highest priority is selected and stored into corresponding bit of

ISR during INTA pulse.

Broadly, there are two types of interrupts .The first is external interrupt and the

second is internal. In external interrupt, the interrupt, the interrupt is generated

outside the processor. In inter al interrupt is generated internally by execution of an

interrupt instruction .In this project there are two external interrupts.

8088 processor has two interrupt pins, viz NMI and INTR .The NMI is a non-mask

able interrupt input pin which means that any interrupt request at NMI input cannot

be masked or disabled by any means .The INTR interrupt may be masked using the

interrupt flag (IF) .when an interrupt occur by an external device, the cpu

acknowledges the requesting device on its INTA pin immediately of it is an INT

request, the CPU checks the IF flag. If the IF is set, the interrupt request is

acknowledged using the INTA pin. If the IF is not set the interrupt requests are

ignored. In this project the interrupts are mask able interrupts.

The INTR types may be from 00 to FFH if more than one types of INTR interrupts

occurs at a time then an external chip called programmable controller is required to

handle them.In this project programmable interrupt controller 8259A is used to handle

the interrupts occur by programmable interval timer 8253 and programmable

communication interface 8251A USART.

U 1

8259A

1110987654

27132161726

1819202122232425

121315

D 0D 1D 2D 3D 4D 5D 6D 7

A 0C SR DW RSP /ENIN TIN TA

IR 0IR 1IR 2IR 3IR 4IR 5IR 6IR 7

C AS 0C AS 1C AS 2

Fig2.11. the pin out of 8259A

2.7 Programmable interval timer 8253

Intel programmable counter / timer device 8253 facilitates the

generation of accurate time delays. When 8253 is used as a timing and delay

generation peripheral, the microprocessor becomes free from the task related to the

counting process and can execute the program in memory, while the timer device may

perform the counting tasks. This minimizes the software overhead on the

microprocessor.

2.7.1 ARCHITECTURE AND SIGNAL DESCRIPTION

The programmable timer device 8253 contains three independent 16-bit counters.

It is possible to generate three independent counters simultaneously. All the three

counters may be independently controlled by the three internal command word

registers.

The 8-bit bidirectional data buffer interface internal circuit of 8253 to microprocessor

system bus. Data is transmitted or received by the buffer upon the execution of IN and

OUT instructions. The internal block diagram and pin diagram of 8253 are shown

below.

Fig.2.12 Architecture and signal description of 8253.

The 8253 can operate in six different modes. The following are the six different modes.

Mode 0 ( interrupt on terminal count )

Mode 1( programmable monoshot )

Mode 2( rate generator )

Mode 3 ( square wave generator )

Mode 4 ( software triggered strobe )

Mode 5 ( hardware triggered strobe )

In this project mode 0 operating mode of 8253 is used. Mode 0

operations are generally called as interrupt on terminal count. In this mode, the output

is initially low after the mode is set. The output remains low even after the count value

is loaded in the counter. The counter starts decrementing the count value after the

falling edge the clock, if the GATE input is high. The process of decrementing the

counter continues at each falling edge of the clock till the terminal is reached, i.e the

count becomes zero. When the terminal count is reached , the output goes high and

remain high till the selected contain word register or the corresponding count register

is reloaded with a new mode of operation or a new count, respectively. This high output

may be used to interrupt the processor whenever required, by setting a suitable

terminal count.

A0, A1 pins are the address input pins and are required internally for

addressing the mode control word registers and the three counter registers. A low on

CS line enables the 8253. The following table shows the selected operation for various

control inputs.

CS RD WR A1 A0 SELECTED OPERATION

0 1 0 0 0 Write counter 0

0 1 0 0 1 Write counter 1

0 1 0 1 0 Write counter 2

0 1 0 1 1 Write control word

0 0 1 0 0 Read counter 0

0 0 1 0 1 Read counter 1

0 0 1 1 1 Read counter 2

0 0 1 1 1 No operation(tristated )

0 1 1 x x No operation(tristated )

1 X x x x Disabled(tristated)

TABLE-2

2.7.3 CONTROL WORD REGISTER A control word register accepts the 8-bit control word register by the

microprocessor and store it for controlling the complete operation of the specific

counter. A control word must be written in the respective control word register by the

microprocessor to initialize each of the counters of 8253 to decide its operating mode.

D7 D6 D5 D4 D3 D2 D1 D0

Sc1 Sc0 RL1 RL0 M2 M1 M0 BCD

SC1 SC0 OPERATION

0 0 SELECT COUNTER 0

0 1 SELECT COUNTER 1

1 0 SELECT COUNTER 2

1 1 ILLEGAL

SC-select control bit definitions

RL1 RL0 OPERATION

0 0 Latch counter for ’on the fly’ reading

0 1 Read /load least significant byte only

1 0 Read /load MSB only

1 1 Read /load LSB first then MSB

RL-read or load bit definition

BCD OPERATION

0 HEXADECIMAL COUNT

1 BCD COUNT

M2 M1 M0 SELECTED MODE

0 0 0 Mode 0

0 0 1 Mode 1

X 1 0 Mode 2

X 1 1 Mode 3

1 0 0 Mode 4

1 0 1 Mode 5

M2M1M0-Mode select bit definition

Fig. control word formats and bit definitions

In this project the control word format selected is as follow

D7 D6 D5 D4 D3 D2 D1 D0

0 1 1 1 0 0 0 0

=30H

2.8 PIO 8255A [ programmable i/o port]

One of the most important programmable chips for our design that is already

hardwired in the MTS-88 kit is the 8255 programmable I/O port.

The Intel 8255A pio is designed for use with Intel 8-bit, 16-bit & higher capability

microprocessors. It has got 24 lines that can be programmed in to two groups of 12

lines or three groups of 8 lines. The two groups of i/o pins are named as group A &

group B. group A contains an 8-bit port A(pa0-pa7) along with a 4_bit port C(pc4-pc7)

upper .similarly group B contains an 8-bit port B (pb0-pb7) & a 4-bit port C lower

bits(pc0-pc3).the port c lower & upper bits can together be used as an 8-bit port c( i.e.

to make up three 8-bit ports)& both of them have the same adders. All of this ports, i.e.

3 d/f 8-bit ports or two 12-bit ports can function independently ass i/o &this can be

achieved by programming the bits in an internal register of 8255a called control word

register(CWR).

Fig2.13. Internal architecture of 8255A PIO

Fig above shows the internal architecture of 8255A.the 8-bit,3 state bidirectional

buffer is used to interface the 8255A internal data bus with the systems bus& it’s

controlled by the read/write control logic ,which manages all the internal & external

transfer of & control words with the input pins from the microprocessor

(RD,WR,A1,A2)

It defines the adders for the d/f ports & CWR data read or write & the data buss buffer

receives or transmits data upon the execution of i/o instruction by the microprocessor

to 8255A.

2.8.1 Pin description of 8255A

Fig.2.14 Pin configuration of 8255A

A01-A02: These lines are the address input lines driven by the microprocessor. This

address lines are used to select one of the four internal registors (i.e. 3 ports & CWR).

This address lines together with RD, WR&CS forms the following operation for 8255A.

TABLE-3 Basic operation of 8255A

Actually in our case all the address have already been decided, since the 8255A is

already hardwired inside MTS-88, here the A1&A0 of 8255A are wired to A2&A1 of

8088 microprocessor respectively & the address for all four registors will be as follows.

10H= 0 0 0 1 0 0 0 0 Port A

12H= 0 0 0 1 0 0 1 0 Port B

14H= 0 0 0 1 0 1 0 0 Port C

16H= 0 0 0 1 0 1 1 0 CWR

Hex. Address

Fig.2.15 Port address for the four registers of 8255A (here the A0 address line is

don’t care)

2.8.2Mode of operation: There are two basic modes of operations of 8255A; these are the I/O mode & the

bit set reset (BSR) mode. In the I/O mode all the 8255 ports work as programmable i/o

ports. But in BSR mode only port C (pc0-pc7) can be used to set or rest it’s individual

port bits. So based on the lack of control of all ports we chose to use the I/O mode of

operation in our project.

Under the I/O mode of operation further there are three modes of operation, this are

mode 0, mode1&mode2. But for our specific design of interfacing LED matrix as o/p

device we found it suitable to use mode 0 of operation.

Mode 0(basic I/O mode): this mode provides a simple I/O capability of using each of

the three ports. Data can be simply read from & written to the input & output ports

respectively, after appropriate initialization.

In this mode two 8-bit ports (port A & port C) & two 4-bit ports (portC upper &

lower) are available. The two 4-bit ports can be combinedly used as a third 8-bit port

i.e. a maximum of four ports is available. Also any port can be used as input or output

while the o/p is latched & the input is not.

The programmable internal registers (CWR) have two formats: i.e. 1st valid for I/O

mode & the other for BSR mode, but since we used only mode0 of I/O mode we only

focus on that.

Fig2.16. Mode 0 CWR format

Here as it can be seen from the picture above, the bit D6& D5 selects the mode

of operation for port A, port B mode can be either 0 or 1 depending on D2 bit . D7

decides whether it’s an I/O mode or BSR mode. Any one of the three ports can be

programmed as o/p or i/p port by simply using 0 for o/p and 1 for i/p port in the

respective bit of the d/f ports in the CWR format.

In our case the CWR format will be as follows:

D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 0 0 0

=80H

Fig2.16. CWR of 8255A implemented on the design

74LS138; 3:8 LINE DECODERS In place of 8255 we prefer to use latch and decoder combination for input/output

peripherals interfacing for it enables us to have a number of columns as we require.

The IC we are going to use for the purpose of decoding is 74LS138. it is the most

widely used 3:8 line decoder in microprocessor or microcontroller based system. It is

also high speed 1 of 8 decoder or demultiplexer.

Table4

74138 chips is 16 pin chips with A, B, C select lines to select required output line to be

active. G2A and G2B, two inputs are active low enable inputs G1 is active HIGH

Pin name description

A,B,C Address inputs

E1-E2 (G2A,G2B)

Enable inputs(active low)

E3(G1) Enable input(active high)

O0-O7

Outputs (active low)

enable input. Finally O0-O7 are, 8 active low outputs, present to understand the

working of the functional diagram.

inputs outputs

G2A G2B G1 A B C O0 O1 O2 O3 O4 O5 O6 O7

H X X X X X H H H H H H H H

X H X X X X H H H H H H H H

X X L X X X H H H H H H H H

L L H L L L L H H H H H H H

L L H H L L H L H H H H H H

L L H L H L H H L H H H H H

L L H H H L H H H L H H H H

L L H L L H H H H H L H H H

L L H H L H H H H H H L H H

L L H L H H H H H H H H L H

L L H H H H H H H H H H H L

TABLE-5 truth table of 74LS138

LATCH (74LS373)

The transmitted data to the display board, in our case LED matrix display, is to

be latched before being displayed. The IC we have selected for this purpose is 74373

which is the most widely one. The 74373 is an 8 bit latch. It contains 8 D type flip flop.

The Q output of this flip flop is connected to inverting buffer 7404. The latch is

controlled by CLK pin and buffer is controlled by OC pin. When CLK=1, the D type

latch will transfer data from input to output. But when negative transition or falling

edge of CLK appears, the contents will get latched into D flip flop.

When OC=0, the output of D flip flop is made available on output pins. But when

OC=1, output lines are tri-stated.

The IC we have used in between 74373 and 74138 is called INVERTER BUFFER . this inverting is made by IC called 7404.