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Copyright 2012, PCI-SIG, All Rights Reserved 1

PCI Express4.0 ElectricalPreviewsParts I & II

Dan Froelich, Intel Corporation, EWG Member

Gerry Talbot, AMD, EWG Co-Chair


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PCI-SIG Developers Conference Copyright 2012, PCI-SIG, All Rights Reserved 2

Disclaimer

The information in this presentation refersspecifications still in the development process.

This presentation reflects the current thinking

of various PCI-SIG workgroups, but all

material is subject to change before thespecifications are released.


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PCI-SIG Developers Conference

Overview

PCIe 4.0 motivations and assumptions

Choice of data rate

Channel Pathfinding studies CEM connector

Channel improvements

Channel HVM simulations

Silicon Pathfinding studies Tx/Rx specifications

Die-pad cap mitigation

Specification update Reorganization of electrical section

Design collateral to be included

Specification release timeline

Next steps for PCIe 4.0

PCIe 3.0 ECRs

3Copyright 2012, PCI-SIG, All Rights Reserved


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PCIe 4.0 Motivations andAssumptions

Looking forward we continue to see a requirement toincrease I/O bandwidth

Graphics, Networking, Storage

Motivations for PCIe 2.x->3.0 apply equally for 3.0->4.0

Given the eco-system impact of a new generation2x increase in delivered bandwidth is required

Highly desirable to extend PCIe 3.0 infrastructure andPHY architecture for another generation

Moving to a new infrastructure such as electrical or opticalwaveguides breaks backwards compatibility

Highly desirable to preserve current usage models

With incremental improvements 3.0 PHY architecture is capableof significantly higher data rates



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EWGs Analysis Approach

PHY assumed to have similar EQ solution to 3.0 Silicon performance assumed to scale with data rate

Jitter performance, Return loss, Tx bandwidth

This assumption is currently being refined

Evaluate CEM channels to determine maximumdata rate Two data rates 16GT/s and 24GT/s initially considered

Determine channel topology limiters

Evaluate mitigation techniques

Investigate component improvements

Conclusion from pathfinding work Existing CEM topologies do not support 24GT/s

16GT/s is the PCIe 4.0 data rate



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Target max length PCIe 3.0 server channel is~20 with 1 or 2 connectors

Pathfinding for 16GT/s shows ~12-14 with 1 or2 connectors possible

Even with reduced channel length mitigation isrequired

Improvements to the CEM connector launch

Clean up via transitions

Minimize crosstalk

Center channel impedance ~85ohm

Channel Topologies



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Client Topology


Socket

Root package

CEM connector

Add-in card

package Add-incard

Motherboard

Socket

Root package

CEM connector

Add-in card

packageAdd-in

card

Motherboard

Swept length

Swept lengthSwept length

Break-out

Bottom-side microstrip route

Top-side microstrip route

5mil pair-pair space 30mil pair-pair space

30mil pair-pair space



Server 2-connector Topology


SKTPKG

CAPCONN

PKG

mbLen {4-10} stripline,

0.015 LossTan,

70,85,100 ohms

acLen {1-3} CONN

rsrLen {1-3}

Stripline route assumed as this has worst via stubs



CEM Connector Improvements

Existing CEM connector has three problems for16GT/s signaling

Insertion loss increase at 8GHz

Return loss at 8GHz

Significant peak in FEXT at 8GHz

Significant improvements can be made bychanging footprint

Improves the launch into the connector structure

Under review by connector vendors

Goal is to minimize cost impact




Possible PerformanceImprovement


Current CEM connector Improved CEM connector

FEXT

RL

IL

FEXT

RL

IL

Substantial improvement in IL, FEXT and RL by creating a true differential launch

from board into connector



Modifications to Footprint


Possible CEM connector launch improvements

under consideration



SMT Measurement Result


-1.3dB

Existing SMT connectors get close to the through hole-launch

Additional measurements in progress on improved footprints



PCB Etch Loss/Inch


StriplineMicrostrip

LossTangent=0.01

LossTangent=0.025

LossTangent=0.01

LossTangent=0.025

Channel performance is approximately proportional to PCB loss

Loss tangent is more significant at 16GT/s



Loss Tangent Impact EyeHeight


Swept loss tangent form 0.01, 0.015, 0.025

Loss

tangent

Loss Tan of 0.025 was assumed for 8GT/s Changing to 0.015 is of medium risk/cost in future

Using to 0.015 increases solution space by about 2

Changing to 0.010 starts to have diminishing returns for thecost


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Via Stub Impact

For 2-connector server channel there are 4 main vias Two for main board to go to stripline and back up to AC cap

- 11 and 58 mills

Two for the connectors- 0 mills and 58 mills

Worst combination can reduce the total routing length

by >3

Via

Stubheight

Copyright 2012, PCI-SIG, All Rights Reserved

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58

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Tool Improvements Needed

Channel response at >8GHz is affected by largenumber of features in the channel

Pre-layout evaluation of topology choices is acomplicated multi-dimensional problem

Need to be able to quickly build and test manydifferent options

Large number of HVM permutations need to beevaluated to determine robustness of solution

Seasim has been enhanced to allow EWGmembers to efficiently evaluate these options

Once validated this tool will be made available to thePCI-SIG membership for 4.0 channel compliance



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PCI-SIG Developers Conference 19

Allows whatif analysis on

the channel components by

changing the touchstone

files that are concatenated

together for the channel

Different analyses can beselected as the channel is

tuned

Either a pre-saved config

can be loaded or the pcie-

gen4.inc for normal simconditions

The other tabs allow

simulation conditions to be

changed from the default

config

Seasim Channel


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Client HVM Sweeps

At 16GT/s small changes in the channel have a big impact on eye openingAn end-end reflection peaks and nulls when flight time changes by

62.5ps or ~0.42

Impedance variations between motherboard and add-in card introducelow frequency reflections that interact with the adapted EQ solution

Different root complex package responses vary significantly Topology differences between top and bottom microstrip routing impact

reflections

Different connector models impact channel reflections

To capture solution space sensitivity channel parameters can be swept

using seasim Set of component touchstone files built

Seasim sweep capability allows large number of cases to be studied

-In this example ~15,000 cases tested



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Seasim HVM Sweep

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Seasim can be used todefine HVM sweeps

The channel model can be

swept to represent

manufacturing variations of

impedance or loss

To consider the impact of

different PCB layout the

length of different channel

segments can be swept

Seasim will launch jobs in

parallel then collect results

and plot them


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Example Client ChannelSimulation



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Client Channel HVM Sweep


Min eye height 47mV

Min eye width 0.38UI

Max IL -21dB

Variables swept:

Motherboard:

-Length: 1-11

-Impedance 70/100ohm

Root package

-Length 10-30mm-Impedance 80/90ohm

-Loss hi/lo

EP package

-Length 10/30mm

-Impedance 80/90

-Loss hi/lo AIC etch

-70/90

15,360 cases


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Server 2-conn Sweep


Eye Height

Eye Width

Total Length inches

Insertion loss @8GHz


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The CEM form factor is the most important usage model for PCIExpress

Can be extended by another generation with improvements to CEMconnector launch

Current CEM channels are electrically very complex beyond 8GT/s

Discontinuities and crosstalk from packages, sockets, vias, etch,coupling capacitors, CEM connector

Non-monotonic frequency domain behavior yields unpredictable datarate scaling

To extend current infrastructure requires enabling SIG membershipto design and build cleaner channels

Tuning via launches, minimizing layer transitions, careful layer choices

For longer reach channels, back-drilling, lower loss materials andrepeaters will be required

Channel Recommendations



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Passive Tx/Rx Improvements

PCIe 3.0 Tx/Rx BW constrained by CPAD

Requires a BW > 10 GHz

Two options considered

Reduce CPADto ~ 400 fFAdd T-coils to Tx and Rx

T-coils also improve RL, reducing reflections

Analysis indicates that T-coils on Tx and Rxdecrease IL by ~ 5 dB



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`

T-coil ModelBlue block is normal driver model in time domain simulator

CPAD= CTX - CE. (Tx or Rx pad capacitance)CESD = 0.35pF (ESD capacitance)

CTX= 0.9 pf

RSERIES= 2W(Metalization resistance)

Driver Model

T-coil lumped element

CESD

-417*CESD

1250*CESD

CESD/12

80 fF

RTX

CTX-CESD

Example of metal stackup

RSERIES RSERIES


1250*CESDpin

pin

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T-coil Effect on IL

Blue curve is Tx package with 0.9pF Cpad Green is with 0.35pF of the 0.9pF compensated for with T-coil.

Red is with Cpad of 0.55pF (0.9-0.35pf)

The magnitude of the ripple on the IL with the 0.9pF cpad (blue) is drivingthe IL down to -10dB at 8GHz

CTX= 0.9 pf, no T-coil

CTX= 0.55 pf, no T-coil

Tcoil, CPAD= 0.55pf, CESD= 0.35pf



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T-coil Effect on RL

RL improves with t-coil for two reasons:

RESDdecoupled from high speed signal path

RSERIESadds a small amount of DC resistance to the signal path


CTX= 0.9 pf

CTX= 0.55 pf

T-coil, CPAD= 0.55pf,

CESD= 0.35pf

-1.5 dB

-5.0dB

-2.5dB

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Platform Topology Variables

main board 7-9, stripline, tand 0.015,Z: 70-100 Riser card 1.5-3.5, mstrip, tand 0.015,

Z: 70-100 Addin Card 1.5-3.5, mstrip, tand 0.015,

Z: 70-100 Models

Connector is EWG web site, 8mm5_26_2011

Tx package is 10-25mm with socket Rx package is 10-20mm BGA

Tx 3 tap EQ, pre, cur, post 800mV swing 0.9-0.55pF

Rx CTLE ADC: 4 to 12 dB, fp1 1.5-4 GHz

2,4,6,8 tap DFE

SKTPKG

CAPCONN

PKG

Len=7- 9

Zo= 70,85,100 ohms

1.5-3.0CONN

EQ training: exhaustive grid search

Vias Motherboard via stub 11 or 58 mill Conn via stub 0 or full 64 mill

T-coils At both Tx and Rx ESD Cap is 0.35pF for both

Rx-cpad = Tx-cpad-0.1pF RSERIES= 2W



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Effect on IL 0.9/0.8pF C

PADintroduces too much rolloff in Tx and Rx

Time constant for 0l;9 pf, 50W= 45 ps vs. UI of 40 ps

0.55/0.45 pf CPADreduces IL slightly, but still exceeds the 25 dB limit

Adding T-coils to Tx and Rx decreases IL to 25 dB, which can beequalized


CTX= 0.9 pfCTX= 0.55 pf

T-coil, CPAD= 0.55pf,CESD= 0.35pf

-25 dB

-30 dB

-27 dB

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Pulse Response Comparison

C=0.55pF Tx yields the largest pulse height

C=0.9 pf with T-coil gives the least amount of pre and post cursorinterference

0.9 pf Tx

0.55 pf Tx

Tcoil



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Eye Height Comparison

Top is with T-Coil

0.9pF Tx Total

T-coil 0.35pF in ESD

tand=0.015, short viastubs

Increasing # of DFEtaps reduces delta

0.9pf,withT-Coil

0.9pF

,noT-coil


0.9 pf with T-coil

0.9 pf no T-coil

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Eye Height Distribution 15

2-tap and 6-tap DFE with and without T-coils, length=15 total

2-tap DFE 6-tap DFE

2 DFE mean 6 DFE mean

Tcoil 45mV 53mV

0.9pF 32mV 47mV

2-tap DFE +T-coil 6-tap DFE + T-coil

2 DFE min 6 DFE min

Tcoil 11mV 27mV

0.9pF 0mV 22mV



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Eye Width Comparison Top is with T-Coil

0.9pF Tx Total

T-coil .35pF in ESD

tand=0.015, short viastubs

Increasing #DFE taps

reduces delta Eye Height target of

25mV is current limiterwith 8 taps DFE

0.9pf,withT-Coil

0.9pF,n

oT-coil


0.9 pf with T-coil

0.9 pf no T-coil

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2 DFE mean 6 DFE mean

T-coil 0.43UI 0.48UI

0.9pF 0.37UI 0.45UI

2 DFE min 6 DFE min

T-coil 0.23UI 0.35UI

0.9pF 0.04UI 0.28UI

Eye Width Distribution2-tap and 6-tap DFE with and without T-coils, length=15

6-tap DFE2-tap DFE


2-tap DFE +T-coil

6-tap DFE + T-coil36

0 9pF with T coil vs


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0.9pF with T-coil vs.0.55pF no t-coil

EH mean EW meanTcoil 40mV 0.41UI

0.55pF 40mV 0.41UI


C=0.55 pf Eye width C=0.9 pf Eye width

C=0.9 pf Eye heightC=0.55 pf Eye height

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Tx/Rx Circuit Improvements

Tx jitter and Rx timing uncertainty must scaleapproximately with data rate

Some parameters such as Tx PWJ may need to scalemore than a factor of 2x wrt. PCIe 3.0

At this time we have not obtained precise jitterestimates for Rx or Rx circuits

Estimates will go into the Rev 0.3 specification



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Only minor enhancements to Tx or Rx equalizationare anticipated for PCIe 4.0

The channel IL at Nyquist for PCIe 4.0 is not appreciablyworse than for PCIe 3.0

Proposed eq capabilities

- Tx FFE: One pre and one post cursor tap. Retain the samepresets and coefficient range/resolution

- Reference Receiver (actual implementations may have more)

-Rx CTLE: Same resolution, but DC gain may be

increased-Rx: DFE, increase the number of taps to 2-3, retainsame tap range and magnitude

-Training method would remain the same, although only certainpresets would be used

Equalization Capability



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Repeater/Retimer/Re-driver


Active component for channel extension will beimportant in more systems for PCIe 4.0

Allowed architectures and compliance for channelextension may need to be specified for PCIe 4.0

Areas for investigation Interaction with TX Equalization negotiation protocol

Clocking

Electrical specifications

Models for simulation


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PCIe 4.0 Electrical Spec

Undergoing reorganization to achieve a moreregularized format

8.0G/Ts methodology and parameters will be appliedto 16G/Ts

Same parameter definitions retroactively applied to2.5G/Ts and 5.0G/Ts

2.5G/Ts and 5.0G/Ts parameters values will bedefined to guarantee interoperability

- Some tightening of certain Tx parameters is likely



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Tx Jitter Specifications


Parameter Description 2.5 GT/s 5.0 GT/s 8.0 GT/s 16 GT/s

TTX-UTJ Tx uncorrelated total

jitter

100 (max) 50 (max) 31.25 (max) 15.62 (max)

TTX-UDJDD Tx uncorrelated

deterministic jitter

40 (max) 20 (max) 12 (max) 6 (max)

TTX-UPW-TJ Total uncorrelated

PWJ

75 (max) 38 (max) 24 (max) 12 (max)

TTX-UPW-DJDD Deterministic DjDD

uncorrelated PWJ

32 (max) 16 (max 10 (max) 5.0 (max)

TTX-DDJ Data dependent jitter 60 (max) 30 (max) 18 (max) 9.0 (max)

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Tx differential and common mode RL masksExtend 2.5-4.0 GHz PCIe 3.0 limits to 8 Ghz while

retaining the same respective values

Makes sense given that Tx/Rx RL at 8G is improved

via T-coils

Redefine Tx behavior during EIEOS

Optimization may be neededstudies ongoing

Double the # of symbols in the high and low intervals

Turn off de-emphasis to avoid hitting boost limit

Others?

Other PCIe 4.0 Tx Parameters



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Max PCIe 4.0 channel IL remains approx thesame s for PCIe 3.0

Plan is to retain same equalization presets

Training will require that only a subset of the presets

be used (P7 and P8)

Equalization coefficient range and resolutionalso are intended to remain unchanged

EIEOS signaling will likely change such that noTxEQ is applied during the EIEOS interval

Transmitter Equalization



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PCIe 4.0 uses same jitter parameters as PCIe 3.0TTX-UPW-TJ, TTX-UPW-DJDD, TTX-DDJ, TTX-UTJand TTX-UDJDD

Jitter will need to scale approximately with bitrate

De-embedding approach will likely remain the same

PCIe 1.x and PCIe 2.x jitter parameters will berecast into the same form as the PCIe 3.0parameters

Backward compatibility will be guaranteed

Some PCIe 1.x/2.x parameters will be effectivelytightened

Example: PCIe 2.x TMIN-PULSEparameter will beconverted into TTX-UPW-TJand TTX-UPW-DJDD

Transmitter Jitter Spec



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Will continue to rely upon a stressed eyeapproach where both EH and EW are stressed

Calibration channels IL will need to be reduced toyield ~24 dB at 8 GHz

Behavioral package model needs to comprehendreduced CPADor include T-coil models

Behavioral DFE model to have increased number oftaps, at least 2

More capable CTLE model

PCIe 4.0 Rx Specification



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PCIe 4.0 Design Collateral

Will be included in PCIe 4.0 spec in response tocustomers requests

A purely normative spec does not give sufficientinformation to allow many developers to successfullyimplement designs.

Some design collateral will be included asseparate subsections for Tx, Rx, channel, etc.

CEM specific collateral will be included in CEM

spec



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CEM s-parameter masksCEM connector: IL, RL, FEXT

Tx and Rx: RL

Baseboard: IL, RL adapter: IL, RL

Reference models for Tx die/pkg, channel, Rxdie/pkg

Others

PCIe 4.0 Design Collateral



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PCIe 3.0 ECNs

Support independent Tx and Rx RefClks withSSC on each This is an optional requirement

Certain cabled applications may not route RefClk, so adaptersRefClk is independent from root ports

Reduce pincount and minimize EMI/RFI

Rx CDR needs to filter SSC 20 db/dec insufficient to filter RefClk spurs and meet the 1 ps

RMS RefClk jitter spec

Previously a 1storder CDR was acceptable

Support will likely be required for PCIe 4.0 basespec compliant silicon



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Next Steps

EWG workStart scoping Tx, Rx jitter parameters

Rev 0.3 spec release

Common parameters across PCIe 1.x-PCIe 4.0

Estimated values for all PCIe 4.0 parameters

Merge PCIe 1.x, PCIe 2.x specific material into PCIe3.0 spec format



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Thank you for attending thePCI-SIG Developers Conference 2012

For more information please go towww.pcisig.com

Documents

PCIexp.pdf