Upload
ethel-pitts
View
216
Download
2
Tags:
Embed Size (px)
Citation preview
Penn ESE370 Fall2010 -- DeHon1
ESE370:Circuit-Level
Modeling, Design, and Optimization for Digital Systems
Day 36: December 6, 2010
Transmission Lines
Last week + today
• General wire formulation• Lossless Transmission Line• Reflections at ends of line• See in action in lab• Where arise?• Termination• Implications• Discuss Lossy
Penn ESE370 Fall2010 -- DeHon2
Transmission Lines
• This is what wires/cables look like– Aren’t an ideal equipotential– Signals do take time to propagate– Shape and topology of wiring effects how
signals propagate • …and the noise effects they see
Penn ESE370 Fall2010 -- DeHon3
Transmission Lines
• Need to understand – How to model how to reason about– What can cause noise– How to engineer high performance
communication
Penn ESE370 Fall2010 -- DeHon4
Transmission Lines
• Cable: coaxial
• PCB– Strip line– Microstrip line
• Twisted Pair (Cat5)
Penn ESE370 Fall2010 -- DeHon5
Coaxial Cable• Inner core conductor: radius r• Insulator: out to radius R• Outer core shield (ground)
• RG-58 Z0= 50 – networking, lab
• (RG-59 Z0= 75 – video)
Penn ESE370 Fall2010 -- DeHon6
€
L =μ
2π
⎛
⎝ ⎜
⎞
⎠ ⎟lnR
r
⎛
⎝ ⎜
⎞
⎠ ⎟
€
Z0 =1
2π
⎛
⎝ ⎜
⎞
⎠ ⎟μ
ε
⎛
⎝ ⎜
⎞
⎠ ⎟lnR
r
⎛
⎝ ⎜
⎞
⎠ ⎟
Printed Circuit Board
• Stripline– Trace between planes
Penn ESE370 Fall2010 -- DeHon7
wt b
r
€
Z0 =1
4
⎛
⎝ ⎜
⎞
⎠ ⎟μ
ε
⎛
⎝ ⎜
⎞
⎠ ⎟ln
1+W btb +W b
⎛
⎝ ⎜ ⎜
⎞
⎠ ⎟ ⎟
Printed Circuit Board
• Microstrip line– Trace over single supply plane
Penn ESE370 Fall2010 -- DeHon8
wt
hr
0
€
Z0 =1
2π
⎛
⎝ ⎜
⎞
⎠ ⎟
μ
0.475ε r + 0.67( )ε 0
⎛
⎝ ⎜ ⎜
⎞
⎠ ⎟ ⎟ln
4h
0.536W + 0.67t
⎛
⎝ ⎜
⎞
⎠ ⎟
Termination / Mismatch
• Wires do look like these transmission lines
• We are terminating them in some way when we connect to gate– Need to be deliberate about how terminate,
if we care about high performance
Penn ESE370 Fall2010 -- DeHon10
Where Mismatch?
• Vias
• Wire corners?
• Connectors
• Board-to-cable
• Cable-to-cable
Penn ESE370 Fall2010 -- DeHon11
http://wiki.altium.com/display/ADOH/An+Overview+of+Electronic+Product+Development+in+Altium+Designer
http://www.fpga4fun.com/Hands-on_Flashy.html
End of Line Reflection
Penn ESE370 Fall2010 -- DeHon13
€
Vr =ViR − Z0
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟
€
Vt =Vi2R
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟
Pipeline Bits
• For properly terminated transmission line– Do not need to wait for bits to arrive at sink– Can stick new bits onto wire
Penn ESE370 Fall2010 -- DeHon15
Limits to Bit Pipelining
• What limits?– Risetime/distortion– Clocking
• Skew• Jitter
– For bus• Wire length differences between lines
Penn ESE370 Fall2010 -- DeHon16
Eye Diagrams• Watch bits over line on scope
– Look at distortion– “open” eye clean place to sample
• Consistent timing of transitions• Well defined high/low voltage levels
Penn ESE370 Fall2010 -- DeHon17
http://en.wikipedia.org/wiki/File:On-off_keying_eye_diagram.svg http://focus.ti.com/analog/docs/gencontent.tsp?familyId=361&genContentId=41762&DCMP=ESD_Solutions&HQS=Other+OT+esd
Bad “eye”
Penn ESE370 Fall2010 -- DeHon18
http://archive.chipcenter.com/knowledge_centers/asic/todays_feature/showArticle.jhtml?articleID=12800254
Impedance Change
• What happens if there is an impedance change in the wire?
Penn ESE370 Fall2010 -- DeHon19
Z0=75, Z1=50
• At junction: – Reflects
• Vr=(50-75)/(50+75)Vi
– Transmits• Vt=(100/(50+75))Vi
Penn ESE370 Fall2010 -- DeHon20
€
ViR − Z0
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vr
€
Vi2R
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vt
Branch
• Transmission line sees two Z0 in parallel
– Looks like Z0/2
Penn ESE370 Fall2010 -- DeHon23
Z0=50, Z1=25
• At junction: – Reflects
• Vr=(25-50)/(25+50)Vi
– Transmits• Vt=(50/(25+50))Vi
Penn ESE370 Fall2010 -- DeHon24
€
ViR − Z0
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vr
€
Vi2R
R + Z0
⎛
⎝ ⎜
⎞
⎠ ⎟=Vt
End of Branch
• What happens at end?
• If ends in matched, parallel termination– No further reflections
Penn ESE370 Fall2010 -- DeHon25
Branch with Open Circuit
• Reflects at end of open-circuit stub
• Reflection returns to branch– …and encounters branch again– Send transmission pulse to both
• Source and other branch
• Sink sees original pulse as multiple smaller pulses spread out over time
Penn ESE370 Fall2010 -- DeHon28
Bus
• Common to have many modules on a bus– E.g. PCI slots– DIM slots for memory
• High speed bus lines are trans. lines
Penn ESE370 Fall2010 -- DeHon31
Multi-Drop Bus
• Capacitive load (stub) at drop?– If tight/regular enough, change Z of line
Penn ESE370 Fall2010 -- DeHon33
€
Z0 =L
C
Multi-Drop Bus
• Long wire stub?– Looks like branch
• may produce reflections
Penn ESE370 Fall2010 -- DeHon34
Lossy Transmission Line
• R’s cause signal attenuation (loss)– Voltage, energy– Reduced signal swing at sink– Limits length of transmission line before
need to restore signal
Penn ESE370 Fall2010 -- DeHon36
Transmission Line Noise
• Frequency limits
• Imperfect termination
• Mismatched segments/junctions/vias/connectors
• Loss due to resistance in line– Limits length
Penn ESE370 Fall2010 -- DeHon37