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Performance Analysis of Low Power High Speed Hybrid Adder By Thallam Keerthi Under Guidance of Mrs.Namitha Palecha RVCE VLSI Design and Embedded systems

Performance of High speed Low power Hybrid Adder

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Page 1: Performance of High speed Low power Hybrid Adder

Performance Analysis of Low Power High Speed Hybrid

Adder

By Thallam KeerthiUnder Guidance of Mrs.Namitha PalechaRVCE VLSI Design and Embedded systems

Page 2: Performance of High speed Low power Hybrid Adder

OverviewOverview

Purpose Review Of Full Adder Design Of Different Logic Styles Proposed Hybrid Adder Presentation Performance Analysis Cadence Implementation Simulation Results Takeaways

Page 3: Performance of High speed Low power Hybrid Adder

PurposePurpose

To minimize the power, increase the speed Which full adder topology does this the best?

Can we make any generalizations in those decisions?

StaticTransmission

Gates

CPL

Page 4: Performance of High speed Low power Hybrid Adder

Static Full Static Full AddersAdders

Static CMOS• Transistor Count: 28• High Capacitance and

need of input buffersCPL• Transistor Count: 32• Area inefficiency

Page 5: Performance of High speed Low power Hybrid Adder

Transmission Logic Transmission Logic AddersAdders

TGA:Transistor Count: 20Power Dissipation: 7.87microwattsDelay: 301.3ps

Page 6: Performance of High speed Low power Hybrid Adder

Hybrid Full Adder ImplementationHybrid Full Adder Implementation

Full Adder is implemented as the combination of 3 modules

Module 1 – Generation of XOR-XNOR module Module 2 – Sum Generation Module 3 – Carry Generation

Page 7: Performance of High speed Low power Hybrid Adder

Comparison of XNOR-XOR ModuleComparison of XNOR-XOR Module

Referred XOR-XNOR ModulePresenting XOR-XNOR Module

Page 8: Performance of High speed Low power Hybrid Adder

Proposed Hybrid AdderProposed Hybrid Adder

A

B XNOR

Condition

0 0 1 strong

0 1 0 weak

1 0 0 strong

1 1 1 weak

Page 9: Performance of High speed Low power Hybrid Adder

Power CalculationPower Calculation

•Dynamic Power Dissipation Contributes to the major power consumption

Voltage Power Consumption

1.8V 2.94μW

1.2V 1.456μW

0.9V 818.2nW

Page 10: Performance of High speed Low power Hybrid Adder

Delay of Hybrid AdderDelay of Hybrid Adder

Critical Path for Delay is the path from Carry-in to Carry-out

Techniques to reduce the delay• Reduce the path between carry-in and carry-out• Increase the width of transistor to decrease the delay. FAST CIRCUITS OCCUPY MORE AREA

Voltage Delay

1.8V 61.4ps

1.2V 112.7ps

0.9V 154.6ps

Page 11: Performance of High speed Low power Hybrid Adder

Comparison with other Hybrid AdderComparison with other Hybrid Adder

•Transistor Count: 22•Maintains Proper Voltage Swing

Take Away:•Transistor Count increased•Delay is increased•Power Consumption increased•Area increased

Page 12: Performance of High speed Low power Hybrid Adder

Simulation ResultsSimulation Results

Page 13: Performance of High speed Low power Hybrid Adder

Simulation ResultsSimulation ResultsAt 1.8V DC Voltage Supply

Page 14: Performance of High speed Low power Hybrid Adder

Simulation ResultsSimulation ResultsAt 1.2V DC Supply Voltage

Page 15: Performance of High speed Low power Hybrid Adder

Simulation ResultsSimulation ResultsAt 0.9V DC Supply Voltage

Page 16: Performance of High speed Low power Hybrid Adder

Any Questions?