Performance of the AMT-3 Based TDC System at Belle

S.Y.Suzuki, T.Higuchi,Y.Arai, K.Tauchi,

M.Nakao, R.Itoh 　 (KEK)H.Nakayama (University of Tokyo)

Belle experiment at KEKB

Designed luminosity

• Study of CP violation in B-meson decays from Y(4S)

• The Belle detector consists of 7 sub-detectors.

• L1 trigger – 500Hz(average)

• Data size – 40kB/ev

• Achieved 160% of the designed lumionsity.

Schematic view of DAQ system

Trigger,SequenceControll

SEQ

ACC

CDC

TOF

ECL

KLM

EFC

TRG

SVD

SVDReadout S

ubsystems

ReconstructionFarm

Online farm

FASTBUS

VME

PC

Multihit TDC

Using Q-to-T + multi-hit TDC technique, most of detectors are read out by the same FASTBUS TDC system.Except deadtime, FASTBUS is excellent.

Present FASTBUS DAQ system

• TDC – LeCroy 1877S FASTBUS– High channel density : 96ch per board– Fine resolution : 16bit x 500ps LSB, 32μsec w

indow– Q-to-T : Multi-hit up to 16 edges per channel

• Unified DAQ system : easy to maintain.• Except deadtime

– No pipeline : trigger and busy hanshake in delay + common-stop

Deadtime fraction

VETO for10Hz continuous injection

So we developed new readout system.

De

adt

ime

fra

ctio

n (%

)

•Deadtime is proportional to the product of the trigger rate and the data size. •This deadtime comes from FASTBUS TDC.•Luminosity increase makes the higher trigger rate and larger data size.

Trigger (Hz)

• Pipelined readout system

• Smooth upgrade path

• Unified readout system

New DAQ concept

Design of new readout system

• Digitizer– Pipelined digitization

• Readout FIFO– Event buffers for

asynchronous readout

• Online processor– Data size reduction– Data transmission

over TCP/IP

Digitizer

Digitizer

Readout F

IFO

Online P

rocessorO

nline Processor

Signals from

detector

Everything on a single board

PMC CPUPMC CPU

local b

us

PC

I b

us

from

dete

cto

r

Network IF

Network IF

Trigger ModuleTrigger Module

Digitizer Digitizer

Digitizer Digitizer

Digitizer Digitizer

Digitizer Digitizer B

rid

ge

Bri

dg

e

PMC modulesFIFO

to e

ven

t b

uild

er

Schematic view of “COPPER”

ReadoutFIFO

TriggerTrigger

BusyBusy

Trigger and busy handshake for the smooth upgrade.Trigger and busy handshake for the smooth upgrade.COPPER co-exists with present FASTBUS TDC readout.COPPER co-exists with present FASTBUS TDC readout.

AMT-3

• Replacement of FASTBUS TDC with pipelined TDC• AMT-3 based TDC is implemented in the digitizer card of

the COPPER. • AMT-3 chip originally developed for ATLAS

– Pipeline TDC– Multiple buffers allow asynchronous readout

• Channel buffer• L1 FIFO• Readout FIFO

– 24ch LVDS input/chip– 780ps LSB x 17bit, 102.4μsec window– 250ps Time resolution (RMS)

• Similar spec to the FASTBUS TDC,suitable for the replacement.

The COPPER TDC• Add-on module for COPPER

– 2 AMT-3 chips per module– 48 ECL inputs (ECL-to-LVDS con

verter)

• COPPER TDC– 2 add-on modules per COPPER – 96 inputs in total – Connector shapes and signal leve

l are compatible with LeCroy FASTBUS TDC’s.

AMT3-FINESSE

AMT3-FINESSE

localbus

PLX9054 EPC-6315

PC

I bus

82559

Data stream

TT-RX(trigger receiver) trigger

Signals from

detector

The COPPER TDC

History of COPPER study

• Since September 2005, first 6-module test setup commissioned in Extreme Forward Calorimeter.

• Since September 2006, 16-module setup commissioned for the Central Drift Chamber readout.

• Performance was compared with the FASTBUS system.

16-module setup

Signals are daisy-chained to FASTBUS via COPPER.

COPPER

FASTBUS…………

CentralDrift

Chamber

ShaperQT

Signals are digitized simultaneously by FASTBUS and COPPERfor the consistency check.

Data consistency

FASTBUS time (ns)

CO

PP

ER

tim

e

(ns)

Linearity / Resolution

It is consistent with the specification of AMT-3 itself,Time resolution ~ 250ps (RMS)

RMS is 0.61LSB

Diffe

ren

ce fro

m th

e exp

ecte

d va

lue

(L

SB

)

AMT-3 time (ns) Diff from the expected value (LSB)

# o

f e

ven

ts

Deadtime improvement

Offset = 25usec

Offset = 0.72us

29.5us

2.8us

# of hits/TDC

De

adt

ime

(u

s)

Nominal data size

Deadtime is < ~ 1/10

Summary

• Higher trigger rate and larger data size are expected in near future.

• We developed a new pipelined TDC to reduce the deadtime.

• 1/10 shorter deadtime is achieved. (29.5us -> 2.8us)

• It was proven to have sufficient performance to supersede current FASTBUS readout system.– Compatible with the FASTBUS TDC