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Belle Trigger/DAQ Workshop 2005 - Workshop Summary - R.Itoh, KEK Shinshu University, 2/17-18/2005 28 participants Shinshu Univ. Matsumoto Catsle and Mountains

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Text of Belle Trigger/DAQ Workshop 2005 - Workshop Summary - R.Itoh, KEK Shinshu University, 2/17-18/2005 28...

  • Belle Trigger/DAQ Workshop 2005- Workshop Summary -R.Itoh, KEKShinshu University, 2/17-18/200528 participantsShinshu Univ.Matsumoto Catsle and Mountains

  • Workshop Goals1. Confirm the feasibility and compatibility of the near-term upgrade plans between Trigger/DAQ and detector groups.

    * We need prompt upgrade of DAQ to cope with the luminosity increase in coming years. * The upgrade should be as much as compatible with the upgrade for Super B.2. Discuss readiness of our design for Super KEKB with L=5x1035 cm-2sec-1.

    * Previous design was for L=1x1035 cm-2sec-1 with rather pessimistic assumption on trigger rate. * Update trigger rate estimation using the latest data and verify our design.

  • CDS Agenda was used to manage program and talk slides!You can reach the page from http://belle.kek.jp/workshops/TDAQ2005

  • Current StatusDAQ dead time during data taking (2/19-20/2005)w/o injectionw/ injectionAverage dead time during data taking = 7.2 % @ 500Hz L1 rate = ~4% (readout) + ~2% (Inj. VETO) + ~1% (CDC current limit.) Dead Time Fraction~3.5% deadtimeadded due toinjection VETO Estimation of dead time with increased luminosity

  • Possible DAQ condition until SuperB upgrade- L is ~1.5 x 1034 in 2005 Ave. trigger rate ~ 500 Hz => intrinsic DAQ deadtime ~ 3-4% can live with current DAQ- L will increase up to 2~5 x 1034 in 2006-20xx (with crab cavity installed) Ave. trigger rate ~ 1-2kHz => intrinsic DAQ deadtime >20% needs effort to reduce deadtime and to increase processing power for event builder/L3 farm- L > 1035 in 20xx (xx can be 08~11?) by SuperB upgrade Ave. trigger rate >10kHz (max. 30kHz) => pipelined DAQ is really necessary >10 x CPU power for EB/L3 farm Clear and Present Danger by Tom Clancy

  • Trigger rate (@L=5x1035)According to present knowledge,Luminosity term is quite large.200Hz x Luminosity ( unit:1034cm-2sec-1)10kHz at L = 5x1035cm-2sec-1To reduce it, better trigger system is necessary.To keep tau events and to suppress two-photon eventsHER beam dominantly affects the background trigger rate.Trigger rate P x IHER I2HER 200Hz at IHER =1.27A 0.2x(4.1/1.27)2 = 2kHzOne worry : Lower y* 6mm 3mmGood point : More bumps at Tsukuba straight section to reduce the vacuum pressure.Uno

  • Iwasaki

  • Trigger Rate Readout deadtime Total efficiency A) 500Hz 4 % ~ 91 %

    B) 1KHz ~20 % ~ 75 %

    C) 2KHz >50 %

  • * Replace existing FASTBUS TDC system with COPPER based pipelined TDC system(no dead time) detector by detector during scheduled accelerator shutdown time (Summer, Winter). - Start from the detector with the longest readout deadtime (CDC) next FY. - Repeat replacement year-by-year and move to fully pipelined readout system in 3 years. - Further upgrade (for SuperB) are managed by replacing FINESSE + increasing no. of modules.

    * Modularize backend DAQ (event builder+reconstruction farm) and add new units whenever more processing power is required.* Keep intrinsic dead time ~ 5% even with increased luminosity* Upgrade is consistent with further SuperB detector upgrade* Upgrade scenario is as much as independent of SuperB budget profile* Do not interrupt accelerator running by the upgradeSmooth adiabatic upgrade scenario to SuperB DAQNo distinction between near-term and SuperB upgrades

  • Common Readout Platform: COPPERO(100) of the COPPER boards are used by each sub-detector system.- Developed in cooperation with KEK electroncs groupOn-board EtherForm factor = VME 9UCOPPER module by KEK.- Common Readout Module to handle pipelined readout- Digitizers are implemented as daughter cards (FINESSE)- Works at >30KHz!HiguchiReady for Mass Production

  • Near-term Upgrade of DigitizersReplace FASTBUS TDC system with COPPER based TDC system COPPER : Common readout module to handle pipeline readoutControllerTDMGate GeneratorFPILeCroy 1877SEvent BuilderFastEtherTrigger (SEQ)VME6UFASTBUSNetwork SWReadout PCCOPPERLeCroy 1877SLeCroy 1877SCOPPERCOPPERTTRXTTRXTTRXTT-SWVME9UX nEvent BuilderGbEGbEFastEtherTrigger

  • Near-term Upgrade of Event Builder/RFARMCurrent DAQ : Readout subsystems are connected to single Event Builder through point-to-point network connection- Modularize (Event Builder + RFARM) as a unit- Have multiple units CDCTOFECLKLMVTXVTXVTXVTXEvent BuilderRFARMCDCTOFECLKLMVTXVTXVTXVTXTransfer Network MatrixL=1.5x1034cm-2sec-1/unit

  • .....~1000 Pipeline ROM(COPPER) (pipelined readout)~50 Readout PCs.....>10 Event Building Farms>10 L3 FarmsTransfer Networkmass storageInput: ~ 100K channelsall components areLinux-based PC'sDesign for SuperKEKBCurrent DAQ

  • L1 trigger rate 500 Hz 20 kHz

    Maximum trigger rate 650 Hz 30 kHz Event size at L1 40 kB/ev 300 kB/ev Data flow rate at L1 25 MB/s 9 GB/sec

    Data flow at storage 13 MB/s 250 MB/sec

    Subdetector readout 26 >1000 HLT reduction 2 12 Belle(L=1.5x1034)SuperKEKB(L=5x1035)Estimated DAQ condition at SuperKEKBUpdated!!

  • Detector Electronics @ SuperKEKBQuick Summary- SVD : CMS APV25 chip

    - Pixel : MAPS(CAP3) or striplet(APV25)

    - CDC : 2 stage upgrade 1) Pipelined TDC with Q-to-T conversion (shorter shaping time) 2) ADC with waveform sampling ([email protected]>100MHz)

    - ECL : Wave form sampling needed to manage pileup effect (14bit [email protected] for barrel, >20MHz for pure CsI)

    - TOP/RICH : Need to manage pixel photo-detector * Time stretcher, HPTDC, Analog pipeline

    - KLM : Readout scheme is not so much different from Belle's regardless of choice of detection device (RPC/Sci. Tile) * "hit" info multiplexing + on-board data compression

  • TDC FINESSE24 ch LVDS input (96 ch / COPPER)~150 COPPER boards in total for the SuperBelle CDC.Time resolution 0.78 ns/bit (w/ 40MHz clock) ~ 27 m position resolutionDynamic range = 17 bit equivalent to 100 s pipeline depthLinearity = 0.49%Higuchi

  • * Current prototypes : channel density is too low* Needs to develop high-density 10bit/100MHz ADC (~ 100 ch / module (VME 9U) ) -> can be used for CDC and PID8 ch differential input

    Sampling clock = 65 MHz

    Dynamic range = 12 bitLinearity = 1.2%Equips 512 word/ch FIFO

    (500 MHz FADC FINESSE of 2 ch / 8 bit has also been developed)The FINESSE with higher channel density is under design.Flash ADC FINESSEHiguchi

  • *(COPPER2)

    2004/5 Hawaii FINESSE EffortsVarner

  • *HPTDC FINESSE32-channels (8 channel HP mode)Varner

  • Overview of APV25Based on IBM 0.25m technology Input stage:shaping time: 50nsecENC(e)=270+38/C (pF) or 2000 electrons at 45 pF input capacitanceAnalog deconvolution is possible but will not be used in Belle SVD.160 out of 192 stage analog pipeline operated at 40 MHz clock~4 sec trigger latency30 events can be queued for readout40 MHz analog multiplexing (3+) sec for 128 channel readout)2 mW/channel

    SVDTsuboyama

  • Readout electronicsfront end: APV25, Vienna repeater (not the final version, a new version with AC coupling and base line restore will be ready in April)

    15m CAT5 cable (like SVD2) back end: Vienna readout system with programmable APV sequencer and fast ADCs (same as on CMS Pixel FED)Schwanda

  • 4 ADC4 times 10 bit data4 clocks with adjustable phaseAltera Daughter 9 inputs 9 data proc + FIFOsP1P264 (or 32 bit) bit data bus 40 MHz+4 control lines 9 lines with information for trigger proc.Fast data transfer to PCIP3VME protocol AlteraAltera daughter with final FIFOData for trigger, serialSchematics of the ADC-Pixel with the possibility of single channel processing and output with data for trigger processor (largely exists) 2 clocks phase shiftedTTC input optical connection12 input optDelayed clock and control sig.distributer, VME controlCMSP 0Transmit crate clock, control signals and event numberControl bus* Signal processing on FPGA for occupancy reduction Vienna group has two ideas on the algorithmSchwanda

  • Nishida PID

  • Nishida PID

  • Schwartz* Wave form sampling is required

  • Schwartz

  • Schwartz

  • Role of FINESSE- Two implementations are cosidered1. On-board digitizers - Original idea - ~ 100 channels / 4 FINESSE cards = 1 COPPER module - AMT based TDC, high-speed ADC cards are being developed

    2. Interface to outside digitizer system - For complicated readout electronics unified with digitizers i.e. SVD (APV25), Pixel (CAP), ECL, etc. - Standard interface FINESSE is being considered ex. Optical S-link

  • Upgrade TimelineFY2004: - Complete R&D on COPPER Almost done TDC FINESSE design and production in progressFY20