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Encoders/Decoders
Overview
• Design Procedure• Code Converters• Binary Decoders
– Expansion– Circuit implementation
• Binary Encoders• Priority Encoders
30-Apr-
2Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Combinational Circuit Design
• Design of a combinational circuit is the development of a circuit from a description of its function.
• Starts with a problem specification and produces a logic diagram or set of boolean equations that represent the circuit.
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
330-Apr-
Design Procedure
1. Determine the required number of inputs and outputs and assign variables to them.
2. Derive the truth table that defines the required relationship between inputs and outputs.
3. Obtain and simplify the Boolean function (K-maps, algebraic manipulation, CAD tools, …). Consider any design constraints (area, delay, power, available libraries, etc).
4. Draw the logic diagram.5. Verify the correctness of the design.
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
430-Apr-
Design Example
• Design a combinational circuit with 4 inputs that generates a 1 when the # of 1s equals the # of 0s. Use only 2-input NOR gates
…
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
530-Apr-
More Examples - Code Converters
• Code Converters transform/convert information from one code to another:– BCD-to-Excess-3 Code Converter
• Useful in some cases for digital arithmetic– BCD-to-Seven-Segment Converter
• Used to display numeric info on 7 segment displays
630-Apr-
BCD-to-Excess-3 Code Converter
• Design a circuit that converts a binary-coded-decimal (BCD) codeword to its corresponding excess-3 codeword.
• Excess-3 code: Given a decimal digit n, its corresponding excess-3 codeword (n+3)2Example:
n=5 à n+3=8 à 1000excess-3n=0 à n+3=3 à 0011excess-3
• We need 4 input variables (A,B,C,D) and 4 output functions W(A,B,C,D), X(A,B,C,D), Y(A,B,C,D), and Z(A,B,C,D).
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
7
BCD-to-Excess-3 Converter (cont.)
• The truth table relating the input and output variables is shown below.• Note that the outputs for inputs 1010 through 1111 are don't cares (not
shown here).
30-Apr-
8Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
930-Apr-
Maps for BCD-to-Excess-3 Code ConverterThe KThe K--maps for are constructed using the don't care termsmaps for are constructed using the don't care terms
BCD-to-Excess-3 Converter (cont.)
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
1030-Apr-
Another Code Converter Example:BCD-to-Seven-Segment Converter
• Seven-segment display:– 7 LEDs (light emitting diodes), each one
controlled by an input– 1 means “on”, 0 means “off”– Display digit “3”?
• Set a, b, c, d, g to 1• Set e, f to 0
30-Apr-
11Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)d
a
b
c e
f g
BCD-to-Seven-Segment Converter
• Input is a 4-bit BCD code à 4 inputs (w, x, y, z).
• Output is a 7-bit code (a,b,c,d,e,f,g) that allows for the decimal equivalent to be displayed.
• Example: – Input: 0000BCD– Output: 1111110
(a=b=c=d=e=f=1, g=0)
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12Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)d
a
b
c e
f g
BCD-to-Seven-Segment (cont.)Truth Table
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
1330-Apr-
DigitDigit wxyzwxyz abcdefgabcdefg00 00000000 1111110111111011 00010001 0110000011000022 00100010 1101101110110133 00110011 1111001111100144 01000100 0110011011001155 01010101 1011011101101166 01100110 X011111X01111177 01110111 11100X011100X0
DigitDigit wxyzwxyz abcdefgabcdefg88 10001000 1111111111111199 10011001 111X011111X011
10101010 XXXXXXXXXXXXXX10111011 XXXXXXXXXXXXXX11001100 XXXXXXXXXXXXXX11011101 XXXXXXXXXXXXXX11101110 XXXXXXXXXXXXXX11111111 XXXXXXXXXXXXXX
??
Decoders
• A combinational circuit that converts binary information from n coded inputs to a maximum 2n decoded outputs à n-to- 2n decoder
• n-to-m decoder, m ≤ 2n
• Examples: BCD-to-7-segment decoder, where n=4 and m=7
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Decoders (cont.)
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
1630-Apr-
2-to-4 Decoder
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
1730-Apr-
2-to-4 Active Low Decoder
3-to-8 Decoder
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
1830-Apr-
addressaddress
datadata
3-to-8 Decoder (cont.)
• Three inputs, A0, A1, A2, are decoded into eight outputs, D0 through D7
• Each output Di represents one of the minterms of the 3 input variables.
• Di = 1 when the binary number A2A1A0 = i• Shorthand: Di = mi
• The output variables are mutually exclusive; exactly one output has the value 1 at any time, and the other seven are 0.
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
1930-Apr-
• Any combinational circuit can be constructed using decoders and OR gates! Why?
• Here is an example:Implement a full adder circuit with a decoder and two OR gates.
• Recall full adder equations, and let X, Y, and Z be the inputs:– S(X,Y,Z) = X+Y+Z = Σm(1,2,4,7) – C (X,Y,Z) = Σm(3, 5, 6, 7).
• Since there are 3 inputs and a total of 8 minterms, we need a 3-to-8 decoder.
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
2030-Apr-
Implementing Boolean functionsImplementing Boolean functionsusing decodersusing decoders
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
2130-Apr-
Implementing a Binary Adder Using a Decoder
S(X,Y,Z) = Σm(1,2,4,7)
C(X,Y,Z) = Σm(3,5,6,7)
Decoder Expansions
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
2230-Apr-
Larger decoders can be constructed using a number of smaller ones.
-> HIERARCHICAL design!Example:A 6-to-64 decoder can be designed using four 4-to-16 and one 2-to-4 decoders. How? (Hint: Use the 2-to-4 decoder to generate the enable signals to the four 4-to-16 decoders).
3-to-8 decoder using two 2-to-4 decoders
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
2330-Apr-
4-input tree decoder
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Encoders
• An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2n input lines and n output lines.
• The output lines generate the binary equivalent of the input line whose value is 1.
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Encoders (cont.)
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Encoder Example• Example: 8-to-3 binary encoder (octal-to-binary)
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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A0 = D1 + D3 + D5 + D7A1 = D2 + D3 + D6 + D7A2 = D4 + D5 + D6 + D7
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
2830-Apr-
Encoder Example (cont.)Encoder Example (cont.)
Simple Encoder Design Issues
• There are two ambiguities associated with the design of a simple encoder:1. Only one input can be active at any given time. If
two inputs are active simultaneously, the output produces an undefined combination (for example, if D3 and D6 are 1 simultaneously, the output of the encoder will be 111.
2. An output with all 0's can be generated when all the inputs are 0's,or when D0 is equal to 1.
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
2930-Apr-
Priority Encoders
• Solves the ambiguities mentioned above.• Multiple asserted inputs are allowed; one
has priority over all others.• Separate indication of no asserted inputs.
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Example: 4Example: 4--toto--2 Priority Encoder2 Priority EncoderTruth TableTruth Table
4-to-2 Priority Encoder (cont.)
• The operation of the priority encoder is such that:
• If two or more inputs are equal to 1 at the same time, the input in the highest-numbered position will take precedence.
• A valid output indicator, designated by V, is set to 1 only when one or more inputs are equal to 1. V = D3 + D2 + D1 + D0 by inspection.
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Example: 4Example: 4--toto--2 Priority Encoder2 Priority EncoderKK--MapsMaps
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Example: 4Example: 4--toto--2 Priority Encoder2 Priority EncoderLogic DiagramLogic Diagram
8-to-3 Priority Encoder
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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A Matrix of switches = Keypad
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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C0 C1 C2 C3
R0
R1
R2
R3
1 2 3 F
4 5 6 E
7 8 9 D
0 A B C
Keypad Decoder IC - Encoder
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
3730-Apr-
1 2 3 F
4 5 6 E
7 8 9 D
0 A B C
COL.4-bit
ROW4-bit
4-bitBinary
(encoded)
Priority Interrupt Encoder Schematic
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
3830-Apr-
Device A
Device B
Device C
Device D
MicroprocessorInterruptEncoder
Req(1:0)
IntRq
InterruptingDevices
Priority Encoding -Interrupt Requests
Interrupting DeviceInterrupting DeviceAA BB CC DD Req (1:0)Req (1:0) IntRqIntRq00 00 00 00 0 00 0 0000 00 00 11 0 00 0 1100 00 11 00 0 10 1 1100 00 11 11 0 10 1 1100 11 00 00 1 01 0 11
Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
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Exercise: Complete this table?