Phase-change memories for energy-efficient data-centric IT

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A. Pirovano

Process R&D, Micron

Phase-change memories for energy-efficient data-centric IT

applications


Outline

▶ Memory trends and power usage

▶ Phase-change memory concept and value

propositions

▶ PCM products specifications

▶ Scaling trends

▶ Power efficency and future perspectives


Background

▶ Memory power consumption in systems has grown over time

▶ Social Network: > 1B users, 40% mobile access, > 3B photos/month, > 12M

videos/month

▶ CO2 emissions due to data centers are half of those due to airplanes

▶ In mid-size servers memory arrays account for 40% of power consumption;

the processor for less than 30%

▶ DRAM stand-by accounts for 35% of a Smart Phone battery life. SRAM

contributes to 15% of a cellular phone talk-time

▶ In HDD 70% of power goes to spinning and tracking. Current SSD’s consume

30% of HDD’s.

A. L. Lacaita, VLSI, 2010


Smartphone trend

▶ Smartphone market is in constant expansion: 350% in 7 years


Smartphone power usage

▶ High-end processors: memory

accounts for 20% of the total

power consumption

▶ Low power processors: memory

accounts for 70% of the total

power consumption

J. Howard, ISSCC, p. 108, 2010


Data center trend

▶ Data center for “cloud” systems is another explosive market: it is

predicted to expand 350% in 5 years


Cloud computing is changing the paradigm

▶ From compute-centric

� Bottleneck:

CPU/Memory

▶ Extrapolation to 2020:

� 5.6M of HDD

� 19’000 sq. ft.

� 25MW

R.F. Freitas, W.W. Wilcke, IBM J. Res. Dev. 52, 2008

▶ To data-centric

� Bottleneck: Storage

and I/O

▶ Extrapolation to 2020:

� 21M of HDD

� 70’000 sq. ft.

� 93MW


Data center power usage

▶ Cooling is becoming a big piece

of the cake with almost 50% of

the total energy spending

▶ Inside a server, HDD and

DRAM, hence memory, is

responsible for 40% of the total


Future in data center

▶ PCM is one of the

candidates to push

to the market the

so called Storage-

Class Memory

(SCM)R.F. Freitas, W.W. Wilcke, IBM J. Res. Dev. 52, 2008

G. W. Burr, IBM, 2010


NAND challenges as SCM

▶ NAND scaling is indeed increasing density

lowering costs but reliability is rapidly getting

worse

▶ Scaling is predicted to slow down with

respect to the past trend

▶ Write and read latency is predicted to

increase opening the serious question if SSDs

price/performance ratio will be competitive

with magnetic disks

L. M. Grupp et al., 2012


Phase Change Memory (PCM)

Page 11

▶ Storing mechanism

� Amorphous/poly-crystal phase of

chalcogenide alloy (Ge2Sb2Te5 – GST)

▶ Writing mechanism

� Current-induced Joule effect

▶ Sensing mechanism

� Resistance change of the GST

▶ Cell structure

� 1 transistor, 1 resistor (1T/1R)

Amorphous Crystalline

High resistivity Low resistivity

Amorphous Crystalline

High resistivity Low resistivity

I

V

I

V

Time

Temperature

Tx

Tm

Reset (amorphization)

Set (crystallization)

Time

Temperature

Tx

Tm

Reset (amorphization)

Set (crystallization)


Selectors and PCM Array Architectures

MOSFET BJT/Diode OTS

Process

Complexity

No mask overhead for

the selector

Dedicated steps for the

p-n-p junction

integration

Dedicated steps in the

BEOL

Cell Size Larger (~20F2) Smaller (~5F2) 3D cross-point (~4F2/n)

Memory Array

OrganizationConventional Innovative Ground-breaking

Application Embedded memoryHigh density/

High PerformanceVery high density

Schematic Cell

Structure

Cross-sectionn+n+

p-substrate

STI

WL

BL

GND

n+n+p-substrate

STI

WL

BL

GND

p-substraten-wellp+

BL

WL

n+

p-substraten-wellp+

BL

WL

n+

BL

WL

OUM

OTS


Phase Change Memory Key Attributes

Attributes PCM EEPROM NOR NAND DRAM

Non-Volatile Yes Yes Yes Yes No

Scaling sub-2x nm n.a. 3x nm 2x nm 3x nm

Granularity Small/Byte Small/Byte Large Large Small/Byte

Erase No No Yes Yes No

Software Easy Easy Moderate Hard Easy

Power ~Flash ~Flash ~Flash ~Flash High

Write Bandwidth 1- 15+

MB/s

13-30

KB/s

0.5-2

MB/s

10+

MB/s

100+

MB/s

Read Latency 50 - 100 ns 200-200 ns 70-100 ns 15 - 50 us 20 - 80 ns

Endurance 106+ 105 -106 105 104-5 Unlimited

PCM provides a new set of features combining properties of NVMs with DRAM

▶ Non Volatility

▶ Flexibility

� No Erase, Bit alterable,

Continuous Writing

▶ Lower power

consumption than RAM

▶ Fast Writes

▶ Read bandwidth and

writing throughput

▶ eXecution in Place

▶ Extended endurance


PCM Value Proposition


PCM – NOR Flash legacy

C.Villa et al., ISSCC 2010

▶ Replace NOR in embedded platforms

� PCM has an edge due to density,

scalability, and write speed

▶ 45nm PCM - 1Gb “Bonelli” specifications

� NOR Flash legacy spec + bit alterability

� Chip area: 37.5 mm2

� Power supply range: 1.7V, 2.0V

� Temperature range: -40°C, +85°C

▶ Measured performance

� Initial access speed: 85ns

� Max read throughput: 266MB/s

� Program throughput: 9MB/s


PCM – LPDDR2

▶ Replace (a part of) DRAM

� PCM has an edge on DRAM due to power and

scalability, but it is slower

▶ 20nm PRAM - 1Gb x 8 LPDDR2 specifications

� LPDDR2 interface

� Chip area: 59.4 mm2

� Power supply range: 1.8V, 1.2V

� Temperature range: -25°C, +85°C

▶ Measured performance

� Initial access speed: 120ns

� IO speed: 800Mb/s/pin

� Program throughput: 40MB/s (133MB/s with

external power and 256b parallel write)

Y. Choi et al., ISSCC, 2012


PCM Application Opportunities

PCM feature can be exploited by all the memory system, especially the ones resulting from the convergence of consumer, computer and communication electronics

▶ Wireless System to store of XiP, semi-static data and files� Bit alterability allows direct-write memory

▶ Solid State Storage Subsystem to store frequently accessed pages and elements easily managed when manipulated in place

� Caching with PCM will improve performance and reliability

▶ Computing Platforms taking advantage of non-volatility to reduce the power

� PCM offers endurance and write latency that are compelling for a number of novel solutions

S.Eilert et al., “PCM: a new memory enables new memory usage models”, IMW, 2009


PCMS Memory Cell Cross-Bar Architecture

Ovonic Threshold Switch, OTS, is a two-terminal switch

Metal 1Met

al 2

Row

Column

Poly

Si-Subst rate

Metal 1Met

al 2

Row

Column

Poly

Si-Subst rate

Chalcogenide materials can be used both for the memory and for the selector to

form stackable cross point PCM

• True high density cross-bar

• Possible multilayer vertical stacking

Intel-Numonyx, IEDM 2009


C. Lam, SRC NVM Forum 2004

Y. C. Chen et al., IEDM 2006

Ultimate Scalability of PCM principles

▶ Device functionality demonstrated on

60 nm2 active area

▶ Reset current <10uA

▶ Phase change mechanism appears

scalable to at least ~5nm

P.Wong, EPCOS 2010


Scaling and Program Disturb

S.H. Lee et al. VLSI, 2010

▶ Program disturb due to thermal crosstalk represents one of the main issues for PCM device scaling

� Anisotropic scaling worsen the problem

� A well-tempered engineering of the thermal conductivity of the surrounding dielectrics and in particular of interfaces keeps this problem under control


PCM Device Scalability

A. Redaelli et al., IRPS 2010

If an isotropic scaling

approach is adopted

▶ Programming current

decreases linearly

▶ Thermal disturb issues do not

rise

▶ Current density increases with

geometrical scaling


Current Density Effects in BJT Devices

▶ BJT devices fabricated at 45nm have been characterized aiming to assess the

BJT reliability after a DC stress at the current density required to program

scaled PCM at different nodes

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.50

5

10

15

20

25

3016 nm

22 nm

32 nm

45 nm

Cur

rent

Den

sity

[M

A/c

m2 ]

Applied Voltage, VEB

[V]


BJT Stress Results

No degradation occurs after stressing the BJT with 25 MA/cm2

DC current density for 100 s (equivalent to 109 program events)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.50

5

10

15

20

25

30Stressing current

Before stress After stress

Applied Voltage, VEB

[V]

Cur

ren

t Den

sity

[MA

/cm

2 ]

0 1 2 3 4 510f

100f

1p

10p

After stress Before stress

Applied Voltage, VBE

[V]

Rev

erse

Cur

rent

[A]


PCM Cell Endurance

0 50 100 150 200105

106

107

108

109

1010

Accelerated stress

Scaling trend in operating conditions

45 nm90 nm180 nm

Cyc

le N

um

ber

[#]

Current Density [MA/cm2]

A. Redaelli et al., IRPS 2010

▶ Intrinsic endurance does not depend on the lithographic node if PCM is

programmed with its own programming current

▶ Premature failures in accelerated tests is related to the temperature reached

inside the device


0.01

0.1

1

10

100

1 10 100 1000 10000

Energy [pJ]

Contact area [nm2]

Reset

Set

PCM energy scaling

▶ Energy to program a bit follows the technology scaling: reducing the

cell size it is possible to reduce it from today 10pJ down to 0.1pJ

Area [nm2]

Reference

2.54 Jiale, VLSI 2011

28.26 Feng, Science 2011

127.5 I.S. Kim, VLSI 2010

400 Pirovano, ESSDERC 2007

487.5 D.H. Kim, IEDM 2008

500 W.S. Chen, IEDM 2007

707 Y. Sasago, VLSI 2006

1257 Breitwisch, VLSI 2007

1963 J.I. Lee, VLSI 2007

3000 Pellizzer, VLSI 2006

4000 Y.H. Ya, VLSI 2003

State of the art for PCM products


Energy-effiicient computation

200 kW 20 W

▶ Performance gap between human brain and machine computing has

been largely reduced, but...

▶ ... an impressive energy consuption gap still exists!


An outlook to the future – I

▶ Recently it has been shown by Tominaga group that by proper

engineering of the active material it is possible to reduce the

programming current of 20x (J. Tominaga et al. E\PCOS 2010, R.E.

Simpson et al., Nature Nanotechnology 2011)

T. Shintami et al., E\PCOS, 2011


An outlook to the future – II

▶ PCM can be use as energy efficient synapse in ultra-dense large scale

neuromorphic systems enabling biologically inspired low power, highly

parallel, and fault-tolerant systems

▶ 4M PCM cells

▶ 2M synapses

▶ 680s learning duration

▶ 112µW/learning

(70’000nm2 cell area)

M. Suri et al., IEDM Tech. Dig., 2011


Conclusions

▶ Memories are becoming growingly fundamental in

electronic systems thanks to the introduction of “memory-

centric” concept.

▶ Demand for high-density memory combined with high-

performance, energy efficient and highly reliable is

continuously increasing.

▶ PCM technology has the potential features that could

match the requests.

Documents

Phase-change memories for energy-efficient data-centric IT