Phil Lehwalder – ECE526

Summer 2011 Dr. Chiang

PLL (Phase Lock Loop) – Dynamic system that produces a clock in response to the frequency and phase of an input clock by varying frequency of an internal oscillator.

DLL (Delay Lock Loop) - Dynamic system that produces a clock in response to the frequency and phase of an input clock by varying frequency the delay of an internal delay line.

Can be modeled as linearized system for simulation if: Near locked condition minimizes non-linear behavior Loop BW << input fin sampled system therefore Nyquist applies

V0ltage Controlled Oscillator (VCO) – fout Vcontrol

When in or near lock:

fout changes quickly with VCTRL, but f error takes time to correct

Gain of this block is Hz/V

Ring oscillator common:

fout = inverse of the 2x round trip delay

fout controlled via inverter current, voltage, or capacitance

Problem: Tuning and gain varies widely with PT

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VCO

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All methods vary R, C or I

Used for PLL VCO control and for DLL delay line control

Divider lowers feedback frequency by factor of N

VCO has to run N time higher than fin to lock

This is one way to make a clock multiplier

N=1 → fout = fin & output tracks input in frequency & phase

N=1 makes a “zero delay buffer”

Divider must be able to function at VCO fmax of PLL may fail to lock at startup

Compares phase of fin & feedback signal

Generates PWM error signal to loop filter based on phase delta of fin & fout over 180 degree phase window Output %Dmin = 0% → fin & fout in phase

Output %Dmax = 100% → fin & fout 180◦ out of phase

Becomes VCO control signal post loop filter

Sensitive to clock jitter and %D variation

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PD VK

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Sequential PD drives the loop filter based on phase delta of fin & fout

Makes UP & DOWN signals to drive charge pump that drives loop filter Signals are only high until both are high, then asynchronously reset.

Good over +/-360◦ phase window

Less sensitive to jitter & duty cycle variation since flops are edge triggered

Preferred phase detector for clock generation Faster to lock & more reliably than XOR PD

Phase–Frequency Detector drives charge pump R,C, & C2 form shunt filter → converts charge pump IOUT to VCO VCTRL

R&C set the bandwidth C2 smooth charge pump ripple → avoids charge pump induced jitter

C2 << C → C2 can be ignored since RC set the loop BW roll off point

Loop filter sets VCO adjustment per unit phase error Kp term is “proportional” → “instantaneous” change Ki term is fine error correction over time “Integral” Filter forms a PI control system that sets BW & system stability

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PLL system is a 2nd order system

Loop is biquadratic low pass

BW selected depending on dominant jitter/noise source On chip noise – set BW high to compensate

Off chip clock noise – lower BW to average out or reject noise

BW should be ≤ fin/10 so continuous time rules apply Avoids alias induced jitter since this is really a sampled system?

Damping factor < 0.707 to avoid ringing on input step change

Similar overall structure to PLL, but VCO replaced with adjustable delay and no FB divider Cannot perform frequency multiplication, but allows for multiple

skewed or phase clock outputs

Delay gain = seconds/V

Can be build using the same elements used to make the VCO adjustable

DLL system is a 1st order system

Filter is single pole (integrator)→ not prone to instability

Output = delay version of input → prone to input noise issues

Communication BW increasing over time

Market driving smaller devices → Cannot just add pins

Speeds > 1GHz becoming common place

Significant challenges of high speed I/O Generate fast pulses & detect logic state reliably

No ideal transmission line effect in play (lossy)

Distinguishing one bit from next when transmitted in succession

Point to point becoming more common vs. multi-drop configurations Easier to achieve good signal integrity (SIE) PCIe, SATA, USB, Fire Wire, GB LAN

Paralleled point to point lanes increase BW

Low Frequency (channel length << l) → system = lumped Channel ~ideal → t-line effects die out in small time relative to signal period

Conductor act like equipotential net → signal same at both ends of the channel Tx Driver see Rx load impedance

High Frequency(channel length > l) → system = distributed t-line effects in play → tf & tf << signal propagation delay

Signal propagate like a wave → signal not same at both ends of the channel

Tx driver see t-line Z0 (characteristic t-line Impedance) as load Impedance matching critical to signal integrity (SIE)

Signal Propagation:

er – relative permittivity → known as dielectric constant of material (e.g.FR4)

e0 – permittivity of free space

m0 – relative permeability of free space

Channel Characteristic Impedance (Z0): Structure dependent Microstrip – routed on outer layers of package or board

Stripline - routed on inner layers of package or board

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ZTERMINATION ≠ ZO (Impedance mismatched case)

Signal energy not completely absorbed at load

Some energy reflected back towards the source

Reflected signal set by reflection coefficient G

ZL < ZO → (-) reflection → Ring back & non-monotonicity

ZL > ZO → (+) reflection → Overshoot, undershot & non-monotonicity

At high data rates (bit time << tPROPAGATION ) reflection from one bit can interfere other bits → Inter-symbol Interference (ISI)

ZTERMINATION = ZO (Impedance matched Case)

No reflections → Tx can send bit n+1 before bit has reached the Rx → no ISI

OL

OL

INCIDENT

REFLECTED

ZZ

ZZ

V

V

G

Dispersion: Frequency dependent attenuation of signal

Results in distorted signal at Rx due to attenuation of high frequency content

Source of issue is dielectric loss & skin effect

Depending on signal pattern signal distortion can result in ISI

Can be corrected with de-emphasis (equalization)

Crosstalk: Capacitive or inductive coupling between near by signals where energy from an aggressor net is coupled into a victim net.

Single ended systems: Coupling must be removed to fix → routing change. Can reduce with guard ground traces to shield signals of aggressors

Differential signaling → crosstalk is common mode so cancels out at Rx

Error correction coding, error detecting codes, and sequencing detection can be used to detect data in the presence of crosstalk Less common in HS I/O → used in digital communications systems.

Return Path Noise: Power path that results in difference between the Tx & Rx sides due to non-ideal VCC and GND → same effect as noise at the Rx input

Ground Bounce: Ground noise induced by driver conduction that has the same effect as noise at the Rx input.

VCC Droop: VCC noise induced by driver conduction that has the same effect as noise at the Rx input.

Return path noise manifest itself in many ways Signal jitter, VOH transient droop, VOL transient ring back

Multi-signal interfaces can suffer from simultaneous switching noise (SSN) Return path noise from signal(s) interferes with other signals

Driver ZOUT varies widely over the transfer characteristic

Need for external termination to minimize reflections and ISI

a). Pull only driver - current mode signal converted to voltage by R=ZO (ex. GTL).

b). Push-Pull CMOS - Standard series termination where Rout << ZO → R=ZO

c). Pull Only – Terminated at both ends, but swing is cut in half for a given current mode signal

Buffers can be RCOMP trimmed to make buffer Rout = ZO

Differential output signals 180◦ out of phase

Increases noise immunity Common mode noise canceled out at Rx

Need for external termination to minimize reflections and ISI

Typical swing < 1V: USB2.0 = +/-400mV @480Mbps

SATA (Gen2) = +/-350mV @ 3Gbpd PCIe = +/-600mV @ 1.2Gbps LVDS = +/-350mV @ up to 3.125Gbps

a). Pull only differential current mode driver Steers Isw between D+ and D- outputs Signal converted to voltage by R=ZO at Rx end

b). Push-Pull CMOS driver Steers Isw between D+ and D- outputs Signal converted to voltage by R=ZO at Rx across

D+ and D- lines\ D+ transistors on for output =1 D- transistors on for output =0

AC Coupling due to unmatched DC operating point between Tx & Rx

May require 8b/10b encoding to minimize LF information & signal loss across the caps

Programmable Drive strength

Switch in or out parallel legs to change drive strength of buffer

Allows for output swing adjustment

Can aid in compensating for signal loss

Can help with signal integrity issues

Programmable Slew Rate (edge control):

Parallel output legs switched in over time

Reduced edge rates lower EMC emissions

Transmitter De-emphasis (Equalization):

Attenuates LF information to make frequency response in loss t-line flat

Corrects distortion due to dispersion

Secondary buffer not active for consecutive data (attenuates low frequency information)

Multi-transmitter time-interleaving

Multiple transmitters in parallel driven by shifted clocks

Example: 4 x 4Gbps transmitter in parallel with clock driven in quadrature

Each runs at 4Gbps → combined Tx rate is 16Gbps

Multi-level Transmitter

Single transmitter encodes multiple bits

Uses paralleled buffers with weighted buffer strengths

Example: 4 level transmitter → encodes 2 bits on a single wire

Receivers:

Core of receiver is a flip-flop that samples the data at the appropriate time

Sub-1v HS differential interfaces may use an SA-FF → low signal swing FF

Time interleaving I/O uses staggered receivers based on tapped DLL clocks

Multi-level signaling interfaces use ADC as Rx

Bit Error Rate (BER):

Main measure of performance for I/O

Statistical measure of the probability of a transferring an erroneous bit

Typical rates for HS I/O are in the 10-10 to 10-12

Number is very low because most logic has little redundancy

Low frequency interfaces typically use handshaking for bit transmission Tx sends bit and Rx notifies or “ACKs” that bit is received Only one on transmission path at any point in time

HS I/O use time a marker for bits Tx clock source is a PLL or DLL → minimize clock edge variation (absolute jitter) Bit transmitted at a constant time intervals → fixed bit time No handshaking signals between the Tx and Rx

Tx and Rx must agree on the timing of each bit → bit time precisely controlled Rx must sync with the transmitter to sample data at middle of signal eye

Example: NRZ encoded differential HS I/O Logical 1 = high (+ polarity) Logical 0 = low level (- polarity)

Clock transmitted with the data on separate on separate I/O channel

Clock is typically common to several I/O channels

Discrepancies in channel propagation delays lead to timing errors at Rx

Forces tight layout matching → common to DDR, SATA, PCIe, USB, Firewire…etc

Single Data Rate System (SDR) – data samples on one edge of clock

Double Data Rate System (DDR) – data sampled on both clock edges

Clock in quadrature (90◦ out of phase) with data for SDR & DDR

Clocks typically need to be buffered on Rx side

Conventional buffers

Generates internal skew shifting data sample point away from middle of eye

Variation in delay across buffers results in substrate noise that can increase jitter

Fix: Use a PLL /DLL to lock to source CLK → acts like zero-delay buffer

Interface clock may be transmitted in phase with data

PLL with multi-tap VCO used to recover proper clock to data phase

At very high transfer rates keeping CLK & DATA aligned becomes difficult

Bit time small → minor clock to data skew is a significant portion bit time

Skew due to systematic variations in tolerances in ZO, propagation delays…etc

Phase is not reliable, but frequency is reliable → need Rx that can realign clock to data phase

In some cases it may be hard to accommodate the added clock channel

Instead – Tx & Rx agree on a bit transfer rate and Rx uses local clock to recover data

Local Rx clock has tolerance that causes it to vary over time

This system has uncertain phase and uncertain clock frequency at Rx side

Common method is for Rx to use a PLL to generate a sampling clock

Clock acts as oversampling clock that is centered on the data eye

Example: Rs232 & RS422 serial interfaces (30+ years old)

True Random Number Generator – uses thermal noise driving a VCO to generate random bits that are sampled via a shift register to form a random bit sequence

Chip ID: Utilizes process variation as a chip finger print – good for tracking illegal re-branding and counterfeiting

Cross coupled inverters who's final state after reset de-assertion is set by device mistmatcing due to process variation, but is consistent for a specific part.

Phil Lehwalder – ECE526

Summer 2011 Dr. Chiang

Can be modeled in terms of their phase: CLK = 1 for f(t)mod 2 <

CLK = 0 for f(t)mod 2 ≥

Signal phase is linearly accumulated over time

Neglects non-ideal effects (jitter, Power supply noise..etc)