Physical Design Key Highlights
Successfully executed multiple turnkey projects from RTL to GDS
and Netlist to GDS
Experience in most advanced Process nodes down to 5nm.
Experience in PDKs from industry leading fabs - TSMC, Intel,
Samsung, Global Foundries etc
Integration of Analog & Mixed signal SOC Low Power design
and High-Performance
designs Expertise on all industry standard EDA tools
– Synopsys, Mentor, Cadence, Ansys etc.
Logic / Physical aware Synthesis with focus on Power,
Performance & Area
Full chip level activities like IO Ring creation, Floor
planning, P&R activities
Block level Place & Route activities Rich experience in
Optimal Timing closure in
multiple process corners as per the application requirements
Sign off Physical Verification and closure of DRC, LVS, Antenna,
ERC
Development/Enhancement of Physical Design flows.
Motivated team, better design capability Rich and extensive
Physical Design (PD) experience has enabled the team to work on
multiple successful tape-outs. Expertise with all Industry standard
EDA tools, Design Flow and well trained to handle low power, high
performance area critical designs.
Value Proposition
Domain Expertise
Team includes highly skilled and experienced professionals
ranging from project managers, testers, programmers, designers, and
developers
Technology / Process Nodes: 180nm down to 7nm, 5nm designs
EDA Tools:Synopsys, Mentor, Cadence, Ansys etc
Fab experience:TSMC, Intel, Samsung, Global Foundries
Servers Graphics Mobile Audio Networking
Physical Design (PD)
Technical AdvantageTeam
Automotive Wireless IoT
www.tessolve.com
Tessolve is the market leader in providing engineering solutions
for silicon and systems development. We offer a unique combination
of both pre-silicon and post-silicon expertise to provide an
efficient turnkey solution for silicon bring up, spec to a product.
With 2100+ employees worldwide, Tessolve enables customers a faster
time-to-market through deep domain expertise in Analog, Digital,
Mixed Signal, and RF, broad ATE platform experience, diverse
embedded software services and built-in infrastructure including a
test floor, characterization, reliability lab, system lab, and PCB
FAB.
Tessolve delivers ASIC design services including advanced
process nodes with a strong eco-system relationship with EDA, IP,
and foundries. Tessolve’s post-silicon solution takes silicon from
the foundry to high volume manufacturing. Our front-end design
strengths integrated with the knowledge from the backend flow,
allows Tessolve to catch design flaws ahead in the cycle, thus
reducing expensive re-design costs, and risks.
Contact For more details https://www.tessolve.com/vlsi-design/ |
www.tessolve.com
Recent Projects Delivered
Activity Technology Domain Tools Metrics, Design Details
RTL/ Block level test bench coding, RTL/ Block level test bench
micro architecting
40nm – 10nm RTL Coding, QC checks
Cadence, Spyglass
RTL/Spyglass clearance/Block level test benches for I2C/I3C,
SPI, UART/HSUART, MIPI, MMC, Secure Digital, USB protocols
Physical implementation of Always on Subsystem.
7nm PD Innovus, ICC2, PT, PTPX, Conf LEC.
Cell count: 1.17M; Size: 720 x 720 um; 3 power domains.;
Frequency 250MHz.
P&R of GPU Block 28nm PD Talus Chip with advance features
& one of the biggest in 28nm. Worked from scratch to GDS in
28nnm on 10 different partitions. Each one has roughly 700K
instances. Fq: 1 GHz
Synthesis-GDS flow dev. Block level (4) and Top-level PD
40nm PD Genus, Innovus, LEC Calibre, RH, Tempus
NXP – HeliosBlock and top-level synthesis; PD flow development
and implementation.Instance count approx. 350K per block. Top RDL
IO routing, Sign-off checks
Physical implementation of 1 block.
180nm PD Encounter, Tempus, Assura; Voltus.
NXP – Automotive group P&R STA & Sign off closure for
the blocks.Gate Count: ~1.5 M; Macros: 1; Clock Domains: 5; Fq:
250MHz.
Physical implementation of 2 blocks for a Server SOC.
10nm PD DC, ICC2, PT, PT-GCA, PT-PX, ICV, Conf LEC
Block1: Gates: ~1.5 M; Macros: 32; Clock Domains: 5; Fq: 1.3
GHzBlock2: Gates: ~5 K; Macros; Clock Domains: 8; Fq: 1.5 GHz
