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© 2005 Microchip Technology Incorporated. All Rights Reserved. Slide 1
PIC18 ReviewArchitecture, Instruction Set, and Assembly Language Programming
Architecture The high performance of the PICmicro® microcontroller
can be attributed to the following architectural features: Harvard Architecture
Instruction Pipelining
Large Register File (RISC)
Single Cycle Instructions
Single Word Instructions
Long Word Instructions (Harvard)
Reduced Instruction Set
Orthogonal Instruction Set
Harvard Architecture Von Neumann
Architecture: Fetches instructions and
data from a single memory space
Limits operating bandwidth
Harvard Architecture: Uses two separate memory
spaces for program instructions and data
Improved operating bandwidth
Allows for different bus widths
Instruction Pipelining Instruction fetch is overlaped with execution of
previously fetched instruction
rcall SUB1addwf REG2
movf PORTB,wreturnmovf PORTC,wreturn
SUB1
SUB2
movlw 0x05MAINmovwf REG1
1234
51525354
Example ProgramFetch Execute
T0
Flush
T1 T2 T3 T4 T5
Instruction Cycles
T6
Fetch Execute
Fetch Execute
Fetch
Fetch Execute
Fetch Execute
Fetch Flush
Fetch
T7
Time to execute normal instruction
Time to execute call instruction includes pipeline flush
Instruction Pipelining
rcall SUB1addwf REG2
movf PORTB,wreturnmovf PORTC,wreturn
SUB1
SUB2
movlw 0x05MAINmovwf REG1
1234
51525354
Example ProgramFetch
T0
Instruction Cycles
movlw 0x05 -Pre-Fetched Instruction Executing Instruction
Instruction Pipelining
rcall SUB1addwf REG2
movf PORTB,wreturnmovf PORTC,wreturn
SUB1
SUB2
movlw 0x05MAINmovwf REG1
1234
51525354
Example ProgramFetch Execute
T0 T1
Instruction Cycles
Fetch
movwf REG1 movlw 0x05Pre-Fetched Instruction Executing Instruction
Instruction Pipelining
rcall SUB1addwf REG2
movf PORTB,wreturnmovf PORTC,wreturn
SUB1
SUB2
movlw 0x05MAINmovwf REG1
1234
51525354
Example ProgramFetch Execute
T0 T1 T2
Instruction Cycles
Fetch Execute
Fetch
rcall SUB1 movwf REG1Pre-Fetched Instruction Executing Instruction
Time to execute normal instruction
Instruction Pipelining
rcall SUB1addwf REG2
movf PORTB,wreturnmovf PORTC,wreturn
SUB1
SUB2
movlw 0x05MAINmovwf REG1
1234
51525354
Example ProgramFetch Execute
T0 T1 T2 T3
Instruction Cycles
Fetch Execute
Fetch Execute
Fetch
addwf REG2 rcall SUB1Pre-Fetched Instruction Executing Instruction
Instruction Pipelining
rcall SUB1addwf REG2
movf PORTB,wreturnmovf PORTC,wreturn
SUB1
SUB2
movlw 0x05MAINmovwf REG1
1234
51525354
Example ProgramFetch Execute
T0
Flush
T1 T2 T3 T4
Instruction Cycles
Fetch Execute
Fetch Execute
Fetch
Fetch
movf PORTB,w rcall SUB1Pre-Fetched Instruction Executing Instruction
Time to execute call instruction includes pipeline flush
Instruction Pipelining
rcall SUB1addwf REG2
movf PORTB,wreturnmovf PORTC,wreturn
SUB1
SUB2
movlw 0x05MAINmovwf REG1
1234
51525354
Example ProgramFetch Execute
T0
Flush
T1 T2 T3 T4 T5
Instruction Cycles
Fetch Execute
Fetch Execute
Fetch
Fetch Execute
Fetch
return movf PORTB,wPre-Fetched Instruction Executing Instruction
Instruction Pipelining
rcall SUB1addwf REG2
movf PORTB,wreturnmovf PORTC,wreturn
SUB1
SUB2
movlw 0x05MAINmovwf REG1
1234
51525354
Example ProgramFetch Execute
T0
Flush
T1 T2 T3 T4 T5
Instruction Cycles
T6
Fetch Execute
Fetch Execute
Fetch
Fetch Execute
Fetch Execute
Fetch
movf PORTC,w returnPre-Fetched Instruction Executing Instruction
Instruction Pipelining
rcall SUB1addwf REG2
movf PORTB,wreturnmovf PORTC,wreturn
SUB1
SUB2
movlw 0x05MAINmovwf REG1
1234
51525354
Example ProgramFetch Execute
T0
Flush
T1 T2 T3 T4 T5
Instruction Cycles
T6
Fetch Execute
Fetch Execute
Fetch
Fetch Execute
Fetch Execute
Fetch Flush
Fetch
T7
addwf REG2 returnPre-Fetched Instruction Executing Instruction
00 00 00 00
Long Word Instruction8-bit Program Memory
16-bit Program Memory
11 00 00 00 00 11 11 00
kk kk kk kk kk kk kk kk
11 11 11 00 kk kk kk kk kk kk kk kk
8-bit Instruction on typical 8-bit MCUExample: Freescale ‘Load Accumulator A’:• 2 Program Memory Locations• 2 Instruction Cycles to Execute
16-bit Instruction on PIC18 8-bit MCUExample: ‘Move Literal to Working Register’• 1 Program Memory Location• 1 Instruction Cycle to Execute
Limits Bandwidth Increases Memory
Size Requirements
Separate busses allow different widths 2k x 16 is roughly equivalent to 4k x 8
ldaa #k
movlw k
Register File Concept
Dat
a B
usD
ata
Bus
d
Decoded Instruction from Program
Memory:Arithmetic/Logic
Function to be Performed Result Destination
Address of Second Source Operand
Register File Concept: All of data memory is part of the register file, so any location in data memory may be operated on directly
All peripherals are mapped into data memory as a series of registers
Orthogonal Instruction Set: ALL instructions can operate on ANY data memory location
The Long Word Instruction format allows a directly addressable register file
w f
w fALU
WREGWREG
Data Memory(Register File)
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
OpcodeOpcode dd aa AddressAddress
Byte Oriented OperationsByte Oriented Operations
PIC18 Instruction Set Overview
addwf f,d,aaddwf f,d,a
addwfc f,d,aaddwfc f,d,a
andwf f,d,aandwf f,d,a
clrf f,aclrf f,a
comf f,d,acomf f,d,a
cpfseq f,acpfseq f,a
cpfsgt f,acpfsgt f,a
cpfslt f,acpfslt f,a
decf f,d,adecf f,d,a
decfsz f,d,adecfsz f,d,a
dcfsnz f,d,adcfsnz f,d,a
incf f,d,aincf f,d,a
incfsz f,d,aincfsz f,d,a
infsnz f,d,ainfsnz f,d,a
iorwf f,d,aiorwf f,d,a
movf f,d,amovf f,d,a
movff fs,fdmovff fs,fdmovwf f,amovwf f,a
mulwf f,amulwf f,a
negf f,anegf f,a
rlcf f,d,arlcf f,d,a
rlncf f,d,arlncf f,d,a
rrcf f,d,arrcf f,d,a
rrncf f,d,arrncf f,d,a
setf f,asetf f,a
subfwb f,d,asubfwb f,d,a
subwf f,d,asubwf f,d,a
subwfb f,d,asubwfb f,d,a
swapf f,d,aswapf f,d,a
tstfsz f,atstfsz f,a
xorwf f,d,axorwf f,d,a
Add WREG and fAdd WREG and f
Add WREG and Carry bit to fAdd WREG and Carry bit to f
AND WREG with fAND WREG with f
Clear fClear f
Complement fComplement f
Compare f with WREG, skip =Compare f with WREG, skip =
Compare f with WREG, skip >Compare f with WREG, skip >
Compare f with WREG, skip <Compare f with WREG, skip <
Decrement fDecrement f
Decrement f, Skip if 0Decrement f, Skip if 0
Decrement f, Skip if Not 0Decrement f, Skip if Not 0
Increment fIncrement f
Increment f, Skip if 0Increment f, Skip if 0
Increment f, Skip if Not 0Increment f, Skip if Not 0
Inclusive OR WREG with fInclusive OR WREG with f
Move fMove f
Move fs (src) to fd (dst)Move fs (src) to fd (dst)
Move WREG to fMove WREG to f
Multiply WREG with fMultiply WREG with f
Negate fNegate f
Rotate Left f through CarryRotate Left f through Carry
Rotate Left f (No Carry)Rotate Left f (No Carry)
Rotate Right f through CarryRotate Right f through Carry
Rotate Right f (No Carry)Rotate Right f (No Carry)
Set fSet f
Subtract f from WREG with borrowSubtract f from WREG with borrow
Subtract WREG from fSubtract WREG from f
Subtract WREG from f with borrowSubtract WREG from f with borrow
Swap nibbles in fSwap nibbles in f
Test f, skip if 0Test f, skip if 0
Exclusive OR WREG with fExclusive OR WREG with f
Bit Oriented OperationsBit Oriented Operationsbcf f,b,abcf f,b,a
bsf f,b,absf f,b,a
btfsc f,b,abtfsc f,b,a
btfss f,b,abtfss f,b,a
btg f,b,abtg f,b,a
Bit Clear fBit Clear f
Bit Set fBit Set f
Bit Test f, Skip if ClearBit Test f, Skip if Clear
Bit Test f, Skip if SetBit Test f, Skip if Set
Bit Toggle fBit Toggle f
Literal OperationsLiteral Operations
PIC18 Instruction Set OverviewControl OperationsControl Operations
bc nbc n
bn nbn n
bnc nbnc n
bnn nbnn n
bnov nbnov n
bnz nbnz n
bov nbov n
bra nbra n
bz nbz n
call n,scall n,s
clrwdtclrwdt
dawdaw
goto ngoto n
nopnop
poppop
pushpush
rcall nrcall n
resetreset
retfie sretfie s
return sreturn s
sleepsleep
addlw kaddlw k
andlw kandlw k
iorlw kiorlw k
lfsr f,klfsr f,k
movlb kmovlb k
movlw kmovlw k
mullw kmullw k
retlw kretlw k
sublw ksublw k
Branch if CarryBranch if Carry
Branch if NegativeBranch if Negative
Branch if Not CarryBranch if Not Carry
Branch if Not NegativeBranch if Not Negative
Branch if Not OverflowBranch if Not Overflow
Branch if Not ZeroBranch if Not Zero
Branch if OverflowBranch if Overflow
Branch AlwaysBranch Always
Branch if ZeroBranch if Zero
Call subroutineCall subroutine
Clear Watchdog TimerClear Watchdog Timer
Decimal Adjust WREGDecimal Adjust WREG
Go to addressGo to address
No OperationNo Operation
Pop top of return stack (TOS)Pop top of return stack (TOS)
Push top of return stack (TOS)Push top of return stack (TOS)
Relative CallRelative Call
Software device RESETSoftware device RESET
Return from interruptReturn from interrupt
Return from subroutineReturn from subroutine
Go into standby modeGo into standby mode
Add literal and WREGAdd literal and WREG
AND literal with WREGAND literal with WREG
Inclusive OR literal with WREGInclusive OR literal with WREG
Move 12-bit literal to FSRMove 12-bit literal to FSR
Move literal to BSR<3:0>Move literal to BSR<3:0>
Move literal to WREGMove literal to WREG
Multiply literal with WREGMultiply literal with WREG
Return with literal in WREGReturn with literal in WREG
Subtract WREG from literalSubtract WREG from literal
Data Memory Program Memory OperationsData Memory Program Memory Operationstblrd*tblrd*
tblrd*+tblrd*+
tblrd*-tblrd*-
tblrd+*tblrd+*
tblwt*tblwt*
Table ReadTable Read
Table Read with post-incrementTable Read with post-increment
Table Read with post-decrementTable Read with post-decrement
Table Read with pre-incrementTable Read with pre-increment
Table WriteTable Write
xorlw kxorlw k Exclusive OR literal with WREGExclusive OR literal with WREG
tblwt*+tblwt*+ Table Write with post-incrementTable Write with post-increment
tblwt*-tblwt*- Table Write with post-decrementTable Write with post-decrement
tblwt+*tblwt+* Table Write with pre-incrementTable Write with pre-increment
Instruction Set Overview
f f f f f f fdOpcode
07815
f f f f f f fOpcode
File Register Address
Byte Oriented Operations
ADDWF 0x25, W, A
DestinationFile Register Address
a f
fa
9
Destination (W or F) Access Bank
Use Access Bank(Optional)
OR
Instruction Set Overview
078915
File Register Address
Bit Position (0-7)
BSF 0x25, 3, A
Access Bank(Optional)
File Register Address
11
Bit Position
078915
File Register Address
Bit Position (0-7)
BSF 0x25, 3, A
Access Bank(Optional)
File Register Address
11
Bit Position
Instruction Set Overview
07815
k k k k k k kOpcodeLiteral Value
Literal and Control Operations
MOVLW 0x25
Literal Value
k
OpcodeOR
Instruction Set Overview
0111215
fs fs fs fs fs fs fsfs fsOpcode fs
Source Register Address
Byte to Byte Move Operations (2 Words)
MOVFF 0x125, 0x140
Source Address
fs fs
fd fd fd fd fd fd fdfdfd fd fdfdOpcodeDestination Register Address
Destination Address
Instruction Set Overview
07815
n7 n6 n5 n4 n3 n2 n1Opcode
Call and Goto Operations (2 Words)
CALL 0x1125
Subroutine Address
n8
n9Opcode
11
n10n11n12n13n14n15n16n17n18n19n20
PIC18 Visual InterpreterADDLW 30 Execute
Register File Address
d
FFFFFFW Register
FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
00h01h02h03h04h05h06h07h08h09h0Ah0Bh
w f
w fALU
000 00 000Z DC C
STATUS
DataBus
Reset
HexDecBin
Literal Data from Instruction Word
,,
012
PIC18 Addressing Modes
Data Memory Access:
clrf <reg>, <dst>
clrf INDFn, <dst>
movff PLUSWn, <dst>
movlw <const>
movff PREINCn, <dst>
movff POSTINCn, <dst>
movff POSTDECn, <dst>
clrf <reg>, <dst>
clrf INDFn, <dst>
movff PLUSWn, <dst>
movlw <const>
movff PREINCn, <dst>
movff POSTINCn, <dst>
movff POSTDECn, <dst>
Access RAMAccess RAM
Data Memory OrganizationPIC16F8F2520/4520Register File Map
000h07Fh
256 Bytes
Bank 0 GPRBank 0 GPR
Bank 1GPR
Bank 1GPR
Bank 2GPR
Bank 2GPR
Bank 13GPR
Bank 13GPR
Bank 14GPR
Bank 14GPR
Bank 15 GPRBank 15 GPR
Access SFRAccess SFR
Access RAMAccess RAM
Access SFRAccess SFR
080h0FFh100h
1FFh
200h
2FFh
D00h
DFFh
E00h
EFFh
F00h
FFFh
F7FhF80h
00h7Fh80hFFh
Access Bank
Data Memory up to 4k bytes
Divided into 256 byte banks
Half of bank 0 and half of bank 15 form a virtual bank that is accessible no matter which bank is selected
11 000 000 000 000 000 000 000
Register Direct Addressing4-bits from BSR Register 8-bits Encoded in Instruction
BSR ‘f’ Operand
000000 000 000 000 0xEFE0xEFE0xEFE
12-bit Effective Address(Use this when coding)
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
00
Bank0
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
010203
7D7E7F808182
FCFDFEFF
Bank1 Bank2
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
Bank13 Bank14 Bank15
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
‘a’ Bit fromInstruction
Access RAMAccess RAM
Bank 0Bank 0
Bank 1Bank 1
Bank 2Bank 2
Bank 15Bank 15
Register Direct Addressing: Example
FF
FFFFFFFFFF
Access SFR
MyReg
PORTB
WREG
TRISB
BSR
LATB
120h
F81h
F8Ah
F93h
FE0h
FE8h
000 000 000 000 000 000 0004-bits from BSR Register 8-bits Encoded in Instruction
BSR ‘f’ Operand
000000 000 000 000 000000000
Effective Address
==
movlwmovlw 0xAA0xAA
movlwmovlw bb’’1111000011110000’’movwfmovwf TRISB, aTRISB, absfbsf PORTB, 0, aPORTB, 0, amovlbmovlb 0x010x01
movwfmovwf MyRegMyReg ; @120h; @120h
MyRegMyReg equequ 0x1200x120
000 000 000
Register Indirect Addressing
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
000h001h002h002h003h004h005h
FFAhFFBhFFChFFDhFFEhFFFh
0xFFD0xFFD0xFFD8-bits from FSR0L 12-bit Effective Address
Data Memory
FSR0L
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
Register File Address Bus
4-bits from FSR0H
000 000 000 000 000 000 000 000 000FSR0H
No banking – RAM is fully linear when using indirect addressing
FSRH:FSRL can be loaded with a single instruction: lfsr
Full 12-bit increment / decrement of pointer possible with pre- or post-modification modes
Three FSR register pairs available: FSR0, 1 & 2
Register Indirect Addressing
Several additional indirect addressing modes have been added to the PIC18: Indirect - no change in FSRn
Auto Post-decrement FSRn (FSRn--)
Auto Post-increment FSRn (FSRn++)
Auto Pre-increment FSRn (++FSRn)
Index Indirect (Address = FSRn + W)
Register Indirect Addressing
These modes are invoked by using special non-physical registers: Indirect - no change: INDFn
Auto Post-decrement: POSTDECn
Auto Post-increment: POSTINCn
Auto Pre-increment: PREINCn
Index Indirect / Offset: PLUSWn
FFFFFFFFFFFFFFFFFFFFFFFF
FFFFFFFFFFFFFFFFFFFFFFFF
000000000000
PLUSW0PLUSW0PLUSW0PREINC0PREINC0PREINC0
POSTDEC0POSTDEC0POSTDEC0POSTINC0POSTINC0POSTINC0
Register Indirect Addressing: Example 1
Register FileExample: Clear all RAM locations from 120h to 17Fh
INDF0INDF0INDF0 FEFh
FEEh
FEDh
FECh
FEBh
FEAh
FE9hFSR0HFSR0L
11Fh
120h
121h
122h
180h
17Fh
17Eh
17Dh
000 000 000FSR0L
000 000 000 000 000 000 000 000 000FSR0H
LOOPlfsr 0,0x120clrf POSTINC0btfss FSR0L,7goto LOOP<next instruction>
000000000FSR0 Decimal Value:
FFFFFF000000010101000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
000000000000
PLUSW0PLUSW0PLUSW0PREINC0PREINC0PREINC0
POSTDEC0POSTDEC0POSTDEC0POSTINC0POSTINC0POSTINC0
Register Indirect Addressing: Example 2
Register File
lfsr 0,0x128clrf INDF0bsf POSTDEC0,0clrf POSTINC0clrf PREINC0
Example: “Spaghetti” Addressing (Don’t try this at home!)
INDF0INDF0INDF0 FEFh
FEEh
FEDh
FECh
FEBh
FEAh
FE9hFSR0HFSR0L
126h
127h
128h
129h
12Eh
12Ch
12Bh
12Ah
movlw 0x02clrf PLUSW0
000 000 000FSR0L
000 000 000 000 000 000 000 000 000FSR0H
12Dh
129129129FSR0 Decimal Value:
PIC18 Addressing Modes
Program Memory Access:
goto <addr>
bra <addr>
tblrd* tblwt*
tblrd*+ tblwt*+
tblrd*- tblwt*-
tblrd+* tblwt+*
goto <addr>
bra <addr>
tblrd* tblwt*
tblrd*+ tblwt*+
tblrd*- tblwt*-
tblrd+* tblwt+*
Program Memory Organization
On-chip Program MemoryOn-chip Program Memory
Reset Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector
000000h
000008h
000018h
1FFFFEh
UnimplementedProgram Memory
(Read as ‘0’)
UnimplementedProgram Memory
(Read as ‘0’)
008000h
007FFEh
21-bit Program Counter
31 Level Stack
Stack Level 1Stack Level 1
Stack Level 2Stack Level 2
Stack Level 30Stack Level 30
Stack Level 31Stack Level 31
One, contiguous linear program memory space up to 2MB (1MWord)
Program Memory is Byte Addressable
Low byte has even address, high byte has odd address
Addresses of instructions are always even
16-bit Program Memory
0x000000
0x000002
0x000004
0x000006
0x000008
0x00000A
0x00000C
0x00000E
0x000001
0x000003
0x000005
0x000007
0x000009
0x00000B
0x00000D
0x00000F
High Byte Address Low Byte AddressWord Address
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Program Counter0123456789101112
PCLPCH
Program Counter
21-bit PC can access up to 221 = 2MB (1MWord) 22nd bit used to access configuration memory at
program time or via table reads & writes Contains address of NEXT instruction (pipelining) Lower byte accessible in data memory as PCL Upper bytes indirectly accessible via PCLATH/PCLATU Bit 0 of PC is always ‘0’ except when reading or writing
program memory via table read/write mechanism
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00131415161718192021
PCU
PC Absolute AddressingCALL and GOTO Instructions:
PC Absolute Addressing (Program Memory) Jump to another program memory location out of PC sequence Call a subroutine
Used by the CALL and GOTO instructions Full address is specified as part of the two word instruction
Used when performing Computed Goto operation Address to jump to is calculated by the program Computed address is written directly into the Program Counter
n8nn88 nnn nnn nnn nnn nnn nnn n1nn11
111 111 111 111 n20nn2020 nnn nnn nnn nnn nnn nnn nnn nnn nnn nnn n9nn99
n0
00112233445566778899101011111212131314141515
Bit 0 of the address is implied since it is always zero due to the byte addressability of program memory
n = Program Memory Address
PC Relative Addressing: Branch Instructions
Used by single word branch instructions: BC / BNC: -128 n 127 BN / BNN: -128 n 127 BOV / BNOV: -128 n 127 BZ / BNZ: -128 n 127 BRA: -1024 n 1023 RCALL: -1024 n 1023
n is the relative offset from the PC
Example: BC CarryBitSet
121212WREG
movlw UPPER 0x011250movwf PCLATUmovlw HIGH 0x011250movwf PCLATHmovff PC_OFFSET, PCL
PC Relative Addressing
PCLATU
To write to PC:Write upper byte to PCLATUWrite high byte to PCLATHWrite low byte to PCL
Used to perform a computed GOTO by directly modifying the program counter
22PC_OFFSET =
8-bit Data Bus
PCLATH
121212010101PCU PCH PCL
222222FFFFFFFFFFFF
PC Relative Addressing: Computed GOTO
JTS movlw UPPER JUMP_TABLE
movwf PCLATU
movlw HIGH JUMP_TABLE
movwf PCLATH
movlw 0x04
mulwf USER_INPUT
movf PRODL, w
addwf PCL, f
JUMP_TABLE goto DoUserInput0
goto DoUserInput1
goto DoUserInput2
goto DoUserInput3
goto DoUserInput4
org 0x002180
FFFF FFFF 9898
0000 2121
PCU PCH PCL
PCLATU PCLATH
Computed GOTO used to index into a jump table
0808WREGUSER_INPUT
2
Compute actual offset into table.Each goto in table occupies 4 bytes: 2 bytes per word, 2 words per goto.
@ 0x002190
0000
00000000
PIC18 Return Address Stack
0000000000
20
Program Counter
01
02
03
04
05
06
07
08
09
30
31
STKPTR RegisterTOSLTOSHTOSU
04567023
STKOVF STKUNF SP4:SP0Top of Stack Registers
Stack LevelStack
PUSH
POP
CALL
RETURN
RCALL Interrupt
RETLW RETFIE
Events that push PC+2 onto the stack:
Events that pop the top of the stack:
0 0--00PCU:PCH:PCL
Stop PC
Table Reads/Writes Allows access to two bytes of data per program
memory location
Table Read / Write Addressing Modes: No Change tblrd * tblwt *
Post Increment tblrd *+ tblwt *+
Post Decrement tblrd *- tblwt *-
Pre Increment tblrd +* tblwt +*
Accessing program memory is conceptually like register indirect addressing (data memory)
Table Reads/WritesRegister Indirect Addressing(Retrieves data from RAM)
Table Indirect Addressing(Retrieves data from Flash)
Pointer Registers
FSR0H : FSR0L (12-bits)
FSR1H : FSR1L (12-bits)
FSR2H : FSR2L (12-bits)
TBLPTRU : TBLPTRH : TBLPTRL(22-bits)
ExampleRead Data to WREGNo Pointer Modification
tblrd*movf TABLAT, w
movf INDF0, w
movf INDF1, w
movf INDF2, w
ExampleRead Data to WREGPost-Increment Pointer
tblrd*+movf TABLAT, w
movf POSTINC0, w
movf POSTINC1, w
movf POSTINC2, w
ExampleRead Data to WREGPost-Decrement Pointer
tblrd*-movf TABLAT, w
movf POSTDEC0, w
movf POSTDEC1, w
movf POSTDEC2, w
ExamplePre-Increment PointerRead Data to WREG
tblrd+*movf TABLAT, w
movf PREINC0, w
movf PREINC1, w
movf PREINC2, w
Table 1-1: Comparison between Register Indirect Addressing and Table Read Operations
Table Reads PIC18F Program Memory is Divided Into:
User Memory Up to 128kB Internal Up to 2MB External
User IDs 8 Modifiable Bytes
Configuration Memory Device Settings, Code Protects,
etc. Device IDs
Part and Revision Signature
Program Counter can only access User Memory (PC is 21-bits wide)
Table Pointer can access all memory (TBLPTR is 22-bits wide)
User FlashUser Flash
User IDsUser IDs
ConfigurationConfiguration
Device IDsDevice IDs
0x000000
0x01FFFF
0x200000
0x200007
0x300000
0x30000D
0x3FFFFE
0x3FFFFF
Program Memory Space
Unimplemented Memory
Unimplemented Memory
Unimplemented Memory
2C2C
Table Read Operation
2C2CTABLAT
Data Memory (RAM) Program Memory (Flash)
0x000000
0x000002
0x000004
0x00000A
0x000008
0x000006
0x1FFFF4
0x1FFFF6
0x1FFFF8
0x1FFFFA
0x1FFFFC
0x1FFFFE
0x000001
0x000003
0x000005
0x00000B
0x000009
0x000007
0x1FFFF5
0x1FFFF7
0x1FFFF9
0x1FFFFB
0x1FFFFD
0x1FFFFF
0x000
0x001
0x002
0x005
0x004
0x003
0xFFA
0xFFB
0xFFC
0xFFD
0xFFE
0xFFF
8-bit Data
0000 0000 0909TBLPTRU TBLPTRH TBLPTRL
High Byte(Odd Addr)
Low Byte(Even Addr)
22-bit Address
Table Read Example Sending Characters to LCD
‘M’ @ 7000h
How ASCII string tables are stored in program memory:
‘i’ @ 7001h
Table Read Examplemovlw LOW MyStringtablemovwf TBLPTRLmovlw HIGH MyStringtablemovwf TBLPTRHmovlw UPPER MyStringtablemovwf TBLPTRU
TableReadLooptblrd*+movf TABLAT,wbtfsc STATUS,Zbra EndLoopcall LCDPutChargoto TableReadLoop
EndLoop…org 0x7000
MyStringTableDW “Microchip\0”
M i c r
0000 7070 0505TBLPTR
6F6FTABLAT
6F6FWREG
6969 4D4D7272 63636363 6F6F6969 68680000 7070
70007002700470067008
70017003700570077009
Program Memory