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POLITECNICO DI MILANO
Master of Science in Electronics Engineering
Department of Electronics, Information and Bioengineering
Design of a power solution for multi-channels SPAD array
detector
Supervisor:
Prof. Ivan Rech
Assistant Supervisor:
Labanca Ivan Giuseppe
Master Graduation Thesis by: Jinghui Liu
Student Id number: 813374
Academic Year: 2017/2018
I
Abstract
In this thesis, we present the design of a power solution for 36-channels SPAD array
detector used in a medical application. In this application, we use SPAD array to
convert radiation rays to electronic signals and through readout circuits, we obtain
information.
The complete system is mainly constituted by the detection head, a power board and
a cooling board. The aim of this thesis is to provide relevant power supplies: one for
polarization power, one for DAC, one for thermoelectric cooler, three for AQC (i.e.
active quenching circuit) from an input source 12V, 5A. We will explain how to choose
the topology and the component value to meet our requirements. Then we will do
some simulations to verify our circuits. In the final chapters, we also take an example
of some circuits to realize a test board and proceed the real measurements.
II
Sommario
In questa tesi, illustriamo la progettazione di una soluzione di alimentazione per un
rivelatore di array SPAD a 36 canali utilizzato in contesto medicale. In questo specifico
contesto, utilizziamo la matrice SPAD per convertire i raggi di radiazione in segnali
elettronici e attraverso i circuiti di lettura, otteniamo informazioni.
Il sistema completo è costituito principalmente dalla testa di rilevamento, da una
scheda di potenza e da una scheda di raffreddamento. Lo scopo di questa tesi è quello
di fornire rilevanti fonti di alimentazione: una per la potenza di polarizzazione, una per
il DAC, una per il refrigeratore termoelettrico, tre per l'AQC (cioè il circuito di
spegnimento attivo) da una sorgente di ingresso 12V, 5A. Andremo a illustrare come
scegliere la topologia e il valore del componente per soddisfare i nostri requisiti. Inoltre,
faremo delle simulazioni per verificare i nostri circuiti. Nei capitoli finali, prendiamo un
esempio di alcuni circuiti per realizzare una scheda di test e procedere con le
misurazioni reali.
III
Contents
Abstract ........................................................................................................................... I
Sommario ....................................................................................................................... II
List of Figures ............................................................................................................... IIV
List of Tables .................................................................................................................. VI
Introduction ................................................................................................................... 1
1. Single-Photon Avalanche Diode .......................................................................... 2
1.1. Principle of operation ..................................................................................... 2
1.2. Device structure .............................................................................................. 4
1.3. Quenching circuits .......................................................................................... 5
1.3.1. Passive quenching circuit …………………………………………………………………5
1.3.2. Active quenching circuit ………………………………………………………………….8
1.3.3. Mixed Active-Passive Quenching Circuit …………………………………………..9
2. A brief description of system…………………..……………………………………………………….11
2.1. Conceptual structure…………………………………………………………………………………11
2.2. AQC requirements…….…………………………………………………………………………..….11
2.3. other requirements…………………………………………………………………………………..16
3. Power board solution ....................................................................................... 17
3.1. The polarization power ................................................................................. 17
3.1.1. 20-50V output ..………..…………….……………………….………………………….…17
3.1.2. 20-100V output ……………………………..………….…………………………………..23
3.2. The AQC quench power ................................................................................ 24
3.2.1. SEPIC converters .…………………………………………………………………………….24
3.2.2. vddH schematic design .………………………………………………………….……….26
3.2.3 Simulation results …………………………………………………………………………….28
3.3. The AQC gndH power .................................................................................... 30
3.3.1. LT8303 …………………………………………………………………………………………….31
3.3.2. LT1964 ….…………………………………………………………………………………………33
3.3.3. Simulation results ……………………………………………………………………………33
3.4. The intermediate voltage .............................................................................. 34
3.5. The AQC vdd power ...................................................................................... 36
3.6. The DAC power…………………………………………….……………………………………….….36
3.7. The Peltier driving power …………………………………………………………………….……37
3.7.1. TEC and Peltier. .………………………………………………………………………..……37
3.7.2. Vpeltier schematic design………………………………………………………………….37
4. Design of testboard .......................................................................................... 40
4.1. Redraw schematics ..................................................................................... 40
4.2. Display of layout design ................................................................................ 42
4.3. Measuring results.......................................................................................... 43
5. Conclusion and future Developments ............................................................... 45
Bibliography ................................................................................................................. 46
IV
List of Figures
Figure 1.1 Photon absorption and avalanche triggering through impact ionization
into SPAD active area ...................................................................................... 3
Figure 1.2 SPAD I-V characteristic .......................................................................... 3
Figure 1.3 Schematic cross-section of a custom SPAD ............................................. 5
Figure 1.4 Schematic view of a Passive Quenching Circuit (PQC) ............................. 6
Figure 1.5 Schematic view of a PQC including SPAD equivalent model along with
temporal behavior of cathode voltage signal and SPAD current ....................... 7
Figure 1.6 Schematic view of an Active Quenching Circuit (AQC) and corresponding
typical cathode voltage and detector current signals ....................................... 9
Figure 1.7 Schematic view of a mixed Active-Passive Quenching Circuit and
corresponding typical cathode voltage and detector current signals………………10
Figure 2.1 Block schematic of the system ……………………………………………………………11
Figure 3.1 Schematic of polarization 20-50V .………………………………………………………17
Figure 3.2 LT3958 Block Diagram Working as a SEPIC Converter ………………………….20
Figure 3.3 Schematic with loop compensation starting from application circuit:
RC=10KΩ, CC1=10nF, CC2=100pF ………………………………………………………………….…20
Figure 3.4 Simulation output result of circuit with loop compensation starting from
application circuit: RC=10KΩ, CC1=10nF, CC2=100pF ……………………………………….21
Figure 3.5 Simulation output result of circuit with loop compensation: RC=50KΩ,
CC1=250pF, CC2=10pF ……………………………………………………………………………………21
Figure 3.6 Simulation output result of circuit with loop compensation: RC=50KΩ,
CC1=250pF, CC2=10pF ……………………………………………………………………………..…….22
Figure 3.7 Load regulation waveform (1) for the lower output ……………………………..22
Figure 3.8 Load regulation waveform (2) for the lower output …………………………….23
Figure 3.9 Load regulation waveform (1) for the higher output …………………………….23
Figure 3.10 Load regulation waveform (2) for the higher output ……………………….…23
Figure 3.11 Schematic of polarization 20-100V………………………………………………..……24
Figure 3.12 SEPIC schematic …………………………………………………………………………………25
Figure 3.13 With S1 closed current increases through L1 (green) and C1 discharges
increasing current in L2 (red) …………………………………………………………………….25
Figure 3.14 With S1 open current through L1 (green) and current through L2 (red)
produce current through the load ……………………………………………………………..26
Figure 3.15 Schematic of converter topology for vddH (SEPIC with coupled inductors)
……………………………………………………………………………………………………………..…………….26
Figure 3.16 Simulation of higher output for vddH ………………………………………………..28
Figure 3.17 Simulation of lower output for vddH ………………………………………………...29
Figure 3.18 Schematic for vddH with C2=50pF ……………………………………………………..29
Figure 3.19 Simulation output result for vddH with C2=50pF ……………………………….29
Figure 3.20 Simulation output result for vddH with C2=100pF ………………………………30
Figure 3.21 Schematic of gndH power ………………………………………………………………….30
Figure 3.22 Snubber Circuits …………………………………………………………………………….….32
V
Figure 3.23 Maximum Voltages for SW Pin Flyback Waveform ………………………………33
Figure 3.24 Simulation output result for gndH ………………………………………….………….33
Figure 3.25 Block of buck and the downstream parts ……………………….……………..…..34
Figure 3.26 Schematic of the intermediate voltage 3.6V ……………………………………….34
Figure 3.27 Table of Stability vs Effective LC Corner Frequency ………………………………35
Figure 3.28 Simulation output result for the intermediate voltage ……………………….36
Figure 3.29 Schematic of vdd power …………………………………………………………………….36
Figure 3.30 Schematic of VDAC power ……………………………………………………………………37
Figure 3.31 Schematic of Vpeltier …….……………………………………………………………………..38
Figure 3.32 Simulation output result for Vpeltier …….………………………………………………38
Figure 3.33 Load regulation waveform (1) for Vpeltier ………………………………………….…38
Figure 3.34 Load regulation waveform (2) for Vpeltier ………………………………………….…39
Figure 4.1 Schematic of transformer windings ……………………………………………………..40
Figure 4.2 Multiple windings current and inductance ……………………..……………………41
Figure 4.3 Schematic of Vpol(20-100V) test board ………………………………………………….41
Figure 4.4 Schematic of BUCK 3.6V test board ………………………………………………………41
Figure 4.5 Layout design of buck+flyback ………………………………………………….…………42
Figure 4.6 Test board of BUCK 3.6V …………………………………………………………….…….…43
Figure 4.7 Test board of flyback 20-100V ………………………………………………….………….43
VI
List of Tables
Table 1 Simulation conditions to obtain power requirements ………………………….....12
Table 2 Static contribution for vdd ………………….……………………………………………….....12
Table 3 Dynamic contribution for vddH-gndH and vdd ………………………………………...12
Table 4 Dynamic contribution per AQC when different ctQ is employed for
vddH …………………………………………….………………………….…………………………………………12
Table 5 Power consumption and current output for vddH-gndH ...…………………….….13
Table 6 Power consumption and current output for vdd ……………………………………....14
Table 7 Power consumption for vddH at 100MHz ………………………………………………….14
Table 8 Power consumption for vddH at 31MHz ……………………………………………………14
Table 9 Power consumption for vddH at 18MHz ……………………………………………………15
Table 10 Current output for vddH at 100MHz ………………………………………………….…..15
Table 11 Current output for vddH at 31MHz ………………………………………………………….15
Table 12 Current output for vddH at 18MHz ………………………………………………………….16
Table 13 Timing Resistor (RT )Value ………………………………………………………………….….18
Table 14 Measurement results of the test board ….……………………………………………….44
1
Introduction
The structure of the thesis is outlined here:
• Chapter 1 – Introduce the concept of Single-Photon Avalanche Diode (SPAD) and to
give the reader the basic information needed in order to understand the work
described in this dissertation.
• Chapter 2 – Present a conceptual description of the system and list all the needed
power supplies, then to introduce the power requirements.
• Chapter 3 – The schematic design of every power supply, including the selection of
topology, how to define the value of every component and simulation results.
• Chapter 4 – Layout design and realization of a test board, measurement of the test
board.
• Chapter 5 – Conclusion
2
1. SPAD
The purpose of this chapter is to introduce the concept of Single-Photon Avalanche
Diode (SPAD) and to give the reader the basic information needed in order to
understand the work described in this dissertation. Therefore, only a brief outline of
the principle of operation of the device will be given along with an introduction about
its main features.
1.1. Principle of operation
A SPAD is essentially based on a pn junction that is reversed biased above the
breakdown voltage. If a photon is absorbed into the space-charge region, an electron-
hole pair is generated. Due to the high value of the electric field, the carriers are
accelerated until they acquire an energy high enough to produce other pairs by impact
ionization (Figure 1.1). Since the applied voltage is greater than the breakdown by a
given amount called over- or excess-voltage (Figure 1.2, (1)), a self-sustained avalanche
is triggered, resulting in the generation of a macroscopic current, in the milliamperes
range (Figure 1.2, (2)). Therefore, the arrival of a single photon can be easily detected.
Once the self-sustained avalanche has been triggered, the detector is completely blind,
consequently the absorption of another photon does not change its state anymore.
The current keeps flowing until the avalanche is quenched by lowing the bias voltage
below the breakdown level (Figure 1.2, (3)). In order to detect subsequent photons,
the SPAD must be reset back to quiescent condition (Figure 1.2, (1)). To this aim,
suitable quenching circuits must be coupled to the device in order to obtain a proper
operation.
Each time a photon is absorbed into the device, a macroscopic pulse is generated; by
counting the number of pulses, it is possible to obtain the number of incident photons,
proportional to the intensity of incident radiation. Note that this digital approach
completely eliminated the contribution of the noise introduced by the electronics.
Thanks to these features, the SPAD detector is exploited in various photon counting
applications such as: Fluorescence Correlation Spectroscopy (FCS), Single Molecule
detection and ratio metric FÖrster Resonance Energy Transfer (FRET).
Moreover, the leading edge of the avalanche current marks the photon arrival time
very precisely, with a resolution of tens of picoseconds, which can be exploited to
reconstruct the shape of optical signals, using the TCSPC techniques.
3
Figure 1.1 Photon absorption and avalanche triggering through impact ionization
into SPAD active area
Figure 1.2 SPAD I-V characteristic: (1) the detector is biased at VBD + VOV, (2) photon
absorption or thermal generation causes avalanche triggering with a macroscopic
current flowing into the device, (3) avalanche is quenched by lowing its voltage
drop under breakdown condition, finally initial bias conditions are restored (1)
4
1.2. Device structure
Figure 1.3 shows the structure of the devices that will be considered in this work. The
device has been designed and simulated at Politecnico di Milano and fabricated at the
facility of CNR-IMM in Bologna.
The first thing to observe is that the active region of the device is constituted by an
asymmetrical junction of type n++- p. Thanks to this approach, the depleted zone
extends almost exclusively into the p region, where the most significant part of
photons will be absorbed. Since in a depleted region, the holes move towards the p
contact, while the electrons towards the n one, the avalanche will be triggered
predominantly by the electrons crossing the high field region near the metallurgical
junction (n++- shallow/p+- enrichment). This is preferable, since in silicon the avalanche
triggering efficiency is higher for electrons.
If no suitable precautions are adopted, the avalanche would occur at the edge of the
n++- shallow region, inherently characterized by a lower breakdown voltage due to the
higher field induced by curvature effect. For this reason, in many traditional
photodiodes and in the older SPAD structures, a n- guard ring was realized all around
the device in order to increase the value of the edge breakdown. An alternative
approach adopted here, is to lower the breakdown in the center of the device, instead
of lowering its value at the edge. This can be accomplished simply by realizing a region
called enrichment under the n+ cathode, with a higher level of dopant. Therefore, in
our device, the enrichment defines the active area.
The junction described, could be in principle obtained simply by fabricating the n++
region along with the enrichment, on a p_ substrate. However, it has been
demonstrated that it is useful to also have a buried n-p junction as displayed in Figure
1.3. In this way, carriers absorbed into the n substrate cannot reach the active junction
and therefore cannot trigger an avalanche. Although the Photon Detection Efficiency
(PDE) is slightly diminished, this solution constituted a great advantage for the time
resolution; carriers absorbed into neutral regions move randomly due to thermal
agitation and therefore can reach the depleted region with a large delay, thus
introducing unwanted slow components in the device temporal response.
The buried junction is fabricated starting from an n+ substrate and then growing a p-
type epitaxial layer on top of it. This approach is beneficial also because epitaxial layers
have a greater quality if compared to bulk silicon and proved to be very useful to
improve the device noise performance. In the structure depicted in Figure 1.3, the
epitaxial layer is doubled, in the sense that it is constituted by a lower p+ layer on which
a p- layer is grown. While the latter is used to accommodate the depletion layer of the
5
device, the former reduces the resistance encountered by current flowing towards
contacts. For the same reason, p++ diffusions, the so-called sinkers, are introduced
under the anode contacts.
At the periphery of the device, n++ regions are added. In this way, the entire p-type
region, where the SPAD is formed, is isolated from the remaining part of the chip by
means of a p-n junction. This solution allows to fabricate, on the same chip, multiple
SPADs with isolated anodes and cathodes.
Figure 1.3 Schematic cross-section of a custom SPAD
1.3. Quenching circuits
In order to be properly operated, SPAD detectors need to be connected to a quenching
circuit in order to quench the avalanche and reset the detector back to initial bias
conditions. These circuits can be divided into three categories: passive, active and
mixed.
1.3.1. Passive quenching circuit
A Passive Quenching Circuit (PQC) is obtained simply by connecting a large resistor in
series with the device.
The temporal behavior of the circuit can be explained following Figure 1.4, which
displays the characteristics curves of the SPAD detector and of the resistive load. The
detector is initially biased above breakdown voltage (1); when the first hole-electron
pair is generated by photon absorption or by thermal generation, avalanche
multiplication occurs and current reaches its peak value before the voltage drop across
the detector can change (2); at this point current begins to flow through the load
6
resistor until a new bias condition given by the intersection of the two I-V
Figure 1.4 Schematic view of a Passive Quenching Circuit (PQC), on the left, and
intersection between load resistance and SPAD characteristics, on the right
characteristics is reached (3); if the final current is in the order of 50-100 uA, the
number of carriers that travels into the high field region is low enough to ensure a
significant probability that all fail to generate a pair and the avalanche quenches.
A more detailed explanation can be given by substituting the SPAD detector with its
equivalent model, as shown in Figure 1.5. The detector can be modeled by a depletion
capacitance CD, given by the p-n junction between cathode (n++ shallow) and anode
(p+ enrichment and p-epi) in parallel with the series of SPAD resistance RSPAD, a voltage
generated Vbd and a switch. CK accounts for external parasitic contributions.
In steady state condition, the switch is open and no current flows into the circuit. The
voltage drop across the SPAD is equal to VREV given by the sum of excess (VOV) and
breakdown (VBD) voltage. Avalanche triggering corresponds to the closing of the switch
of the diode equivalent circuit. In a few picoseconds, the current reaches the peak
value, while the SPAD voltage is kept to VREV by CD and CK. Then the high current flowing
through the diode discharges the capacitors, while ISPAD and VK decrease exponentially
to the steady-state condition. After the triggering event, the current flowing into the
photodiode as a function of time can be written as:
ISPAD (t) = VK (t)−VBD
𝑅𝑆𝑃𝐴𝐷 =
VOV (t)
𝑅𝑆𝑃𝐴𝐷 (1.1)
where VOV(t) is the residual over-voltage as a function of time. Consequently, the
current peak is about equal to:
ISPAD,max = VOV
𝑅𝑆𝑃𝐴𝐷 (1.2)
At the end of the quench operation, when capacitances are completely discharged,
the voltage across the SPAD is:
7
VK = VBD + VOV∗𝑅𝑆𝑃𝐴𝐷
𝑅𝑆𝑃𝐴𝐷+𝑅𝐿 ≈VBD (1.3)
since RL is significantly larger than RSPAD (few hundreds of ohms). By substituting eq.
1.3 in eq. 1.1, it is possible to obtain the final value reached by the SPAD current:
ISPAD,off = VOV
𝑅𝑆𝑃𝐴𝐷+𝑅𝐿 ≈
VOV
𝑅𝐿 (1.4)
to accomplish avalanche quenching, this value should be less than 100 uA; for instance
with VOV = 5V, RL must be greater than 50kΩ.
The time constant regulating quenching operation is:
τq= RSPAD *(CK+CD) (1.5)
with CD on the order of 0.5pF and CK 2-3pF, resulting in τq of about 1ns.
Once the avalanche is quenched, the switch of the equivalent model is opened, and
cathode voltage returns to the initial condition with a time constant given by:
τreset= RL *(CK+CD) (1.6)
on the order of 200ns.
The first limit affecting PQC is given by the large reset time constant, resulting in an
overall recovery time equal to 5τ≈1us, which also sets a limit to the maximum
counting rate achievable by the system (lower than 1MHz).
In addition, photons absorbed during reset phase can retrigger an avalanche. More
specifically, a photon that arrives during the first part of the recovery is almost
certainly lost, since the avalanche triggering probability of triggering an avalanche.
However, if a photon fires the avalanche at a voltage lower than VREV, and consequently
at a lower over-voltage level, the SPAD operates with lower photon detection efficiency,
worse photon-timing resolution, and produced voltage and current pulse that have
smaller amplitudes. This is the so called small pulses phenomena whose effects are
also shown in Figure 1.5.
Figure 1.5 Schematic view of a Passive Quenching Circuit (PQC) including SPAD
equivalent model along with temporal behavior of cathode voltage signal and SPAD
current; the phenomena of small pulses during reset is also shown
8
The main drawback is a dead-time that is not well defined, since every time a photon
is absorbed during recovery, the quench and reset phases are started again and their
new duration depends on retriggering bias condition. Moreover, time resolution is
severely degraded by small-amplitude pulses. First of all, intrinsic time resolution of
the SPAD is impaired when diode voltage is reduced, since timing performance are
inherently field – and consequently bias – dependent. Secondly, an additional jitter is
introduced because, if avalanche signal is read through a proper voltage comparator,
pulses with different amplitudes cross a fixed threshold at different times. Constant-
fraction trigger circuits can be employed, but they are only partially effective since the
output current pulse does not only have variable amplitude but also variable shape.
As a result, the real maximum count rate is significantly lower than the theoretical
value defined by the inverse of 5 τreset.
1.3.2. Active quenching circuit
In order to avoid the drawbacks of PQC highlighted previously and fully exploit the
intrinsic performance of SPADs, a new approach was devised by prof. Sergio Cova at
Politecnico di Milano. The basic idea was to sense the rise of the avalanche pulse and
react back on the SPAD, by forcing the quenching and reset transitions over very short
times, on the order of few nanoseconds, with a controlled bias-voltage source. This
approach was named Active Quenching Circuit (AQC) and soon became widely
adopted in the scientific literature.
As shown in Figure 1.6, when the SPAD is quiescent and no current is flowing, its
cathode is biased to ground level by the AQC, using the low-impedance driver. The fast
onset of the avalanche current is sensed by a fast comparator, which triggers the
monostable circuit and drives the output stage. The latter provides a standard output
pulse synchronous with avalanche triggering. The monostable controls the driver,
which lowers the SPAD bias voltage by applying a quenching pulse equal to Vquench. In
order to quench the avalanche, Vquench must be high enough to reduce the diode
voltage below VBD. The detector is then kept switched off for a well-controlled time,
the so-called hold-off time (Thold-off). At the end of Thold-off, the driver swiftly restores
the diode bias voltage to the operating level and the SPAD is ready to detect another
ignition.
9
Figure 1.6 Schematic view of an Active Quenching Circuit (AQC) and corresponding
typical cathode voltage and detector current signals
This solution presents several advantages. First of all, the reset transition is very fast
and consequently the probability of avalanche triggering during the recovery phase is
minimized. As a result, dead-time is reduced and well defined by hold-off duration,
and the maximum allowed count rate is consequently increased. Moreover, avalanche
current amplitude is kept constant since bias condition are always the same, thus not
impairing SPAD performance, in particular guaranteeing that detector timing jitter is
preserved.
The main drawback of this structure is related to the fact that the sensing comparator
requires a certain amount of time to detect and quench the avalanche. During this
time interval, a large, almost constant current (VOV/RSPAD) flows into the detector, since
there is no large impedance, as for example in the case of PQC (Figure 1.5), to limit it.
This causes a significantly increase in afterpulsing probability and requires a
consequent increase of Thold-off, with a reduction of the maximum count rate, in order
to assure traps depopulation.
1.3.3. Mixed Active-Passive quenching circuit
To solve the previously described issue affecting AQC, another approach was studied
in our laboratories, relying on a mixed Active-Passive Quenching structure in order to
combine the positive aspects of both circuits.
A passive load RL is added on the cathode side (Figure 1.7), providing a prompt passive
quasi-quenching of the avalanche current; then an active loop completes the task by
forcing the SPAD voltage well below the nominal VBD, with sufficient margin to ensure
the final quenching. After a controlled hold-off time, the active loop applies a fast reset
transition.
10
Figure 1.7 Schematic view of a mixed Active-Passive Quenching Circuit and
corresponding typical cathode voltage and detector current signals
By minimizing the pulse charge, trapping and power dissipation are educed. Optical
crosstalk is also limited since, by minimizing avalanche current, the hot-carrier photo-
emission probability is reduced. Furthermore, this mixed approach gives flexibility in
the choice of the passive load, since passive quasi-quenching action is anyhow
followed by the active quenching. Therefore, the load resistor RL can be smaller than
the minimum required for a complete passive quenching. More specifically, a good
trade-off is necessary in the choice of RL since the larger its value, the lower the current
value reached by ISPAD, but also the larger the time constant that regulates this
transition (equation 1.5). In addition, to detect the avalanche, the cathode voltage,
which evolves with the same time constant, should cross the comparator threshold;
consequently RL also defines the total passive quenching duration. The final objective
is to minimize the integral of avalanche current in order to limit the afterpulsing
probability as much as possible.
Finally, mixed active-passive architecture guarantees low avalanche charge pulses
along with stable dead-time and high count rate operation. Different versions of the
integrated circuit have been fabricated over the years using different standard CMOS
technologies; one of them is also included in photon counting modules sold by Micro
Photon Devices s.r.l., a spin-off company of the Politecnico di Milano.
From now on, the acronym AQC will refer to mixed active-passive architecture, since
this kind of structure has in practice replaced the full active one
11
2. A brief description of system
Our focus is to design the power solution, so a conceptual description of the system is
presented instead of a detailed introduction. And we would list the power
requirements in this chapter, too.
2.1. Conceptual structure
As Figure 2.1 shows,
Figure 2.1 Block schematic of the system
Vpol is the polarization voltage for SPAD, while VddH, gndH and vdd are desired by
AQC. Besides, we need Vpeltier to drive our cooling device and VDAC for controller. From
simulation, we obtain relevant power data to determine our output currents for each
regulator. Among them, pay attention to gndH, we can see that it sinks current instead
of providing current, which means we need a unique design idea for it.
2.2. AQC requirements
To understand the data in the table, some items are explained:
ctR means voltage to control reset time,
12
ctQ means voltage to control quenching,
ctS means voltage to control sense,
LVDS load is low voltage differential signaling load.
Now simulation conditions are as followed:
LVDS load = 100 Ohm
vdd=1.8V
floating anode
vddH=vquench=3.6-25V
ctR= 0.9V (t_reset = 3.7ns)
gndH=vddH-1.8V
Table 1 Simulation conditions to obtain power requirements
Static contribution is showed:
P(vdd-gnd) 1.10E-02
Table 2 Static contribution for vdd
Dynamic contributions are displayed:
P(vddH-gndH)_avg 5.00E-06
per MHz
P(vdd-gnd)_avg 2.34E-05
per MHz
Table 3 Dynamic contribution for vddH-gndH and vdd
P(vddH-gnd) _avg depends on vddH and ctQ
values
ctQ \ vddH 5V 8V 10V 20V 21V 25V
0.9V (4.7ns) 4.10E-05 9.74E-05 1.35E-04 4.56E-04 4.88E-04 6.17E-04
1.3V (27ns) 5.50E-05 1.21E-04 1.65E-04 5.18E-04 5.54E-04 6.95E-04
1.35V (50ns) 7.00E-05 1.46E-04 1.96E-04 5.82E-04 6.21E-04 7.75E-04
Table 4 Dynamic contribution per AQC when different ctQ is employed for vddH
Then the calculation of power (or output current) for each regulator is proceeded
according to the following rules:
P(vdd)= static consumption + dynamic consumption
13
= P(vdd-gnd) + P(vdd-gnd)*frequency
P(vddH)=P(vddH-gnd)*frequency
P(gndH)=P(vddH-gndH)*frequency
And given ctS=1.6ns, frequency cases are exhibited:
1) ctQ=0.9V
Ttotal= t_reset + t_sense + t_quench
=3.7ns + 1.6ns +4.7ns = 10ns
Frequency= 1/Ttotal = 100MHz
2) ctQ=1.3V,
Frequency=31MHz
3) ctQ=1.35V
Frequency=18MHz
Finally, power and current specifications are showed:
P(vddH-gndH) per
AQC
I(vddH-gndH) per
AQC
Frequency(MHZ) P(vdd)
Frequency(MHZ) I(vddH-gndH)
100 5.00E-04
100 2.78E-04
31 1.55E-04
31 8.61E-05
18 9.00E-05
18 5.00E-05
Table 5 Power consumption and current output for vddH-gndH
Emphasized data means the worst case for each channel, we have 32 channels in the
board, then
Iout (vddH-gndH) = 8.9mA;
14
P(vdd-gnd) per AQC
I(vdd-gnd) per AQC
Frequency(MHZ) P(vdd)
Frequency(MHZ) I(vdd-
gnd)
100 1.33E-02
100 7.40E-03
31 1.17E-02
31 6.50E-03
18 1.14E-02
18 6.33E-03
Table 6 Power consumption and current output for vdd
Iout (vdd) =237mA;
P(vddH-gnd) per
AQC
100MHZ
ctQ \ vddH 5V 8V 10V 20V 21V 25V
0.9V (4.7ns) 4.10E-03 9.74E-03 1.35E-02 4.56E-02 4.88E-02 6.17E-02
1.3V (27ns) 5.50E-03 1.21E-02 1.65E-02 5.18E-02 5.54E-02 6.95E-02
1.35V (50ns) 7.00E-03 1.46E-02 1.96E-02 5.82E-02 6.21E-02 7.75E-02
Table 7 Power consumption for vddH at 100MHz
31MHZ
ctQ \ vddH 5V 8V 10V 20V 21V 25V
0.9V (4.7ns) 1.27E-03 3.02E-03 4.19E-03 1.41E-02 1.51E-02 1.91E-02
1.3V (27ns) 1.71E-03 3.75E-03 5.12E-03 1.61E-02 1.72E-02 2.15E-02
1.35V (50ns) 2.17E-03 4.51E-03 6.08E-03 1.80E-02 1.92E-02 2.40E-02
Table 8 Power consumption for vddH at 31MHz
15
18MHZ
ctQ \ vddH 5V 8V 10V 20V 21V 25V
0.9V (4.7ns) 7.38E-04 1.75E-03 2.43E-03 8.21E-03 8.79E-03 1.11E-02
1.3V (27ns) 9.90E-04 2.18E-03 2.97E-03 9.33E-03 9.97E-03 1.25E-02
1.35V (50ns) 1.26E-03 2.62E-03 3.53E-03 1.05E-02 1.12E-02 1.40E-02
Table 9 Power consumption for vddH at 18MHz
I(vddH-gnd) per
AQC
100MHZ
ctQ \ vddH 5V 8V 10V 20V 21V 25V
0.9V (4.7ns) 8.20E-04 1.22E-03 1.35E-03 2.28E-03 2.33E-03 2.47E-03
1.3V (27ns) 1.10E-03 1.51E-03 1.65E-03 2.59E-03 2.64E-03 2.78E-03
1.35V (50ns) 1.40E-03 1.82E-03 1.96E-03 2.91E-03 2.96E-03 3.10E-03
Table 10 Current output for vddH at 100MHz
31MHZ
ctQ \ vddH 5V 8V 10V 20V 21V 25V
0.9V (4.7ns) 2.54E-04 3.77E-04 4.19E-04 7.07E-04 7.21E-04 7.65E-04
1.3V (27ns) 3.41E-04 4.69E-04 5.12E-04 8.03E-04 8.17E-04 8.62E-04
1.35V (50ns) 4.34E-04 5.64E-04 6.08E-04 9.02E-04 9.16E-04 9.61E-04
Table 11 Current output for vddH at 31MHz
16
18MHZ
ctQ \ vddH 5V 8V 10V 20V 21V 25V
0.9V (4.7ns) 1.48E-04 2.19E-04 2.43E-04 4.11E-04 4.19E-04 4.44E-04
1.3V (27ns) 1.98E-04 2.72E-04 2.97E-04 4.67E-04 4.75E-04 5.00E-04
1.35V (50ns) 2.52E-04 3.28E-04 3.53E-04 5.24E-04 5.32E-04 5.58E-04
Table 12 Current output for vddH at 18MHz
As far as vddH case is concerned, the worst power doesn’t coincide with the worst
current and we will take into account the worst current case, that is,
Iout (vddH) =43.2mA.
2.3. other requirements
A liquid cooling system is used to ensure a sufficient dissipation capability from the hot
side of the Peltier to allow the temperature control system to work properly. The
Thermo-Electric Cooler (TEC) we use is RS 490-1323, the parameters from datasheet
are enough for our application.
As for DAC, we consider the regulator absorbs 1.16mA from it and supply is usually
given as 3.3V. Meanwhile, 3.3V is also provided to micro-controller and practically its
current requirement is 15mA.
17
3. Power board solution
In this chapter, the power solutions will be designed according to the previous
requirements and the specific topologies, values of components would also be
introduced. And we would simulate the circuits and verify our ideas.
3.1. The polarization power
Referred to chapter 2, we need a Vpol to reversely bias SPAD. Here we have two cases:
20-50V and 20-100V with a Iout=128mA. To leave some margins, we set Iout=200mA.
After inputting all the data into the website, we select LT3958. As for topology, because
the application calls for high voltage (at relatively low power), the flyback type comes
to our mind. The flyback regulator employs a transformer to ensure galvanic isolation
for safety reasons that is to isolate the high voltage from things that might find it
dangerous (for example, sensitive electronic components and frail humans),
replacing the (non-isolating) inductor used in conventional switching step-up/step-
down (buck/boost) regulators.
3.1.1. 20-50V output
The schematic (Figure 3.1) is drawn due to application circuit from datasheet and we
modify component values to satisfy our requirements.
Figure 3.1 Schematic of polarization 20-50V
1) Ro1, Ro2 and Rcontrol ?
To obtain a variable output, we need a control voltage (0-3.3V) to regulate it. Given
18
VFB=1.6V, without control part, VOUT=1.6*(1+R2/R1), a suitable value for Rcontrol is
10KΩ .
Considering a margin space, we set VOUT=50V @Vcontrol=0.2V, VOUT=20V @Vcontrol=3V,
then we get two equations: 1.6
𝑅𝑜1 +
1.4
10 =
50−1.6
𝑅𝑜2 ,
1.6
𝑅𝑜1 -
1.4
10 =
20−1.6
𝑅𝑜2
Finally, Ro1=107KΩ, Ro2=5.13KΩ, Rcontrol=10KΩ;
2) Selection of operating frequency?
The operating frequency of LT3958 can be set with an external resistor RT over a
100kHz to 1MHz range,
Switching
Frequency(KHz)
RT(KΩ)
100 140
200 63.4
300 41.2
400 30.9
500 24.3
600 19.6
700 16.5
800 14
900 12.1
1000 10.5
Table 13 Timing Resistor (RT)Value
we choose RT = 24.3KΩ and corresponding fSW = 500KHz.
3) Selection of transformer and turn ratio?
From datasheet, we obtain the following equation: 𝑁𝑝
𝑁𝑠 ≤
84−𝑉𝐼𝑁(MAX)
𝑘𝑉𝑂𝑈𝑇 where 84V
is SW voltage Absolute Maximum value according to the Absolute Maximum
Ratings table and k typically is 1.5~2. Let VIN(MAX)=12V and VOUT=50V, the turn ratio
is chosen as 1.
Then looking at this equation: DMAX = 𝑉𝑂𝑈𝑇∗
𝑁𝑝
𝑁𝑠
𝑉𝑂𝑈𝑇∗𝑁𝑝
𝑁𝑠+VIN(MAX)
= 0.806, next set the
transformer ripple current △ISW = 2A, so the primary winding inductance could
be derived by L = VIN(MIN)
△ISW∗fSW* DMAX ≈ 10uH. Note that in the schematic designing
step, we use coupled inductance to replace transformer in our software.
Later in Chaper 4, we will study deep into this power circuit and find how to choose
19
real transformer and draw them.
4) Selection of capacitors ?
Contributions of ESR (equivalent series resistance), ESL (equivalent series
inductance) and the bulk capacitance must be considered when choosing the
correct output capacitors for a given output ripple voltage.
The choice of component(s) begins with the maximum acceptable ripple voltage
(expressed as a percentage of the output voltage), and how this ripple should be
divided between the ESR step ΔVESR and the charging/discharging ΔVCOUT.
Ceramic capacitors make a good choice for the capacitor thanks to its low ESR and
we only consider effect of bulk capacitance: 𝐼𝑂𝑈𝑇(𝑀𝐴𝑋)
𝑓𝑆𝑊∗𝐶𝑂𝑈𝑇 < △v (typically 10% of
output). Our choice is Cout = 20uF.
C2 is connected to feedback resistance to improve the transient response,
experientially ranging from 20pF to 220pF, but we should regulate it in the
simulation.
5) Loop compensation ?
Loop compensation determines the stability and transient performance. The
LT3958 uses current mode control to regulate the output which simplifies loop
compensation. The optimum values depend on the converter topology, the
component values and the operating conditions (including the input voltage, load
current, etc.). To compensate the feedback loop of the LT3958, a series resistor-
capacitor network is usually connected from the VC pin to SGND. Figure 3.2 shows
the typical VC compensation network. For most applications, the capacitor should
be in the range of 470pF to 22nF , and the resistor should be in the range of 5k to
50k. A small capacitor is often connected in parallel with the RC compensation
network to attenuate the VC voltage ripple induced from the output voltage ripple
through the internal error amplifier. The parallel capacitor usually ranges in value
from 10pF to 100pF . A practical approach to design the compensation network is
to start with one of the circuits in this datasheet that is similar to your application
and tune the compensation network to optimize the performance. Stability should
then be checked across all operating conditions, including load current, input
voltage and temperature.
Application Note 76 is a good reference. It tells us that RC,CC1 provides a zero while
RC,CC2 generates a pole. CC2 is smaller than CC1.
20
Figure 3.2 LT3958 Block Diagram Working as a SEPIC Converter
First, let us simulate as application circuit (Figure 3.3) shows:
Figure 3.3 Schematic with loop compensation starting from application circuit:
RC=10KΩ, CC1=10nF, CC2=100pF
21
The result shows an overshoot (Figure 3.4):
Figure 3.4 Simulation output result of circuit with loop compensation starting
from application circuit: RC=10KΩ, CC1=10nF, CC2=100pF
We try to increase the pole to obtain a large loop gain, then our loop
compensation is as Figure 3.5 displays:
Figure 3.5 Schematic with loop compensation: RC=50KΩ, CC1=250pF, CC2=10pF
Obviously, there is a good output transient (Figure 3.6):
22
Figure 3.6 Simulation output result of circuit with loop compensation:
RC=50KΩ, CC1=250pF, CC2=10pF
Next, load regulation is a very important parameter for circuit performance. Load
regulation is the capability to maintain a constant voltage (or current) level on the
output channel of a power supply despite changes in the supply's load (such as a
change in resistance value connected across the supply output).
We substitute the resistor with a pulse generator in which the current varies from
2mA to 130mA. Here we should know that not every circuit needs to check load
regulation. To be clear, in this case, 2mA implies dark SPAD, that is, there is no light
to be incident on SPAD; while 130mA means light SPAD. We are interested in the
current change due to the light incidence, however, for vddH in the next section,
this power is for the quenching, there is no need to care about the current variation,
therefore, we don’t carry on load regulation for Vquench.
Figure 3.7 Load regulation waveform (1) for the lower output
We could see the voltage change due to variation of load current is smaller than
0.1V and this is acceptable. Meanwhile the time to recover to the steady state is
0.4ms.
23
Figure 3.8 Load regulation waveform (2) for the lower output
Then the voltage drop is 0.05V with the transient time equal to 0.9ms.
The case is similar for high limit of the output,
Figure 3.9 Load regulation waveform (1) for the higher output
The transient is 0.6ms.
Figure 3.10 Load regulation waveform (2) for the higher output
The transient is 0.8ms.
3.1.2. 20-100V output
The procedure is almost the same.
Now the turn ratio is 𝑁𝑝
𝑁𝑠 ≤
84−𝑉𝐼𝑁(MAX)
𝑘𝑉𝑂𝑈𝑇 where VOUT = 100V, we select
𝑁𝑝
𝑁𝑠=
1
3;
Ro1=280KΩ, Ro2=8KΩ, Rcontrol=10KΩ;
RC = 25KΩ, CC1 = 125pF, CC2 = 100pF;
24
Figure 3.11 Schematic of polarization 20-100V
The transformer in the Figure 3.11 is the real component and we will talk in detail in
the following chapter.
3.2. The AQC quench power
From previous chapter, we obtain vddH=vquench=3.6-25V and Iout=43.2mA.
Considering margin space, Iout=100mA. The problem becomes how to find a DC-DC
converter to transfer from 12V to 3.6-25V, in which the output is greater than, less
than or equal to input, then our choice comes to buck-boost or SEPIC.
3.2.1. SEPIC converter
A SEPIC is essentially a boost converter followed by a buck-boost converter, therefore
it is similar to a traditional buck-boost converter, but has advantages of having non-
inverted output (the output has the same voltage polarity as the input), using a series
capacitor to couple energy from the input to the output (and thus can respond more
gracefully to a short-circuit output), and being capable of true shutdown: when the
switch is turned off, its output drops to 0 V, following a fairly hefty transient dump of
charge.
25
Figure 3.12 SEPIC schematic
When switch S1 is turned on, current IL1 increases and the current IL2 goes more
negative. (Mathematically, it decreases due to arrow direction.) The energy to increase
the current IL1 comes from the input source. Since S1 is a short while closed, and the
instantaneous voltage VL1 is approximately VIN, the voltage VL2 is approximately −VC1.
Therefore, the capacitor C1 supplies the energy to increase the magnitude of the
current in IL2 and thus increase the energy stored in L2. The easiest way to visualize
this is to consider the bias voltages of the circuit in a d.c. state, then close S1.
Figure 3.13 With S1 closed current increases through L1 (green) and C1 discharges
increasing current in L2 (red)
When switch S1 is turned off, the current IC1 becomes the same as the current IL1, since
inductors do not allow instantaneous changes in current. The current IL2 will continue in
the negative direction, in fact it never reverses direction. It can be seen from the diagram
that a negative IL2 will add to the current IL1 to increase the current delivered to the load.
Using Kirchhoff's Current Law, it can be shown that ID1 = IC1 - IL2. It can then be concluded,
that while S1 is off, power is delivered to the load from both L2 and L1. C1, however is
being charged by L1 during this off cycle and will in turn recharge L2 during the on cycle.
26
Figure 3.14 With S1 open current through L1 (green) and current through L2 (red)
produce current through the load
3.2.2. vddH schematic design
According to power specifications, we choose LT3467/3467A. Here we will use coupled
inductors at a slightly higher cost not only to provide a smaller footprint but also to get
the same inductor ripple current, requiring only half the inductance of that in SEPIC
circuit with two separate inductors, which means higher efficiency is accomplished.
Figure 3.15 Schematic of converter topology for vddH (SEPIC with coupled
inductors)
With aid of datasheet, all the parameters would be calculated to satisfy our application.
1) R1, R2 and Rcontrol ?
To obtain a variable output, we need a control voltage to regulate it. Given
VFB=1.255V, without control part, VOUT=1.255*(1+R2/R1), a good value for R1 is
13.3Kohm.
Considering a margin space, we set VOUT=27V @Vcontrol=0V, VOUT=3.3V @Vcontrol=3V,
27
then we get two equations: 1.255
𝑅3 +
1.255
13.3 =
27−1.255
𝑅2 ,
3−1.255
𝑅3 +
3.3−1.255
𝑅2 =
1.255
13.3
Finally, R1=13.3Kohm, R2=169Kohm, Rcontrol=21.2Kohm;
2) L1 and L2 ?
Referring to Figure 3.3 and Figure 3.4, duty cycle in CCM (continuous-conduction
mode) case is as followed:
D = 𝑉𝑂𝑈𝑇+𝑉𝐹𝐵
𝑉𝐼𝑁+𝑉𝑂𝑈𝑇+𝑉𝐹𝐵
then Dmin=27.7%, Dmax=68.4%.
A SEPIC is said to be in CCM if the current through the inductor never falls to zero,
that is △iL1 < 2IL1, △iL2 < 2IL2. Specifically, in our circuit, the conditions become:
𝑉𝐼𝑁∗𝐷
𝑓𝑆𝑊∗𝐿1 < 2*IIN = 2*
𝐼𝑂𝑈𝑇∗𝐷
1−𝐷
Where fSW = 1.3MHz, VIN = 12V, D= Dmin=27.7%, IOUT = 100mA, and L2 is the same
case as L1, so we choose L1 = L2 = 35uH.
3) Selection of capacitors ?
Output capacitor is served to reduce output voltage ripple, we have:
𝐼𝑂𝑈𝑇∗𝐷
𝑓𝑆𝑊∗𝐶𝑂𝑈𝑇 < △v (typically 10% of output)
According to datasheet, a 4.7μF to 15μF output capacitor is sufficient for most
applications, we pick Cout=20uF, and we could modify it with simulation results. Pay
attention to the two parallel output capacitors C1 and C2, we introduce a
component called ferrite bead in order to suppresses high frequency noise in
electronic circuits.
Ceramic capacitors also make a good choice for the input decoupling capacitor,
which should be placed as close as possible to the LT3467. A 1μF to 4.7μF input
capacitor is sufficient for most applications.
C2 is connected to feedback resistance to improve the transient response,
experientially ranging from 20pF to 220pF, also we could regulate it in the
simulation.
Cp is AC coupling capacitor, we could start from the application and choose the
proper value afterwards.
4) Selection of diode ?
28
A Schottky diode is recommended for use with the LT3467 and the LT3467A. The
Philips PMEG 2005 is a very good choice. Where the switch voltage exceeds 20V,
use the PMEG 3005 (a 30V diode). Where the switch voltage exceeds 30V, use the
PMEG 4005 (a 40V diode). These diodes are rated to handle an average forward
current of 0.5A. In applications where the average forward current of the diode
exceeds 0.5A, a Philips PMEG 2010 rated at 1A is recommended. For higher
efficiency, use a diode with better thermal characteristics such as the On Semi-
conductor MBRM120 (a 20V diode) or the MBRM140 (a 40V diode).
We firstly use a default Schottky diode in LTspice and from the simulation, we check
the switch voltage and current to define the type, our choice is PMEG6020EP.
Note that in the existent library, there is no PMEG6020. We need to go to website
to download its spice file and transfer it to our LTspice.
3.2.3. Simulation results
First, the output is simulated to check if it meets the requirement:
Simulation condition is with a load Rload=500Ohms, then the output current will be
limited below 100mA;
1) When Vcontrol=0.2V, steady-state output is 25.64V;
Figure 3.16 Simulation of higher output for vddH
2) When Vcontrol=3V, steady-state output is 3.074V;
29
Figure 3.17 Simulation of lower output for vddH
Then let us simulate to see how to regulate C2 and how does it work in the circuit:
1) When C2=50pF, we could find there is an overshoot at the output;
Figure 3.18 Schematic for vddH with C2=50pF
Figure 3.19 Simulation output result for vddH with C2=50pF
2) When C2=100pF, the overshoot is obviously decreased;
30
Figure 3.20 Simulation output result for vddH with C2=100pF
And looking at Figure 3.16 and 3.17, there is no overshoot.
3.3. The AQC gndH power
As we mentioned before, this power is different from other powers because of the
opposite desired output current direction. The negative regulator will be introduced.
Figure 3.21 Schematic of gndH power
To achieve gndH = vddH -1.8V, we adopt a combination of one flyback topology
(LT8303) and one negative linear regulator (LT1964), which will provide a relatively
stable 1.8V with respect to vddH.
The LT8303 operates from an input voltages range of 5.5V to 100V and can deliver up
to 5W of isolated output power. We use it to generate an intermediate voltage -2.5V
with respect to vddH, which means an VIN = -2.5V for the following linear regulator
31
LT1964. Next -2.5V will be transferred to -1.8V relatively, meanwhile with a gnd equal
to vddH, the output is to be vddH-1.8V.
Talking about this combination, these two types of regulators have their advantages
and disadvantages respectively. Switching regulators are highly efficient and available
as modular chips which are compact and reliable, but cost and noise/ripple/EMI are
medium to high (PIN = POUT ideally). Linear regulators are a great choice for powering
very low powered devices or applications where the difference between the input
and output is small, they are easy to use, simple and cheap but is normally inefficient
(η=𝑉𝑂𝑈𝑇
𝑉𝐼𝑁 ).
3.3.1. LT8303
1) Calculation of RFB ?
The output voltage is programmed with a single external resistor. According to
datasheet, we employ equation: VOUT = 100uA*RFB
𝑁𝑃𝑆 - VF where VOUT =2.5V, VF
(Output diode forward voltage) ≈ 0.3V and we set NPS = 1, hence RFB = 28KΩ.
2) Primary inductance requirement ?
The LT8303 obtains output voltage information from the reflected output voltage
on the SW pin. The conduction of secondary current reflects the output voltage
on the primary SW pin. The sample-and-hold error amplifier needs a minimum
350ns to settle and sample the reflected output voltage. In order to ensure proper
sampling, the secondary winding needs to conduct current for a minimum of
350ns. The following equation gives the minimum value for primary-side
magnetizing inductance:
LPRI≥tOFF(MIN)∗NPS∗(VOUT+VF)
𝐼𝑆𝑊(𝑀𝐼𝑁)
tOFF(MIN) = Minimum switch-off time = 350ns
ISW(MIN) = Minimum switch current limit = 105mA
after substituting all the data, LPRI≥9.3uA;
In addition to the primary inductance requirement for the minimum switch-off
time, the LT8303 has minimum switch-on time that prevents the chip from
turning on the power switch shorter than approximately 160ns. This minimum
switch-on time is mainly for leading-edge blanking the initial switch turn-on
current spike. If the inductor current exceeds the desired current limit during
that time, oscillation may occur at the output as the current control loop will
lose its ability to regulate. Therefore, the following equation relating to
maximum input voltage must also be followed in selecting primary-side
magnetizing inductance:
32
LPRI≥tON(MIN)∗VIN(MAX)
𝐼𝑆𝑊(𝑀𝐼𝑁)
tON(MIN) = Minimum switch-on time = 160ns
then LPRI≥18.3uF;
In general, choose a transformer with its primary magnetizing inductance about
40% to 60% larger than the minimum values calculated above. A transformer
with much larger inductance will have a bigger physical size and may cause
instability at light load.
Our last selection is LPRI = 23.3uF.
3) ZD snubber ?
A snubber circuit is recommended for most applications. Two types of snubber
circuits shown in Figure 3.22 that can protect the internal power switch include the
DZ (diode-Zener) snubber and the RC (resistor-capacitor) snubber. The DZ snubber
ensures well defined and consistent clamping voltage and has slightly higher power
efficiency, while the RC snubber quickly damps the voltage spike ringing and
provides better load regulation and EMI performance. Figure 3.23 shows the
flyback waveforms with the DZ and RC snubbers. For the DZ snubber, proper care
must be taken when choosing both the diode and the Zener diode. Schottky diodes
are typically the best choice, but some PN diodes can be used if they turn on fast
enough to limit the leakage inductance spike. Choose a diode that has a reverse-
voltage rating higher than the maximum SW pin voltage.
Figure 3.22 Snubber Circuits
33
Figure 3.23 Maximum Voltages for SW Pin Flyback Waveform
3.3.2. LT1964
The LT1964 is a micropower low noise, low dropout negative regulator. The device is
available with a fixed output voltage of –5V and as an adjustable device with a –1.22V
reference voltage.
Refer to equation: VOUT = VADJ*(1 + 𝑅2
𝑅1 ) where VADJ = -1.22V, let R1 = 100KΩ, then to
obtain VOUT = -2.5V, R2 = 47.5KΩ.
3.3.3. Simulation results
Figure 3.24 Simulation output result for gndH
Obviously, the output is 25V-1.8V = 23.2V.
34
3.4. The intermediate voltage
As we talked before, ripples of switching regulator are medium to high, but DAC
requires precision, so to accomplish a both efficient and less noisy solution, we again
adopt the combination of one switching regulator and one linear regulator. We set
intermediate voltage 3.6V and we choose TPS62160 with output current equal to 0.5A
(almost doubles Iout (vdd) =237mA).
Figure 3.25 Block of buck and the downstream parts
Figure 3.26 Schematic of the intermediate voltage 3.6V
1) Programming the output voltage ?
The adjustable TPS62160 can be programmed for output voltages from 0.9 V to
6V by using a resistive divider from VOUT to AGND. The voltage at the FB pin is
regulated to 800 mV. The value of the output voltage is set by the selection of
the resistive divider from equation: VOUT = 0.8*(1+𝑅𝑓𝑏𝑡
𝑅𝑓𝑏𝑏 ). It is recommended to
choose resistor values which allow a current of at least 2 µA, meaning the value
of Rfbb should not exceed 400KΩ. Lower resistor values are recommended for
highest accuracy and most robust design.
Our choice is Rfbt = 634KΩ, Rfbb = 180KΩ.
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2) Selection of output LC filter ?
The LC output filter's inductance and capacitance have to be considered together,
creating a double pole, responsible for the corner frequency of the converter.
The inductor selection is affected by several effects like inductor ripple current,
output ripple voltage, PWM-to-PSM transition point and efficiency. In addition,
the inductor selected has to be rated for appropriate saturation current and DC
resistance (DCR). Refer to equation:
△IL(max)= VOUT*1−
𝑉𝑂𝑈𝑇
𝑉𝐼𝑁(max)
𝐿𝑚𝑖𝑛∗𝑓𝑠𝑤
where fsw=2.25MHz,
then we select: L1 = 4.7uH with acceptable △IL(max)=0.24A.
As for COUT, according to (1−𝐷)∗𝐷∗𝐼𝑂𝑈𝑇
△VOUT∗𝑓𝑠𝑤, and D=
𝑉𝑂𝑈𝑇
𝑉𝐼𝑁=0.3, △VOUT=1%*3.6V=0.036,
so COUT is larger than 2.6uF. Finally, refer to the Figure 3.30, we select COUT=22uF.
Figure 3.27 Table of Stability vs Effective LC Corner Frequency
3) Input capacitor ?
For most applications, 10 µF is sufficient and is recommended, though a larger
value reduces input current ripple further. The input capacitor buffers the input
voltage for transient events and also decouples the converter from the supply. A
low ESR multilayer ceramic capacitor is recommended for best filtering and should
be placed between VIN and PGND as close as possible to those pins.
TI has its own simulation platform and we could see the output as followed:
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Figure 3.28 Simulation output result for the intermediate voltage
3.5. The AQC vdd power
We add a linear regulator after BUCK and obtain vdd=1.8V with output current
requirement 237mA.
Figure 3.29 Schematic of vdd power
3.6. The DAC power
Similarly, to acquire 3.3V for DAC power from the intermediate power 3.6V, we simply
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get the schematic (Figure 3.30):
Figure 3.30 Schematic of VDAC power
3.7. The Peltier driving power
3.7.1. TEC and Peltier
A thermoelectric device can convert electric energy into a temperature gradient, by
means of the physical phenomena discovered by Peltier in 1834. This device is basically
made up of two ceramic plated which thermally connects several pairs of n- and p-
type semiconductor materials in parallel. When those p-n junctions are forward biased,
the device acts as a cooler, otherwise, when the junctions are reversed biased, as a
heater.
In order to regulate the temperature with the desired precision, a control circuit is
needed to drive the thermoelectric device. The point is we would connect two
converters on the two sides of the Peltier to generate positive or negative voltage
across it to achieve both cooling and heating. Then we select one regulator LTC 3413
that sources or sinks up to 3A of output current.
3.7.2. Vpeltier schematic design
We start from typical application circuit “1.25V, ±3A DDR Memory Termination Supply
at 1MHz” of datasheet and modify compensation components.
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Figure 3.31 Schematic of Vpeltier
According to VOUT=𝑉𝑟𝑒𝑓
2(1 +
𝑅2
𝑅3), we decide Vref=1.65V, R2=R3, then VOUT=1.65V;
The tuning of RIth, CIth, Cc is to remain same pole and zero and increase resistor, through
simulation, we could find suitable values.
Output and load regulation are good.
Figure 3.32 Simulation output result for Vpeltier
Figure 3.33 Load regulation waveform (1) for Vpeltier
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Figure 3.34 Load regulation waveform (2) for Vpeltier
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4. Design of test board
In this chapter, we will show you a real board design by making an example of BUCK
(3.6V) and FLYBACK (20-100V) schematics. We first draw new schematics and turn
them to layouts, next to export the job file and produce the test board for making
measurements.
4.1. Redraw the schematics
As we talked before, we select VPH5-0067-R because we consider both the simulation
inductor current and R(BASE). Then according to datasheet of this transformer and
multiple winding information (Figure 4.1 and 4.2), we realize turn ration of 1
3 through
paralleling the primary windings and connecting the secondary in series. Also, we
could fill in the correct values of inductances and currents in the previous schematic
(as showed in Figure 3.11), that is: LP=9.65uH, LS=9.65*32=86.86uH. Then we check the
real component values in the market of Altium Designer and replace with them. Refer
to Figure 4.3, we divide capacitances into many paralleling parts just for simplicity
(remember it is just a test board, there is no need to precisely define every component).
Moreover, we add two extra capacitances close to the transformer to reduce the noise
furthermore.
Figure 4.1 Schematic of transformer windings
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Figure 4.2 Multiple windings current and inductance
Figure 4.3 Schematic of Vpol(20-100V) test board
We use LP5912 to replace LT1965 because we couldn’t find the model in the device
library. So, we find a similar one in the layout and pins configuration to replace it.
Figure 4.4 Schematic of BUCK 3.6V test board
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4.2. Display of layout design
Figure 4.5 Layout design of buck+flyback
When designing the layout, we should notice some points:
to make the distance between SW and the parts connect to SW as short as possible
because SW node is noisy;
to make the distance between FB pin and the intersection point with feedback
resistor as short as possible because FB is a high impedance node and if it is too long,
there will produce a big loop to dissipate much power; meanwhile, the output is
connected to capacitor, so it is a low impedance node, the long distance will not
make too much pressure to the power consumption;
to find the loop with current variation and to diminish those loops as small as
possible;
commonly, connection to capacitor would reduce some noise, so it is better to
connect first to capacitor;
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to increase the width of the traces as much as possible to dissipate the heat better.
Of course, we couldn’t reach all the perfections at the same time, we would make
some trade-offs.
4.3. Measuring results
Figure 4.6 and 4.7 are our real test boards, we use oscilloscope to measure outputs
and see the waveforms.
Figure 4.6 Test board of BUCK 3.6V
Figure 4.7 Test board of flyback 20-100V
We check the output and compare the efficiency.
And real efficiency = 𝑃𝑜𝑢𝑡
𝑃𝑖𝑛, ideal efficiency is derived by simulation:
In the LTspice, cancel the Vcontrol, and rename load resistance with Rload, then choose
the steady state in the transient response.
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EFFICIENCY OF FLYBACK 20-
100V
Vin Iin Pin Vout Iout Pout Rload ideal
efficiency
real
efficiency
Vcontrol
12.01 0.274 3.291 20.22 0.130 2.638 155 87.6 80.156
2.85V
12.01 0.162 1.946 20.22 0.076 1.531 267 84.0 78.703
12.00 0.083 0.996 20.22 0.036 0.721 567 75.2 72.397
Vin Iin Pin Vout Iout Pout Rload ideal
efficiency
real
efficiency
Vcontrol
12.01 0.184 2.210 50.00 0.033 1.667 1500 83.0 75.420
1.784V
12.01 0.157 1.886 50.00 0.027 1.334 1874 82.8 70.750
12.01 0.108 1.297 50.00 0.017 0.850 2940 73.8 65.558
Vin Iin Pin Vout Iout Pout Rload ideal
efficiency
real
efficiency
Vcontrol
12.01 0.199 2.390 99.90 0.017 1.733 5760 81.7 72.496
0.002V
12.01 0.187 2.246 99.90 0.015 1.528 6530 79.8 68.051
12.01 0.176 2.114 99.90 0.014 1.367 7300 77.4 64.677
Table 14 Measurement results of the test board
We could find the outputs are good, the efficiencies are not so close.
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5. Conclusion and future Developments
Our design for now is not so bad, but still need to improve. In the future, we would
realize other circuits respectively and after testing all, we would realize the whole
board and verify its feasibility.
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Bibliography
[1]. Steven Keeping “Flyback Regulators as a First Choice for Isolated Power Supplies“
https://www.digikey.com/en/articles/techzone/2012/oct/flyback-regulators-as-a-
first-choice-for-isolated-power-supplies
[2]. The datasheet of LT3958
[3]. Application note 76 for loop compensation
[4]. Wikipedia, “Single-ended primary-inductor converter”
[5]. The datasheet of LT3467
[6]. Linear vs. Switching Regulators
https://www.intersil.com/en/products/power-management/linear-vs-switching-
regulators.html
[7]. The datasheet of LT8303
[8]. The datasheet of LT1964
[9]. The datasheet of TPS62160
[10]. The datasheet of LT1965
