POWER ELECTRONICSLaboratory Manual

Department of Electrical and Electronic Engineering

Gokaraju Rangaraju Institute of Engineering & Technology

BACHUPALLY, MIYAPUR, HYDERABAD-500072

Griet

POWER ELECTRONICSLaboratory Manual

Department of Electrical and Electronic Engineering

Gokaraju Rangaraju Institute of Engineering & Technology

BACHUPALLY, MIYAPUR, HYDERABAD-500072

V.Vasantha & P.V.Basavaiah

Griet

List of Experiments

Description of Kit

Characteristics of SCR, IGBT, MOSFET and DIAC

Resistance Triggering of Thyristor

Resistance Capacitance Triggering of Thyristor

UJT Triggering of Thyristor

Making of PCB for Extended pulse using UJT

Triggering

1- Half Wave Converter using R-Load

1- Half Wave Converter using RL-Load with and

without FWD

1- AC Voltage controller using R-Load

1- AC Voltage controller using RL-Load

1- Full Wave converter Controller using R-Load

1- Full Wave converter Controller using RL-Load

with and without FWD

Triggering of Thyristor using 555 Timer

Triggering of Thyristor using Astable Multivibrator

DC Chopper using MOSFET

Single Phase Series Inverter

Single Phase Parallel Inverter

Single Phase Inverter using MOSFET

Single Phase Cyclo Converters

Commutation of SCRs

Viva Questions

01

05

21

24

27

34

38

40

43

45

47

50

54

58

63

66

69

73

75

78

84

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

Name of the Experiment Page NoS. No

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T2 T4 D2

T1 T3 D1 D3

D4

RL1

1K, 100W

1E, 10W

1K, 100W

47K, 2W

1K, 100W

2.4K, 5W

R1

Rl2

R2

Rl3

Bulb

12 VDCmotor

R3

RLE

+-

+

-

0 to 15VDC(Control Knobson left side ofKit)

100K, 3W 10K, 3W

POT POT

Multimeter

kitSupplyswitch

Terminalsfor CROConnections

L

230V, 1-50 Hz,ACSupply

N

+

30V/5ADCSupply

_

OX

OY

OGND

CRO Points15V 15V

500mA

230 V, Input

PT1 PT2

POT Control Knobs

Experiment 1 DESCRIPTION OF KIT

The Universal Power Electronics Trainer kit

Fig- 1.1

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Description of the main components on the kit: 1. SILICON CONTROLLED RECTIFIERS(thyristors)- 4 Nos. (T , T , T , T )1 2 3 4 Electrical specifications and data sheets are enclosed.

2. SILICON POWER DIODES- 4 Nos. (D , D , D , D )1 2 3 4 Electrical Specifications and Data sheets are enclosed.

3. BULB (R-LOAD) - 1 No. 230V, 60W

4. RLE LOAD - 1 No. (12V permanent magnet DC MOTOR / 2400 RPM)

5. RESISTORS

1. RL , RL , RL - 3 Nos.1 2 3 1K, 100W Mounted on the back side of kit. 2. R - 1 No.1 1, 10W Current sense resistor. Useful for measurement of current. 3. R - 1 No.2 47 K, 2W Useful for attenuation. 4. R - 1 No.3 47 K, 2W Useful for attenuation.

6. AC INPUT (L-N) SOURCE Mains supply, Single Phase AC Input 0-230V, 50Hz. 7. DC INPUT SOURCE Fixed DC input source +30V, 5A current rating provided on the front panel. DC source is designed by using SMPS technology. The specification of the DC source and data sheets are enclosed. 8. AC VOLTAGES FIXED 15-0-15V The step down transformer, secondary voltages 15-0-15V, 500mA, 50Hz provided on the front panel.

9. X, Y, GND Are the output test points connected to terminals fixed on the right side of the kit. These test points are useful to make connections to the CRO.

10. 1:1:1 Pulse Transformer No 2503- 2 No's Useful for triggering circuits.

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11. Digital Meter- 1 No MODEL: 830B Useful to measure Input /Output AC/DC Voltage and Currents. SPECIFICATIONS: DC Voltage - 0.2V, 2V, 20V, 200V, 1000V. AC Voltage - 200V, 750V DC Current - 2mA, 20mA, 200mA, 10A Transistor Measurement Diode Test Continuity Test and Resistance Measurement.

12. VARIABLE DC SOURCES- 2 No's 0 to +15V, 500mA and 0 to -15V, 500mA variable electrically isolated DC voltages are provided on the breadboard.

13. FIXED AC VOLTAGES- 2 No's Fixed AC voltages 0-15V & 0-15V/500mA are provided on the bread board.

14. VARIABLE RESISTORS- 2 No's 0-10 K, 1W & 0-100 K, 3W Variable resistors are provided on the bottom of the strip of the bread board.

15. BREADBOARD Solder less Breadboards (WB-102, WISH Make)- 2 No's To accept 0.3 to 0.85mm single strand wires. The breadboard on the trainer is very convenient for constructing any type of firing circuits.

It has three distinctive strips: top, bottom and the middle. The top and bottom strips are small compared to the middle strip. The top and the bottom are divided into two strips each. First half of the top strip contains 0 to +15V DC variable supply and second half of the strip contains 0-15V AC fixed supply. First half of the bottom strip contains 0 to 10 K variable resistors and second half of the strip contains 0- 100 K variable resistors.

16. Use of potential divider circuit

Fig -1.2 Whenever 230V signal observed on the CRO Potential divider circuit should be connected as shown in the above figure.

hFE

47 K

230 VI/P

2.4 KTo CRO

3

+

-

+

-

Griet Fig-1.3

17. To observe two signals at a time, a common point should exists between two signals and that common point should be connected to CRO ground.

18. To check the Working of the thyristor Connect a half wave rectifier using the thyristor, 30V DC supply and the bulb available on the kit. Between the gate and cathode, connect a variable voltage DC supply of 2V with positive terminal to gate and negative terminal to cathode. After the bulb glows, remove the gate connection.

+-

GND

Vs

Y

X

CommonPointbetweenTwo ignals

4

Grietpn

pn

gate

cathode

anode

J1J2J3 cathode

Anode

gate

SCR Characteristic:

1.1. AIM: To study the V-I characteristics of SCR.

1.2. APPARATUS: 1. SCR (TYN 616) characteristics trainer 2. Ammeters 0-500mA dc 0-25mA dc 3. Voltmeters 0-50V dc 0-20V dc 4. Patch chords

1.3. THEORY:

The SCR is a controlled rectifier, allowing the current to pass only in one direction, from anode to cathode. So it is unidirectional device. It has two states, one conducting and the other non-conducting. If anode is positive with respect to cathode, and can be forward biased, and conduct. When anode is negative with respect to the cathode, these two junctions reverse bias and SCR turns off. J junction has n on top and2 p below. With a positive voltage on the anode, this junction is reverse biased. Without the voltage applied to the gate, the SCR is indeed always off, When the anode is positive with respect to cathode, it can tolerate 50V before it turn ON without giving gating pulse.

Fig: 2.1

Thyristor V-I characteristics is drawn between anode to cahode voltage and anode current at constant gate current. This divided into three modes: 1. Reverse blocking mode 2. Forward blocking mode 3. Forward conducting mode

J J1 3

Experiment 2 CHARACTERISTICS OF SCR, TRIAC, IGBT,

MOSFET AND DIAC

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Refer to figure 2.3, In reverse blocking mode, thyristor exhibits blocking characteristics like diode. A small leakage current flows. When reverse voltage applied is less than V , then BR device offers high impedance in reverse direction. So in reverse blocking mode, SCR acts as an open switch. In forward blocking mode, anode is made positive with respect to cathode with gate open. So in this mode a small current called leakage current flows. In this mode (curve O-M), the device does not conduct. In forward conduction mode the anode to cathode forward voltage is increasing with gate circuit open. Forward break-down occurs at the reverse biased junction J 2 at a critical Forward break over voltage (V ). Then the SCR switches into low BO impedance state. The curve M-N shows the device latches on to its ON state. Then the voltage across the device suddenly drops from high voltage to low voltage(1 to 2 volts). Suddenly a large amount of current starts flowing through the device. The curve N-K is called the forward conduction state.

Forward Voltage Triggering: When anode to cathode forward voltage is increased with gate open circuit, the reverse biased junction J will break. This is 2 known as avalanche break-down and the voltage at which avalanche break-down occurs is called forward break over voltage V . At this voltage, thyristor changes BO from OFF state to ON state, characterized by a low voltage across it with large forward current. This current is called Latching current in ON mode. The forward voltage drop across the SCR during ON state is of the order of 1 to 1.5V and increases slightly with load current. After avalanche break down J junction loses 2 its reverse blocking capability. Therefore, if the anode voltage is reduced below V , BO SCR will continue conduction of the current. SCR will be turned OFF only by reducing the anode current below a certain value called Holding current value. Holding current is always less than Latching current (I >I ). L H

Gate Triggering: This is the most common method used for triggering of SCRs. In fig.2.2(a); let SCR be OFF. Then the voltage

For gate triggering, 3 types of signals are applied between gate and cathode of the device 1. DC signal 2. AC signal 3. Pulse signal

V between anode and cathode will be AK V volts, with anode positive. Now if a voltage is applied between gate and cathode, 2 making the gate positive with respect to cathode, the SCR turns ON; and the voltage V will become nearly zero. The gate loses further control on the SCRAK

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1.4. CIRCUIT DIAGRAM:

1.5. PROCEDURE: - CHARACTERISTICS:(Table -1) 1. Make all the connections as per the circuit diagram 2. Initially keep V & V at minimum position and R & R also at minimum 1 2 1 2 position. 3. Adjust gate current I to some constant, say 2.5mA or 5mA, by varying V or G 1 gate current potentiometer R . 1 4. Now slowly vary V and observe anode to cathode voltage and anode current 2 Also note down readings for every 5V. 5. Vary V till SCR conducts. This can be identified by sudden drop of anode, to 1 cathode voltage and rise of anode current. 6. The above procedure is repeated with different values of gate current. Draw the graph between V Vs I for each gate currentAK AK

GATE TRIGGERING AND V vs I :(Table -2)GK G 1. Initial settings: a) potentiometer

V I AK A

R : maximum resistance position 1 b) source V : minimum voltage position.1 c) potentiometer R : Approximately half the value.2 d) Source V : 10V2 e) SCR off 2. Slowly increase V . If I is too small to be read reduce R till I becomes readable.1 G 1 G 3. At this value of R , increase V from zero and for different values of V ; note V I and Ia1 1 1 G , G

(I will be small, indicating that the SCR is still off) A 4. As V is being increased, at same value of V ; the SCR triggers, as will be indicated by 1 1 a sudden increase in I . Note V I and I at this point. Turn off the SCR by opening A G, B A the anode-cathode circuit, and reduce V to zero. 1 5. Repeat steps (1) to (4) for different values of V . As V is increased, R should also be 2 2 2 increased appropriately, to limit the SCR current when it turns on. 6. Draw V ~I graphs for different values of V .G G 2

Cathode (K)

Anode (A)

Gate(G)

Fig 2.2 (b)

0-500mA

I II II I

Fig 2.2 (a)

Lamp

I A R 2

V2 (2.5-35V)

VAK 0-50V

V 1 (1.5-15V) VG

0-20V

IG R 1

7

SCRA

K

G

+

-

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FOR LATCHING CURRENT

FOR HOLDING CURRENT:

1.6. TABULAR FORMS:

1. Initial settings: R potentiometer: Minimum resistance position. 1 V : zero1 R potentiometer: Small value2 V :10V2 2. Gradually increase V till SCR is on (I suddenly increases). Note I . 1 A A 3. Now make V as zero by opening gate- cathode circuit. If I is unaffected, I > latching 1 A A current. 4. Assuming I to be greater than latching current, repeat steps (1) to (3); with an A increased value of R . For some I opening gate- cathode circuit will cause I to go to 2 A A zero. This is the latching current of the SCR.

1. Initial settings: a) potentiometer R : maximum resistance position 1 b) Source V minimum voltage position.1: c) Potentiometer R : Approximately half the value.2 d) Source V : 10V2 e) SCR off 2. Slowly increase V till SCR remains off. Then reduce V to zero. 1 1 3. If SCR current is less than latching current; SCR turns off. In that case, either reduce resistance R , or increase voltage V (or both); and repeat step (2), until you get an 2 2 anode current greater than the latching current at the end of step (2). 4. Now decrease the anode current ( by increasing R , decreasing V , or both ) slowly and 2 2 note the current at which the SCR if off. ( Anode current suddenly decreases nearly zero). This is the holding current and should be lesser than latching current.

At IG = mAVAKVolts

IAmA

Table 1

At IG = mAVAKVolts

IAmA

Table 2

At = 10 VVGKVolts

IGmA

VAK At = 30 VVGKVolts

IGmA

VAK

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1.7. vs characteristic:

TRIAC Characteristic:

2.1. AIM: To study the V-I characteristics of TRIAC.

2.2. APPARATUS: 1. TRIAC ( BT 136-600) characteristics trainer 2. Ammeters 0-500mA dc 0-25mA dc 3. Voltmeters 0-50V dc 0-20V dc 4. Patch chords

2.3. THEORY:

Thyristor has reverse blocking characteristic that prevents current flow from cathode to anode direction. In TRIAC, two SCRs are connected in anti parallel. So it conducts current in both directions.

V IAK A

Forward conduction(on state)

Forwardblocking

Reverse blocking

V Bo = Forward breakover voltageV BR = Reverse breakover voltageIg = Gate current

Latching current

Holding current

Forward LeakageCurrent

Reverse Leakage Current

VBRVB0 + VAK

Ig3

-Ia

+Ia

Ig3 Ig2 Ig1Ig=0

Ig2 Ig1

v v v

M

Fig 2.3

AMP

mA

9

N

K

O

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2.4. CIRCUIT DIAGRAM:

Refer to fig 2.4, An AC sinusoidal voltage V sin t in series with a load resistance R is appliedm between the terminals MT and MT . A pulse voltage V will be applied between gate and terminal 1 2 g MT whenever the switch S in the gate is closed. ( Note that triggering signal is applied between 1 gate and MT only, but never between gate and MT ). In the following, whenever current flow 1 2 between MT and MT is mentioned, it is understood that the current flow is through the device 1 2 only. MT positive with respect to MT : If gate is made positive with respect to MT ; current starts flow 2 1 1from MT to MT . If gate is made negative with respect to MT ; then again current flows from MT2 1 1 2to MT ; but a larger gate voltage is needed for triggering the TRIAC.1

MT negative with respect to MT : If gate is made positive with respect to MT ; current starts to2 1 1 flow from MT to MT , but here also, a larger magnitude of gate voltage is needed for triggering. 1 2If gate is made negative with respect to MT ; the current flow from MT to MT is triggered, with1 1 2a much smaller magnitude of gate voltage.

J1J2J3

P1N1P2

N2

N3 N4

gateMT1

MT2Fig 2.4

S

MT1

MT2

Fig 2.5 (a)

0-500mA

I II II I

Lamp

I L R 2

V2 (2.5-35V)

VT2T1 0-50V

V 1 (1.5-15V)

VG

G

0-20V

IG R 1

MT2

MT1

Gate (G)MT1 (main terminal 1)

MT2 (main terminal 2)

Symbol:

Fig 2.5 (b)

0 - 25 mA

10

+

-

V (t)=V Sin tS m

+

-

gate signal Vg

R

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2.5. PROCEDURE:

V-I CHARACTERISTICS:

1. Initially keep all control pots at minimum position. 2. Adjust gate current I to some constant, say 10mA, by varying V or G 1 gate current potentiometer R . 1 3. Now slowly vary V and note down corresponding VT T & I readings for every 2 2 1 L 5V. 4. Vary V till TRIAC conducts. This can be identified by sudden drop VT T1 2 1 and rise of I . L Same procedure is also repeated for reverse direction by reversing the polarity of V2 Same wave from is obtained in reverse direction also.

TO FIND V /I : (Table 4)G G 1. Adjust V to zero and set VT T to some value say 10V.1 2 1 2. Slowly increase V till TRIAC conducts. 1 3. Note down corresponding V and I values. G G

FOR LATCHING CURRENT:

FOR HOLDING CURRENT:

1. Initial settings: R potentiometer: Minimum resistance position. 1 V : zero1 R potentiometer: Small value2 V :10V2 2. Gradually increase V till TRIAC is on (I suddenly increases). Note I . 1 A A 3. Now make V by opening gate- MT circuit. If I is unaffected, I > latching 1 1 A A current. 4. Assuming I to be greater than latching current, repeat steps (1) to (3); with an A increased value of R . For some I opening gate- MT circuit will cause I to go to 2 A 1 A zero. This is the latching current of the TRIAC.

1. Initial settings: a) potentiometer R : maximum resistance position 1

b) Source V minimum voltage position.1: c) Potentiometer R : Approximately half the value.2 d) Source V : 10V2 e) TRIAC off 2. Slowly increase V till TRIAC remains off. Then reduce V to zero. 1 1 3. If TRIAC current is less than latching current; TRIAC turns off. In that case, either reduce resistance R , or increase voltage V (or both); and repeat step (2), until you get 2 2 an anode current greater than the latching current at the end of step (2). 4. Now decrease the anode current ( by increasing R , decreasing V , or both ) slowly and 2 2 note the current at which the TRIAC if off. ( Anode current suddenly decreases nearly zero). This is the holding current and should be lesser than latching current.

11

(Refer to fig. 2.5)

(Table 3)

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2.6. TABULAR FORMS:

IG = mA

VT2T1Volts

ILmA

Table 3

= VVG

VoltsIG

mA

Table 4

VT2T1

2.7. WAVEFORMS:

DIAC Characteristic:

3.1. AIM: To study the V-I characteristics of DIAC.

3.2. APPARATUS: 1. DIAC ( DB-3) characteristics trainer 2. Ammeter 0-25mA dc 3. Voltmeter 0-50V dc 4. Patch chords

VBR-VB01 -Va

-IL

+IL

Ig2 Ig1 Ig0 = 0

-Ig0 -Ig1 -Ig2Quadrant III(MT2 negative, positive)MT1

mA

Quadrant I(MT2 positive, negative)MT1 Ig2 Ig1 Ig0v v

+Va

Fig 2.6

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3.3. THEORY:

(Refer to fig 2.9) At voltage less than V a very small amount of leakage currentBO1 flows through the device. This is not sufficient to conduct the device. So the state 0-A is called blocking state. Whenever voltage reaches break-over voltage it starts conducting with VI characteristics as shown. The value of current corresponding to point is A known as break over current. For negative half cycle the characteristics is similar. Once the device turns on, it can carry a high current with only a small voltage drop across it. DIAC is mainly used to trigger TRIAC. When the current through the switch fall below the holding current, the DIAC goes off. 3.4. CIRCUIT DIAGRAM:

A DIAC is a two terminal device which can conduct in both directions. It has no triggering mechanism to initiate conduction, and in this respect it is similar to a piece of ordinary conducting wire. But unlike a wire, it can block up to 30V in either direction before it starts conducting.Once it is conducting, there is a small ( about 3V) voltage drop across the device.

MT1 (main terminal 1)

MT2 (main terminal 2)

Symbol:

N3P1N1P2

MT1

MT2

P1

N1

P2 N2

N3

MT2

MT1

P1N1P2N2

Fig 2.7

I

V2 (2.5V-35V)

0-25mA

V 0-50V

R 2 I II II I

Fig 2.8

Lamp

13

MT2

MT1

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3.5. PROCEDURE: (Refer to fig 2.8; Table 5)

1. Keep V at minimum position and R at maximum position. 2 2 2. Switch ON and vary V in steps of 5V and note down corresponding ammeter 2 reading I . o 3. At a particular value of voltage, device conducts as indicated by the sudden rise in ammeter reading and sudden fall in the voltage across the device. This is known as break-over voltage of the device. 4. If start of conduction is not clearly observable; repeat steps (3) and (4) with a reduced value of R .2 5.Repeat the same procedure in reverse direction, that is by changing MT connections 1 to MT . We obtain the same readings as in forward bias, note down and draw a 2 graph, Graph is similar to both in forward and reverse directions.

3.6. TABULAR FORMS:

3.7. WAVEFORMS:

VVolts

ImA

Table 5

Conduction stateFor negative halfcycle

Conduction stateFor Positive halfcycle

Blocking State

mA

VBo2VBO1

I Bo

I Bo

+Ia

-Ia

+Va

-Va

14

oA

Fig. 2.9

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MOSFET Characteristic:

4.1. AIM: To study the output and transfer characteristics of MOSFET.

4.2. APPARATUS: 1. MOSFET ( IRF 540) characteristics trainer 2. Ammeter 0-500mA dc 3. Voltmeters 0-50V dc 0-20V dc 4. Patch chords

4.3. THEORY:

MOSFET is a power electronics device with three terminals called Gate, source and drain. (Similar to the base, emitter, collector respectively of a transistor). A control voltage is applied between the gate and source; with gate positive for N channel enhancement type MOSFET and gate is negative for P channel type MOSFET. Because of the high impedance that the device offers between the gate and the source; it draws virtually zero current from the signal connected between the gate and source. Hence it is called a voltage controlled device. In MOSFET, current flow is either due to flow of electrons or flow of holes, but never due to both.Hence it is called unipolar.

N

Fig 2.10

P

N

Drain

Gate

Oxide Layer

Source

Substrate

Gate (G)

Source (S)

DRAIN (D)

Symbol:

Substrate

15

Output Characteristics: Refer to fig 2.12(b)

The output characteristics of MOSFET indicates the variation of drain current I as a function of drain-source voltage V with V as a parameter. For lowD DS GS value of V the graph between I -V is almost linear, this indicates a constantGS D DS value of ON resistance R = V /I . At very low value of drain-source voltage theDS DS D device has constant resistance characteristics. But at high value of drain source voltage, the current is determined by the gate voltage. For low V , graph linearDS but V is increased output characteristics is relatively indicating that drain currentDS is nearly constant. A load line intersects the output characteristics at point A& B. Here A indicates fully ON condition, B indicates fully OFF condition. So it behaves as a switch.

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Transfer Characteristics: Refer to fig.2.12(a) This transfer characteristic shows the variation of drain current I as aD function of gate source voltage V , here V is the threshold voltage. Below thisGS GST voltage, the device turns off. The magnitude of the threshold voltage is of the order of 2 to 3V.

4.4. CIRCUIT DIAGRAM:

4.5. PROCEDURE: Refer to fig. 2.11 TRANSCONDUCTANCE: (Table 6) 1. Initially keep all the voltages and potentiometers at minimum positions. 2. Set V to some value say 10V. DS 3. Slowly vary the gate-source voltage V by varying V .GS 1 4. Note down I -V readings for every 5V.D GS 5. The device will turn on at some voltage. This voltage is called threshold voltage VGST. 6. If V < V small leakage current flows from drain to source.GS GST 7. If V > V drain current depends on the magnitude of gate voltage.GS GST 8. Repeat the above procedure for V . = 20 & 30 V.DS

16

0-500mA

VDS 0-50V

R 2 I II II I

Fig 2.11

Lamp

I D

V1 (1.5-15V) VGS 0-20V

V2 (25or2.5V)

MOSFET

D

S

G

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OUTPUT OR DRAIN CHARACTERISTICS: (Table 7) 1. Initially set V to some value say 3V by varying V .GS 1 2. Slowly vary V and note down I & V . 2 D DS 3. At particular value of V , there is pinch off voltage (V ) between Drain and GS P Source. 4. If V < V device works in the constant resistance region and I is directly DS P D proportional to VDS. 5. If V > V then I flow from the device and this is known as constant current DS P D region. 6. Repeat the procedure for different values of V and note down the readings. GS

4.6. TABULAR FORMS:

4.7. WAVEFORMS:

Table 6

At VDS = 10 V

VGS Volts ID mA

At VDS = 30 V

VGS Volts ID mA

Table 7

At VGS = 3 V

VDS Volts ID mA

At VGS = 3.6 V

VDS Volts ID mA

Fig: 2.12

VGS 7

VGS 7 > VGS 6...........>VGS 1

VGS 6

VGS 5

VGS 4

VGS 3

VGS 2

VGS 1

A

DrainCurrent.I (mA)D

Drain Source Voltage VDSOut put characteristics

I D(mA)

Transfer Characterisitics2 4 6 8 10

VGS T

V (Volts)GS

17

Load Line

B

(a) (b)

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IGBT Characteristic:

5.1. AIM: To study the output and transfer characteristics of IGBT.

5.2. APPARATUS: 1. IGBT (IRGBC 20S) characteristics trainer 2. Ammeter 0-500mA dc 3. Voltmeters 0-50V dc 0-20V dc 4. Patch chords

5.3. THEORY: The Insulated Gate Bi-polar Transistor (IGBT) is a voltage controlled device that combines the advantages of both MOSFET & BJT. That is the fast acting feature and high power capability of the bipolar transistor, with the voltage control feature of the MOSFET. Its emitter characteristics are similar to those of the bipolar transistor and control features are those of MOSFET. It has high input impedance like MOSFET.

VI Characteristics: Static VI characteristics of an IGBT show the plot of collector current I versus collector emitter voltage V , for various values of gate emitter C CE voltages. In VI characteristics of IGBT in forward direction, the shape of the output characteristics is similar to that of BJT. But here the controlling parameter is gate emitter voltage V , because IGBT is a voltage controlled device. GE Refer to fig. 2.15 In forward conducting mode, positive voltage is applied to the collector of the device with gate short circuited to the emitter terminal then the device operates in its forward blocking mode. Then the positive gate to emitter voltage applied of sufficient magnitude then the device switches in to forward conducting state. In forward conducting state, the device characteristics are similar to that of a forward biased P-N diode. This continuous up to gate-bias voltage sufficiently larger than the device forward current will saturate by increasing gate- bias voltage this state the device will operate it is active region. To turn off the device, remove the gate-bias voltage, then the collector current decays gradually and device becomes off. Actually the current flow cannot occur when negative voltage is applied to the collector with respect to the emitter, hence the device has reverse blocking capability.

(G) Gate

(E) EmitterFig 2.13

(C) Collector

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Transfer Characteristic: Refer to fig. 2.15(b) This is the plot of collector current I versus gate-emitter C voltage V . This characteristic to identical to that of MOSFET characteristic. GE When V is less than V (threshold voltage), the device is in off state, after that GE GET it is in ON state.

5.4. CIRCUIT DIAGRAM:

5.5. PROCEDURE: Refer to fig. 2.14 TRANSFER CHARACTERISTICS: (Table 8) 1. Initially keep all the voltages and potentiometers at minimum positions. 2. Set V to some value say 10V. CE 3. Slowly vary the gate-emitter voltage V by varying V .GE 1 4. Note down I -V readings for every 0.5V.C GE 5. The device will turn ON at some voltage. This voltage is called threshold voltage VGET 6. If V < V , small leakage current flows from collector to emitter.GE GET 7. If V > V , collector current depends on the magnitude of gate voltage.GE GET 8. Repeat the above procedure for V . =20 & 30VCE

VI CHARACTERISTICS:(Table 9) 1. Initially set V to some value say 5V by varying V .GE 1 2. Slowly vary V and note down I & V . 2 C CE 3. At particular value of V , there is pinch off voltage (V ) between drain and GE P source. 4. If V < V , device works in the constant resistance region and I is directly CE P C proportional to VGE. 5. If V > V , then I flow from the device and this is known as constant current CE P C region. 6. Repeat the procedure for different values of V and note down the readings. GE

0-500mA

VCE 0-50V

R 2 I II II I

Fig 2.14

Lamp

I C

V2 (2.5-35V)

0-500mA

V 1 (1.5-15V) VGE

0-20V

19

C

GE

Griet

5.6. TABULAR FORMS:

5.7. WAVEFORMS:

Fig: 2.15

RESULT: Characteristics of SCR, TRIAC, IGBT, MOSFET and DIAC are verified.

Table 8

At VCE = 10 V

VGE Volts IC mA

At VCE = 30 V

VGE Volts IC mA

Table 9

At VGE = 5.0 V

VCE Volts IC mA

At VGE = 5.4 V

VCE Volts IC mA

VGE 7VGE 7 > VGE 6...........>VGS 1

VGE 6

VGE 5

VGE 4

VGE 3

VGE 2

VGE 1

0

VRM

IC(A)

VCE

I C(A)

Transfer Characterisitics (b)

VGE T VGE

20

VI Characteristics (a)

Griet

1. AIM: To study resistance triggering of thyristor.

2. APPARATUS: 1. Universal Power Electronic Trainer Kit. 2. 230V, 15W bulb. 3. 560, 250W. 4. CRO 3. THEORY:

3.1) Consider the half cycle 0 < t< for the supply voltage V (t)= V sin t. In the s m initial part of this half cycle, the voltage V is very small, and the SCR is in off state. s I =0 and i =I, the small current flowing through the resistance R , R and R ; V 0 A L 1 2 b l and V (t) V sin t = V (t).AK m s

3.2) As t increases V (t) increases; and the SCR anode becomes more and more AK positive with respect to cathode. Simultaneously, V (t); the voltage between the GK gate and cathode increases, making the gate more positive with respect to cathode.

3.3) These larger anode-cathode, and gate-cathode voltages cause the SCR to turn on at some instant 0 t . Once it turns on; V reduces to nearly zero, and the AK supply voltage gets applied across the load. The SCR continues to conduct till the current through it tends to reverse; at which point of time the SCR turns off. For a purely resistive load, turn off occurs at t = . For an inductive load, current lags behind the voltage and turn off occurs at a later instant.

3.4) The maximum value that V can attain, if the SCR does not turn on, is V at AK m t = . At this instant, V also is maximum. Suppose this maximum value of VGK GK cannot turn on the SCR with its anode to cathode voltage maximum. As t increases beyond , both V and V decreases, and so the SCR can ever turn AK GK on. In resistance triggering, maximum firing angle that can be obtained is 90.

pi

pi/2

pi

pi/2

pi/2

Experiment 3R-TRIGGERING

K

A

G

+

VGK

VAK

+

_

_

Fig -3.1

21

Griet4. CIRCUIT DIAGRAM:

3.5) To achieve a firing angle less than 90; the resistance R must be decreased. This 2 increases V for a given V ; and hence SCR turns on at a lesser V GK AK AK ( at t< ). Firing angle can thus be controlled from a little more than 0 to 90.

3.6) Once it is off , the SCR remains off till the next positive half cycle of the supply, when the turn on process is repeated.

3.7) Diode D prevents the current flowing in R , R , R branch during the negative half 1 2 b cycle of the supply voltage.

pi/2

Fig -3.2

22

K

V

VAK

_

+

_+

_

Load

R1

R2

R b

+I

I i

g

L

VGK

o

A

C

TYN 612

D

K

V

VAK

_

+

_+

_

Load

R-Load230V, 60W bulb

R1=10K, 3W

R2= 100k, 3W

560W0.25W

Rb

+

I

I IL

Vg

o

A

G

TYN 612

D

Fig- 3.3

IA

G

iA

G

Vs = Vm V Sint

Vs = Vm V Sint

Griet

5. PROCEDURE: 5.1. Connect the circuit diagram as shown in figure. 5.2. Initially keep POT at minimum position. 5.3. Vary the POT and observe the lamp glowing. 5.4. Observe the waveforms across thyristor, supply and load with potential divider on CRO.

6. RESULT: By using resistance triggering, the thyristor is triggered and corresponding firing angle is noted.

23

VM

o

-Vm

+Vm

+Vm

VT

-Vm

tSupplyVolatage2 3 4 5

a

Ig

Load Voltage

7. WAVEFORMS: (Resistive load assumed)

Fig- 3.4

t

t

t

Griet

1. AIM: To study resistance -capacitance triggering of thyristor.

2. APPARATUS: 1.Universal Power Electronic Trainer Kit. 2.230V, 15W bulb. 3. 4.7K, 0.25W. 4. 0.2F Capacitor. 5. CRO

3. THEORY:

3.1) Like R-triggering, RC triggering can also be used along with an AC supply voltage to turn on an SCR during every positive half cycle of the supply. But, unlike in R

o o triggering, the firing angle in RC triggering can be varied from 0 to 180 (nearly).

3.2) C, D , and R of fig.4.1 are in series across the ac source, which circulates a current 2 L in the ACW direction in the loop containing these elements. For this direction of current, D in ON and shorts the potentiometer R. The voltage drop across R 2 L caused by this current is small and can be neglected. So, all the supply voltages appears across C; V =V and V reaches the value V at t=-/2, as shown in the C S C m figure 4.2.

3.3) Period: - /2 t 0: The voltage (V -V ) drives a current in the clockwise direction through R and R. C S L For this direction of current, D is in open circuit, and if R is large; the capacitor has 2 a large time constant. The voltage across C decreases in magnitude at a small rate as shown in the fig.4.2.

Experiment 4RC-TRIGGERING

C

R

Vc VGK

VAKD2

D1

T1

VoR- Load

+

+

++

+

-

-

--

-

Fig- 4.1

24

A

K

c

RL

Vs = Vm V Sint

Griet

b

4. PROCEDURE: 5.1. Connect the circuit diagram as shown in figure. 5.2. Initially keep POT at minimum position. 5.3. Vary the POT and observe the lamp glowing. 5.4. Observe the waveforms across thyristor, supply and load using potential divider circuit on CRO.

3.4) Period: 0= t= : In this period a) V is positive and anode of the SCR is +vewith respect to the cathode.S

) At the same instant during this period, V assumes a positive value just sufficient C to turn on the SCR taking into account the anode-cathode voltage of the SCR at that instant. This instant is represented by t= . Since V is always applied between C gate and cathode through D ; the SCR torns ON at t= .Once the SCR turns ON C 1 discharges through D and the SCR, and V becomes zero. The triggering process 2 C is then repeated for t2 ; 3 t4 and so on.

V

Vo-Vm

+Vm

+Vm

o

VT1

-Vm

P/2

RC triggering waveformss

o

Fig- 4.2

25

A

OB

C

t

t

t

t

2 3 4

Griet

Fig- 4.4

Vm

-Vm

-Vm

+Vm

0

-P/2

2

2 3 4

Supply voltageVs

V0

Output Voltage

5. CIRCUIT DIAGRAM:

6. RESULT: By using resistance-capacitance triggering, the thyristor is triggered and corresponding firing angle is noted.

7. WAVEFORMS:

C, 0.2mFVc+

+

+

+

-

-

-

-

D1IN4007 100 k3W

R2

D2

R1 4.7K0.25W

TYN612 VAK

GK

R-Load

Lamp230V, 60W

230 V50 Hz1-AC

IN4007

26

A

KFig- 4.3

G

Voltageacrossthyristor

t

t

t

2 3

3

Griet

1. AIM: To study 1. The UJT oscillator triggering 2. Ramp triggering 3. The ramp and Pedestal triggering

2. APPARATUS:1. Universal Power Electronic Trainer Kit. 2. CRO. 3. UJT 2N 2646. 4. Zener diode No.20V, 1W. 5. Resistors 560 2W. 560 0.25W.- 2 Nos. 6. 0.2F Capacitor.

3. THEORY:

3.1) The symbolic representation of the UJT is given in fig 5.1

Fig. 5.2 is a representation of UJT when it is held in hand with the connecting leads facing the viewer. The terminals E, B B are marked in the fig.5.2 The distance between1, 2 B and B is high compared to others.1, 2

Experiment 5UJT TRIGGER CIRCUITS

(Emitter)

B1 (base 1)

B2 (base 2)

E

Fig-5.1

2N2646E B1

B2

Fig- 5.2

27

Griet

The operation of the UJT is explained using the circuit of fig-5.3. R , R and the B1 B2 diode D are internal to the UJT. V , R , R and V . Are externally connecteds 1 2 EG

When V is kept at zero volts, the current EG

Fig-5.3

ED

R1

R2

B2

B1

Vs

Vo+

+

-

-VD

I

VRB1

+

+-

-

V and V have the values IR and IR respectively. RB1 o B1 1 V = - ( V + V ) a negative quantity. So I = 0D RB1 o E Now let V be increasedEGV = (V - ( V + V ))D EG RB1 o

Becomes less negative., But till V reaches zero value I remains zero and V D E RB and V are unchanged. When V reaches the value - ( V + V ), V becomes 0. o EG RB1 o D I starts flowing and due to internal changes in the UJT, R becomes 0, V E B1 o becomes equal to V .EG

3.2) The UJT Oscillator Circuit:

In a UJT oscillator circuit, the variable voltage source V (fig 5.4) is made up of a EG capacitor(C) which is charged by an external source through a resistance(R).

R

R2

B2

A

Vs

Vc

B

B1

R1Vo (t)

IE E

+

-

+

+

-

-

C (t)

Fig-5.428

Rb2

Rb1

IE

VEG

Griet

Fig- 5.4 gives the UJT oscillator circuit, in which the capacitance is charged by the voltage source V through the variable resistance R. Till it reaches the required s value, I remains zero. The UJT is an open circuit for C. When V reaches the E c required value, the UJT suddenly becomes conducting, R becomes zero and R B1 1 gets directly across C. C discharges quickly through R (R has a small value) and 1 1 V decreases to small value. Now the UJT again becomes open, and C starts getting c charged again by V through R. Typical waveforms of V (t) and V (t) are shown s c o in fig-5.5.

3.3) Ramp triggering:

This is also called synchronized UJT triggering. The V (t) pulses of fig-5.5 are o usually used to trigger thyristor in power electronics circuit which have the AC source. These pulses must therefore be synchronized with AC source. For example, a pulse may be required degrees from every zero-crossing of an AC sinusoidal voltage. A circuit to achieve this is given in fig 5.6.

Triggering Pulses

Time Constant RC

Vc(t)

V0(t)

Fig- 5.5

Fig-5.6

D1

Vs

+ -

D3

A

B

+

-

D4 D2

I VR1+ -

1

+

-

VZ

ER 1

29

m E Sint

The voltage source V to the right points of A and B in fig-5.4 is replaced by the s circuit of fig 5.6. Waveforms of the AC voltage V ,voltages after diodes the zener s diode voltage V are shown in fig 5.7, from which it is evident that theses twoz waveforms have a definite phase relationship. It is the voltage V which charges z the capacitance of the UJT circuit and so the trigger pulses from the UJT bear a finite phase relation with V , and hence with the ac voltage V . Pulse output z s voltages are shown in fig 5.7.

Fig5.7 also gives the waveform of the voltage across R , assuming terminals A&B 1 are open. V is determined by the zener diode. (V -V ) is the voltage appearing z s z across R . A large R will reduce the current due to this voltage across R .1 1 1

The zener voltage goes to zero at the end of every half cycle of the supply voltage. So, the RC circuit starts with zero voltage across it every half cycle. Hence, the trigger pulse occurs a fixed time after every zero crossing of the supply voltage, and synchronization is achieved.

GrietVoltageafterdiodes

VZ1=Em-VZ

2

+ Vm

+ Vm

- Vm

VZ1

Output of Pulse Transformer

Fig- 5.7

30

Vs = m V Sint

t

t

t

Griet

3.4) Ramp and PedestalTriggering:

Across the terminals A and B (zener diode terminals) of fig 5.6, a resistance R is 2 connected, which serves as a potential divider. The is shown in fig 5.8. When V reaches the V early in the half cycle of the AC supply voltage, the diode z z D enables C to be charged to a voltage V (pedestal voltage) very quickly. There after, 1 PD C gets charged through R and V increases beyond V . When V reaches the c PD c required value, the UJT is turned on and one pulse is obtained. In this type of triggering, a large value for V means that the triggering pulse PD occurs earlier. So the setting of the slider R controls the output pulse timing.2

3.5) Pulse Transformer:

Pulse transformers are often used in the firing circuits for SCRs. These transformers have three windings: one primary and two secondaries. The three windings usually have the same number of turns each. The windings are designed to have low resistances, low leakage reactance and low inter -3winding capacitances.

If the magnetizing inductance of the transformer is small (this can be easily achieved by using air core, which reduces the weight), the input and output voltages waveforms will be as in fig 5.9

+

-

+

-

VZR2

D1

VPD

R

C

+

-

VcToUJT

Fig-5.8

Fig-5.9

Input voltage to pluse transformer primary

output at a secondary of the pulse transformer

31

Griet

The positive pulses only will be useful in triggering SCRs. The negative pulses can be removed, if desired, using suitable clipping circuits. The pulse transformer provides an electrical isolation between the primary side and secondary sides which is needed in power electronics.

4. CIRCUIT DIAGRAM:

10 K3W

B2

UJT 2N 2646

560W , 0.25 W

B1

Vo 560W, 0.25 WTo CRO

15 VDCSupply

100K3W

0.1mFVc

+

- -

-

-

+

E

+

+

Fig- 5.10

IN 4007

+ -

Vs

20 V, 1WZener

IN 4007

IN 4007

560 ,2W

IN 4007

1 MW

IN 4007

B2

UJT 2 N2646

560W , 0.25W

B1

560W, 0.25 WTo CRO

100K W3W

0.1mF

E

+

-

30 V, 50 Hz1-f,AC

Fig- 5.12

10 kW3WIN4007

+ -

Vs20 V, 1WZener

IN4007

IN4007

IN4007

560W ,2W

B2

UJT 2N2646

560W, 0.25 W

B1

560W, 0.25 WTo CRO

100k W3W

30 V, 50 Hz1-f,AC

0.1mF

E

+

-

Fig- 5.11

32

Griet

5. PROCEDURE:

5.1) UJT Oscillator:

1. Connect the oscillator circuit as shown if fig.5.10. 2. Observe the V and V waveforms on the CRO as the 100K POT is varied. Note c o the waveforms for one position of the 100K POT.

5.2) Ramp Triggering Circuit:

1. Connect the oscillator circuit as shown if fig.5.11. 2. Observe the waveforms of the output voltage and zener voltage on the CRO as the 100K POT is varied. Note the waveforms for one position of the 100K POT.

5.3) Ramp and Pedestal Triggering:

1. Connect the oscillator circuit as shown if fig.5.12. 2. Observe the waveforms of the output voltage and zener voltage on the CRO as the 100K POT is varied. Note the waveforms for one position of the 100K POT.

5.4) Pulse Transformer:

1. Connect the primary of the pulse transformer across 560. 2. Observe the primary and secondary voltages of the pulse transformer for different positions of the 100K POT.

6. RESULT: The pulses useful for triggering of thyristor are generated by using UJT triggering.

33

Griet

1. AIM: To study the generation of extended pulse for RL- load using UJT triggering. To make PCB for the circuit.

2. APPARATUS:1. Universal Power Electronic Trainer Kit. 2. CRO. 3. UJT 2N 2646 - 1 No. 4. Zener diode No. 20V, 1W. -1No. No. 10V, 1W- 2 Nos. 5. Resistors 33K 2W.- 2Nos. 15K, 2W - 2Nos. 22, 2W - 2Nos. 33, 2W - 2Nos. 560, 0.25W.- 2 Nos. 6. POT 470 K 1W - 1No. 7. Pulse Transformer No. 2503-1No. 8. Transformer 230V / 30V, 500mA, 1- , 50 Hz -1No. 9. Thyristor No. TYN 2P4 - 2Nos. 10. Capacitor 0.02F - 2Nos. 0.01F - 2Nos.

Experiment 6EXTENDED PULSE USING UJT TRIGGER

34

3.1) Extended pulse: UJT circuits (for example UJT ramp triggering circuit) give a narrow pulse as the output. Such a pulse is sufficient to turn on a thyristor, if the load is resistive. But consider an inductive load; the load current needs time to reach latching value( since an inductance delays current changes). If the gate cathode pulse goes to zero before this time; the SCR turns off as soon as the pulse is over. So, when an SCR is used with an inductive load, pulses of larger duration are needed. These are called extended pulses.

3.2) Circuit to produce extended pulse: Operation of the circuit: Refer to fig 6.1, 6.3 During 0 < t< when V (t) is positive, a pulse of V (t) occurs at t= . Before this s i instant, the SCR is off and there is no current in the circuit. Both SCR and the zener are off, and V (t)=V (t)-V (t). Since they are off; both the SCR and the zener act like s a z

high resistances, and share the total voltage V (t) in proportion to their resistances. sV (t) is positive, and the SCR turns on at t= ; .when the gate pulse occurs it a

remains on for the rest of the half cycle, with V (t)=0. The SCR is ON,when t= . a At this time, let V (t)= V ; V < E. The SCR is on then the current through the circuit is s 1 1 still zero and V (t) appears across the zener with V (t) = -V (t).s z s

pi

3.THEORY:

Griet

The SCR is ON When V (t) reaches E; the zener is on; and the output voltage stayssat E as long as V (t) remains greater than E. Subsequently, it follows the V (t) s swaveform for the rest of the half cycle. During the half cycle < t< 2 ; the zener is forward biased and has zero voltage across it, V (t)=0. Since V (t)=V (t);o a sV (t) is negative; V (t) also is negative and the SCR does not conduct, even when s atriggered.

4

pi pi

. PROCEDURE: 4.1. Make a PCB for the circuit shown in the fig 6.2. 4.2. Observe the waveforms of the output voltage on CRO.

5. RESULT: The pulses useful for triggering of thyristors in inductive circuit are generated by using UJT triggering.

35

Fig.6.1

V (t)=V Sin tS m

Va (t)+

-

Vo (t)+

-

+

-

R VR (t)+

-

Vi (t)+

-

Vz (t)+

-

Output pulses

Griet

5. CIRCUIT DIAGRAM:

IN 40

07IN

40

07

1-,

230

V, 50

H

ZAc

Su

pply

20 V,

IW

Zen

er

33 K

W2W

IN 40

07

B2

UJT

2 N

2646

560W

, 0.

25 w

B1 560

W, 0.

25 W

15 KW 2W 470

K

1W Pot

0.02

mF

E

IN 40

07

Fig-

6.2

36

33W

, 2W

22 W

2WTYN

2P4

10 V

Zen

er

IW

22W

2W 33W

, 2W

TYN

2P4

230V

/12-

0-12

V

10V

Zen

er

IW

0.01

m F

0.01

m F

1-,

230

V, 50

H

ZAc

Su

pply

Vs =

mV Sin

t

Griet

6. WAVEFORMS:

Fig- 6.3

Supply voltage

UJT EXTENDED PULSE WAVEFROMS

Zener voltage

0

+Vm

-Vm

Vc

VZ

Pulse Transformer

Output trigger pulse 2

voltagel aftercliodes

Capacitorvoltage

Output trigger pulse 1

2

37

Griet

1. AIM: To study the performance of a single phase half wave controlled converter with R-load.

2. APPARATUS: 1. Universal Power Electronics Trainer Kit 2. UJT Triggering Circuit 3. CRO

3. THEORY:

4. CIRCUIT DIAGRAM:

5. PROCEDURE: 5.1. Connect the PCB and observe the extended pulse on CRO. 5.2. Connect the observed pulse to the thyristors between gate and cathode. 5.3. Connect the circuit diagram as shown in figure. 5.4. Observe the waveforms across load, thyristor and supply using potential divider on a CRO.

Refer to fig 7.13.1) In the period 0 < t ;let the SCR be of .Then current through the load, and voltage drop across the load are zero, and all the supply voltage appears between the anode and cathode of the SCR; and the SCR is forward biased.

3.2) Let it be triggered at t= (0 ). Because of the forward bias, it turns on; and the voltage across the device drops to zero( neglecting the small voltage drop across the device when it conducts). Supply voltage appears across the load; causing a load current V (t)/R where R is load resistance in ohms.s L L

3.3) During the remaining part of the half cycle t ; V (t) is positive , the load s current is positive, and the SCR continues to be on. When the load current tends to reverse ( at t= ); the SCR turns off.

3.4) The SCR continues to be off from t= up to t= (2 );when it is turned on again, and the cycle repeats. Wave forms of the supply voltage V (t); the gates cathode triggering signal V (t); and the load voltage V (t); can be plotted from the gk o above .

pi

pi

pi

pi

pi pi+

Experiment 71- HALF CONTROLLED CONVERTER WITH R-LOAD

1-f, 50 HZ230 V Ac Supply

V (t)=V Sin tS m

230V, 60 W Bulb Vo

To CRO

T1

V T1

+

-

+ -

-

+

R-Load

Fig-7.1

38

Griet

6. CALCULATIONS:

Firing Angle = Peak Value of the Supply Voltage (Vm) = Average value of Load Voltage =

R.M.S.Value of Load Voltage =

7. RESULT: The performance of a single phase half wave controlled with R-load is verified and firing angle, average and rms value of the load voltages are calculated.

8. WAVEFORMS:

2 3

2 3

+ Vm

-Vm

V T1

V0

-V m

OSupply Voltage

0

Fig- 7.2

39

t

t

t

Griet

1. AIM: To study the performance of a single phase half wave controlled converter with RL-load.

2. APPARATUS: 1. Universal Power Electronics Trainer Kit 2. 12V DC motor 3. CRO 4. 1, 10W resistor, 5.Diode-IN4007.

3. THEORY:

Refer to Fig 8.1

3.1) Shows a single phase half wave controlled converter with an input voltage of V Sin t, and a permanant magnet dc motor as the load. A dc motor is an R-L-E m load. For just an RL load, the motor is to be replaced by one winding for a transformer(whose other winding is left open).

3.2) At t= (0< ), the thyristor is triggered and it turns ON. The input voltage which till this instant is across the thyristor, will now appear across the load and current starts flowing through the thyristors and the load.

3.3) If the load were purely resistive, the load current and the load voltage will be in phase. At t= ; when load voltage reaches zero, the load current also will reach zero. But since the load inductance opposes changes in the load current also will reach zero. But since the load inductance opposes change in load current at this instant load current is still greater than zero. Let the load current finally reach zero at t= , > . The SCR then remains ON from t= to t= and the output voltage

becomes veduring the period t= to t= . This negative voltage across the load while the current through it is positive implies that part of energy stored in the inductance of the load is returned back to the supply. The rest of the stored energy of the inductor is dissipated in the load resistance.

3.4) Fig.8.2.is identical with fig.8.1.except for the free wheeling diode FWD across the load .FWD does not permit the load voltage to be negative .Hence, in the period from t= to t= ; a) load current flows through the free wheeling diode and load voltage is zero and b) SCR current is zero, the SCR is reverse biased , and it turns off. Energy in the inductance has to be dissipated only in the load resistance and is larger than when a free wheeling diode is not used. If the inductance is large enough; the load current may persist till t= 2 + ; at which instant the SCR is triggered again.

pi

pi

pi pi

pi

pi

Experiment 81- HALF CONTROLLED CONVERTER WITH

RL AND RLE-LOAD

40

-

Griet

4. CIRCUIT DIAGRAM:

5. PROCEDURE:

5.1. Connect the PCB and observe the extended pulse on CRO. 5.2. Connect the observed pulse to the thyristors between gate and cathode. 5.3. Connect the circuit diagram as shown in figure, 8.1 and 8.2 5.4. Observe the waveforms across load, 1 resistor, thyristor and supply with and without FWD on CRO.6.1 CALCULATIONS (WITHOUT FWD):

Firing Angle = Extinction Angle =Conduction Angle =-Peak Value of the Supply Voltage (Vm) =

Average Value of Load Voltage =

R.M.S.Value of Load Voltage =

6.2 CALCULATIONS (WITH FWD):

Firing Angle =Peak Value of the Supply Voltage (Vm) =

Average Value of Load Voltage =

R.M.S.Value of Load Voltage =

1-, 50 HZ15v, AC Supply

IN 4007

FWD To CRO

1,10W To CRO

MOTOR

+

-

A K

G

Fig-8.2

1-, 50 HZ15v, AC Supply

V (t)=V Sin tS m

To CRO

1,10W To CRO

MOTOR

+

-

A K

G

Fig-8.1

41

Vm

Vm

Vm

Vm

Griet

7. RESULT: The performance of a single phase half wave controlled with RL-load is verified and firing angle, average and rms values of the load Voltage are calculated.

8. WAVEFORMS:

-Vm

+Vm

+Vm

SupplyVoltage

Vs

out putVoltageVo

VoltageAcross

Thyristor

O

VT1

2

2

3

3

4

4

Without Freeweeling diode

Fig- 8.3

VsSupplyVoltage

Vm

-Vm

Vm

VT

-Vm

out put Voltage

Vo

Voltageactross

Thyriston

2 3

Fig- 8.4

42

With Freeweeling diode

out putcurrent

Io

out putcurrent

Io

t

t

t

t

t

t

t

t

Griet

1. AIM: To study and test the performance of a single phase AC voltage controller with R-load.

2. APPARATUS: 1. Universal Power Electronics Trainer Kit 2. UJT Triggering Circuit 3. CRO

3. THEORY: Refer to Fig 9.1 and 9.2

3.1) When ac voltage is to be stepped down, transformer can do the job efficiently, and without introducing harmonics in the output voltage. We can also get reduced voltages by employing SCRs. These are useful in applications where harmonics in the output voltages are acceptable. The circuit is as shown in fig.9.1

3.4) As long as T is ON; the small positive value of V will keep T reverse biased and1 t1 2 OFF. A similar process takes place when T is turned ON in the negative half cycle of 2 the supply.

4. CIRCUIT DIAGRAM:

3.2) Then i) i (t) and v (t) are zero; and ii) V (t)= V sin t and V (t)= -V sin t. During o o T1 m T2 m the half cycle 0 t ; V (t) is positive while V (t) is negative. Thyristor T will T1 T2 1 turn on if triggered while T cannot. Similarly, during the half cycle t 2 ; it is 2 T that will turn on if triggered; while T cannot. 2 1

3.3) Let T be turned on t= in the half cycle 0 t From t= to t= ; the load 1 voltage V (t) and load current i (t) become V sin t and (V sin t/R ) respectively. o o m m L At t= ; i tends to become negative and T turns off. Now if T is turned on at t= o 1 2 + in the half cycle t 2 , and a non zero i (t) and v (t) will be obtained for o o + t 2 . The process is repeated for subsequent cycles of the supply.

pipi pi

pi pi

pi

pi pi pipi pi

Experiment 91- AC VOLTAGE CONTROLLER WITH

R-LOAD

R - LoadBulb, 230 V60 W

+

+

-

-

T1

T2

Fig-9.1

43

1-, 50 HZ15v, AC Supply

V (t)=V Sin tS m

V T1

+

- V T2Vo (t)

+

-

Io (t)

Griet

5. PROCEDURE:

0 5.1. Connect the PCB and observe the extended pulses with 180 phase shift on CRO. 5.2. Connect the observe pulses to the thyristors between gate and cathode. 5.3. Connect the circuit diagram as shown in fig. 5.4. Observe the waveforms across supply, load and thyristors using potential divider circuit on CRO.

6. CALCULATIONS:

Firing Angle = Peak Value of the Supply Voltage (Vm) =

R.M.S.Value of Load Voltage = Vm

7. RESULT: The performance of a single phase AC voltage controller with R-load is verified, firing angle and rms value of the load voltage is calculated.

8. WAVEFORMS:

Fig-9.2

+Vm

-Vm

-Vm

+Vm

VT1

VT2

2 3 4 5 Supply

Volatage

Output Voltage

44

t

t

t

t

Griet

1. AIM: To study and test the performance of a single phase AC voltage controller with RL-load.

2. APPARATUS: 1. Universal Power Electronics Trainer Kit 2. UJT Triggering Circuit 3. CRO 4. 1, 10W resister 5. 230/12V,500mA(lv) transformer to serve an RL load.

3. THEORY:

4. CIRCUIT DIAGRAM:

Refer to fig 10.1 and 10.2

3.1) 10.1 gives the circuit of on ac voltage controller with R-L load. Fig 10.2 gives the waveforms of various voltages and currents in the circuit.

3.2) Referring to fig 10.1, during the interval 0 t ; Let T be turned ON at t= 1 i =i starts building up through the inductive load R-L. V (t) becomes equal to V (t).0 T 0 s At t= ,V (t)=V (t) goes to zero ,but i (t) does not become zero because of the s 0 0 inductance L in the load. T continues to conduct beyond t= .Finally, i becomes 1 0 zero at t= ; where >

3.3) For the period ( t= ) to ( t= ); the load voltage V (t) is the source voltage V (t), 0 s and V (t)=0 .At ( t= ),i becomes zero and tends to be negative, T turns off, V (t) T1 0 1 0 becomes zero, V (t) becomes V (t) which is negative, and thus effectively turn off T .T1 s 1

3.4) From ( t= ) to ( + ); i (t) and V (t) remain zero .(It is assumed that 0 0

Griet

5. PROCEDURE:

0 5.1. Connect the PCB and observe the extended pulses with 180 phase shift on CRO. 5.2. Connect the observe pulses to the thyristors between gate and cathode. 5.3. Connect the circuit diagram as shown in fig. 5.4. Observe the waveforms across supply, load and thyristors on CRO.

6. CALCULATIONS:

Firing Angle = Extinction Angle = Peak Value of the Supply Voltage (Vm) =

R.M.S.Value of Load Voltage = Vm

7. RESULT: The performance of a single phase AC voltage controller with RL-load is verified, firing angleand rms value of the load voltage is calculated.

8. WAVEFORMS:

Fig-10.2

2 3 4

+ Vm

-Vm

Vo

VT1

VT2

O

=+

VS

46

t

t

t

t

Griet

Experiment 111- SEMI CONVERTER WITH R-LOAD

1. AIM: To study and test performance of a semi converter with R-load.

2. APPARATUS: 1) Universal power electronics kit. 2) UJT triggering circuit. 3) CRO.

3. THEORY: Refer to fig.11.1

3.1) Diode voltages V (t) and V (t) can never be positive. They can only be zero or 3 4 negative. (The anode to cathode voltage of an ideal diode can only be zero or negative).

3.2) KVL gives V (t) =V (t)-V (t); valid for any t.s 3 4

3.3) During the half cycle 0 < t , V (t) is positive. So V (t)-V (t) must be positive. In s 3 4 this half cycle at some instant, let V (t) be 10V. Then, at this instant, (V -V ) must s 3 4 be 10V. Satisfying the condition of 3.1, at this instant, V &V can possibly have the 3 4 values (0V & -10V) ;(-2V & -12V); & so on. We can argue that the pair of values V =0V and V =-10V is the only practically possible value. (Practically, there is a 3 4 small leakage current being delivered by the source V (t) through the diodes. This s current is a forward current in diode D , and so V must be 0).3 3

3.4) We can thus conclude that during the half cycle 0 t , V is 0, diode D acts as a 3 3 short circuit,V is negative and diode D acts as an open circuit. If we assume that 4 4 none of thyristors is ON, i (t) and V (t) will be zero. KVL then gives V (t) =0 and 0 0 3 V (t) =V (t), which is positive. Thus thyristor T is ready to turn ON if triggered. If 1 s 1 T is turned ON at t= in this half cycle, the load current flows through T , load, 1 1 D and the supply for the rest of half cycle. At t= , the current i tends to reverse 2 0 and T turns OFF.1

3.5) In the half cycle t 2; it is T that can turn ON and load current flows through 2 T , load and D .2 4

3.6) Waveforms of V (t), V (t),V (t),V (t), V (t), V (t), and i (t) for some value of s T1 T2 3 4 0 0 as shown in figure 11.2. It may be observed that for a purely resistive load, the fully controlled converter and half controlled converter yield identical load voltage and load current waveforms.

pi

pi

pi

47

Griet5. PROCEDURE:

0 5.1. Connect the PCB and observe the extended pulses with 180 phase shift on CRO. 5.2. Connect the observed pulses to thyristors between gate and cathode. 5.3. Connect the circuit diagram as shown in figure. 5.4. Observe the waveforms across supply, Load, Thyristor using potential divider circuit.

6. CALCULATIONS:

Firing angle = Peak value of supply voltage Vm =

Average load Voltage =

Rms value of load voltage =

7. RESULT: The performance of a single phase semi converter with R-load is verified and firing angle, average and rms values of the load voltage are calculated.

48

Vm

Vm

1-, 50Hz230 V AC Supply

T 2 T 1

D 4D 3

+

+

-

-

V (t)=V Sin tS m

R-Load230 V, 60wBulb

IN4007

TYN612

IN4007

TYN612

Fig-11.1

+

-

V (t)3 V (t)4

V (t)T1

+

-

V (t)T2+

-

+

-

V (t)0

V

i (t)o

4. CIRCUIT DIAGRAM:

Griet

8. WAVEFORMS:

49

Wt

Wt

Wt

Wt

Wt

Wt

VsSupplyVoltage

Vm

2

VT1(t)

VT2(t)

VD3

VD4

V0,I0

Griet

1. AIM: To study and test performance of a semi converter with RL-load.

2. APPARATUS: 1) Universal power electronics kit. 2) UJT triggering circuit. 3) CRO.

3. THEORY: Refer to fig. 12.1,12.2

3.1) Whenever both T and T are OFF, the following will be true:1 2 a) I (t) = 0. (No path for current to flow). 0 b) di /dt = 0 (since i (t) is zero continuously, this follows. This means that 0 0 Voltage across the inductance L is zero). c) v (t) = E. (from KVL).0

3.2) In addition to T and T both being OFF, if V (t) is +ve ( half cycles 0 t , 1 2 s 2 t 3 ,), V (t)=0, V (t)= -V (t); V (t)= -E, and V (t)= -E+ V (t). On the 3 4 s T2 T1 s other hand, if Vs(t) is ve( half cycles t , 3 t ,) V (t)=0,V (t)=V (t),V (t)= -E, and V (t)= -E -V (t).4 3 s T1 T2 s (All these relations can be shown using KVL).

3.3) Now consider the half-cycle 0 t , with T and T both off. V becomes 1 2 T1 positive when V (t) > E. Let it occur for t> . Then T will turn ON if triggered at s 1 t= , for any > . Let T1 be so turned ON. Then i (t) starts flowing through T , 0 1 the RLE load, D , and the supply. This current is opposed by E and so i reach zero 3 0 earlier than it would if E is zero. Let i reach zero at t= depending on the values 0 of E, L, and R, can be less than, equal to, or greater than . As an example, is considered to lie between and ( + ) in the waveforms of fig.12.2.

3.4) From t= onwards, both T and T will be OFF. T2 will be triggered at t= ( 1 2 + ), to cause another cycle of load voltage and load current, similar to those described in (3) above.

3.5) Waveforms of V , V , V and i are shown in fig.12.2. During the period s T1 0 0 t ; while the load current is not zero, the load voltage V is zero in this semi 0 converter circuit. (It would be negative in a fully controlled converter). Waveform of V is complementary to that of V .T2 T1

3.6) For an R-L Load, simply assume that E=0 in the above. Waveforms will get suitably modified.

2 4

,

Experiment 121- SEMI CONVERTER WITH RL-LOAD

50

4. CIRCUIT DIAGRAM:

110W

-

+

sT1

D4

T2

D3

R

LRLE Load

CurrentSense

V

TYN 612 TYN 612

IN4007 IN4007

15V,50 Hz,1- AC Supply

Fig-12.2

V (t)0

I (t)0

V (t)T1

-

+

V (t)4

-

+

V (t)T2

-

+

V (t)3

-

+

V

i (t)o

-

-

+

+

V (t)=V Sin tS m

V (t)0

-

+

E

51

Wt

Wt

Wt

VsSupplyVoltage E

-E

Vm

Vm

VT

Vo(t)

Io(t)

2

Fig-12.1

pi+pi+

E

Griet5. PROCEDURE:

0 5.1. Connect the PCB and observe the extended pulses with 180 phase shift on CRO. 5.2. Connect the observed pulses to thyristors between gate and cathode. 5.3. Connect the circuit diagram as shown in figure 12.1, and then as shown in fig. 12.2 5.4. Observe the waveforms across supply, load, thyristor, 1? resistor with and without free-wheeling diode on CRO. ( theoretically same result should be obtained with and without free-wheeling diode).

6.1 CALCULATIONS (for RL load):

Firing Angle =

Peak Value of the Supply Voltage ( ) =

Average Value of Load Voltage =

R.M.S.Value of Load Voltage =

For RLE load

Firing Angle =

Peak Value of the Supply Voltage ( ) =

Average Value of Load Voltage ( )pipi

COSVEV mAVG ++

+= 11

Vm

Vm

( ) ( )( )pi

2212

SinSinVm

( )pi

CosVm +1

52

Griet

7. RESULT: The performance of a single phase semi converter with RL-load is verified and firing angle, average and rms value of the load is calculated.

8. WAVEFORMS:Practical

+

2 3 4

Out putCurrent

+Vm

-Vm

SupplyVoltage

Vs

out put Voltage

Vo

+ 3 4

o

Fig-12.3

Fig-12.4

2

2

3

3

2 3 4

4

4

Out putCurrent

+ Vm

-Vm

+Vm

SupplyVoltage

Vs

out put Voltage

Vo

O

o

With Free Wheeling diode :-

Without Free Wheeling diode :-

53

+2

t

t

t

t

t

t

Griet

1. AIM: To study the operation of triggering of thyristors using 555 timer.

2. APPARATUS: 1. Universal Trainer Kit 2. CRO 3. 555 Timer 4. BC107 Transistor 5. 10V, 1W Zener 6. Resistor 250 10W 1K 1W3 No's 4.7K 0.25W 250 0.25W 7. 4.7K 1W POT 8. 1F, 0.01 F, 0.047 F Capacitor

3. THEORY: Internal connections of the 555 Timer chip:

External connections to be made to the 555 chip:

Experiment 13TRIGGERING OF THYRISTOR USING 555 TIMER

Fig-13.1

8

5

3

76

2

1

4R

R

R

+

+

2

1S

-

-

Comparator 1

Comparator 2

FF

Out putstage

InputsR

23 VCC

13 VCC

VREF

Y

YY

Out put

Points 1 to 8are brought out through pins for external connections

Out put

R

12

3

4

56

78

Ground-VC

A

RB

+V

Fig-13.2

555

54

1C

Griet

8

5

37

R R

R R

R

+

+

2

1

-

-

Comparator 1

Comparator 2

ControlFF

Out putstage

Inputs

R

23

VCC

13

VCC

Y

Y6

C

CCCv

A

B

S

(NPN)VCC+

Out put

+_

Fig-13.3

55

1

Y

Equivalent circuit diagram of connections:

(PNP transistor is not shown in the circuit .The capacitor C is for smoothing any 1 ripples in the V supply and is not essential for understanding the operation of the cc circuit) Operation:

3.1) From the circuit of fig.13.3, it can be seen that the resistance of 3R is directly across the dc supply V volts. The inputs to the + terminal of comparator1; and cc to the terminal of comparator2 are (2/3)V and (1/3)V respectively. These cc cc do not change during operation of the circuit. 3.2) It can also be noted that the capacitance C, in series with the resistances R and A R , is also directly across V . The voltage V (t) across C is applied to the B cc c -terminal of comparator1 and also to the +terminal of comparator 2.3.3) At the instant of switching on power, V (t) =0.As can be verified from c Fig.13.3, R=0, S=1 and =0 at this instant. The NPN transistor of fig.13.3 acts as an open-circuit, and C starts getting charged through R and R , with a time A B constant (R +R ) C sec. V (t) increases.A B c3.4) When V (t) reaches V /3 and continues to increase, R become 1. The flip-flop c cc assumes the state R=1, S=1 and =0. Initial transient operation is now over. 3.5) When V (t) increases from V /3 to 2V /3 and slightly more, S becomes 0, R c cc cc stays at 1 and becomes 1. The NPN transistor acts as a short circuit and C in series with R is shorted.B3.6) V (t) now starts decreasing, and as it becomes less than 2V /3, S returns back to C cc the value 1; but stays at when V (t) decreases to V /3 and slightly lesser, R c cc becomes 0; and with R=0, S=1; becomes 0.

In case of comparators +input>-input; output=1 +input=input; output=0 Regarding SR filp flop S R Y 0 0 ___ 0 1 0 1 0 1 1 1 Previous state

C eliminates the ripples in DC.1

Y

Y

Y

YY

Griet

3.7) The NPN transistor starts acting as an open- circuit. C now starts getting charged through R and R , and R resumes the value 1. With R=1, S=1, A stays at 0 A B while the capacitor is getting charged.

4. CIRCUIT DIAGRAM:

1 k

, 1W

84 55

5

5

3

6

4.7

K0.

25 W

4.7k

PO

T

1 k

0.25

W

1 K 1W

1

f

0/P

2N52

96

250

,

w

230

V1-

AC

Supp

ly50

H

Z

TYN

612

15 W

Bulb

Loa

d

1

2

0.01 f

0.04

7

f

10 V,

1W

+ 30

V

250

10

W

0.1

FC

E

G KA

+ -

B

Fig-

13.4

56

Griet

5. PROCEDURE: 5.1. Connect the circuit as shown in fig.13.4 5.2. Observe the waveform at the emitter terminal of the transistor on CRO without potential divider. 5.3. Observe the waveform at the supply, load and thyristors using potential divider circuit on CRO.

6. RESULT: The operation of triggering of thyristors using 555 timer is studied and firing angle is calculated

7. WAVEFORMS:

Fig-13.5

30 VDcInput

Output Pulse

+VmSupplyVoltage

Vs

out putVoltage

Vo

VoltageAcross

Thryvistor

O

-Vm+Vm

VT1

WT

WT

WT

WT

2

2

3

3

4

4

57

Griet

1. AIM: To study the operation of triggering of thyristors using astable multivibrator.

2. APPARATUS: 1. Universal Power Electronics Trainer Kit 2. CRO 3. UJT 2N2646 2 Nos. 4. BC107 Transistor 2 Nos. 5. 15V, 1W Zener 6. Resistor 180,2W 6.8K , 0.5W 2 Nos. 2.7K, 0.5W 2 Nos. 330, 0.5W 4 Nos. 7. 4.7K, 1W POT 8. Capacitor 0.02 F 2 Nos. 0.47 F 2 Nos.

3. THEORY:

3.1) Fig.14.1 shows the collector coupled astable multivibrator using NPN transistor. The collectors of both transistors Q , Q are connected to the bases of the other 1 2 transistor through the coupling capacitor C , C . Since both are ac coupling, 1 2 neither transistor can remain permanently cut off.

3.2) Instead the circuit has two quassi states and it makes transition between these states. Hence it is used as a master oscillator. No triggering signal is required for this multivibrator.

3.3) The component values are selected such that, the moment it is connected to the supply, due to transients, one transistor will go into saturation and the transistor into cut off, and also due to capacitive coupling, it keeps on oscillating.

Experiment 14TRIGGERING OF THYRISTOR USING

ASTABLE MULTIVIBRATOR

Fig- 14.1

I1 I2

C2 C1

R2 R1Rc1 Rc2

Q1 Q2OFF ON

58

Vc1 Vc2

Vb1 Vb2

Vcc+

Griet

Q1 ONQ2 OFF

Vcc

Vc2

0

VCE (Sat)

t = 0 t = T1 t = T1+T2

Q1 ONQ2 OFF Q1 ON

Q2 OFF

t

IB Rc(a)

(b)

Vcc

VB2

0

VBE (Sat)

t = 0 t = T1 t = T1+T2

IB Rc

T1 T2

V

Vcc

Vc1

0

VCE (Sat)

t = 0 t = T1 t = T1+T2 t

( c )

Vcc

VB2

0

t = 0 t = T1 t = T1+T2T1 T2

I R2 C

VV (Sat)BE

Fig- 14.2

59

t

( d ) t

Griet

3.4) At t=0, Q goes to ON state and Q goes to OFF state. So for t

Griet

6. CIRCUIT DIAGRAM:

180 2w

330

1/2w

330

1/2w

10 K

, 2w

dua

lPo

T

2.7

K1/

2w0.

47

f0.

47

f

+ 30

V

Dc

Supp

ly

15V,

IW

Zen

er

UJT

2N26

46

Puls

e

Tra

nsf

orm

er0.0

22F

6.8

K

W

330

K

W

330

K

W

6.8

K

W

UJT

2N26

46

0.02

2F

Q1Q2

230

V1-

AC

Supp

ly50

H

Z

TYN

612

Puls

e Tr

an

sfo

rms

R Loa

d23

0V60

WBu

lb

B2 B1

E

CC

EE

EB

B

B2 B1

Fig-

14.3

61

Griet

7. WAVEFORMS:

Fig-14.4

2 3

VCE Q 1

VCE Q 2

DC Voltage

30 V

15 V

15 V

Vm

+Vm

-Vm

-Vm

SupplyVoltage

OutputVoltage

ThyristorVoltage

Pulse

62

t

t

t

t

t

t

t

Griet

1. AIM: To study the performance of speed control of DC motor using MOSFET.

2. APPARATUS: 1. Universal Power Electronics Trainer Kit 2. Diodes IN4007- 4 3. CRO 4. 741 OP-AMP- 1No 5. Resistors 15k and 10k- 1No 6. MOSFET( IRF 730)- 1No

3. THEORY: Refer to fig 15.1 and 15.2

3.1) 15V, 50Hz single phase sine wave is converted into full wave rectified DC by using rectifier bridge.30V, 5amp fixed DC voltage is converted to variable DC voltage by using the 100k POT.

3.2) The variable dc voltage is compared with full wave rectifier by using 741 op- amp. Here the op-amp is used as a comparator. When a sine wave is compared with dc output of the comparator is a square wave.

3.3) The output of op-amp which is a square wave is available at pin 6. This is used as a gating signal to trigger MOSFET. When dc voltage is varying, the width of the output pulse gets varied.

3.4) When width of the output pulse varies, average DC output voltage between the drain and source of the MOSFET varies, and the circuit acts as a chopper. The chopper output controls the speed of a DC motor. The circuit achevies power amplification as compared to the DC potential divider used in the comparator.

Experiment 15DC CHOPPER USING MOSFET

63

Griet5. PROCEDURE: 5.1. Connect the circuit as shown in figure. 15.1. 5.2. By varying 100k POT observe variation of speed of motor. 5.3. Observe the waveforms of gating signal and load voltage in CRO.

6. RESULT: The performance of speed control of DC Motor using MOSFET is studied.

30 vDCSupply 100k 3w

10k

0.5w

741 lC3 4

6

-12v

+12v

12v

MOSFETIRF 730G D S

12VDCMotor

Motor

15k, 0.5w

IN4007 IN4007

IN4007 IN4007

D2

D4D3

D11-, 50 Hz

15v AC Supply

Vs

_ ++

-

7

+

- 2