POWER INTEGRITY ANALYSIS AND MANAGEMENT

I CIRCUITS

Raj Nair Donald Bennett

P R E N T I C E H A L L

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C O N T E N T S

P r e f a c e x v

A c k n o w l e d g m e n t s xx i

A b o u t the A u t h o r s xxi i i

C o n t r i b u t o r s x x v

C h a p t e r 1 P o w e r , D e l i v e r i n g P o w e r , a n d P o w e r In tegr i ty 1 1.1 Electromotive Force (emf) 1

1.1.1 Force-Voltage Analogy 2

1.2 Electrical Power 5

1.2.1 Physical Analogy for Power 6 1.2.2 Sources of Electrical Power 6 1.2.3 Powering Electrical and Electronic Circuits and Systems 7

1.3 Power Delivery 8 1.3.1 Central DC Power Delivery Module 9 1.3.2 Integrated Power Delivery 11

1.3.3 Power Distribution Networks 11 1.3.4 Power Delivery Regulation 12

1.4 Power Integrity (PI) 13 1.4.1 Contributors to PI Degradation 14

1.5 Exercises 17 References 18

C h a p t e r 2 U l t r a - L a r g e - S c a l e I n t e g r a t i o n a n d P o w e r C h a l l e n g e s 19

2.1 Exponential Integration and Semiconductor Scaling 20 2.1.1 Microprocessor Architecture Power Trend 21

2.1.2 Scaling of Transistor Dimensions and Its Impact 22

2.2 Power and Energy Consumption 27 2.2.1 Power and Energy Expenditure in Charging a Capacitor 28

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viii Contents

2.2.2 Other Sources of Power Consumption 34 Short-Circuit Current 34 Charge Sharing and Interconnect Capacitance 35 Leakage 35

2.3 Power, Heat, and Power Integrity Challenges 39 2.3.1 Power Integrity and the Impact of Scaling 40

Loop Inductance Scaling 44 Resistance Scaling 48

2.4 Exercises 50 References 51

C h a p t e r 3 1С P o w e r In tegr i ty a n d O p t i m a l P o w e r D e l i v e r y 5 3

3.1 Power Transfer and Efficiency 53 3.1.1 Maximum Power Transfer Theorem 54 3.1.2 1С Power Supplies 55

Linear and Switching DC-DC converters 55 Linear Regulators 56 High-Bandwidth Linear Regulators 57 Switching DC-DC converters 60 Voltage References 65

3.1.3 Supply Noise and the Differential Nature of Closed-Loop Power Transfer 68

3.1.4 Noise and Total Power Integrity 72 Resistance, Capacitance, Inductance, and di/dt 72 Resistance 73 Inductance and di/dt 74 Capacitance and System-Level Effects 76

3.2 Optimal 1С Power Delivery: On-Chip Inductance and Grid Design 81 3.2.1 Equivalent Circuit Model for On-Chip Power Grid Analysis 81

Full PEEC versus Simplified PEEC 82 3.2.2 Noise Dependency on Slope of Load Current and Capacitance Position 83

Current Slope versus Noise Amplitude 84 Decap Size and Position 85 Qualitative Discussion on Current Slope and Capacitance Placement 85 Analysis of Decoupling Capacitance Position in Frequency Domain 88

3.2.3 Power Grid Analysis Focusing Distribution of Power Consumption 89 Without Decoupling Capacitance 90 With Decoupling Capacitors 91

Contents

3.2.4 Power Grid Design for Robustness with On-Chip Inductance 94 Power Grid Pitch and Wire Area 94 Spacing between Power and Ground Wires 98

3.3 Power Grid Cost Factor Trade-off Analysis and Design 99 3.3.1 Cost Factors for Power Di stribution Grid Design 100

Power Grid Inductance 100 Power Grid Resistance 101 Power Grid Area Ratio 101

3.3.2 Trade-off Analysis for Power Distribution Grid Design 102 3.4 Exercises 106

References 107

Chapter 4 Early Power Integrity Analysis and Abstraction 111

4.1 Process, Voltage, and Temperature: Design Verification Space 112 4.1.1 Supply Variability Allocation 112

4.2 Back-End and Front-End PI Analysis 115 4.2.1 Gaps in 1С PI Analysis 117 4.2.2 Front-End PI Analysis 118 4.2.3 Abstraction of Chip Components 118

On-Chip Power Grid Abstraction 120 Circuit Block and Decoupling Capacitance Abstraction 123 System-Level Characteristics 124

4.3 Simulation Environment for Models of High Abstraction Levels 126 4.3.1 Continuum Models 128

4.4 Abstraction and PI Analysis Examples 129 4.4.1 Optimal On-Chip Power Network Design 132 4.4.2 System-Level Front-End Simulation 133

4.5 Summary and Enhancements 135 4.6 Exercises 136

References 138

Chapter 5 Power Integrity Analysis and E M I / E M C 141 5.1 Introduction 141 5.2 Analysis of Noise Generation and Propagation through

a Power Distribution Network 143 5.2.1 Sources of Power and Ground Noise 143 5.2.2 Calculating the Target Impedance of a PDN 146 5.2.3 Estimation of Power-Ground Noise from PDN Impedance 147

Contents

5.3

5.4

5.5

5.6

5.7

5.8

5.9 5.10

Modeling Decoupling Capacitors for Noise Mitigation in PDNs 150 5.3.1 On-Board Decoupling Capacitors 152 5.3.2 On-Package Decoupling Capacitance 152

5.3.3 On-Chip Decoupling Capacitors 152 Current Design Methodology for Power Delivery Networks 154

5.4.1 Step 1: Reduce the PDN Inductance as Much as Possible 154 5.4.2 Step 2: The Use of Board Decoupling Capacitors 156 5.4.3 Step 3: The Use of Package Decoupling Capacitors 158

5.4.4 Step 4: Use of On-Chip Decoupling Capacitors 158 Modeling Methodologies 159 5.5.1 Approximations Based on Lower Frequency 161

5.5.2 Higher-Frequency Methods 164

5.5.3 Classification of Numerical Methodologies 165 5.5.4 A Case Study to Compare Numerical Methods 166 Numerical Methods 169

5.6.1 Integral Equation Methods 170 Method of Moments 170

5.6.2 Differential Equation Methods 173 Finite Difference Methods 173

Power and Signal Delivery Analysis Tools and Limitations 176

5.7.1 Limitations Based on Tool Categories 177 5.7.2 Illustration of Tool Limitations 179

Cross-Coupling Characteristics 180 Power Supply Impedance Characteristics 182 Causality Challenges 184 Frequency Sweep and DC Extrapolation Challenges 186

Power Integrity-Aware Electromagnetic Interference Analysis 188 5.8.1 Components of a PDN and Associated Power Integrity Issues 189

5.8.2 System-Level Power Rail Noise Due to SSO/SSN High-Current Transients 190

5.8.3 Package and PCB Plane Resonance 193 5.8.4 System-Level Decoupling Optimization 193 5.8.5 Return Reference Plane Discontinuity 195 Strengths and Limitations of Existing Early EMI methodologies 197 Early Power Integrity-Aware EMI Modeling and Analysis Flow 198 5.10.1 Components of an Early Power Integrity-Aware EMI Flow 199

Layout Creation, Extraction, and Model Abstraction 200 Die-Level Optimization (Dynamic and AC Analyses) at System Level 205 Conducted/Radiated EMI Analysis at System Level 211

Contents

5.11 SI, PI, and EMI Summary 215 5.12 Exercises 216

References 216

Chapter 6 Power Distribution Modeling and Integrity Analysis 221

6.1 Introduction 221 6.2 Modeling of a Power Distribution Grid 224 6.3 Numerical Analysis of Power Distribution Model 229 6.4 Differential and Common-Mode Noise 230 6.5 Verification and Error Analysis 233 6.6 Modeling of On-Chip Bus Switching Current 239 6.7 Verification of the Bus Model 245 6.8 Bus Skewing to Reduce Power Distribution Noise 248 6.9 Case Study: Reduction of Power Distribution Noise 250

6.10 Exercises 252 6.11 Appendix: Coefficients for Equation (6-37) 253

References 255

Chapter 7 Effective Current Density and Continuum Models 259

7.1 Circuit and Model Simplification 259 7.2 Definition of Effective Current Density 260 7.3 Effective Current Density and Virtual Currents 263 7.4 Symmetry in Networks Containing Conductors, Insulators,

and Other Components 263 7.5 A Continuum Model Using ECD 264 7.6 Practical Application of a Continuum-Based Simulator

to 1С Floorplanning 273 7.7 Continuum Models Compared to SPICE Models 280 7.8 Model Enhancement for Nanoscale CMOS Integrated Circuits 284 7.9 Exercises 285

References 286

C h a p t e r 8 P o w e r I n t e g r i t y - A w a r e C h i p F l o o r p l a n n i n g a n d D e s i g n 2 8 7

8.1 Design for Power Integrity: Nanometer Era Considerations 287 8.1.1 System Requirements 288 8.1.2 Die Cost 289 8.1.3 Performance 290

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8.1.4 Power Minimization 290 8.1.5 Other Considerations 291

8.2 Design for Power Integrity: Techniques 291 8.2.1 Power Consumption Management 291 8.2.2 Power Grid Design 294 8.2.3 Chip Floorplanning and Decoupling Capacitance 297

8.3 Power Management and Power Integrity 300 8.3.1 Power Management Techniques 302

Clock Gating 302 Multi-Vt Libraries 303 Body Biasing 305 Voltage Islands/Power Domains 305 Power Gating 305 Adaptive Voltage Scaling/Dynamic Voltage Scaling 307

8.3.2 Power Integrity Implications 308 References 314

C h a p t e r 9 P o w e r I n t e g r i t y M a n a g e m e n t i n I n t e g r a t e d Circu i t s a n d S y s t e m s 3 1 7

9.1 Chip-Level PI Management 318

9.1.1 Primary Techniques 318 Resistance 318 Inductance 318 Capacitance 318

9.1.2 On-Chip Noise Measurement and Modeling 319 Channel Length of On-Chip Decoupling Capacitance (DECAP) 321 Impact of Well Structure on Noise 323

9.1.3 Voltage-Dependent Decoupling Capacitance 326 Charge and Energy in Voltage-Variable Capacitance 328

9.1.4 Advanced Aspects and Techniques 330 Leakage 330 Architecture and Circuit Techniques 331

9.2 System-and Package-Level PI Management 331 9.2.1 System-Level PI Management 331

Power Delivery Path Impedance 332 9.2.2 Package-Mounted Capacitors 334

Contents

9.2.3 Active Packaging and Active Noise Regulation 335 Charge and Energy Multiplication 336 Copious Charge Flow for Noise Minimization 337 High Bandwidth Local Regulation 337 PI Enhancement with ANR Implementation 338

9.2.4 Package PI Management Summary 341 9.3 Exercises 341

References 343 Additional Reading 346

C h a p t e r 1 0 I n t e g r a t i o n T e c h n o l o g i e s , T r e n d s , a n d C h a l l e n g e s 3 4 7

ЮЛ Chip-Level Integration 348 10.1.1 Device Architecture for Low-Power Systems 348

The Double-Gate MOSFET 348 The MIGFET 350

10.1.2 Beneficial Applications of Multiple Independent-Gate FinFETs 350 SRAM 350 Low-Power Circuits for Analog 351

10.1.3 Device Architecture Summary 351 10.2 Package-Level Integration 352

Packaging Technology Development Vectors 353 10.2.1 Advanced Packaging Technologies 354

Wafer-Level Packaging 354 System-in-Package 356 Stacked-Die Packages 359 Package-on-Package (PoP) 360 Through-Silicon-Vias (TSVs) 362 Packaging Integration Summary and Challenges 365

10.3 Integration Trend for Power Integrity Management Components 366 References 367 Additional Reading 369

A p p e n d i x A E C D C o n t i n u u m M o d e l D e r i v a t i o n 3 7 1

A p p e n d i x В D e r i v a t i o n of the H e l m h o l t z E q u a t i o n for P l a n a r Circu i t s 3 8 3

I n d e x 3 8 5