Department of Biomedical Engineering

Digital Logic Design

And Computer Architecture Lab

BME (438)

Prepared By: Eng.Ruba AL.Omari Supervised by:

Dr.Mashhour Bani-Amer & Dr.Hossam ElKhalil Spring 2011

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Table of Contents

EXP.#

TITLE

Page

Exp#1

Introduction

Exercise#1:Development of assembly program 3

Exercise#2: Speaker Control

Exp#2 LED display control 13 Pre-lab #2 16 Exp#3 7-Segment Display Control 18 Pre-lab #3 21 Exp#4 DOT Matrix LED Control 23 Pre-lab #4 28 Exp#5 Matrix Keyboard Control 30 Pre-lab #5 36 Exp#6 Speaker Control

Pre-lab #6

Exp#7 Step Motor Control

Pre-lab #7

Exp#8 Photo-Interrupter Control

Pre-lab #8

Exp#9 Output Port Expansion

Pre-lab #9 Appendix A Instructions

References

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Assembly language includes:

1. A mnemonic or opcode (abbreviation easy to remember) includes: A. instructions (tell the CPU what to do) B. Directives (give directions)

2. Optionally followed by one or two

operands (data items being

manipulated)

For example: A. instructions: MOV, ADD, SWAP… etc. B. Directives (or pseudo-instructions): ORG, JMP…etc

Experiment#1: Introduction

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An assembly program consists of four fields:

[Label:] Mnemonic [operands] [; Comment] For example: Next: MOV A, #99H ; load 99H into A Example:

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Development of Assembly Program

Flow charts of 8051 system development

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1. Write Source Program

The first step for the development of 8051 program is to writing the source program in assembly language using word processing software.

Exercise#1

The following program is an example of assembly language program written in standard format. We will use this source program to demonstrate the processes of assembling and linking later. Using a word processing program (notepad), edit and save as test.txt

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2. Assembling The assembler is used to translate the assembly language program to machine language. After assembling process, an object file will be generated as well as a listing and a cross reference table if they are selected. Once the source program (test.txt) completed, the next step is to assemble it. This task is performed by X8051.exe. The monitor screen will show the following message:

N: No listing file will be generated. T: Terminal. Print the listing file on computer screen. D: disk. Save the listing file generated on disk and use LST as the extension file name.

E: Error only L: LIST ON/OFF P: printer. Print the listing file generated from computer. If D is selected, the following message will appear to ask the user whether a cross reference table is to be generated or not.

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*Input filename: enter the source program filename to be assembled. (test.txt) *Output filename: Enter output filename (test), this filename will be the filename of object (.OBJ) and listing (.LST) generated (TEST.OBJ & TEST.LST) Listing file is a text file includes line number, address, machine code, and source code as shown below

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3. Linking

To link an object, load and run LINK51.EXE as shown below

*Input filename: enter the first object filename to be linked. Since OBJ is the

default extension filename, therefore an extension is not necessary.

*Enter offset for 'CODE': Enter the offset value of memory fro machine code. In

general press enter key to assign this task to linker.

*Input filename: Enter the second object filename to be linked. If none press the

enter key.

*output filename: enter output executable filename. If same as the first object,

press enter key.

*library filename: Enter the library filename to be linked. If none, press enter

key.

*Options(D,P,U,A,C,M,N,R,S,Z,E,H,T,X,1,2,3 ) : These options are used to

select the format of executable file to be generated. (The default is hex file

(.HEX))

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4. Programming1: Once HEX code file is generated, the next step is to write this code into the program memory of the 8051. The code will be downloaded into flash memory by ISP driver through the serial port on the PC. According to the I/O device to be controlled, set the corresponding switch of SW2 in ON position and others in off position. Exercise #1 will sequentially and repeatedly turn on/off the 8 LEDs (LED pack D5) from the left most LED to the right most LED, so you should place the SW2-4 in ON position. 1. Turn on the power of MTS-51 and connect RS-232 cable to PC COM port as shown in Figure#1. 2. Make sure that JP5 is connected to +12V as programming voltage. 3. Press ISP button to enable the ISP function (LED D1 will light up) 4. Place 3rd (RXD3) and 8th (TXD3) switch of SW1 to ON position to enable the serial transmission function.

Figure#1: MTS-51 Programming

1 http://www.kandh.com.tw

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5. Launch Flash Magic (Figure#2) 6. Select Chip to 89C51RD+ (make sure that the chip model on Your MTS-51 also mark as ''89C51RD+'') 7. Select Port No. (Must match the COM port No. in your PC) 8. Input Oscillator frequency as 12.

Figure#2

9. Select [Erase all flash] to erase the old programs stored in 8051 chip. 10. Press [browse] button and browse the complied file (*.HEX) into the software buffer. Important: DO NOT check Security bits “Bit 1, 2, and 3” . Or you will not be able to program the chip in the future. 11. Press start to start programming the chip 12. Release the ISP button.

13. Use DIP switches SW1 or SW2 to enable the related I/O.

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14. Press RESET button to execute the program.

Figure#3

Exercise# 2: Speaker Control Download the following program on the MTS-51 trainer and describe the program function as you will see on the trainer.

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Experiment# 2: LED Display Control

I. Objective 1. To demonstrate that I/O port 2 controls LED pack (D5) on the MTS-51 Trainer. 2. To study the driving circuit for the LED Pack (D5) using 74LS240. II. Circuit Description LED pack (D5) containing 8 LEDs is driven by 74LS240. If input is a one, the corresponding LED will be turned on. If input is a zero, the corresponding LED will be turned off. Resistor pack RS4 serves current limiting to LEDs. P2: used to control LED pack D5.

Exercise# 1: Functional Description: Sequentially turn on/off the 8 LEDs from the left most LED to the right most. When the right most LED is reached, the sequence is inverted. The ON time of each LED is 0.1 seconds.

For more details about the circuit, return to 74LS240 datasheet.

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Return to the introduction to follow the development of assembly program procedure.

Source Program and Description

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Software delay is usually needed to hold the output data an appropriate time because CPU runs at high speed. Delay is done by executing the instructions which have no effect to output data.

Delay Calculations: Delay of the delay subroutine is equal to the product of total machine cycles and the machine cycle time as follows:

Total Machine cycles= Total product of machine cycle and execution time = .203,10022224912001 Since the oscillator frequency of the MTS-51 trainer is 12 MHz, 1 µs every machine cycle, therefore a total of delay is equal to 0.1 second (= ss 1.01100203 ).

Exercise#2…………. will be given in the Lab (10%)

Instruction Machine cycle

Execution Time (µs)

MOV R6, #200 1 1 DL1: MOV R7, 249

1 200

DJNZ R7, $ 2 249 X 200

DJNZ R6, DL1 2 200

RET 2 1

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Faculty of Engineering Biomedical Engineering Department

Digital Logic Design and Computer Architecture Lab

BME 438

Exp.2: LED Display Control

Pre-lab

Name:

Number:

10

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1. Complete the following table according to Exercise#1. (Return to Figure#1 and 2)

2. Describe the operation of 74LS240.

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Experiment#3: 7-Segment Display Control

I. Objective 1. Describe how to use the BCD-to-7-segment decoder/driver (74LS47). 2. To demonstrate that I/O lines of P2.3-P2.0 are the inputs of DS4 (units digits) and P2.7-p2.4 lines are the inputs of DS3 (tens digit). II. Circuit Description

The control signals to these sections are from P2 lines. The BCD-to-7-seg decoder/driver (74LS47) decodes BCD input and shows the corresponding number on the 7-seg-display.

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Truth Table of 74LS47

7-seg display (Common anode) Connection

Exercise#1: Functional Description: Sequentially and repeatedly show the numbers 00 through 99 on DS3 and DS4. Each number stays on 0.5 seconds.

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Return to the introduction to follow the development of assembly program procedure: Note: SW2-3 switch should be placed in ON position. Source Program & Description

Exercise#2…………. will be given in the Lab (10%)

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Faculty of Engineering Biomedical Engineering Department

Digital Logic Design and Computer Architecture Lab

BME 438

Exp.3 7-Segment Display Control

Pre-lab

Name:

Number:

10

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1. According to exercise#1 and Figure#1, complete the following table:

HINT: Loop# 2 will display 0 1 on DS3 and DS4 respectively as shown below

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Experiment# 4: Dot Matrix LED Control.

I. Objective 1. To demonstrate that port 2 and 0 controls 88 dot matrix LED on the MTS-51 trainer. 2. To understand how to use 74LS245 and 2803 for controlling the rows and columns signals respectively. II. Circuit Description D3 is a common cathode matrix LED (all LED Cathodes are connected to the column line) as shown in Figure #1 below. When a row signal is high and a column signal is low, the corresponding LED is turned on.

The row scan signal is emitted from P2 lines through IC (74LS245) and the column scan signal is emitted from P0 through IC (2803).

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Both row and column scan signal are active-high signals. That is, all LEDs are turned on when the row and column signals are all 1s. The 2803 Darlington pairs are used to sink column currents (Return to 2803 datasheet). See Figure#2. 74LS245

The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction control (DIR) input (pin 1). The enable input (G) can be used to disable the device so that the buses are effectively isolated. Function Table for 74LS245

Enable DIR Operation L L B data to A bus L H A data to B Bus H L or H Isolation

Exercise#1 Functional Description: Sequentially turn on the column LEDs from column 1 to column 8 eight time, and then turn on the row LEDs from row 1 to row 8 eight times.

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Return to the introduction to follow the development of assembly program procedure. Source Program

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Program Description

Command Description

CLR P1.7 When the matrix LED is controlled by program, this command must be used to float LCM data bus to prevent the P0 signal from electrical interference

MOV P2,#FFH P2 emits FFH to row lines

MOV A,#10000000B MOV P0,A

P0 emits a 1 to column 1(C1), then the LEDs in this column are turned on

RR A The 1 is shifted to column 2 by rotate instruction to turn on the LED in C2.

MOV P0,#FFH

To turn on the LEDs row after row, P0 emits FFH to column lines

MOV A,#10000000B MOV P2,A

P2 emits a 1 to row 1 (R1), then the LEDs in this row are turned on

RR A

The 1 is shifted to row 2 by rotate instruction to turn on the LED in R2.

Exercise#2 Now modify the above program to show a 57 letter A on dot matrix LED.

Source Program and Description:

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Exercise#3…………. will be given in the Lab (10%)

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Faculty of Engineering Biomedical Engineering Department

Digital Logic Design and Computer Architecture Lab

BME 438

Exp.4: Dot Matrix LED Control

Pre-lab

Name:

Number:

10

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1. According to Exercise#1, complete the following table and color the suitable LED (column or row) for each DOT matrix in loops# 3, 65, 67 and 68.

2. Describe the operation of the source program in exercise#2.

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Experiment# 5: Matrix Keyboard Control.

I. Objective 1. To demonstrate the using of the keyboard circuit KB1. 2. Evaluate the operation of 74C922. II. Circuit Description The keyboard circuit is built by the matrix keyboard KB1 and encoder 74C922. Referring to figure#1 shown below, if a key is pressed, the corresponding binary value will present on the outputs DOD-DOA (P1.3-P1.0) of the encoder and a high potential presents on the DA (data available) pin. The DA signal is inverted by an inverter and then connected to the P3.2 (INT0) pin.

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Keyboard Encoder Features: 1. The output is a key value in binary. 2. It has a debouncing circuit for eliminating the noise produced by mechanical keys. 3. Tri-state output is compatible with data bus of microcomputer. 4. Pin description: 4.1. X1, X2, X3, and X4: Inputs for the column lines of the matrix keyboard. 4.2. Y1, Y2, Y3, and Y4: Inputs for the row lines of the matrix keyboard The relationship between X and Y is shown in Figure#2 below.

The binary value on the 74C922 output is listed on Table#1.

Key

Location Encoded Output

DOD DOC DOB DOA Keys in row 1 X1,Y1 0 0 0 0

X2,Y1 0 0 0 1 X3,Y1 0 0 1 0 X4,Y1 0 0 1 1

Keys in row 2 X1,Y2 X2,Y2 X3,Y2 X4,Y2

0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1

Keys in row 3 X1,Y3 X2,Y3 X3,Y3 X4,Y3

1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1

Keys in row 4 X1,Y4 X2,Y4 X3,Y4 X4,Y4

1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

Table#1

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4.3. DOA, DOB, DOC, and DOD: Tri-state encoded outputs. DOA is LSB and

DOD is MSB.

4.4 OE: Output Enable. When this pin is low, the encoded value presents on the

Encoded output pins. When this pin is high, the encoded outputs present high

impedance.

4.5 DA: Data Available. When a key is pressed, a high presents on the DA pin.

4.6 OSC: On-Chip oscillator input. The pin can directly receive external clock

pulses or externally connects a 0.1µF capacitor.

4.7 KBM: when a 1- µF capacitor is connected to this pin, the noise caused by

mechanical keys is eliminated.

5. CMOS configuration operates in the voltage 3-15 Volts range.

6. The use of 74C922 simplifies the task of program design and improves the

efficiency of execution.

7. The DA signal is an active-high signal. To communicate the microprocessor

with active-low interrupt input (INT0), the DA signal should be inverted by an

inverter gate.

Registers related to interrupt: 1. Interrupt Enable Register(IE)

The bit diagram of the IE register is shown below.

EA X ET2 ES ET1 EX1 ET0 EX0

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EA (IE.7): Disable all interrupts. If EA=0, no interrupt will be acknowledged.

If EA=1, each interrupt source is individually enabled or disabled by

setting or clearing its enable bit. The instruction CLR EA will

disable all interrupts.

EX0 (IE.0): Enable or disable external interrupt 0.

ET0 (IE.1): Enable or disable timer 0 overflow interrupt.

EX1 (IE.2): Enable or disable external interrupt 1.

ET1 (IE.3): Enable or disable timer 1 overflow interrupt.

ES (IE.4): Enable or disable serial port interrupt.

ET2 (IE.5): Enable or disable timer 2 overflow or capture interrupt (8052 only).

For example, the instruction MOV IE, #10001001 Enables external interrupt 0 and timer 1 overflow interrupt, and disables other interrupts. 2. Timer/Counter Control register (TCON) The bit diagram of the IE register is shown below.

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

IT0, IT1: External interrupt 0 type control bit IT0 (bit 0) and external interrupt 1

type control bit IT1 (bit 2). These two bits must be set/ cleared by software to

specify falling-edge/low- level triggering external interrupt.

IT0=0 ------------ Low-level triggering.

IT0=1------------- Falling-edge triggering.

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Exercise #1 Functional Description: It shows the key number on the 7-seg display (DS4) when a key is pressed. Place SW2_3 in ON position.

Source Program

Program Description Interrupt System Control 1. Main Program (1) The starting address of main program must leave from the interrupt vector area-----------------------(ORG 100H)

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(2) Specify IE to enable the interrupts to be used and disable unused interrupts------------------ (MOV IE, #10000001B) (3) Specify IT0 or IT1 to determine the triggering type if external interrupt are used-----------------------(CLR IT0) (4) Write main program and wait for an interrupt.

2. Interrupt service routine (ISR) (1) Place a jump instruction in the interrupt vector and point to the starting

address of interrupt service routine-----------(ORG 003H)

(2) Reset IE to disable other interrupts during the interrupt service routine is

executing---------------------(CLR EX0)

(3) Save the contents PSW or other registers in main program onto stack

using PUSH instruction.

(4) Write interrupt service routine--------------(MOV P2,P1)

(5) Enable interrupts---------------------(SETB EX0)

(6) Return from interrupt using RETI instruction.

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Faculty of Engineering Biomedical Engineering Department

Digital Logic Design and Computer Architecture Lab

BME 438

Exp.5: Matrix Keyboard Control

Pre-lab

Name:

Number:

10

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1. According to exercise# 1, answer the following: 1.1 Complete the following table.

1.2 When a key is pressed as shown in the figure#3, CPU detects the external interrupt input and executes the interrupt service routine (ISR) INT0. The ISR reads the encoded outputs of 74C922 and sends to the inputs of BCD –to- 7-segment decoder

I. What are the value of a, b, c, d, e, f, g, and h?

a b c d e f g h

II. Color the suitable numbers on DS3 and DS4.

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Appendix A Instructions

Data Transfer Instructions Mnemonic Description Byte Cycle MOV A,#data Move immediate data to accumulator 2 1 MOV A,direct Move direct byte to accumulator 2 1 MOV A,Rn Move register to accumulator 1 1 MOV A,@Ri Move indirect RAM to accumulator 1 1 MOV direct,A Move accumulator to direct byte 2 1 MOV direct,#data Move immediate data to direct byte 3 2 MOV direct,direct Move direct byte to direct 3 2 MOV direct,Rn Move register to direct byte 2 2 MOV direct,@Ri Move indirect RAM to direct byte 2 2 MOV Rn,A Move accumulator to register 1 1 MOV Rn,#data Move immediate data to register 2 1 MOV Rn,direct Move direct byte to register 2 2 MOV @Ri,A Move accumulator to indirect RAM 1 1 MOV @Ri,#data Move immediate data to indirect RAM 2 1 MOV @Ri,direct Move direct byte to indirect RAM 2 2 MOV DPTR,#data16 Load data pointer with a 16-bit

constant 3 2

MOVC A,@A+DPTR Move code byte relative to DPTR to ACC

1 2

MOVC A,@A+PC Move code byte relative to PC to ACC 1 2 MOVX A,@Ri Move external RAM (8-bit addr) to ACC 1 2 MOVX A,@DPTR Move external RAM (16-bit addr) to

Acc 1 2

MOVX @Ri,A Move Acc to external RAM (8-bit addr) 1 2 MOVX @DPTR,A Move Acc to external RAM(16-bit addr) 1 2 PUSH direct Push direct byte into stack 2 2 POP direct Pop direct byte from stack 2 2 XCH A,direct Exchange direct byte with accumulator 1 1 XCH A,Rn Exchange register with accumulator 2 1 XCH A,@Ri Exchange indirect RAM with

accumulator 1 1

XCHD A,@Ri Exchange low order digit indirect RAM with Accumulator

1 1

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Arithmetic Operation Instructions Mnemonic Description Byte Cycle ADD A,#data Add immediate data to accumulator 2 1 ADD A,direct Add direct byte to accumulator 2 1 ADD A,Rn Add register to accumulator 1 1 ADD A,@Ri Add indirect RAM to accumulator 1 1 ADDC A,#data Add immediate data to acc with carry 2 1 ADDC A,direct Add direct byte to accr with carry 2 1 ADDC A,Rn Add register to accumulator with carry 1 1 ADDC A,@Ri Add indirect RAM to acc with carry 1 1 SUBB A,#data Subtract immediate data from acc with borrow 2 1 SUBB A,direct Subtract direct byte from acc with borrow 2 1 SUBB A,Rn subtract register from acc with borrow 1 1 SUBB A,@Ri Subtract indirect RAM from acc with borrow 1 1 INC A Increment Accumulator 1 1 INC direct Increment direct byte 2 1 INC Rn Increment register 1 1 INC @Ri Increment indirect RAM 1 1 INC DPTR Increment data pointer 1 2 DEC A decrement Accumulator 1 1 DEC direct decrement direct byte 2 1 DEC Rn decrement register 1 1 DEC @Ri decrement indirect RAM 1 1 MUL AB Multiply A and B 1 4 DIV AB Divide A by B 1 4 DA A Decimal adjust acc 1 1

Logical Operation Instructions Mnemonic Description Byte Cycle ANL A,#data AND immediate data to accumulator 2 1 ANL A,direct AND direct byte to accumulator 2 1 ANL A,Rn AND register to accumulator 1 1 ANL A,@Ri AND indirect RAM to accumulator 1 1 ANL direct,A AND accumulator to direct byte 2 1 ANL direct,#data AND immediate data to direct byte 3 2 ORL A,#data OR immediate data to accumulator 2 1 ORL A,direct OR direct byte to accumulator 2 1 ORL A,Rn OR register to accumulator 1 1 ORL A,@Ri OR indirect RAM to accumulator 1 1 ORL direct,A OR accumulator to direct byte 2 1 ORL direct,#data OR immediate data to direct byte 3 2 XRL A,#data Exclusive-XOR immediate data to accumulator 2 1 XRL A,direct Exclusive-XOR direct byte to accumulator 2 1 XRL A,Rn Exclusive-XOR register to accumulator 1 1 XRL A,@Ri Exclusive-XOR indirect RAM to accumulator 1 1 XRL direct,A Exclusive-XOR accumulator to direct byte 2 1 XRL direct,#data Exclusive-XOR immediate data to direct byte 3 2 CLR A Clear acc 1 1

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CPL A Complement acc 1 1 RL A Rotate acc leftct RAM 1 1 RLC A Rotate acc left through the carry flag 1 1 RR A Rotate acc right 1 1 RRC A Rotate acc right through the carry flag 1 1 SWAP A Swap nibbles within acc 1 1

Boolean Variable Operation Instructions Mnemonic Description Byte Cycle CLR C Clear carry flag 1 1 CLR bit Clear direct bit 2 1 SETB C Set carry flag 1 1 SETB bit Set direct bit 2 1 CPL C Complement carry flag 1 1 CPL bit Complement direct bit 2 1 ANL C,bit AND direct bit to carry flag 2 2 ANL C,/bit AND complement of direct bit to carry flag 2 2 ORL C,bit OR direct bit to carry flag 2 2 ORL C,/bit OR complement of direct bit to carry flag 2 2 MOV C,bit Move direct bit to carry flag 2 1 MOV bit,C Move carry flag to direct bit 2 2 JC rel Jump if carry flag is set 2 2 JNC rel Jump if no carry flag 2 2 JB bit,rel Jump if direct bit is set 3 2 JNB bit,rel Jump if direct bit is not set 3 2 JBC bit,rel Jump if direct bit is set and clear bit 3 2

Branch and jump Instructions Mnemonic Description Byte Cycle ACALL addr11 Absolute subrou ne call,2K range 2 2 LCALL addr16 Long subrou ne call, 64K range 3 2 RET Return from subroutine 1 2 RET1 Return from interrupt 1 2 AJMP addr11 Absolute jump 2 2 LJMP addr16 Long jump, 64K range 2 3 SJMP rel Short jump(relative addr,-128~+127) 2 2 JMP @A+DPTR Jump indirect relative to the DPTR 1 2 Jz rel Jump if acc is zero 2 2 JNZ rel Jump if Acc is not zero 2 2 CJNE A,#data,rel Compare immediate to Acc and jump if not equal 3 2 CJNE A,direct,rel Compare direct to Acc and jump if not equal 3 2 CJNE Rn,#data,rel Compare immediate to register and jump if not

equal 3 2

CJNE @Ri,#data,rel Compare to indirect RAM and jump if not equal 3 2 DJNZ Rn,rel Decrement register and jump if not zero 2 2 DJNZ direct,rel Decrement direct and jump if not zero 3 2 NOP No operation 1 1

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Contents of the SFRs after reset:

Register Name

Reset value Register Name Reset Value

PC 0000H P0 FFH ACC 00H P1 FFH B 00H P2 FFH DPTR 0000H P3 FFH IE 0x000000B PCON 0xxx0000B IP xx000000B PSW 00H SBUF xxxxxxxxB SCON 00H SP 07H TH0 00H TMOD 00H TL0 00H TCON 00H TH1 00H T2CON 00H TL1 00H RCAP2H 00H TH2 00H RCAP2L 00H TL2 00H

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References

Technical Training and education (MTS51-E051101-EC)

URL:http://www.kandh.com.tw

URL:http://www.keil.com

The 8051 Microcontroller and embedded systems using assembly and C ,Second

edition, Mohammad Ali Mazidi, Janice Gillispie Mazidi and Rolin D.

McKinlary.