PRESENTED BY YONGQUAN CHAI VIKRAM MADINENI. INTRODUCTION TO VENDING MACHINES VENDING MACHINE CONTROLLER DESIGN AND PROGRAMMING CONCLUSION & FUTURE

PRESENTED BYPRESENTED BY

YONGQUAN CHAIYONGQUAN CHAIVIKRAM MADINENIVIKRAM MADINENI

INTRODUCTION TO VENDING MACHINES

VENDING MACHINE CONTROLLER

DESIGN AND PROGRAMMING

CONCLUSION & FUTURE SCOPE

The history of Vending Machine (or” automatic retailing “as it is increasingly known) dates back to the time of B.C.

In the early 1880’s first commercial coin operated vending machines were installed in London to dispense the stamps.

The first vending machines in USA were installed in the year 1888 by the Thomas Adams Gum Company and it sold Tutti-Fruiti gum.

Now Vending Machines offer everything stamps , food products, drinks ,cigars etc. and have become a part of our lives.

Most of the vending machines being used are microcontroller based and as the number of functions and products increase, the complexity of controller is also increased.

We feel VHDL program is less complex and cost effective when implemented small scale vending machine.

We have developed VHDL code for a vending machine, which will be targeting small Offices , Motels etc. where the number of products required is limited.

Block Diagram

Vending

Machine

Money

Return all Money

Selection

Clock

Deliver Door

Money Return

Money can be inserted in the combination of nickel, dime, quarter or dollar.

Three products are available –

1. Pepsi 2. Cookies 3. Chips

Selection is done at the input

FIGURE 1

Release Pepsi Release Cookies Release Chips

No

Yes

>50c

= 6 5 c= 6 0 c= 5 0 c

<60c

Release Changes

ChangeAvailable

?

Return All Money

Coo

kies

ChipsPepsi

START

Selectthe

Prodcut

Insert Money – Nickel, Dime , Quarter or Dollar

>65c Check

Sum

Check

Sum

Check

Sum

<50c

>60c

<65c

FLOW CHART

State Assignment

• S0: Waiting for money or other instruction• S1: Custom selection (10: Cookies, 01: Pepsi, 11: Chips)• S2: Total money condition 1 (buying Pepsi)• S3: Total money condition 2 (buying Cookies)• S4: Total money condition 3 (buying Chips)• S5: Deliver Pepsi• S6: Availability of changes• S7: Return Change• S8: Return all money• S9: Deliver Cookies• S10:Deliver Chips

Mny

’, R

tn

Sum

=60

Sum

>65

Sum

=65Sum<65

S

um=

50

Change Available

Sum>50

Sum<50

Sel:1

0

Sum<60

Sel:01

Sel:11

Sum>60

S0

S1

S2

S3 S4

S5S6

S7

S8

S9S10

Mny, Rtn’

Mny

’,R

tn’

Sel:11

Sel

:01

S

el:10

FIGURE 2 STATE DIAGRAM OF VENDING MACHINE CONTROLLER

PepsiPepsi

CoCookokiesies ChipsChips

Return All Return All MoneyMoney

Return Return ChangesChanges

S0S0

S0 if S0 if Myn=0&RtMyn=0&Rt

n=0n=0

S1 if S1 if Mny=1&RtMny=1&Rt

n=0n=0

S8 if S8 if Mny=0&RtMny=0&Rt

n=1n=1 00 00 00 00 00

S1S1S2 if S2 if Sel01=1Sel01=1

S3 if S3 if Sel10=1Sel10=1

S4 if S4 if Sel11=1Sel11=1 00 00 00 00 00

S2S2

S0 if S0 if Sum<50Sum<50

cc

S5 if S5 if Sum=50Sum=50

cc

S6 if S6 if Sum>50Sum>50

cc 00 00 00 00 00

S3S3


cc


cc


cc 00 00 00 00 00

S4S4


cc


cc


cc 00 00 00 00 00

S5S5 S0S0 ____ ____ 11 00 00 00 00

S6S6 S7 if CA=1S7 if CA=1 S8 if CA=0S8 if CA=0 ____ 00 00 00 00 00

S7S7S5 if S5 if Sel01=1Sel01=1

S9 if S9 if Sel10=1Sel10=1

S10 if S10 if Sel11=1Sel11=1 00 00 00 00 11

S8S8 S0S0 ____ ____ 00 00 00 11 00

S9S9 S0S0 ____ ____ 00 11 00 00 00

S10S10 S0S0 ____ ____ 00 00 11 00 00

State Table

OutputsNext StatePresent

State

TABLE 1

BEHAVIOR ARCHITECTURE PROGRAMBEHAVIOR ARCHITECTURE PROGRAM

entity Vend isentity Vend isport ( Mny : in bit_vector (3 downto 1);port ( Mny : in bit_vector (3 downto 1); Sel : inout bit_vector (2 downto 1); Sel : inout bit_vector (2 downto 1); Rt,Clk,Ca : in bit; Rt,Clk,Ca : in bit; Pe,Co,Ch,Rm,Rc : out bit ); Pe,Co,Ch,Rm,Rc : out bit );end vend;end vend;

architecture Vend_bhv of vend is architecture Vend_bhv of vend is

signal S,NS : integer :=0;signal S,NS : integer :=0;signal Sum : integer:=0;signal Sum : integer:=0;function Sum1 (Mny : in bit_vector(3 downto function Sum1 (Mny : in bit_vector(3 downto 1))1))return integer isreturn integer is

variable Sum2 : integer :=0;variable Sum2 : integer :=0;

begin begin

case Mny is case Mny is

when "001" => Sum2:= Sum2+1;when "001" => Sum2:= Sum2+1;

when "010" => Sum2:=Sum2+2;when "010" => Sum2:=Sum2+2;

when "011" => Sum2:=Sum2+5;when "011" => Sum2:=Sum2+5;

when "100" => Sum2:= Sum2+20;when "100" => Sum2:= Sum2+20;

when others => null;when others => null;

end case;end case;return Sum2;return Sum2;end Sum1;end Sum1;

beginbeginprocess ( clk,S)process ( clk,S)beginbegin

Case S is Case S is

when 0 =>when 0 =>Pe <='0';Co <='0';Ch <='0';Pe <='0';Co <='0';Ch <='0';if Sum =0 then Sum <= Sum+Sum1(Mny); if Sum =0 then Sum <= Sum+Sum1(Mny); end if;end if;if Mny = "000" and Rt ='0' then NS <=0; if Mny = "000" and Rt ='0' then NS <=0; end if;end if;if Mny /= "000" and Rt='0' then NS <=1; if Mny /= "000" and Rt='0' then NS <=1; end if;end if;if Mny /= "000" and Rt='1' then NS <=8; if Mny /= "000" and Rt='1' then NS <=8; end if;end if;

when 1 =>when 1 =>

if Sel ="01" then NS <=2; end if;if Sel ="01" then NS <=2; end if;if Sel ="10" then NS <=3; end if;if Sel ="10" then NS <=3; end if;if Sel ="11" then NS <=4; end if;if Sel ="11" then NS <=4; end if;

when 2 =>when 2 =>

Sum <= Sum+Sum1(Mny);Sum <= Sum+Sum1(Mny);

if Sum < 10 then NS <=0; end if;if Sum < 10 then NS <=0; end if;if Sum = 10 then NS <=5; end if;if Sum = 10 then NS <=5; end if;if Sum > 10 then NS <=6; end if;if Sum > 10 then NS <=6; end if;

when 3 =>when 3 =>



when 4 =>when 4 =>



when 5 =>when 5 =>Rc <='0';Rc <='0';Pe <='1' ; Sel <="00";NS <=0; Pe <='1' ; Sel <="00";NS <=0;

When 6 =>When 6 =>

if Ca='0' then NS <=7; end if;if Ca='0' then NS <=7; end if;if Ca='1' then NS <=8; end if;if Ca='1' then NS <=8; end if;

when 7 =>when 7 =>

Rc <='1';Rc <='1';if Sel ="01" then NS <=5; end if;if Sel ="01" then NS <=5; end if;if Sel ="10" then NS <=9; end if;if Sel ="10" then NS <=9; end if;if Sel ="11" then NS <=10; end if;if Sel ="11" then NS <=10; end if;

when 8 =>when 8 =>

Rm<='1'; NS <=0;Rm<='1'; NS <=0;

when 9 =>when 9 =>Rc <='0';Rc <='0';Co <='1' ; Sel <="00"; NS <=0;Co <='1' ; Sel <="00"; NS <=0;

when 10 =>when 10 =>Rc <='0';Rc <='0';Ch <='1' ; Sel <="00";NS <=0;Ch <='1' ; Sel <="00";NS <=0;

when others =>null;when others =>null;end case;end case;end process;end process;

process (clk)process (clk)beginbeginif clk='1' thenif clk='1' thenS <= NS;S <= NS;end if;end if;end process;end process;end vend_bhv;end vend_bhv;

PLOT 1 BEHAVIOR ARCHITECTURE WAVEFORM FOR RELEASE OF CHIPS

PLOT 2 BEHAVIOR ARCHITECTURE WAVEFORM FOR RELEASE OF COOKIES

DESIGN PROCEDURE FOR STRUCTURAL DESIGN PROCEDURE FOR STRUCTURAL ARCHITECTUREARCHITECTURE

Return All Money

SumSum

Signals

Generation

Block

Vending

Machine

Controller

Nickel

Dime

Quarter

Dollar

Pepsi

Cookies

Chips

Money

Availability of Changes

Clock

Release Pepsi

Release Cookies

Release Chips

Return all Money

Return Changes

FIGURE 3

Return all Money

Sum>65c

Sum>60c

Sum=60c

Sum<60c

Sum>50c

Sum=50c

Sum<50c

Chips

Money

Pepsi

Availability of Changes

Cookies

Sum<65c

Sum=65c

Clock

Release Pepsi

Release Cookies

Vending

Machine

Controller

Release Chips

Return All Money

Return Changes

FIGURE 4

TABLE 2 EXPANDED STATE TABLE FOR DESIGINING THE STRUCTURAL ARCHITECTURE

entity vm isentity vm is

port(Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,S65l,port(Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,S65l, S65e,S65m,CA,Clk:in bit;Rpp,Rck,Rcp,Rac,Rch: out bit);S65e,S65m,CA,Clk:in bit;Rpp,Rck,Rcp,Rac,Rch: out bit);

end vm;end vm; architecture vm_structural of vm isarchitecture vm_structural of vm is

signal S:bit_vector(24 downto 0);signal S:bit_vector(24 downto 0);signal Q:bit_vector(3 downto 0):="0000";signal Q:bit_vector(3 downto 0):="0000";signal D:bit_vector(3 downto 0);signal D:bit_vector(3 downto 0);signal N:bit_vector(14 downto 0);signal N:bit_vector(14 downto 0);signal T:bit_vector(5 downto 0);signal T:bit_vector(5 downto 0);signal QN:bit_vector(3 downto 0):="1111";signal QN:bit_vector(3 downto 0):="1111";component xor2component xor2port(a,b:in bit;c:out bit);port(a,b:in bit;c:out bit);end component;end component;component and4 component and4 port(a,b,c,d:in bit;e:out bit);port(a,b,c,d:in bit;e:out bit);end component;end component;component and5component and5port(a,b,c,d,e:in bit;f:out bit);port(a,b,c,d,e:in bit;f:out bit);end component;end component;component and6component and6port(a,b,c,d,e,f:in bit;g:out bit);port(a,b,c,d,e,f:in bit;g:out bit);end component;end component;component and7component and7port(a,b,c,d,e,f,g:in bit;h:out bit);port(a,b,c,d,e,f,g:in bit;h:out bit);end component;end component;component or5component or5port(a,b,c,d,e:in bit;f:out bit);port(a,b,c,d,e:in bit;f:out bit);end component;end component;component or6component or6port(a,b,c,d,e,f:in bit;g:out bit);port(a,b,c,d,e,f:in bit;g:out bit);end component;end component;component or7component or7port(a,b,c,d,e,f,g:in bit;h:out bit);port(a,b,c,d,e,f,g:in bit;h:out bit);end component;end component;component not2component not2port(a:in bit;c:out bit);port(a:in bit;c:out bit);end component;end component;component DFFcomponent DFFport(D,clk:in bit;Q:inout bit;QN:inout bit:='1');port(D,clk:in bit;Q:inout bit;QN:inout bit:='1');end component;end component;beginbegin

not21:not21: not2 port map(Mny,N(0));not2 port map(Mny,N(0));not22:not22: not2 port map(Rtn,N(1));not2 port map(Rtn,N(1));not23:not23: not2 port map(Sel01,N(2));not2 port map(Sel01,N(2));not24:not24: not2 port map(Sel10,N(3));not2 port map(Sel10,N(3));not25:not25: not2 port map(sel11,N(4));not2 port map(sel11,N(4));not26:not26: not2 port map(S50l,N(5));not2 port map(S50l,N(5));not27:not27: not2 port map(S50e,N(6));not2 port map(S50e,N(6));not28: not28: not2 port map(S50m,N(7));not2 port map(S50m,N(7));not29:not29: not2 port map(S60l,N(8));not2 port map(S60l,N(8));not210:not210: not2 port map(S60e,N(9));not2 port map(S60e,N(9));not211:not211: not2 port map(S60m,N(10));not2 port map(S60m,N(10));not212:not212: not2 port map(S65l,N(11));not2 port map(S65l,N(11));

STRUCTURALPROGRAM

FOR MAIN BLOCK

not213:not213: not2 port map(S65e,N(12));not2 port map(S65e,N(12));not214:not214: not2 port map(S65m,N(13));not2 port map(S65m,N(13));not215:not215: not2 port map(CA,N(14));not2 port map(CA,N(14));and61:and61: and6 port map(QN(3),QN(2),QN(1),QN(0),N(0),Rtn,S(0));and6 port map(QN(3),QN(2),QN(1),QN(0),N(0),Rtn,S(0));and71:and71: and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),S60e,N(10),S(1));and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),S60e,N(10),S(1));and72:and72: and7 port map(QN(3),Q(2),QN(1),QN(0),N(11),S65e,N(13),S(2));and7 port map(QN(3),Q(2),QN(1),QN(0),N(11),S65e,N(13),S(2));and51:and51: and5 port map(QN(3),Q(2),Q(1),QN(0),N(14),S(3));and5 port map(QN(3),Q(2),Q(1),QN(0),N(14),S(3));xor21:xor21: xor2 port map(Sel10,N(4),T(0));xor2 port map(Sel10,N(4),T(0));and62:and62: and6 port map(QN(3),Q(2),Q(1),Q(0),N(2),T(0),S(4));and6 port map(QN(3),Q(2),Q(1),Q(0),N(2),T(0),S(4));or51:or51: or5 port map(S(0),S(1),S(2),S(3),S(4),D(3));or5 port map(S(0),S(1),S(2),S(3),S(4),D(3));DFF1:DFF1: DFF port map(D(3),Clk,Q(3),QN(3));DFF port map(D(3),Clk,Q(3),QN(3));and52:and52: and5 port map(QN(3),QN(2),QN(1),Q(0),Sel11,S(5));and5 port map(QN(3),QN(2),QN(1),Q(0),Sel11,S(5));and73:and73: and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),S50e,N(7),S(6));and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),S50e,N(7),S(6));and74:and74: and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),N(6),S50m,S(7));and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),N(6),S50m,S(7));and75:and75: and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),N(9),S60m,S(8));and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),N(9),S60m,S(8));and76:and76: and7 port map(QN(3),Q(2),QN(1),QN(0),N(11),N(12),S65m,S(9));and7 port map(QN(3),Q(2),QN(1),QN(0),N(11),N(12),S65m,S(9));and53:and53: and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(10));and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(10));and77:and77: and7 port map(QN(3),Q(2),Q(1),Q(0),Sel01,N(3),N(4),S(11));and7 port map(QN(3),Q(2),Q(1),Q(0),Sel01,N(3),N(4),S(11));or71:or71: or7 port map(S(5),S(6),S(7),S(8),S(9),S(10),S(11),D(2));or7 port map(S(5),S(6),S(7),S(8),S(9),S(10),S(11),D(2));DFF2:DFF2: DFF port map(D(2),Clk,Q(2),QN(2));DFF port map(D(2),Clk,Q(2),QN(2));and54:and54: and5 port map(QN(3),QN(2),QN(1),Q(0),Sel01,S(12));and5 port map(QN(3),QN(2),QN(1),Q(0),Sel01,S(12));and55:and55: and5 port map(QN(3),QN(2),QN(1),Q(0),Sel10,S(13));and5 port map(QN(3),QN(2),QN(1),Q(0),Sel10,S(13));and78:and78: and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),N(6),S50m,S(14));and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),N(6),S50m,S(14));and79:and79: and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),N(9),S60m,S(15));and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),N(9),S60m,S(15));xor22:xor22: xor2 port map(S65e,S65m,T(1));xor2 port map(S65e,S65m,T(1));and64:and64: and6 port map(QN(3),Q(2),QN(1),Q(0),N(11),T(1),S(16));and6 port map(QN(3),Q(2),QN(1),Q(0),N(11),T(1),S(16));and56:and56: and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(17));and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(17));and710:and710: and7 port map(QN(3),Q(2),Q(1),Q(0),N(2),N(3),Sel11,S(18));and7 port map(QN(3),Q(2),Q(1),Q(0),N(2),N(3),Sel11,S(18));or72:or72: or7 port map(S(12),S(13),S(14),S(15),S(16),S(17),S(18),D(1));or7 port map(S(12),S(13),S(14),S(15),S(16),S(17),S(18),D(1));DFF3:DFF3: DFF port map(D(1),Clk,Q(1),QN(1));DFF port map(D(1),Clk,Q(1),QN(1));and65:and65: and6 port map(QN(3),QN(2),QN(1),QN(0),Mny,N(1),S(19));and6 port map(QN(3),QN(2),QN(1),QN(0),Mny,N(1),S(19));and57:and57: and5 port map(QN(3),QN(2),QN(1),Q(0),Sel10,S(20));and5 port map(QN(3),QN(2),QN(1),Q(0),Sel10,S(20));and711:and711: and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),S50e,N(7),S(21));and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),S50e,N(7),S(21));and712:and712: and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),S60e,N(10),S(22));and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),S60e,N(10),S(22));and58:and58: and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(23));and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(23));xor23:xor23: xor2 port map(Sel01,Sel10,T(2));xor2 port map(Sel01,Sel10,T(2));and66:and66: and6 port map(QN(3),Q(2),Q(1),Q(0),N(4),T(2),S(24));and6 port map(QN(3),Q(2),Q(1),Q(0),N(4),T(2),S(24));or61:or61: or6 port map(S(19),S(20),S(21),S(22),S(23),S(24),D(0));or6 port map(S(19),S(20),S(21),S(22),S(23),S(24),D(0));DFF4:DFF4: DFF port map(D(0),Clk,Q(0),QN(0));DFF port map(D(0),Clk,Q(0),QN(0));and41:and41: and4 port map(QN(3),Q(2),QN(1),Q(0),Rpp);and4 port map(QN(3),Q(2),QN(1),Q(0),Rpp);xor24:xor24: xor2 port map(Sel01,Sel10,T(3));xor2 port map(Sel01,Sel10,T(3));xor25:xor25: xor2 port map(T(3),Sel11,T(4));xor2 port map(T(3),Sel11,T(4));and59:and59: and5 port map(T(4),QN(3),Q(2),Q(1),Q(0),Rch);and5 port map(T(4),QN(3),Q(2),Q(1),Q(0),Rch);and42:and42: and4 port map(Q(3),QN(2),QN(1),QN(0),Rac);and4 port map(Q(3),QN(2),QN(1),QN(0),Rac);and43:and43: and4 port map(Q(3),QN(2),QN(1),Q(0),Rck);and4 port map(Q(3),QN(2),QN(1),Q(0),Rck);and44:and44: and4 port map(Q(3),QN(2),Q(1),QN(0),Rcp);and4 port map(Q(3),QN(2),Q(1),QN(0),Rcp);end vm_structural;end vm_structural;

Sum

Signals

Generation

Block

Nickel

Dime

Quarter

Dollar

Pepsi

Cookies

Chips

Sum<50c

Sum=50c

Sum>50c

Sum<60c

Sum=60c

Sum>60c

Sum<65c

Sum=65c

Sum>65c

FIGURE 5

entity sum isentity sum isport(clk,M3,M2,M1,M0,sel2,sel1,sel0:in bit; port(clk,M3,M2,M1,M0,sel2,sel1,sel0:in bit;

s8,s7,s6,s5,s4,s3,s2,s1,s0:out bit);s8,s7,s6,s5,s4,s3,s2,s1,s0:out bit);end sum;end sum;

architecture sum_bhv of sum isarchitecture sum_bhv of sum is signal sum:integer:=0; signal sum:integer:=0; --initially sum=0 --initially sum=0 signal M:bit_vector(3 downto 0);signal M:bit_vector(3 downto 0);

begin begin M<=M3&M2&M1&M0;M<=M3&M2&M1&M0;process(clk,M)process(clk,M)beginbeginif clk='1' and clk'event thenif clk='1' and clk'event then

case M iscase M iswhen "1000" =>when "1000" =>

sum<=sum+1;sum<=sum+1;when "0100" =>when "0100" =>

sum<=sum+2;sum<=sum+2;when "0010" =>when "0010" =>

sum<=sum+5; sum<=sum+5; when "0001" =>when "0001" =>

sum<=sum+20;sum<=sum+20;when others => null; when others => null;

end case;end case; end if;end if;

end process;end process;process(clk)process(clk)begin begin if sel2='1' then if sel2='1' then

if sum<10 then s8<='1';s7<='0';s6<='0'; end if;if sum<10 then s8<='1';s7<='0';s6<='0'; end if; --sum<50c--sum<50cif sum=10 then s7<='1';s8<='0';s6<='0'; end if;if sum=10 then s7<='1';s8<='0';s6<='0'; end if; --sum=50c--sum=50cif sum>10 then s6<='1';s8<='0';s7<='0'; end if;if sum>10 then s6<='1';s8<='0';s7<='0'; end if; --sum>50c--sum>50c

elsif sel1='1' thenelsif sel1='1' thenif sum<12 then s5<='1';s4<='0';s3<='0'; end if;if sum<12 then s5<='1';s4<='0';s3<='0'; end if; --sum<60c--sum<60cif sum=12 then s4<='1';s5<='0';s3<='0'; end if;if sum=12 then s4<='1';s5<='0';s3<='0'; end if; --sum=60c--sum=60cif sum>12 then s3<='1';s4<='0';s5<='0'; end if;if sum>12 then s3<='1';s4<='0';s5<='0'; end if; --sum>60c--sum>60c

elsif sel0='1' thenelsif sel0='1' thenif sum<13 then s2<='1';s1<='0';s0<='0'; end if;if sum<13 then s2<='1';s1<='0';s0<='0'; end if; --sum<65c--sum<65cif sum=13 then s1<='1';s2<='0';s0<='0'; end if;if sum=13 then s1<='1';s2<='0';s0<='0'; end if; --sum=60c--sum=60cif sum>13 then s0<='1';s1<='0';s2<='0'; end if;if sum>13 then s0<='1';s1<='0';s2<='0'; end if; --sum>65c--sum>65c

end if;end if;

end process;end process;end sum_bhv;end sum_bhv;

entity vm isentity vm isport(Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,S65l,port(Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,S65l,

S65e,S65m,CA,Clk:in bit;Rpp,Rck,Rcp,Rac,Rch: out bit);S65e,S65m,CA,Clk:in bit;Rpp,Rck,Rcp,Rac,Rch: out bit);end vm;end vm;

architecture vm_bhv of vm isarchitecture vm_bhv of vm issignal s,ns: integer:=0;signal s,ns: integer:=0;beginbeginprocess(s,Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m, process(s,Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,

S65l,S65e,S65m,CA)S65l,S65e,S65m,CA)beginbegincase s iscase s iswhen 0=>when 0=>if Mny='0' and Rtn='0' thenif Mny='0' and Rtn='0' then

Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if;if Mny='1' and Rtn='0' thenif Mny='1' and Rtn='0' then

Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=1;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=1;end if;if Mny='0' and Rtn='1' thenif Mny='0' and Rtn='1' then

Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=8;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=8;end if;when 1=>when 1=>if Sel01='1' thenif Sel01='1' then

Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=2;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=2;end if;if Sel10='1' thenif Sel10='1' then

Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=3;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=3;end if;if Sel11='1' thenif Sel11='1' then

Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=4;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=4;end if;when 2=>when 2=>if S50l='1' thenif S50l='1' then

Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if;if S50e='1' thenif S50e='1' then

Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=5;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=5;end if;if S50m='1' thenif S50m='1' then

Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=6;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=6;end if;when 3=>when 3=>if S60l='1' thenif S60l='1' then

Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if;if S60e='1' thenif S60e='1' then

Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=9;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=9;end if;if S60m='1' thenif S60m='1' then

Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=6;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=6;end if;

BEHAVIOR

PROGRAM

FOR MAIN

BLOCK

when 4=>when 4=>

if S65l='1' thenif S65l='1' thenRpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if;

if S65e='1' thenif S65e='1' thenRpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=10;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=10;end if;

if S65m='1' thenif S65m='1' thenRpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=6;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=6;end if;

when 5=>when 5=>Rpp<='1';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;Rpp<='1';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;

when 6=>when 6=>

if CA='1' thenif CA='1' thenRpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=7;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=7;end if;

if CA='0' thenif CA='0' thenRpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=8;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=8;end if;

when 7=>when 7=>

if Sel01='1' thenif Sel01='1' thenRpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='1';ns<=5;end if;Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='1';ns<=5;end if;






when others=> when others=> null;null;

end case;end case;end process;end process;process(Clk)process(Clk)beginbeginif Clk='1' thenif Clk='1' thens<=ns;s<=ns;end if;end if;end process;end process;end vm_bhv;end vm_bhv;

entity newvm isentity newvm isport(Mny,Rtn,Sel01,Sel10,Sel11,nickel,dime,quarter,dollar,CA,Clk:in bit;port(Mny,Rtn,Sel01,Sel10,Sel11,nickel,dime,quarter,dollar,CA,Clk:in bit; Rpp,Rck,Rcp,Rac,Rch: out bit); Rpp,Rck,Rcp,Rac,Rch: out bit);

end newvm;end newvm;

architecture newvm_structural of newvm isarchitecture newvm_structural of newvm issignal sm:bit_vector(8 downto 0);signal sm:bit_vector(8 downto 0);

component sumcomponent sumport(clk,M3,M2,M1,M0,sel2,sel1,sel0:in bit; s8,s7,s6,s5,s4,s3,s2,s1,s0:out bit)port(clk,M3,M2,M1,M0,sel2,sel1,sel0:in bit; s8,s7,s6,s5,s4,s3,s2,s1,s0:out bit)

end component;end component;

component vmcomponent vmport(Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,S65l,S65e,S65port(Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,S65l,S65e,S65m,m,

CA,Clk:in bit; Rpp,Rck,Rcp,Rac,Rch: out bit);CA,Clk:in bit; Rpp,Rck,Rcp,Rac,Rch: out bit);end component;end component;

beginbeginsum1:sum portmap (Clk,nickel,dime,quarter,dollar,Sel01,Sel10,Sel11, sum1:sum portmap (Clk,nickel,dime,quarter,dollar,Sel01,Sel10,Sel11, sm(8),sm(7), sm(8),sm(7),

sm(6),sm(5),sm(4),sm(3),sm(2),sm(1),sm(0));sm(6),sm(5),sm(4),sm(3),sm(2),sm(1),sm(0));vm1:vm1: vm port map (Mny,Rtn,Sel01,Sel10,Sel11,sm(8),sm(7),sm(6), vm port map (Mny,Rtn,Sel01,Sel10,Sel11,sm(8),sm(7),sm(6), sm(5),sm(4), sm(5),sm(4),

sm(3), sm(2),sm(1), sm(0),CA,Clk,Rpp,Rck,Rcp,Rac,Rch);sm(3), sm(2),sm(1), sm(0),CA,Clk,Rpp,Rck,Rcp,Rac,Rch);end newvm_structural;end newvm_structural;

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