Print Verilog Code

BUFFER.V`resetall`timescale 1 ns / 1 ns`view vlog

//Define our own Inverter,

module inverter( Y, A );

// Declarations of I/O ,Power and Ground Lines

output Y; input A; supply1 pwr; supply0 gnd;

// Instantiate pmos and nmos switches pmos (Y,pwr,A);nmos (Y,gnd,A); endmodule

// Define our own Buffer

module buffer( out, in);

// Declarations of I/O Lines

output out; input in;

// Wire Declaration

BUFFER_TEST`resetall`timescale 1 ns / 1 ns`view vlog

// Testbench for Buffer Module

module buf_test;

wire out ; reg in ; ùselib view = vlog

// Instantiate Buffer Module

buffer b1 ( out, in ) ;

`nouselib

// Display

task display ; begin $display ( "time=%0d" , $time , " ns" , " Input=" , in , " Output=", out ) ; end endtask

// Apply Stimulus

initial begin in = 1'b0 ; #10 ; display ; in = 1'b1 ; #10 ; display ; in = 1'bx ; #10 ; display ;

wire a;

// Instantiate Inverter module

inverter i1 (a,in);inverter i2 (out,a);

endmodule

`noview

in = 1'bz ; #10 ; display ; end

endmodule

`noview

TG.V`resetall`timescale 1 ns / 1 ns`view vlog

//Define our own Transmission Gate,

module trangate( out , in , cntrl1, cntrl2);

// Declarations of I/O and Control Lines

output out; input in; input cntrl1,cntrl2;

// Instantiate pmos and nmos switches

TG_TEST.V`resetall`timescale 1 ns / 1 ns`view vlog// Testbench for Inverter Modulemodule trangate_test; wire out ; reg in ; reg cntrl1,cntrl2;

ùselib view = vlog

// Instantiate trangate Module trangate t1 ( out, in, cntrl1,cntrl2 ) ;

`nouselib

// Display

task display ; begin $display ( "time=%0d" , $time , " ns" , " Input=" , in

pmos (out,in,cntrl1);nmos (out,in,cntrl2);

endmodule

`noview

, " Output=", out , " Control1=",cntrl1 , " Control2=",cntrl2 ) ; end endtask

// Apply Stimulus

initial begin in = 1'b0 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1 ; #10 ; display ; in = 1'b0 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0 ; #10 ; display ; in = 1'b1 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1 ; #10 ; display ; in = 1'b1 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0 ; #10 ; display ; end

endmodule

`noview

INVERTER.V`resetall`timescale 1 ns / 1 ns`view vlog

INVERTER_TEST.V`resetall`timescale 1 ns / 1 ns`view vlog

// Testbench for Inverter Module

//Define our own Inverter,

module inverter( out , in );


output out; input in; supply1 pwr; supply0 gnd;

// Instantiate pmos and nmos switches pmos (out,pwr,in);nmos (out,gnd,in); endmodule

`noview

module inv_test; wire out ; reg in ; ùselib view = vlog

// Instantiate inverter Module

inverter i1 ( out, in ) ;

`nouselib

// Display

task display ; begin $display ( "time=%0d" , $time , " ns" , " Input=" , in , " Output=", out ) ; end endtask

// Apply Stimulus

initial begin in = 1'b0 ; #10 ; display ; in = 1'b1 ; #10 ; display ; in = 1'bx ; #10 ; display ; in = 1'bz ; #10 ; display ; end

endmodule

`noview

D_FF.Vmodule d_ff(q,clk,n_rst,din);

output q;input clk,din,n_rst;reg q;

always @(posedge clk or negedge n_rst)

beginif(!n_rst)

q <= 1'b0;else

q <= din;end

endmodulemodule d_ff_test;

reg clk, din, n_rst;wire q, d1, clk1;d_ff df1 (q, clk, n_rst, din);

assign d1=din;assign clk1=clk;initial

clk = 1'b0;

always

T_FF.Vmodule t_ff(q,qbar,clk,tin,rst);

output q,qbar;input clk,tin,rst;reg tq;always @(posedge clk or

negedge rst)begin

if(!rst)tq <= 1'b0;

elsebegin

if (tin)tq <= ~tq;

endendassign q = tq;assign qbar = ~q;

endmodule

module t_ff_test; reg clk,tin,rst; wire q,qbar; t_ff t1(q,qbar,clk,tin,rst); initial clk = 1'b0; always

#10 clk = ~clk;

initial begin

din = 1'b0;n_rst = 1'b1;#20 n_rst = 1'b0;#10 din = 1'b1;#20 n_rst = 1'b1;#18 din = 1'b0;#1 din = 1'b1;#20 din = 1'b0;#10 ;

end

always#5 $display ($time," clk=%b din=%b q=%b", clk, din, q);

initial#100 $finish;

specify$setup(d1, posedge

clk1, 2);$hold(posedge clk1,

d1, 2);$width(negedge d1, 2);

endspecifyendmodule

#10 clk = ~clk; initial begin rst = 1'b0; tin = 1'b0;

#30 rst = 1'b1;#10 tin = 1'b1;#205 tin = 1'b0;#300 tin = 1'b1;#175 tin = 1'b0;#280 rst = 1'b0;#20 rst = 1'b1;#280 tin = 1'b1;#10 ;

end initial #2000 $finish;endmodule

JK_FF.Vmodule jk_ff(q,qbar,clk,rst,j,k);

input clk,rst,j,k;output q,qbar;reg q,tq;

always @(posedge clk or negedge rst)

begin

#50 rst = 1'b0; #10 ; end

always#5 $display($time,"

clk=%b j=%b k=%b ",clk,j,k);

initial #300 $finish;

if (!rst)begin

q <= 1'b0;tq <= 1'b0;

endelsebeginif (j == 1'b1 && k ==

1'b0)q <= j;

else if (j == 1'b0 && k == 1'b1)

q <= 1'b0; else if (j == 1'b1 && k

== 1'b1)begintq <= ~tq;q <= tq;end

endendassign q_bar = ~q;

endmodule

module jk_ff_test;reg clk,rst,j,k;

wire q,qbar;

wire clk1,j1,k1;

jk_ff inst(q,qbar,clk,rst,j,k);

assign clk1=clk;assign j1=j;assign k1=k;

initial clk = 1'b0; always #10 clk = ~clk; initial begin j = 1'b0; k = 1'b0; rst = 1'b0;

specify$setup(j1, posedge

clk1, 2);$setup(k1, posedge

clk1, 2);$hold(posedge clk1, j1,

2);$hold(posedge clk1,

k1, 2);endspecify

endmodule

#30 rst = 1'b1; #60 j = 1'b0; k = 1'b1; #29 j = 1'b1; k = 1'b0;

#1 j = 1'b0; k = 1'b1; #20 j = 1'b1; k = 1'b1; #40 j = 1'b1; k = 1'b0;

#5 j = 1'b0; #20 j = 1'b1;

MS_FF.Vmodule ms_jkff(q,q_bar,clk,j,k);

output q,q_bar; input clk,j,k;reg tq,q,q_bar;

always @(clk)begin

if (!clk)beginif (j==1'b0 &&

k==1'b1)tq <= 1'b0;

else if (j==1'b1 && k==1'b0)

tq <= 1'b1;else if (j==1'b1 &&

k==1'b1)tq <= ~tq;

endif (clk)begin

q <= tq;q_bar <= ~tq;

endend

endmodule

module tb_ms_jkff;reg clk,j,k;

wire q,q_bar;

initial #200 $finish; specify $setup(j2, posedge clk2, 2); $setup(k2, posedge clk2, 2); $hold(posedge clk2, j2, 2); $hold(posedge clk2, k2, 2); endspecify endmodule

wire clk2,j2,k2;

ms_jkff inst(q,q_bar,clk,j,k);

assign clk2=clk;assign j2=j;assign k2=k;

initial clk = 1'b0;

always #10 clk = ~clk;

initial begin j = 1'b0; k = 1'b0; #60 j = 1'b0; k = 1'b1; #40 j = 1'b1; k = 1'b0; #20 j = 1'b1; k = 1'b1; #40 j = 1'b1; k = 1'b0; #5 j = 1'b0; #20 j = 1'b1; #10 ; end always #5 $display($time," clk=%b j=%b k=%b ",clk,j,k);

SR_FF.Vmodule SR_ff(q,qbar,s,r,clk);

output q,qbar;input clk,s,r;reg tq;

always @(posedge clk or tq)beginif (s == 1'b0 && r == 1'b0)

tq <= tq;else if (s == 1'b0 && r ==

1'b1)tq <= 1'b0;

initial #500 $finish;

specify$setup(s1, posedge

clk1, 2);$setup(r1, posedge

clk1, 2);$hold(posedge clk1, s1,

2);$hold(posedge clk1, r1,

2);endspecify

endmodule

else if (s == 1'b1 && r == 1'b0)

tq <= 1'b1;else if (s == 1'b1 && r ==

1'b1)tq <= 1'bx;

endassign q = tq;assign qbar = ~tq;

endmodule

module SR_ff_test;reg clk,s,r;wire q,qbar;

wire s1,r1,clk1;

SR_ff sr1(q,qbar,s,r,clk);

assign s1=s;assign r1=r;assign clk1=clk;

initial clk = 1'b0; always #10 clk = ~clk; initial begin s = 1'b0; r = 1'b0; #30 s = 1'b1; #29 s = 1'b0; #1 r = 1'b1; #30 s = 1'b1; #30 r = 1'b0; #20 s = 1'b0; #19 s = 1'b1; #200 s = 1'b1; r = 1'b1;

#50 s = 1'b0; r = 1'b0;#50 s = 1'b1; r = 1'b0;#10 ;

end always

#5 $display($time," clk=%b s=%b r=%b ",clk,s,r);

AND.V`resetall`timescale 1 ns / 1 ns`view vlog

//Define our own And Gate,

module andgate ( out , in1 , in2 );


output out; input in1,in2; supply1 pwr; supply0 gnd;

// Declaration of Wires

wire contact; wire nout;

// Instantiate pmos and nmos switches to form Nand gate pmos (nout,pwr,in1); pmos (nout,pwr,in2); nmos (nout,contact,in1); nmos (contact,gnd,in2); // Instantiate pmos and nmos

AND_TEST.V`resetall`timescale 1 ns / 1 ns`view vlog

// Testbench for And Module

module and_test;

wire out ; reg in1,in2 ; ùselib view = vlog

// Instantiate And Gate Module

andgate a1 ( out, in1, in2 ) ;

`nouselib

// Display

task display ; begin $display ( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 , " Output=" , out ) ;

switches to form Inv

pmos (out,pwr,nout); nmos (out,gnd,nout);

endmodule

`noview

end endtask

// Apply Stimulus

initial begin in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ; end

endmodule

`noview

NAND.V

`resetall`timescale 1 ns / 1 ns`view vlog

//Define our own Nand Gate,

module nandgate ( out , in1 , in2

NAND_TEST.V`resetall`timescale 1 ns / 1 ns`view vlog

// Testbench for Nand Gate Module

module nand_test;

wire out ; reg in1,in2 ;

);



// Declaration of Wire

wire contact;

// Instantiate pmos and nmos switches pmos (out,pwr,in1); pmos (out,pwr,in2); nmos (out,contact,in1); nmos (contact,gnd,in2); endmodule

`noview

ùselib view = vlog

// Instantiate Nand Gate Module

nandgate n1 ( out, in1, in2 ) ;

`nouselib

// Display

task display ; begin $display ( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 , " Output=" , out ) ; end endtask

// Apply Stimulus


endmodule

`noview

NOR.V`resetall`timescale 1 ns / 1 ns`view vlog

//Define our own Nor Gate,

module norgate ( out , in1 , in2 );



// Declaration of Wire

wire contact;

// Instantiate pmos and nmos switches pmos (contact,pwr,in1); pmos (out,contact,in2); nmos (out,gnd,in1); nmos (out,gnd,in2); endmodule

`noview

NOR_TEST.V`resetall`timescale 1 ns / 1 ns`view vlog

// Testbench for Nor Gate Module

module nor_test;


// Instantiate Nor Gate Module

norgate n1 ( out, in1, in2 ) ;

`nouselib

// Display


// Apply Stimulus


endmodule

`noview

OR.V

`resetall`timescale 1 ns / 1 ns`view vlog

//Define our own Or Gate,

module orgate ( out , in1 , in2 );


output out;

OR_TEST.V`resetall`timescale 1 ns / 1 ns`view vlog

// Testbench for Nor Gate Module

module or_test;


// Instantiate Orgate Module

orgate n1 ( out,

input in1,in2; supply1 pwr; supply0 gnd;

// Declaration of Wires

wire contact; wire nout;

// Instantiate pmos and nmos switches for Nor gate pmos (contact,pwr,in1); pmos (nout,contact,in2); nmos (nout,gnd,in1); nmos (nout,gnd,in2); // Instantiate pmos and nmos switches for Not gate

pmos (out,pwr,nout); nmos (out,gnd,nout); endmodule

`noview

in1, in2 ) ;

`nouselib

// Display


// Apply Stimulus


endmodule

`noview

XNOR.V`resetall`timescale 1 ns / 1 ns`view vlog

//Define our own XNOR Gate,

module xnorgate( out , in1 , in2 );

// Declarations of I/O ports

output out; input in1,in2; wire in2bar;

assign in2bar = ~in2;

// Instantiate pmos and nmos switches :

pmos (out,in2bar,in1);nmos (out,in2,in1);pmos (out,in1,in2bar);nmos (out,in1,in2);

endmodule

`noview

XNOR_test.v`resetall`timescale 1 ns / 1 ns`view vlog

// Testbench for Xnor Module

module xnor_test;


// Instantiate Xnor gate Module

xnorgate x1 ( out, in1, in2 ) ;

`nouselib

// Display


// Apply Stimulus

initial begin in1 = 1'b0 ; in2 = 1'b0 ; #10 ;

display ; in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ; end

endmodule

`noview

XOR.V`resetall`timescale 1 ns / 1 ns`view vlog

//Define our own XOR Gate,

module xorgate( out , in1 , in2 );

// Declarations of I/O ports

output out; input in1,in2; wire in2bar;

assign in2bar = ~in2;

XOR_TEST.V`resetall`timescale 1 ns / 1 ns`view vlog

// Testbench for Xor Module

module xor_test;


// Instantiate Xorgate Module

xorgate x1 ( out, in1, in2 ) ;

// Instantiate pmos and nmos switches :

pmos (out,in2,in1); nmos (out,in2bar,in1); pmos (out,in1,in2); nmos (out,in1,in2bar);

endmodule

`noview

`nouselib

// Display


// Apply Stimulus


endmodule

`noview

ADDER.Vmodule adder4

ADDER4_T.Vmodule adder4_t ;

( carryin,x,y,sum,carryout);

input carryin; input [3:0] x,y; output [3:0] sum; output carryout;

fulladd stage0 (carryin,x[0],y[0],sum[0],c1); fulladd stage1 (c1,x[1],y[1],sum[1],c2); fulladd stage2 (c2,x[2],y[2],sum[2],c3); fulladd stage3 (c3,x[3],y[3],sum[3],carryout);

endmodule

FULLADD.Vmodule fulladd (cin,x,y,s,cout);

input cin,x,y; output s,cout;

assign s = x^y^cin; assign cout =( x & y) | (x & cin) |( y & cin);

endmodule

reg [3:0] x,y;reg carryin;wire [3:0] sum;wire carryout;

adder4 a1 ( carryin,x,y,sum,carryout);

initial begin $monitor($time,"SUM=%d",sum); x = 4'b0000; y= 4'b0000;carryin = 1'b0; #20 x =4'b1111; y = 4'b1010; #40 x =4'b1011; y =4'b0110; #40 x =4'b1111; y=4'b1111;

#50 $finish;end

endmodule

mycounter.vmodule counter_behav ( count,reset,clk); input wire reset, clk; output reg [3:0] count;

always @(posedge clk) if (reset) count <= 4'b0000; else count <= count + 4'b0001;

endmodule

mycounter_t.vmodule mycounter_t ;wire [3:0] count;reg reset,clk; initialclk = 1'b0;always #5 clk = ~clk;counter_behav m1 ( count,reset,clk);initialbegin reset = 1'b0 ;

#15 reset =1'b1; #30 reset =1'b0; #300 $finish;endinitial$monitor ($time, "Output count = %d ",count );endmodule

SERIAL_ADDER.Vmodule serial_adder ( A,B, reset, clock, sum);input [7:0] A,B;input reset,clock;output [7:0] sum;reg [3:0] count;reg s,y,Y;wire [7:0] qa,qb,sum;wire run;parameter G=0,H=1;

shiftrne shift_A (A,reset,1'b1,1'b0,clock,qa);shiftrne shift_B (B,reset,1'b1,1'b0,clock,qb);shiftrne shift_sum (8'b0,reset,run,s,clock,sum);

//adder fsm //output and next state combinational circuitalways @(qa or qb or y) case (y) G: begin s = qa[0]^qb[0]; if (qa[0] & qb[0])

SHIFT_REGISTER.Vmodule shiftrne ( R,L,E,w,clock,q);

parameter n=8;input [n-1:0] R;input L,E,w,clock;output [n-1:0] q;reg [n-1:0] q;integer k;

always @(posedge clock) if (L) q <= R; else if (E) begin for (k=n-1;k>0;k=k-1) q[k-1] <= q[k]; q[n-1] <= w; endendmodule

SERIAL_ADDER_t.Vmodule serial_adder_t ;reg [7:0] A,B;reg reset,clock;wire [7:0] sum ;

Y = H; else Y = G; end

H: begin s = qa[0] ~^qb[0]; if (~qa[0] & ~qb[0]) Y =G; else Y = H; end default : Y = G;

endcase

//sequential blockalways @(posedge clock) if (reset) y <= G; else y <= Y; //control the shifting processalways @(posedge clock) if (reset) count = 8; else if (run) count = count - 1;assign run=|count;

endmodule

initial clock = 1'b0;

always #5 clock =~clock;

serial_adder s1 (A,B,reset,clock,sum);

initial begin reset = 1'b0;A = 8'b10101010; B = 8'b11111111; #20 reset = 1'b1; #20 reset = 1'b0; #150 reset = 1'b1; A = 8'b11110000 ; B = 8'b11110011; #20 reset = 1'b0;

#200 $finish;end

initial$monitor ($time, " SUM = %d ", sum);

Endmodule

RIPPLE_COUNTER.V`view rtlmodule ripple_counter (clock, toggle, reset, count); input clock, toggle, reset; output [3:0] count;

RIPPLE_COUNTER_t`noviewmodule ripple_counter_t ;reg clock,toggle,reset;wire [3:0] count ;ripple_counter r1

reg [3:0] count; wire c0, c1, c2; assign c0 = count[0], c1 = count[1], c2 = count[2]; always @ (posedge reset or posedge clock) if (reset == 1'b1) count[0] <= 1'b0; else if (toggle == 1'b1) count[0] <= ~count[0]; always @ (posedge reset or negedge c0) if (reset == 1'b1) count[1] <= 1'b0; else if (toggle == 1'b1) count[1] <= ~count[1]; always @ (posedge reset or negedge c1) if (reset == 1'b1) count[2] <= 1'b0; else if (toggle == 1'b1) count[2] <= ~count[2]; always @ (posedge reset or negedge c2) if (reset == 1'b1) count[3] <= 1'b0; else if (toggle == 1'b1) count[3] <= ~count[3];endmodule

(clock,toggle,reset,count);

initial clock = 1'b0;

always #5 clock = ~clock;initial begin reset = 1'b0;toggle = 1'b0; #10 reset = 1'b1; toggle = 1'b1; #10 reset = 1'b0; #190 reset = 1'b1; #20 reset = 1'b0; #100 reset = 1'b1; #40 reset = 1'b0; #250 $finish;

end

SAR.Vmodule shiftrne ( R,L,E,w,clock,q);

parameter n=8;input [n-1:0] R;input L,E,w,clock;output [n-1:0] q;reg [n-1:0] q;

SAR_T.Vmodule sar_t;

reg [7:0] r;reg l;reg e;reg w;reg clk;wire [7:0] q;

integer k;

always @(posedge clock) if (L) q <= R; else if (E) begin for (k=n-1;k>0;k=k-1) q[k-1] <= q[k]; q[n-1] <= w; end

endmodule

shiftrne sf(.R(r),.L(l),.E(e),.w(w),.clock(clk),.q(q));initial begin clk = 1'b0; l = 1'b1; w = 1'b0; e = 1'b0;#5 r = 8'b1111_0000;#10 l = 1'b0; e = 1'b1; w = 1'b0;#10 w = 1'b0;#10 w = 1'b0;#10 w = 1'b0; #10 w = 1'b1; #10 w = 1'b1; #10 w = 1'b1; #10 w = 1'b1; #10 $finish; endalways #5 clk = ~clk;endmodule

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