University of California, Berkeley Spring 2012EE 42/100 Prof. A. Niknejad

Problem Set 9Solutions

Please note that these are merely suggested solutions. Many of these problems can beapproached in different ways.

1. From the truth table, we obtain the following SOP expression:

F = A BC + ABC + ABC + ABC + ABC = AC + AC + ABC = AB + C

Inverting this expression to get all the input complements, we get

F = (A + B)C

The CMOS logic circuit is the following:

A B

C

F

VDD

C

A

B

2. The Boolean expression for the given logic circuit is

F = AB + BC + AC = (A + B)(B + C)(A + C) = (A B + A C + B + B C)(A + C)

= (B + A C)(A + C) = A B + B C + A C = A(B + C) + B C

By simplifying it into this form, we can build a CMOS circuit with ten transistors,since there are only five variables.

VDD

F

A

A

B

B

B

B

C C

C

C

3. (a) To quickly derive the NAND-only expression for F , we can use the followingequivalent form (second one above): F = (A + B)(B + C)(A + C). Using

DeMorgan’s law, we have that F = AB BC AC = AB BC AC. Thus we have aNAND of three individual NAND terms, followed by a NOT, which can berealized using NAND gates as well.

A

B

C

F

(b) We start with F = A B + B C + A C = (A + B) + (B + C) + (A + C). By

DeMorgan’s law, (A + B) + (B + C) + (A + C). Like before, we have a NOR ofthree individual NOR terms, followed by a NOT, which can also be realizedusing NOR gates.

A

B

C

F

2

4. The D latch is transparent whenever the clock is high; otherwise it keeps its previousvalue. For the flip flop, transparency activates only on the rising edge of the clock.

CLK

D

Q(latch)

Q(FF)

5. (a) The FSM is shown below.

00 10

01 11

00

10

00

10

01 00 11 10

11

01

0111 01

10

11

00

(b) The truth table has sixteen rows, as there are four inputs. The output columnsare S ′

1 and S ′0.

I1 I0 S1 S0 S ′1 S ′

0

0 0 0 0 0 00 0 0 1 0 00 0 1 0 0 00 0 1 1 1 00 1 0 0 0 10 1 0 1 0 10 1 1 0 0 10 1 1 1 1 11 0 0 0 1 01 0 0 1 0 01 0 1 0 1 01 0 1 1 1 01 1 0 0 1 11 1 0 1 0 11 1 1 0 1 11 1 1 1 1 1

3

(c) Using SOP for S ′1, we obtain

S ′1 = I1 I0S1S0 + I1I0S1S0 + I1I0 S1 S0 + I1I0S1S0

+ I1I0S1S0 + I1I0S1 S0 + I1I0S1S0 + I1I0S1S0

= I1S1S0 + I1I0 S0 + I1S1S0 + I1I0S0

= S1S0 + I1S0

Notice that S ′0 is only depends on I0. Thus, our expression can be written as

S ′0 = I0

4