Computer Organization and ArchitectureDesigning For PerformanceWilliam StallingsSeventh Edition

Team #5Team #5 - 12.1 Processor Organization - 12.2 Register Organization - 12.3 Instruction Cycle - 12.4 Instruction Pipelining/ Dealing with

Branches

12.1 Processor OrganizationFetch InstructionInterpret instructionFetch DataProcess DataWrite Data

Remember….The processor needs to store some

data temporally. It must remember the location of the

last instruction so that it can know where to get the next instruction.

It needs to store instructions and data temporally while an instruction is being executed.

CPU with System Bus

CPU Internal Structure

Register Organization

User-visible registers

Control and status registers

User Visible Registers

General PurposeDataAddressCondition Codes

General Purpose RegistersData

Accumulator

AddressingSegment pointersIndex registersStack Pointer

Control & Status Registers

Program CounterInstruction Decoding RegisterMemory Address RegisterMemory Buffer Register

Program Status WordSign ZeroCarryEqualOverflowInterrupt enable/disableSupervisor

Example Register Org.

Instruction CycleIt is the time in which a single instruction is fetched from memory,

decoded, and executed

An Instruction Cycle requires the following subcycle:

Instruction CycleFetch

Read next instruction from memory into the processor

Indirect Cycle (Decode Cycle)May require memory access to fetch operands, therefore more memory accesses.

Interrupt

Save current instruction and service the interruptExecute

Interpret the opcode and perform the indicated operation

Instruction CycleFetch

Execute

Fetch

Execute

Indirect

Fetch

Execute

Interrupt

Fetch

Execute

IndirectInterrupt

Data Flow (Fetch Diagram)

PC

ControlUnit

PC MARMAR

MemoryMemory

ControlUnit

MBR

Memory

IR MBR

Data Flow (Indirect Diagram)

MBR

MARMAR

Memory

ControlUnit

Memory

MBR

Memory

Data Flow (Execute)May take many formsDepends on instruction being executed

May includeMemory read/writeInput/OutputRegister transfersALU operations

Data Flow (Interrupt Diagram)

ControlUnit

PC

MBR

PC

ControlUnit

MARMAR

Memory

MBR

MemoryMemory

ControlUnit

ControlUnit

PC

12.4 Instruction PipeliningInstruction processing is subdivided:

- Fetch/ Execute instructionPipeline has two independent stages:

1st Stage – Fetch an instruction and buffers it.2nd Stage – Temporarily free until first stage passes it the buffered instruction.While the second stage is executing the instruction, the first stage fetches and buffers the next instruction.

Instruction prefetch or fetch overlap.- Purpose? To speed up instruction execution.

Two-Stage Instruction Pipeline

Instruction ProcessingFetch instruction (FI)Decode instruction (DI)Calculate operands (CO)Fetch operands (FO)Execute instruction (EI)Write operand (WO)

Successive instructions in a program sequence will overlap in execution.

Timing Diagram for Instruction Pipeline Operation

Six-Stage CPU Instruction PipelineThe logic needed for pipelining to account for branches, interrupts, and arising problems.

Alternative Pipeline Depiction

RISC Pipeline1.Instruction fetch2.Instruction decode and register

fetch3.Execute4.Memory Access5.Register write back

Branches

Branch- group of instructions

Branch Instructions – (Jump Instruction) One of it’s operands is the address of the next instruction to be executed.

BranchesTwo Types of Branch Instructions

Unconditional – Branch always happensConditional – Branch only happens if

certain condition is met.The PC is updated to the address specified in the operand of the conditional branch instruction.

A conditional branch instruction is similar to an if statement.

Conditional Branch InstructionsCondition Codes

BRP XBranch to location X if result is

positiveBRZ X

Branch to location X if result is zeroBRE R1,R2,X

Branch to location X if contents of R1 = R2

Conditional Branch Instructions

Dealing with BranchesA major problem in designing an

instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline.

Since conditional branches alter the steady flow of instructions, we must come up with ways to execute them efficiently.

Dealing with Branches5 Approaches to Dealing with

Conditional BranchesMultiple StreamsDelayed BranchPrefetch Branch targetLoop BufferBranch Prediction

Dealing with Branches• Multiple Streams (IBM 370/168 and IBM 3033)

Pipeline fetches both instructions. Leads to contention delays, and branches

can lead to too many streams.• Delayed Branch

Branch Instruction occurs later than desired.• Prefetch Branch Target (360/91 IBM)

The target of the branch is prefetched, along with the instruction following the branch, so if the branch is taken this will speed up performance.

Dealing with BranchesLoop buffer ( Motorola 68010)

Memory containing the n most recently fetched instructions.

Useful with if-then and if-then-else statements, as well as loops

Branch PredictionDifferent techniques are used to predict

whether the branch will be taken or notIf the prediction is correct this will

speed up performance

Dealing with Branches

Intel Pentium BranchThe prediction of whether a jump will occur or not, is based on the branch’s previous behavior. There are four possible states that depict a branch’s disposition to jump:

Stage 0: Very unlikely a jump will occurStage 1: Unlikely a jump will occurStage 2: Likely a jump will occurStage 3: Very likely a jump will occur

Intel Pentium BranchIt is actually believed that Pentium’s original algorithm for branch prediction was incorrect. (Left)

Researchhttp://www.it.jcu.edu.au/Subjects/cp1300/resourc

es/lectnotes/system/fde.htmlhttp://dr-pisit.com/csc331/Lec10-

CPU&Pipeline.pdf http://

en.wikipedia.org/wiki/Instruction_pipelininghttp://www.itreviews.co.uk/hardware/h738.ht

m

Review Questions1. What are the major components of a processor?2. What is the function of the ALU?3. What is the function of the control unit?4. What are the two roles that registers in the

processor perform?5. What are bits set by the processor hardware as

a result of operations?6. What is an instruction cycle?7. What are the four subcycle of an instruction

cycle?

8. Is the fetch or execute cycle the same for all CPU?

9. What is the sequence of an interrupt cycle?10. What is the main purpose for instruction

pipelining?11. How can you make the pipelining more

efficient?12. What is a condition code?13. What is another name for a branch

instruction?

Answers1. Arithmetic and Logic Unit (ALU) and the Control Unit

(CU).2. The ALU does the actual computation or processing of

data.3. The control unit controls the movement of data and

instructions into and out of the processor and controls the operations of the ALU.

4. User-visible registers, and control and status registers. 5. Condition codes. 6. It is the time in which a single instruction is fetched

from memory, decoded, and executed. 7. Fetch, Indirect (if any) , execute, and interrupt (if any).

8. No, it depends on the CPU’s design. 9. PC MBR

Address of Stack MAR MAR Memory

PC Memory Control Unit request memory write via Control Bus PC is loaded with address of Interrupt handler

10. To speed up the instruction execution rate. 11. To gain further speedup, the pipeline must have more stages

for decomposition.

12.A statement that if true will allow the branch to be executed.

13.A jump instruction.