Product Version 4.0.8 May 2001 - ece.virginia.edumrs8n/soc/SynthesisTutorials/syncomref.pdfCommand Reference for Ambit® BuildGates® Synthesis and Cadence® PKS Product Version 4.0.8

Command Reference for Ambit ®

BuildGates ® Synthesis and Cadence ® PKS

Product Version 4.0.8May 2001

2000-2001 Cadence Design Systems, Inc. All rights reserved.Printed in the United States of America.

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Command Reference for Ambit BuildGates Synthesis and Cadence PKS

Contents

Preface .......................................................................................................................... 16

About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Other Information Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Text Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17About the Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Using Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Using Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1BuildGates Synthesis Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Command Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24ac_shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25alias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28all_children . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29all_parents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31check_netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32check_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33create_module_reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37delete_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38delete_aware_component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39delete_object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40delete_unconnected_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41do_blast_busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42do_build_generic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44do_change_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48do_copy_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52do_create_hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54do_dissolve_hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56do_extract_critical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

May 2001 3 Product Version 4.0.8


do_extract_fanin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61do_extract_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63do_extract_non_critical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65do_optimize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66do_pop_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69do_push_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70do_rebind . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71do_remove_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73do_rename . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74do_uniquely_instantiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Arguments for Transform (do_xform_*) Commands . . . . . . . . . . . . . . . . . . . . . . . . . . 78do_xform_buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87do_xform_buffer_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88do_xform_clone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90do_xform_fast_optimize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91do_xform_fix_design_rule_violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92do_xform_fix_hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93do_xform_fix_multiport_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94do_xform_footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95do_xform_ipo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96do_xform_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98do_xform_optimize_generic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99do_xform_optimize_slack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100do_xform_pre_placement_optimize_slack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101do_xform_propagate_constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102do_xform_reclaim_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103do_xform_remove_redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104do_xform_resize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105do_xform_restructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106do_xform_structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107do_xform_timing_correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108do_xform_unmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109dump_adb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110eval_bottom_up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111find . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113get_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120



get_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122get_buswidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123get_cell_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124get_current_instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125get_current_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126get_equivalent_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127get_global . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128get_hdl_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129get_hdl_hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130get_hdl_top_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132get_hdl_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133get_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134get_message_count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136get_message_verbosity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137get_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138get_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139get_parent_instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141get_tempfilename . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143highlight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144issue_message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146quit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148read_adb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149read_dc_script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151read_edif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153read_symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154read_symbol_update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155read_verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156read_vhdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158record_macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161report_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162report_aware_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164report_design_rule_violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165report_fanin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167report_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169



report_fsm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171report_globals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174report_hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176report_resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178report_vhdl_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179reset_dont_modify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180reset_failsafe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181reset_global . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182reset_register_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183reset_vhdl_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184set_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185set_aware_component_property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189set_aware_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190set_cell_property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191set_current_instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192set_current_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193set_dont_modify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194set_failsafe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197set_global . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198set_logic0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262set_logic1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263set_message_count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264set_message_verbosity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265set_port_property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266set_register_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267set_table_style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269set_unconnected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272set_vhdl_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273unalias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275write_adb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276write_edif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278write_verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279write_vhdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281



2CTPKS Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

set_clock_tree_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284get_clock_tree_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286get_clock_tree_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287set_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289define_structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290do_build_clock_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294do_build_physical_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297report_clock_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299report_clock_tree_violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305reset_clock_tree_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

3Distributed Synthesis Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

check_batch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310check_dist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312check_host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313get_host_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314get_job_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317get_weight_batch_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323kill_job . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324remove_host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325remove_job . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326report_job . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327reset_dist_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328reset_dist_point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329reset_dist_weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330set_dist_bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331set_dist_point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332set_host_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334set_host_list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337set_dist_weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338set_weight_batch_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339



4PKS Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

check_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344check_libraries_and_design_compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345check_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346create_blockage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348create_placement_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350delete_blockage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352do_extract_route_parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353do_generate_estcap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354do_initialize_floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355do_place . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356do_placement_spread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361do_reset_floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362do_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363do_snap_instance_to_row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369do_xform_tcorr_eco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370generate_supply_rails_on_rows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372get_cluster_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373get_current_congestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374get_current_utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375get_library_layer_capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376get_library_layer_offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377get_library_layer_resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378get_library_layer_usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379get_logic_0_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380get_logic_1_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381get_min_porosity_for_over_block_routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382get_min_wire_length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383get_physical_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384get_pin_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385get_route_availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386get_special_netpins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387get_steiner_capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388get_steiner_channel_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389



get_steiner_length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390get_steiner_resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391read_def . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392read_layer_usages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394read_lef . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395read_lef_update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396read_pdef . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397remove_placement_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399remove_supply_rails_on_rows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400report_block_halo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401report_floorplan_parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402report_placement_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404report_preroute_parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405report_supply_rails_on_rows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406reset_dont_move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407set_block_halo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408set_dont_move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409set_floorplan_parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410set_layer_usages_table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413set_lef_multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415set_library_layer_offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417set_library_layers_cap_multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418set_library_layers_res_multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419set_library_layer_usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420set_logic_0_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422set_logic_1_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423set_min_porosity_for_over_block_routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424set_min_wire_length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425set_net_physical_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426set_physical_instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429set_pin_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430set_power_stripe_spec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432set_preroute_parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434set_route_availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436set_special_netpin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437set_steiner_channel_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438



set_steiner_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439set_supply_rails_on_rows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441write_def . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443write_layer_usages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445write_pdef . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

5Low Power Synthesis (LPS) Commands . . . . . . . . . . . . . . . . . . . . . 448

do_xform_optimize_power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449get_clock_gating_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452get_power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454get_sleep_mode_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456read_tcf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458report_power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461report_tc_stats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464set_clock_gating_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467set_sleep_mode_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475Low Power Options for Existing BuildGates Synthesis Commands . . . . . . . . . . . . . 477

6Test Synthesis Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

check_dft_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480display_scan_chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482do_xform_connect_scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483do_remove_scan_order_data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486get_scan_chain_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487read_scan_order_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489report_dft_assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490report_dft_registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491reset_dft_compatible_clock_domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493reset_dft_internal_clock_domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494reset_dft_transparent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495reset_dont_scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496reset_dont_touch_scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497reset_must_scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498



reset_scan_data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499reset_test_mode_setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500set_dft_compatible_clock_domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501set_dft_internal_clock_domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503set_dft_transparent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505set_dont_scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506set_dont_touch_scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507set_lssd_aux_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508set_lssd_scan_clock_a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509set_lssd_scan_clock_b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510set_max_scan_chain_length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511set_must_scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512set_number_of_scan_chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514set_scan_data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515set_scan_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518set_scan_style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520set_test_scan_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521set_test_mode_setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522write_atpg_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524write_scan_order_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

7Timing Analysis Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

Command Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531check_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532do_cppr_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535do_derive_context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537do_time_budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539do_xform_timing_correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542get_cell_drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543get_cell_pin_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545get_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546get_clock_propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548get_clock_source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549get_constant_for_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551



get_dcl_calculation_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552get_dcl_functional_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553get_dcl_functional_mode_array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554get_dcl_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555get_derived_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556get_drive_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557get_fanin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559get_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561get_load_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563get_module_worst_slack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564get_operating_parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565get_scale_delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567get_slack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568get_tech_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569get_time_borrow_limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574get_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575get_top_timing_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578libcompile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579load_dcl_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580read_alf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581read_ctlf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583read_library_update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584read_ola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586read_sdf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587read_spf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591read_spef . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593read_stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594read_tlf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596remove_assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598report_annotations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600report_cell_instance_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602report_clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604report_functional_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608report_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609report_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611report_path_exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615



report_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617report_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622reset_clock_gating_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636reset_clock_root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638reset_constant_for_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639reset_disable_cell_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640reset_disable_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641reset_external_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643reset_functional_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645reset_input_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646reset_tech_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648reset_time_borrow_limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653reset_wire_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654reset_wire_load_selection_table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655set_begin_tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656set_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657set_clock_arrival_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660set_clock_gating_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661set_clock_info_change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664set_clock_insertion_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668set_clock_propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672set_clock_required_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674set_clock_root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676set_clock_uncertainty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678set_constant_for_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682set_cycle_addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683set_data_arrival_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689set_data_required_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690set_dcl_calculation_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692set_dcl_functional_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693set_dcl_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694set_default_slew_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695set_disable_cell_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696set_disable_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697set_drive_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699set_drive_resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703



set_external_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705set_false_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708set_fanout_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713set_fanout_load_limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714set_functional_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715set_input_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716set_max_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718set_min_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719set_num_external_sinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720set_num_external_sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721set_operating_condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722set_operating_parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724set_path_delay_constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726set_port_capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730set_port_capacitance_limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732set_port_wire_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734set_scale_delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735set_slew_limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737set_slew_time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738set_slew_time_limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740set_tech_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741set_time_borrow_limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747set_top_timing_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749set_wire_capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750set_wire_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752set_wire_load_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755set_wire_load_selection_table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756set_wire_resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757unload_dcl_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758write_assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759write_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761write_gcf_assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763write_library_assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765write_rspf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766write_sdf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767write_spf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773



Path Exception Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774Examples of Path Exception Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775

Bidirectional Pin Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

Command Index ................................................................................................... 778



Preface

This preface contains the following sections:

■ About This Manual on page 16

■ Other Information Sources on page 16

■ Syntax Conventions on page 17

■ About the Graphical User Interface on page 18

About This Manual

This manual is a complete alphabetical collection of BuildGates synthesis commands.BuildGates synthesis can be run both in command line mode and in graphical user interface(GUI) mode.

Other Information Sources

For more information about Ambit BuildGates synthesis and other related products, you canconsult the sources listed here.

■ Ambit BuildGates Synthesis User Guide

■ Timing Analysis for Ambit BuildGates Synthesis and Cadence PKS

■ Test Synthesis for Ambit BuildGates Synthesis and Cadence PKS

■ HDL Modeling for Ambit BuildGates Synthesis

■ Distributed Processing of Ambit BuildGates Synthesis

■ Constraint Translator for Ambit BuildGates Synthesis and Cadence PKS

Depending on the product licenses your site has purchased, you could also have thesedocuments.

■ PKS User Guide

■ Datapath Option of Ambit BuildGates Synthesis and Cadence PKS


Command Reference for Ambit BuildGates Synthesis and Cadence PKSPreface

■ Low Power Option of Ambit BuildGates Synthesis and Cadence PKS

BuildGates synthesis is often used with other Cadence® tools during various design flows.The following documents provide information about these tools and flows. Availability of thesedocuments depends on the product licenses your site has purchased.

■ Cadence Timing Library Format Reference

■ Cadence Pearl Timing Analyzer User Guide

■ Cadence General Constraint Format Reference

The following books are helpful references.

■ IEEE 1364 Verilog HDL LRM

■ TCL Reference, Tcl and the Tk Toolkit, John K. Ousterhout, Addison-WesleyPublishing Company

Syntax Conventions

This section provides the Text Command Syntax used in this document.

Text Command Syntax

The list below describes the syntax conventions used for the Ambit BuildGates synthesis textinterface commands.

Important

Command names and arguments are case sensitive. User-defined information iscase sensitive for Verilog designs and, depending on the value specified for theglobal variable hdl_vhdl_case , may be case sensitive as well.

literal Nonitalic words indicate keywords that you must enter literally.These keywords represent command or option names.

argument Words in italics indicate user-defined arguments or informationfor which you must substitute a name or a value.

| Vertical bars (OR-bars) separate possible choices for a singleargument.



[ ] Brackets denote optional arguments. When used with OR-bars,they enclose a list of choices from which you can choose one.

{ } Braces are used to indicate that a choice is required from the listof arguments separated by OR-bars. You must choose one fromthe list.

{ argument1 | argument2 | argument3 }

{ } Bold braces are used in Tcl commands to indicate that thebraces must be typed in literally.

... Three dots (...) indicate that you can repeat the previousargument. If the three dots are used with brackets (that is,[argument ]...) , you can specify zero or more arguments. Ifthe three dots are used without brackets (argument ...) , youmust specify at least one argument, but can specify more.

# The pound sign precedes comments in command files.

About the Graphical User Interface

This section describes the conventions used for the BuildGates synthesis graphical userinterface (GUI) commands and describes how to use the menus and forms in the BuildGatessynthesis software.

Using Menus

The GUI commands are located on menus at the top of the window. They can take one ofthree forms.

CommandName A command name with no dots or arrow executes immediately.

CommandName… A command name with three dots displays a form for choosingoptions.

CommandName -> A command name with a right arrow displays an additional menuwith more commands. Multiple layers of menus and commandsare presented in what are called command sequences, forexample: File – Import – LEF. In this example, you go to the Filemenu, then the Import submenu, and, finally, the LEF command.



Using Forms

… A menu button that contains only three dots provides browsingcapability. When you select the browse button, a list of choicesappears.

Ok The Ok button executes the command and closes the form.

Cancel The Cancel button cancels the command and closes the form.

Defaults The Defaults button displays default values for options on theform.

Apply The Apply button executes the command but does not close theform.

Help The Help button provides information about the command.



1BuildGates Synthesis Commands

This chapter describes the commands and global variables used with Ambit® BuildGates®

Synthesis.

■ ac_shell on page 25

■ alias on page 28

■ all_children on page 29

■ all_parents on page 31

■ check_netlist on page 32

■ check_option on page 33

■ create_module_reference on page 36

■ debug on page 37

■ delete_attribute on page 38

■ delete_aware_component on page 39

■ delete_unconnected_ports on page 41

■ delete_object on page 40

■ do_blast_busses on page 42

■ do_build_generic on page 44

■ do_change_name on page 48

■ do_copy_module on page 52

■ do_create_hierarchy on page 54

■ do_dissolve_hierarchy on page 56

■ do_extract_critical on page 58


Command Reference for Ambit BuildGates Synthesis and Cadence PKSBuildGates Synthesis Commands

■ do_extract_fanin on page 61

■ do_extract_fanout on page 63

■ do_extract_non_critical on page 65

■ do_optimize on page 66

■ do_pop_module on page 69

■ do_push_module on page 70

■ do_rebind on page 71

■ do_remove_design on page 73

■ do_rename on page 74

■ do_uniquely_instantiate on page 76

■ Arguments for Transform (do_xform_*) Commands on page 78

■ do_xform_buffer on page 87

■ do_xform_buffer_tree on page 88

■ do_xform_clone on page 90

■ do_xform_fast_optimize on page 91

■ do_xform_fix_design_rule_violations on page 92

■ do_xform_fix_hold on page 93

■ do_xform_fix_multiport_nets on page 94

■ do_xform_footprint on page 95

■ do_xform_ipo on page 96

■ do_xform_map on page 98

■ do_xform_optimize_generic on page 99

■ do_xform_optimize_slack on page 100

■ do_xform_pre_placement_optimize_slack on page 101

■ do_xform_propagate_constants on page 102

■ do_xform_reclaim_area on page 103

■ do_xform_remove_redundancy on page 104



■ do_xform_resize on page 105

■ do_xform_restructure on page 106

■ do_xform_structure on page 107

■ do_xform_timing_correction on page 108

■ do_xform_unmap on page 109

■ dump_adb on page 110

■ eval_bottom_up on page 111

■ find on page 113

■ get_area on page 120

■ get_attribute on page 122

■ get_buswidth on page 123

■ get_cell_area on page 124

■ get_current_instance on page 125

■ get_current_module on page 126

■ get_equivalent_cells on page 127

■ get_global on page 128

■ get_hdl_file on page 129

■ get_hdl_hierarchy on page 130

■ get_hdl_top_level on page 132

■ get_hdl_type on page 133

■ get_info on page 134

■ get_message_count on page 136

■ get_message_verbosity on page 137

■ get_names on page 138

■ get_net on page 139

■ get_parent_instances on page 141

■ get_tempfilename on page 142



■ help on page 143

■ highlight on page 144

■ issue_message on page 145

■ limit on page 146

■ read_adb on page 149

■ read_dc_script on page 151

■ read_symbol on page 154

■ read_symbol_update on page 155

■ read_verilog on page 156

■ read_vhdl on page 158

■ record_macro on page 161

■ report_area on page 162

■ report_aware_library on page 164

■ report_design_rule_violations on page 165

■ report_fanin on page 167

■ report_fanout on page 169

■ report_fsm on page 171

■ report_globals on page 174

■ report_hierarchy on page 176

■ report_resources on page 178

■ report_vhdl_library on page 179

■ reset_dont_modify on page 180

■ reset_failsafe on page 181

■ reset_global on page 182

■ reset_register_type on page 183

■ reset_vhdl_library on page 184

■ set_attribute on page 185



■ set_aware_component_property on page 189

■ set_aware_library on page 190

■ set_cell_property on page 191

■ set_current_instance on page 192

■ set_current_module on page 193

■ set_dont_modify on page 194

■ set_failsafe on page 197

■ set_global on page 198

■ Command Arguments for set_global on page 203

■ set_logic0 on page 262

■ set_logic1 on page 263

■ set_message_count on page 264

■ set_message_verbosity on page 265

■ set_port_property on page 266

■ set_register_type on page 267

■ set_table_style on page 269

■ set_unconnected on page 272

■ set_vhdl_library on page 273

■ unalias on page 275

■ write_adb on page 276

■ write_edif on page 278

■ write_verilog on page 279

■ write_vhdl on page 281

Command Descriptions

Command syntax is provided in the following sections.



ac_shell

ac_shell [-64] [-pks] [-no_pks] [-no_pks_1st] [-datapath] [-power] [[-f] filename ][-cmdfile command_filename ] [-logfile log_filename ] [-cdsdocd {on | off}][-queue] [-expire] [-version] [-help] [-continue] [-no_init][-set var =value ...] [-which] [-gui] [-display machine :0][-geometry int x int +int +int ] [-fullscreen] [-large] [-limit][-colormap colormap_file ]

The ac_shell command starts the Ambit BuildGates synthesis tool. For more detail onstarting ac_shell , refer to Getting Started in the Ambit BuildGates Synthesis UserGuide.

Arguments

-64Start a 64-bit ac_shell session. Default is 32 bit.

-cdsdocd {on | off}Enable or disable the use of browser-based documentation forac_shell help . When set to on , the full documentation set isavailable from the Help button in the GUI. When set to off , onlythe syntax is displayed in the command line. The default is onwhen running in GUI mode and off when running in commandline mode.

-cmdfile command_filenameName of command file.Default: ac_shell.cmd

-colormapColor map file.

-continueDo not exit after an error in Tcl script file.

-display machine:0Display to use.

-datapathRun the Ambit BuildGates synthesis application with theDatapath option. A separate license must be purchased for theDatapath option.



-expireDisplay the expiration date of the license.

-f filenameName of Tcl script file to source at startup. You can usefilename without specifying the -f .

-fullscreenUse entire screen for the ac_shell .

-geometry intxint+int+intSet the initial size and position of the GUI main screen window.Where width and height are in pixels. And xoff and yoffare the number of pixels from the corner; a negative value ismeasured from the bottom or right corners, and a positive valueis measured from the top or left corners. No spaces are allowedbetween the values.

For example: -geometry 800x400+10-30 means create awindow 800 by 400 pixels with its left edge offset 10 pixels fromthe left edge of the screen and its bottom edge offset 30 pixelsfrom the bottom of the screen

Valid only in GUI mode.

-guiInvoke graphical user interface (GUI) mode

-helpPrint usage message for this command.

-largeIncrease the memory limit above 2GB for the process runningac_shell if the memory is available.

-limitPrint the current datasize limit and memory allocation limit for themachine on which the software will run.

-logfile log_filenameName of log file.Default: ac_shell.log



-no_initDisable sourcing of ~/.ambit/.acshrc

-no_pksUse a regular license.

-no_pks_1stTry to use a regular license, otherwise use a PKS license.

-powerInitialize the Cadence™ low power synthesis (LPS) option. Youcan use -power with the -gui option to enable the graphicaluser interfaces for the power option.

See the Cadence low power synthesis user guide for detailsabout this option.

-pksUse a PKS license.

-queueWait for a license if none is available.

-set var=valueInitialize a Tcl variable.

-versionDisplay version of this ac_shell .

-whichDisplay the full path name of the ac_shell executable.

Examples

Start the Ambit BuildGates Synthesis graphical user interface and save the session log incpu_design.log .

ac_shell -gui -logfile cpu_design.log



alias

alias command_name name

The alias command creates a simple alias for command names. It does not support aliasinga command with options to a new name. It only performs a simple renaming of a previouslydefined command.

A more general mechanism for renaming or repackaging commands is the built-in Tcl proccommand.

Arguments

command_nameThe alias name.

nameThe name of an existing command.

Database Impact

There is no effect on the database

Related Information

unalias

Examples

Create the wv alias for the write_verilog command:

alias wv write_verilog



all_children

all_children [ module_id | module_name ]

The all_children command returns a Tcl list of object identifiers representing the childmodules that are instantiated in the specified parent module. You can use this routinerecursively to traverse through the netlist in a top-down fashion. An example is providedbelow.

The command pair set_attribute and get_attribute are also related to thiscommand. These commands can be used to mark the modules as they are visited, if thedesign is not unique and if an action is to be performed at most once during a traversal.

Note: The list returned by the all_children command excludes black box children unlessyou use the -instances option.

Arguments

module_id | module_nameThe object identifier or name associated with a module. If neitheris specified, command returns the children of the current module.

Related Information

all_parents

find

get_attribute

set_attribute

Examples

■ Get the names of children of module a.

get_names [all_children [find -module a]]

b c

■ Write a netlist for all children of module a.

foreach i [all_children [find -module a]] {

set_current_module $i

write_ver $i.ver

}



■ Traverse the hierarchy using attributes.

proc traverse_hier {mod} {

set_current_module $mod

foreach i [all_children] {

traverse_hier $i

}

if {[get_attribute [find -module $mod] MY_ATTR] == ""} {

set_attribute [find -module $mod] MY_ATTR "visited"

# do action

}



all_parents

all_parents [-instances] [-hierarchical] [ module_id | module_name ]

The all_parents command returns a Tcl list of object identifiers of modules that instantiatethe specified module. It is similar to the all_children command. This routine is used to doa bottom-up traversal of the netlist hierarchy.

Arguments

-instancesThe -instances option returns a Tcl list of object identifiersrepresenting the instance_ids of the instantiated childmodules in the given parent module, including black boxchildren.

-hierarchicalThe -hierarchical option returns the module_ids of all themodules instantiated in the specified module and its hierarchicalsubmodules. The tool ignores this option when used with the-instances option.

module_id | module_nameThe object identifier or name associated with a module. If neitheris specified, the command returns the parents of the currentmodule.

Related Information

all_children

find

get_attribute

set_attribute



check_netlist

check_netlist [-module module ] [-blocklevel] [-verbose] [ file_name ]

The check_netlist command performs a number of checks on the structural connectivityof the netlist, including recursively defined modules, combinational feedback, undriven netsand pins, multiply driven nets and pins, and undriven ports.

This command can be applied to generic and mapped modules.

Arguments

-blocklevelChecks the current module only, not the hierarchy.

file_nameOptional file name for the output.

-module moduleChecks a specific module. By default, check_netlist checksthe current module.

-verbosePrints detailed information for each violation check and also thesummary.

Examplescheck_netlist

The number of recursively defined modules (at least):0

The number of combinational feedbacks(at least):0

The total number of undriven nets/pins:0

The total number of multiple driven nets:0

The total number of potential multiple driven nets:1

The total number of undriven ports:0



check_option

check_option [-hide | -show {-datapath | -power | -64 | -large | -PKS | -no_PKS |-gui | -visual}][[-]datapath] [[-]power] [[-]64] [[-]large] [[-]PKS] [[-]no_PKS] [[-]gui][[-]visual]

The check_option command allows you to determine with which command line options thecurrent ac_shell executable has been invoked. It returns all enabled options when thecommand is invoked without any arguments. Options which require a license are printed incapitalized letters. When invoking the ac_shell , all options requiring a license can beentered in any upper and / or lower case combination.

The invokable options (datapath , power , 64, large , PKS, no_PKS, gui , and visual ) maybe specified with or without the preceding dash to return different types of values. The optionwithout a dash will return a 1 or 0 to indicate ac_shell is running with or without the optionenabled, respectively. The option with a dash will return the name of the enabled option or theempty set (“ “) if the option is not enabled. See examples below for clarification.

Arguments

64If the current session was executed with ac_shell -64,the check_option command:Returns 1 If the 64 option is specified.Returns the word -64 if the -64 option is specified.

powerIf the current session was executed with ac_shell -power(the Low Power license), the check_option command:Returns 1 If the power option is specified.Returns the word -Power if the -power option is specified.

datapathIf the current session was executed with ac_shell -datapath(the Datapath license), the check_option command:Returns 1 If the datapath option is specified.Returns the word -Datapath if the -datapath option isspecified.

largeIf the current session was executed with ac_shell -large,the check_option command:



Returns 1 If the large option is specified.Returns the word -large if the -large option is specified.

PKSIf the current session was executed with ac_shell -pks(the PKS license), the check_option command:Returns 1 If the pks option is specified.Returns the word -PKS if the -pks option is specified.

no_PKSIf the current session was executed with ac_shell -no_pks(or without the -pks option), the check_option command:Returns 1 If the no_pks option is specified.Returns the word -no_PKS if the -no_pks option is specified.

guiIf the current session was executed with ac_shell -gui(the graphical user interface), the check_option command:Returns 1 If the gui option is specified.Returns the word -gui if the -gui option is specified.

visualThis option provides the same functionality as the -gui optionand is used only for backward compatibility with previousreleases.If the current session was executed with ac_shell -visual(the graphical user interface), the check_option command:Returns 1 If the visual option is specified.Returns the word -visual if the -visual option is specified.

-hideTemporarily disables an option that was invoked whenac_shell was started.

-showRe-enables an option that was previously disabled with the-hide option.

Related Information

ac_shell



Examplescheck_option [datapath | large | pks | power | gui]

Returns the following for a session invoked with the PKS and GUI options:

0 0 1 0 1

check_option -power -pks -large

Returns the following for a session invoked with the PKS option:

-PKS

The following shows the commands and the output for an ac_shell session started with the-gui and the -large options. The example demonstrates the disabling (- hide ) andre-enabling (- show) of the -large option.

check_option -gui -large

-gui -large

check_option -hide -large


-gui

check_option -show -large


-gui -large



create_module_reference

create_module_reference [-module module ] module_id

The create_module_reference command creates a cell reference for a module. A cellreference is necessary when creating an instance of a module.

This command does not modify the netlist. It creates an intermediate data structure that isnecessary before creating an instance or rebinding.

Arguments

-module moduleThe module in which to create the cell reference.

module_idThe identifier of the created module to be referenced.

Related Information

do_copy_module

do_rebind

Examplesdo_copy_module sub sub_copy_1

create_module_reference [find -module sub_copy_1]

do_rebind sub1 sub_copy_1



debug

debug { 0 | 1 }

The debug command enables the debugging mode in the Tcl interface. It places theinteractive shell into a debugging mode. Use debug 1 to enable debugging, debug 0 to quitdebugging.



delete_attribute

delete_attribute object_id attribute_name

Removes the specified attribute_name from the specified object_id .

Arguments

object_idThe object identifier of the module, instance, cellref, net, port, orpin from which to delete the specified attribute_name .

attribute_nameThe name of the attribute to delete. Refer to theset_attribute command’s Attributes on page 186 for a list oftool-defined attributes.

Related Information

get_attribute

set_attribute

Examples

The following example clears the attribute net_node in the object $net .

delete_attribute $net net_node



delete_aware_component

delete_aware_component [-library library_name ] { -all | component_name }

The delete_aware_component command deletes the specified aware component or allaware components from the specified library.

Arguments

-library libnameSelects the aware library specified by lib name . If no libraryor no component name is specified, the first componentfound in all aware libraries is deleted.

component_nameName of the aware component.

-all Specifies that all components in the specified library are deleted.If you use this option and no library is specified, all thecomponents in all aware libraries are deleted.

Related Information

set_aware_library

report_aware_library

set_aware_component_property

Examples

The following example deletes the component AWMYCOMP1 from the library AWMYLIB.

delete_aware_component -library AWMYLIB AWMYCOMP1



delete_object

delete_object list_of_object_ids

The delete_object command deletes any design object. The object type is known to theobject, therefore it is unnecessary to specify the type of object.

Be careful when deleting individual objects. To remove all the design objects from thedatabase use the do_remove_design command.

Removes the specified design object from the database.

Arguments

list_of_object_idsThe list of object identifiers of the objects to be removed.

Related Information

do_remove_design

Examples

The following example creates a new module new_mod by copying the contents of a intonew_mod. The object id of the new module is returned and used to delete the newly createdmodule.

do_copy_module a new_mod 28993

delete_object {28993}



delete_unconnected_ports

delete_unconnected_ports [-preserve_busses] [-verbose]

The delete_unconnected_ports command deletes the unconnected Input and Outputports in the netlist.

Arguments

-preserve_bussesPorts belonging to the busses are not deleted, such that the portbusses are preserved.

-verbosePrint detailed information for each port detailed from the netlist.



do_blast_busses

do_blast_busses [-nets] [-ports] [-current_module]

The do_blast_busses command removes bus objects in the hierarchy or in the currentmodule. When followed by the write_verilog command, writes a netlist with all of thebusses converted to scalars. For example, when a physical design tool does not support theconcatenation operator {} in Verilog, then the command do_blast_busses performs thisconversion to scalars for the current module. When converted to scalars, thebuscomp_generator global will be used to name the scalars. If buscomp_generator isnot defined, a default naming convention will be used.

To remove all the bus nets from the top level and the lower levels of the design use thefollowing command:

do_blast_busses -nets

Converts pin, port, and net bus objects in the current module or in the hierarchy to scalars. Ifinstances of the module exist they are modified to connect each bit of the previously bussedport separately.

Arguments

-current_moduleBlast bus objects only in the current module.

-netsBlast bus nets as well as bus pins on the instance.

-portsBlast bus ports as well as bus pins on the instance.

Related Information

set_global buscomp_generator

do_rename

do_remove_design

Examples

The following example shows two modules, a and b. “Before do_blast_busses” contains busobjects before the do_blast_busses command was executed. In “After do_blast_busses”



all the bus objects have been removed by the do_blast_busses command and convertedto scalars.

Before do_blast_busses

module a(out);

output [1:0] out;

b b1(out);

endmodule

module b(out);

output [1:0] out;

endmodule

After do_blast_busses

module a(\out[1], \out[0]);

output \out[1] ;

output \out[0] ;

b b1(.\out[1] (\out[1] ), .\out[0] (\out[0] ));

endmodule

module b(\out[1] , \out[0] );

output \out[1] ;

output \out[0] ;

endmodule



do_build_generic

do_build_generic [-all] [-module name] [-extract_fsm] [-group_all_processes][-group_named_processes] [-group_process list_of_processes ][-group_all_subprograms] [-group_subprograms list_of_subprograms ][-parameters | -generics tcl_list ] [-sleep_mode]

Transforms the design read in by the commands read_vhdl and read_verilog into ahierarchical, gate-level netlist consisting of technology-independent logic gates, usingcomponents from the Ambit Synthesis Technology Library (ATL) and Extended ATL (XATL).The command performs constant propagation, loop unrolling, lifetime analysis, registerinferencing, and logic mapping.

You must run do_build_generic after specifying the source Verilog or VHDL files for theinitial design database and before calling do_optimize or any do_xform_* commands.You must run do_build_generic on a netlist even if it is already mapped to the targetlibrary. After running do_build_generic , any instance of a target library cell in the sourcedescription will remain mapped to that cell in the design database.

This command must be executed before any optimization commands (e.g., do_optimize ,do_xform_* ) can be applied. The generated netlist can then be written as a Verilog netlist(using the write_verilog command), a VHDL netlist (write_vhdl ), and an AMBITdatabase (write_adb ). These netlists can be loaded later for optimization and analysisusing the read_verilog , read_vhdl , and read_adb commands, respectively.

The options associated with this command allow for customization and control of logicalpartitions grouped by various processes. By default, this command treats all proceduralblocks (initial and always blocks in Verilog and processes in VHDL) as part of the module inwhich they appear without any hierarchy. When the grouping is done, a new level of hierarchyis created that only contains the logic represented by the selected blocks.

The do_build_generic options also allow the user to generate netlists for selectedmodules in the design hierarchy.

The netlist created by this command uses technology-independent logic gates usingcomponents from the ATL.

Tip

Use the find command to find all instances of a particular module. For example,the following command returns the names of all instance in module level2_mod.

find -of_cell_type level2_mod



Arguments

-allBuilds a generic netlist for all modules in the design hierarchy. Ifthere are multiple top-level modules in the design hierarchy, the-all or -module option must be specified. If -all is specified,the first module returned by [find -top *] is selected as thetop of the design hierarchy and as the default top timing module.

-extract_fsmExtract fsm for registers marked with the state vector directive.

-group_all_processesCreates a new level of hierarchy by grouping the logic from all theprocesses.

-group_named_processesCreates a new level of hierarchy by grouping the logic from all thenamed processes.

-group_process list_of_processesCreates a new level of hierarchy by grouping the logic from all thenamed processes specified by the list_of_processes .

-group_all_subprogramsCreates a new level of hierarchy by grouping the logic from all ofthe subprograms.

-group_subprograms list_of_subprogramsCreates a new level of hierarchy by grouping the logic from thesubprograms (functions and tasks in Verilog).

-module nameBuilds a generic netlist for the named module and allsub-modules in the hierarchy. Selects the named module as thetop of the design hierarchy and as the default top timing module.The commands get_hdl_hierarchy andget_hdl_top_level can be used prior todo_build_generic to identify the modules in the database.

-parameters tcl_listProvides a list of parameter names and values to use for theindicated generics.



-sleep_modeExplores areas of the design where power could be saved byusing the sleep mode technique and inserts sleep-mode logic forcommitment during gate level power optimization.

Related Information

do_dissolve_hierarchy

do_remove_design

get_hdl_hierarchy

get_hdl_top_level

read_symbol

read_verilog

read_vhdl

write_assertions

write_verilog

write_vhdl

Examples

The sequence of commands shown below read a Verilog file, design.v , perform high leveloptimizations and resource allocation, and then report the hierarchy.

read_verilog design.vdo_build_genericreport_hierarchy

To build a generic netlist for all modules:

do_build_generic

or:

do_build_generic -all



or:

do_build_generic -module des_top

To build a generic netlist for unit1 , blk11 , and blk12 in the diagram below, use thecommand:

do_build_generic -module unit1

Building a Generic Netlist

des_top

unit 1 unit 2

blk 11 blk 12 blk 21 blk 22



do_change_name

do_change_name { object_id new_name } | {-use_rules [-verbose] [-log filename ]}

The do_change_name command lets you rename objects within the design database. Theexecution of this command will change the name of one object only. An error will result if youattempt to change to a name that already exists in the corresponding name space.

Upon execution of the command, an attribute is created on the renamed object whose valueis the name being replaced. Use get_info or get_attribute to retrieve the name. Thename of the attribute created reflects the type of object being renamed.

There are two modes of operation -single object change name and -rules based changename:

■ Single object

do_change_name [ object_id ] [ new_name]

■ Rules baseddo_change_name -use_rules [ -verbose ] [ -log file ]

❑ Uses conversion rules specified by the set_global dcn_* variables.

❑ Default is no conversion.

❑ Process all objects hierarchically from current module down.

The following is the order for rule processing:

1. Remove reserved word - prefix reserved words with AMBIT_ so they don’t appear innetlist.

2. Replace first restricted character - if the FIRST character of the name is a restrictedcharacter, then it is replaced with the replacement character.

3. Replace last restricted character - if the LAST character of the name is a restrictedcharacter, then it is replaced with the replacement character.

4. Replace characters - Pass 1 - any character in the name that is restricted is replaced withthe replacement character. Pass 2 - any character in the name that is NOT in the allowedlist of characters is replaced by the replacement character.

5. Add prefix - add the prefix if present.

6. Check length and chop back middle if required - check name length, if too long removecharacters from middle until name is correct length.



7. Check for name collisions and change name, if required. Check new name for collisionswith existing names, if there is a collision create a new unique name.

The following are set_global variable conversion rules. Refer to the set_global commanddcn_* variables for additional details.

dcn_net_allow_conversion - set if conversion allowed (default is no conversion)dcn_net_max_length - max name lengthdcn_net_allowed - string of allowed charactersdcn_net_first_restricted - string of first restricted charactersdcn_net_last_restricted - string of last restricted charactersdcn_net_remove_chars - string of characters to removedcn_net_replacement_char - single replacement characterdcn_net_reserved_words - string of reserved words to changedcn_net_restricted - string of all restricted charactersdcn_net_prefix - prefix to add to name

dcn_bus_allow_conversion - set if conversion allowed (default is no conversion)dcn_bus_max_length - max name lengthdcn_bus_allowed - string of allowed charactersdcn_bus_restricted - string of all restricted charactersdcn_bus_first_restricted - string of first restricted charactersdcn_bus_last_restricted - string of last restricted charactersdcn_bus_replacement_char - single replacement characterdcn_bus_remove_chars - string of characters to removedcn_bus_reserved_words - string of reserved words to changedcn_bus_prefix - prefix to add to name

dcn_inst_allow_conversion - set if conversion allowed (default is no conversion)dcn_inst_max_length - max name lengthdcn_inst_allowed - string of allowed charactersdcn_inst_restricted - string of all restricted charactersdcn_inst_first_restricted - string of first restricted charactersdcn_inst_last_restricted - string of last restricted charactersdcn_inst_replacement_char - single replacement characterdcn_inst_remove_chars - string of characters to removedcn_inst_reserved_words - string of reserved words to changedcn_inst_prefix - prefix to add to name

dcn_module_allow_conversion - set if conversion allowed (default is no conversion)dcn_module_max_length - max name lengthdcn_module_allowed - string of allowed charactersdcn_module_restricted - string of all restricted charactersdcn_module_first_restricted - string of first restricted characters



dcn_module_last_restricted - string of last restricted charactersdcn_module_replacement_char - single replacement characterdcn_module_remove_chars - string of characters to removedcn_module_reserved_words - string of reserved words to changedcn_module_prefix - prefix to add to name

dcn_port_allow_conversion - set if conversion allowed (default is no conversion)dcn_port_max_length - max name lengthdcn_port_allowed - string of allowed charactersdcn_port_restricted - string of all restricted charactersdcn_port_first_restricted - string of first restricted charactersdcn_port_last_restricted - string of last restricted charactersdcn_port_replacement_char - single replacement characterdcn_port_remove_chars - string of characters to removedcn_port_reserved_words - string of reserved words to changedcn_port_prefix - prefix to add to name

Arguments

new_nameThe replacement name for the specified object.

object_idThe object identifier of the specified object.

-use_rulesEnable rules-based renaming ability controlled by theset_global command’s dcn_* variables.

-verbosePrints conversion progress messages in the console (old nameto new name) only valid for -use_rules option.

-log filenameWrites the conversion progress messages to the specified fileonly valid for -use_rules option.

Related Information

set_global



Examplesdo_change_name [find -instance instance_name ] new_name

get_info [find -instance new_name]



do_copy_module

do_copy_module module name

The do_copy_module command creates a single new module by copying the contents ofan existing module to the new module. You can only create one at a time. This command doesnot descend into the hierarchy of the design. That is, if the module contains instances of otherhierarchical objects, those objects and their contents are not copied to the new module. It onlyworks at the level from which it was called.

An example of this is to use the command to cache a module before making changes to thenetlist. The effect of the change on the quality of the new netlist can be tested using theget_area or get_module_worst_slack commands.This command can also be used toperform a uniquify_module function.

Arguments

moduleThe name of the source module.

nameThe name of the new module. The name must be unique.

Related Information

do_rebind

Examples

Below, “Copy contents from Source Module” demonstrates the creation of a new module,new_module1 , by copying the contents of the source module, a, to the new module.“Optimization Loop” shows how to use the do_copy_module in an optimization loop.

Copy contents from Source Module

do_copy_module a new_module1

72705

The object_id of the new module is returned and the command can be used as follows:

set_current_module [do_copy_module a new_module2]

72977



Optimization Loopproc xform {} {

set orig_slack [get_module_worst_slack]

do_copy_module top temp_module

# do some transforms here with the goal of improving timing

do_optimize -flatten on -effort high

set new_slack [get_module_worst_slack]

if { $new_slack > [expr $orig_slack + 0.001] } {

# Commit this change if the new slack is better by > 1 ps

delete_object [find -module temp_module]

} else {

# Abort this change since the slack is not significantly better.

delete_object [find -module top]

do_rename temp_module top

}



do_create_hierarchy

do_create_hierarchy [-module name] [-instance name] [-no_feedthrough][-dont_preserve_busses] instance_list

The do_create_hierarchy command creates a new level of hierarchy by placing a list ofinstances in a new module. The ports of the new module are derived automatically throughthe connections between the instances that are in the new module and the instances that areoutside the new module. By default, the command preserves the net and port busses in thenewly created hierarchy.

The command do_create_hierarchy introduces a new module in the database andalters the existing hierarchy.

Arguments

-dont_preserve_bussesDoes not preserve the busses in the new hierarchy.

-instance nameName of the instance created in the parent module. The defaultname is generated using instance_generator .

instance_listList of instances that make up the new module.

-module nameName for the new module. The default name is automaticallygenerated using the string set by the attribute.

-no_feedthroughNo feedthrough wires are created in the new hierarchy. Thisprevents the formation of feedthrough ports to model externaluses of an input signal.

Attributes

instance_generator

Related Information




set_global

Examples

In this example the new module pcimod is created by placing all instances whose name startwith pci .

do_create_hierarchy -module pcimod [find -inst pci*]




do_dissolve_hierarchy [-hierarchical] [-view name] [ instance_list | module_list ]

The do_dissolve_hierarchy command dissolves hierarchical instances of modules byflattening the hierarchy of the instance. Each instance specified in the instance_list isexpanded into its parent module. The parent module now contains all the logic for thesub-modules. The hierarchical components inside the modules referenced by the instancesare now components in the current module. The new names of the cells in the parent moduleare derived by appending a number to the original instance. Once dissolved, an instance nolonger exists in the design and constraints can not be placed on it.

By default, the command dissolves the current module into its parent.

The netlist changes as the hierarchical components inside the modules referenced by theinstances are now components in the current module.

Arguments

-hierarchicalAll hierarchical components of the instances are recursivelyexpanded to flatten the current module. The current module nowonly has instances of the library cells and instances of themodules marked by the set_dont_modify command. If theinstance list and the hierarchical option are not specified, then allinstances of the current module are expanded in their respectiveparent modules.

instance_list List of all instances to be dissolved.

module_listList of all modules to be dissolved.

-view nameList of all names to be dissolved.

Attributes

hierarchy_divider



Related Information

do_create_hierarchy

do_uniquely_instantiate

set_current_module

set_dont_modify

Examples

The hierarchical design before and after the command do_dissolve_hierarchy [find-instance unit2] .

Before do_dissolve_hierarchy [find -instance unit2]1

After do_dissolve_hierarchy [find -instance unit2]

des_top

unit 1 unit 2


des_top

unit2_blk22unit2_blk21unit 1

blk 11 blk 12



do_extract_critical

do_extract_critical [-critical_ratio float ] [-critical_offset float ][-fanin_depth integer ] [-fanout_depth integer ] [-hierarchical]

The do_extract_critical command extracts a section of the current module based onthe worst slack. The critical_ratio option allows you to specify a wider extraction regionbased on a fraction of the worst slack. For example, a critical_ratio of 0 causes onlythe critical path to be extracted. A critical ratio value of 0.5 means that all components onpaths having slack up to 0.5 times the worst (most negative critical) slack are also extracted.Likewise, the critical_offset option allows you to specify a wider extraction regionbased on a specific relative amount from the worst slack. For example, a critical_offsetvalue of 1.5 means that all nets whose slack falls between the worst slack and the worst slacknumber minus1.5 time units are extracted including the two nets defining this region. Theextracted module can be manipulated or written in the same way as any other design module.

When the -hierarchical option is used, the do_extract_critical command extractsthe critical path of a design and writes it to a separate new module at each level of thehierarchy, starting with the current module. Thus, all of the hierarchical components on thecritical path are extracted from the current module and the hierarchy of the components ismaintained. In the absence of this option, extraction is done for the current level of hierarchy.It is not done for sub-levels.

The do_extract_* set of commands extract sections of the current module and write it toa separate visible module in the design hierarchy. The extracted section of the module isdetermined by the particular do_extract_* command used. The set of do_extract_*commands only work on the current module (identified by the set_current_modulecommand). Paths between modules are not extracted. To extract a path that exceeds amodule boundary, you must execute a do_dissolve_hierarchy command to group thedesired logic within a single module boundary, then execute the particular do_extract_*command.

In all cases, when using the extraction commands, the extracted module contains more inputsand outputs than expected. This is necessary to capture the arrival and required constraintsof the extracted piece of logic in the context of the original module. For example, a net thatexists in the middle of a critical path that also fans out to non-critical logic will appear as anoutput of the extracted module.

A new module and an instance of that module is created by extracting the critical section ofthe netlist. The hierarchy is changed. You must run the do_dissolve_hierarchycommand to restore the original hierarchy



Arguments

-critical_ratio floatIndicates the range of slack as a fraction of the worst slack in themodule for which the gates would be extracted. The default valueis 0, indicating the critical path only.

-critical_offset floatIndicates the range of slack as a relative amount of the worstslack in the module for which the gates would be extracted. Thedefault value is 0, indicating the critical path only.

-fanin_depth integerSpecifies the number of levels of fanin logic to extract. Thedefault is 0.

-fanout_depth integerSpecifies the number of levels of fanout logic to extract. Thedefault is 0.

-hierarchicalExtracts the critical path through the hierarchy starting with thecurrent module and placing the portion extracted from aparticular module in its own module at each level of the hierarchy.

Related Information


do_extract_fanin

do_extract_fanout

do_extract_non_critical

Examplesset extracted_mod [do_extract_critical] 73473

get_name $extracted_mod

top_critical_0_critical_0

report_hierarchy



|-top(g)

| |-top_critical_0(g)

| | |-top_critical_0_critical_0(g)



do_extract_fanin

do_extract_fanin [-level integer ] [-threshold float ] [-early] [-module module ][-tristate] [-sequential] list_of_object_id

The do_extract_fanin command extracts a section of the netlist defined by thefanin-cone of the specified list of object identifiers. All the logic associated with the list ofobject ids is placed in one extracted module.

See the command do_extract_critical on page 58 for a more information about the extractioncommands.

A new module and an instance of the module is created by extracting a section of the netlistspecified by the fanin-cone. An extra level of hierarchy is added to the design.

Arguments

-earlyUsed with the threshold option to specify early slack. The defaultvalue is late. This option is also known as hold.

-level integerSpecifies a maximum number of logic levels to extract. Thedefault is to extract all the logic in the fanin cone.

list_of_object_idA list of the nets, pins, or ports from which to start the extraction.

-module moduleWork on the specified module, not the current module.

-sequentialExtract sequential element into the new module. If not specified,the extraction will not include sequential elements. The valuereturned is the object id of the module created. If no module iscreated a null string is returned.

-threshold floatExtract only the logic having a slack of the value specified byfloat or a worse slack value.The threshold option is anoptional qualifier that limits the fanin cone based on slack, not onlogic levels. For example, setting a threshold of -2 and a level of4 extracts all gates within 4-levels of logic of the inputs to the



given objects that have slack of -2 or worse. The more negativethe number for slack, the worse it is.

-tristateExtracts a 3-level cone from any bit of the output bus. Cones oflogic will include tristate cells and the respective fanin based onthe other options specified. The default without the -tristateoption is to stop extraction on the logic cone when a tristate cellsis found.

Related Information


do_extract_fanin

do_extract_fanout


Examples

This command extracts a 3-level cone from any bit of the output bus out .

do_extract_fanin -level 3 [find -output -port out*]



do_extract_fanout

do_extract_fanout [-level integer ] [-threshold float ] [-early] [-module module ][-tristate] [-sequential] list_of_object_id

The do_extract_fanout command extracts a section of the design determined by thefanout cone of the specified list of object identifiers. All the logic associated with the list ofobject ids is placed in one extracted module.

A new module and an instance of the module is created from the extracted section of thenetlist, specified by the fanout cone. A level of hierarchy is added to the design.

For more general information on the extraction commands see the commanddo_extract_critical on page 58 and also do_extract_fanin on page 61.

Arguments

-earlyUsed with the threshold option to specify early slack. The defaultvalue is late. This option is also known as hold.

-level integerSpecifies a maximum number of logic levels to extract. Thedefault is to extract all the logic in the fanout cone.

list_of_object_idA list of the nets, pins, or ports from which to start the extraction.

-module moduleWork on the specified module, not the current module.

-sequentialExtract sequential element into the new module. If not specified,the extraction will not include sequential elements. The valuereturned is the object id of the module created. If no module iscreated a null string is returned.

-threshold floatExtract only the logic having a slack of the value specified byfloat or a worse slack value. The threshold option is anoptional qualifier that limits the fanout cone based on slack, noton logic levels. For example, setting a threshold of -2 and a levelof 4 extracts all gates within 4-levels of logic of the inputs to the



given objects that have slack of -2 or worse. The more negativethe number for slack, the worse it is.

-tristateExtracts a 3-level cone from any bit of the input bus. Cones oflogic will include tristate cells and the respective fanout based onthe other options specified. The default without the -tristateoption is to stop extraction on the logic cone when a tristate cellsis found.

Related Information


do_extract_fanin

do_extract_fanout


Examples

This command extracts a three-level cone from any bit of the input bus in :

do_extract_fanout -level 3 [find -input -port in*]




do_extract_non_critical [-critical_ratio float ] [-critical_offset float ]

The do_extract_non_critical command extracts the section of the netlist that is not onthe critical path. Specifying the -critical_ratio and -critical_offset optionswidens the region of the critical path to be excluded from extraction. This command is rarelyused.

A new module and an instance of the module is created by extracting the non critical sectionof the netlist. A level of hierarchy is added to the design.

See the command do_extract_critical on page 58 for more general information.

Arguments

-critical_offset floatIndicates the range of slack as a relative amount of the worstslack in the module for which gates would be excluded fromextraction. The default is 0, indicating the critical path only.

-critical_ratio floatIndicates the range of slack as a fraction of the worst slack in themodule for which gates would be excluded from extraction. Thedefault is 0, indicating the critical path only.

Related Information


do_extract_fanin

do_extract_fanout




do_optimize

do_optimize [-checkpoint] [-critical_offset float ] [-critical_ratio float ][-design_rule_have_been_fixed] [-distributed] [-dont_legalize][-dont_propagate_constants] [-dont_reclaim_area | -reclaim_maximum_area][-dont_remove_redundancy] [-dont_structure] [-dont_uniquify][-effort { low | medium | high }] [-flatten { on | auto | off }][-force] [-incremental] [-max_area float ][-minimize { single_output | multiple_output | single_pass }][-no_design_rule] [-no_partition] [-phase_assignment] [-pks][-power {no_gatelevel_opt | low | medium | high}] -restructure_aware[-priority { area | time }] [-remap_for_timing] [-scan_file][-stop_before_placement] [-time_budget]

The do_optimize command performs logic optimization on the current module as specifiedwith the set_current_module command. Depending upon the state of the designdatabase, logic optimization will include some or all of the following: uniquification, constantpropagation, structuring, redundancy removal, technology mapping, timing-drivenoptimization, buffering of multiport nets, and design-rule fixing.

Child modules which are not marked with the dont_modify attribute are always included inthe optimization process.

If the default do_optimize flow is used, all child modules are simultaneously optimizedalong with the parent module (current_module).

If the -time_budget option is used, some level of optimization is done on the non-uniquifiedchild modules prior to uniquification and optimization of the parent module. With the-time_budget option, the initial timing optimization of the non-unique child modules usestime budgeting to derive the constraints for each child module. After each child module hasundergone this initial optimization, uniquification is performed and the parent module and allchild modules are simultaneously optimized as in the default flow. The use of the-time_budget option may improve the run time and quality of results obtained. The designsmost likely to benefit from this option are those with a fair amount of module reuse or largedesign databases.

This command maps a generic cell netlist (ATL) or a technology specific cell netlist to atechnology specific cell netlist. The netlist is optimized according to the constraints.

Arguments

-power {no_gatelevel_opt | low | medium | high}Performs all types of gate-level transformations tosimultaneously optimize power, delay, and area.



If you have sleep-mode logic inserted from running thedo_build_generic -sleep_mode command,do_optimize-power will first commit/decommit the logic based on potentialpower savings. The -power argument will alsocommit/decommit clock-gating logic inserted when running thedo_xform_optimize_generic -clock_gate commandbased on a power savings analysis.

The effort level you include with the -power argument specifiesthe scope of the power optimization that you want. In general, thehigher the level, the better the power results, but the longer therun time for the optimization.Default: mediumValue: Specify one of the following four effort levels:

-scan_fileDeclares a file name to be given to the scan report file. Thisoption is used when test synthesis is enabled.Default: top_module .scan

no_gatelevel_opt Commits only the sleep mode and clock gatinglogic that was inserted with thedo_build_generic anddo_xform_optimize_generic commands. Nogate-level optimization is performed.

low Performs gate-level transformations, such asresizing, pin swapping, and restructuring, tominimize power consumption while trying to meettiming.

medium Performs the same gate-level transformations asthe low effort level, but does more iterations tosimultaneously optimize the power and timing.This level is recommend for a non-optimizedcircuit.

high Performs gate-level power optimizations at thehighest level. It does more iterations than the lowand medium effort levels to minimize the powerconsumption.



See “Arguments for Transform (do_xform_*) Commands” on page 78 for descriptions ofoptional arguments.

Attributes

map_inversion_through_register

slew_propagation_mode

target_technology

time_budget_stop_before_uniquification

time_budget_min_size

Related Information


get_attribute

read_verilog

set_attribute

set_current_module

set_top_timing_module

write_verilog

Examplesdo_optimize -checkpoint

do_optimize -effort high -flatten auto

do_optimize -time_budget



do_pop_module

do_pop_module

The do_pop_module command restores the current_module that was active before the lastdo_push_module command. Pop and push commands can be stacked arbitrarily. If there isno module on the stack, a do_pop_module command sets the current_module to anempty string.

Related Information

do_push_module

get_current_module

Examples

See the examples for do_push_module on page 70.



do_push_module

do_push_module module_id

The do_push_module command temporarily changes the current_module by pushingthe existing current_module onto an internal stack, and changing the new current_moduleto the module specified. Use the do_pop_module command to recover the previouscurrent_module .

Note: This command does not affect the top_timing_module .

Arguments

module_idThe object identifier of the module that is to be made the currentmodule after pushing the current module on the stack.

Related Information

do_pop_module

get_current_module

Examples

Get the object_id of the current_module, a.

get_names [get_current_module]

a

The module is pushed onto the top of the stack, changing the current_module to thatspecified, b.

do_push_module [find -module b]


b

The previous current_module is restored from the stack

do_pop_module


a



do_rebind

do_rebind instance_name_or_id cell_name_or_id

The do_rebind command can change any instance of a cell from a technology library toreference another cell in that library or change the cell reference of an hierarchical moduleinstance, provided that you create a cellref first with the create_module_referencecommand. See the example below for more details.

Note that a functional match is not required by do_rebind and that the command does notperform any consistency checks, such as pin compatibility. Therefore, it is possible to corruptthe logical function of a netlist by rebinding cells inappropriately. Use the functionget_equivalent_cells to determine the set of functionally equivalent cells for resizingpurposes.

The timing analysis information is updated automatically for this change. There is no need totake any additional action to guarantee accurate timing reports or optimization after executingthe do_rebind command.

Changes the instance data structure to refer to a different cell reference. No change to thedesign netlist connectivity to that instance.

Arguments

instance_name_or_idObject ID or name of the instance to rebind.

cell_name_or_idThe new cell name or ID to bind the instance to.

Related Information

create_module_reference

do_copy_module

get_equivalent_cells

Examples

■ Rebind a technology cell instance.

get_names [find -cellref IV*]

IV IVA IVAP IVDA IVDAP IVP



get_equivalent_cells [find -cellref IV]

IVP IVA IV IVAP B5I B4I B5IP B4IP B2A

do_rebind [find -instance iv] IVP

Info: Bound instance 'iv' to cell 'IVP' <TCLCMD-705>

■ Rebind a module instance.

Before

module top (in, out);

input in;

output out;

sub sub1(in, out);

sub sub2(in, out);

endmodule

module sub(in, out);

input in;

output out;

assign out = ~in;

endmodule

Script excerpt

do_copy_module sub sub_copy_1

create_module_reference [find -module sub_copy_1]

do_rebind sub1 sub_copy_1

After

module sub(in, out);

input in;

output out;

not i_0(out, in);

endmodule

module sub_copy_1(in, out);

input in;

output out;

not i_0(out, in);

endmodule

module top(in, out);

input in;

output out;

sub sub2(.in(in), .out(out));

sub_copy_1 sub1(.in(in), .out(out));

endmodule



do_remove_design

do_remove_design [-hierarchical] [-all] [ list_of_module_name_or_id ]

The do_remove_design command deletes modules from the database.

Arguments

-allDeletes all modules. If you use the -all option and provide alist_of_module_name_or_id , the list is ignored.

-hierarchicalDeletes the specified module and its hierarchical submodules.

list_of_module_name_or_id



do_rename

do_rename [-hierarchical] [-net] [-instance] [-net_to_port]

The do_rename command is used to change the names of instances or nets in a design. Thegenerators are used to generate names for instances and the nets created in the design. Theac_shell has an instance generator and a net generator. The name generators defaults canbe set by the set_global command. See the set_global net_generator andset_global instance_generator commands on setting net and instance names. Youcan change the naming convention for nets or instances previously generated in the currentmodule by using the do_rename command.

To change the name of a specific net or instance use the do_change_name command.

Arguments

-hierarchicalSpecifies that the renaming is also to be done for the modules inthe downward hierarchical path of the current module.

-netIndicates that only the net names are modified based on thecurrent net generator, set using the set_global command.The instance names remain unchanged.

-instanceIndicates that only the instance names are changed, based onthe current instance generator, set using the set_globalcommand. The net names remain unchanged.

-net_to_portSometimes the back-end layout tools require that the netconnected to the port be of the same name as the port (toeliminate non structural statement, such as the assignstatement in Verilog). This option changes the net names tomatch that of the ports, when possible.

Related Information

do_change_name

set_global



do_blast_busses

set_global net_generator

set_global buscomp_generator

set_global instance_generator




do_uniquely_instantiate [-hierarchical | instance_list ]

The do_uniquely_instantiate command creates unique instances for modules. Thiscommand is used when one instance of a module needs to be optimized differently fromanother by placing different constraints on each of them. Therefore one needs to uniquelyassociate each instance with the module.

Each instance in the design is referenced by a unique module, so that different constraintscan be applied on each module, and different transforms may be performed on each module.

This command is automatically executed as part of do_optimize command when it detectsthat one module has more than one instance, and each instance has a different environment(drivers and loads connected to its ports).

The current module, as specified by set_current_module , is affected by the command.

Each instance (specified in the instance_list ) in the netlist now refers to a uniquemodule. So the number of unique modules referenced by the instances in the netlist changesafter this command.

Arguments

-hierarchicalAll instances in the hierarchical tree of each instance in thecurrent module will be associated with uniquely created modules

instance_listA list of instances that will be instantiated uniquely. Ifinstance_list is not specified, unique modules will begenerated for all instances of the current module as set byset_current_module command. The modules that haveinstances of the current module will be modified to reflect thechange in binding the instances to their respective uniquemodules.

Related Information


do_optimize



set_current_module

Examples

If blk11 and blk21 are instances of an adder (mod_adder ) that need different constraintsduring optimization we can use

do_uniquely_instantiate blk11 blk21

After the unique modules have been generated, the two instances would appear as follows:

mod_adder_0 blk11( …port connections…);mod_adder_1 blk21( …port connections…);

where mod_adder_0 and mod_adder_1 are unique instances of mod_adder

des_top

unit 1 unit 2




Arguments for Transform (do_xform_*) Commands

The following is a list of the options available for use with the do_xform_* commands, whichare defined in the following sections. Most of these commands have an option list that is asubset of the list provided here.

-bufferWhen used with do_xform_fix_hold , allows buffers to beused to fix hold violations.

When used with do_xform_reclaim_area , removes bufferswhich can be removed from the design without worsening theworst slack in the design.

When used with do_xform_timing_correction , buffersnon-critical fanouts of the critical nets so that the load driven bythe critical net is reduced and the effective timing on the criticalpath is improved.

When used with do_xform_fast_optimize , creates buffertrees to improve delays on nets, then skews these trees toimprove delay on the critical path.

-change_file filenameIndicates the file name where the changes need to be written.When doing in-place-optimization (IPO) you must have writepermissions to the specified file. The filename can be the fullpath name to a file. If not, the file is opened in the currentdirectory. Each line contains information about a specific changein the following format:change old_cell new_cellhierchical_instance_name : ADD or DELETE orRESIZE old_cell : The name of the cell bounded to thisinstance initially.If it is a new instance, then it is printed as:’-’. new_cell : Name of the cell bounded to this instance afteroptimization is completed.

-change_limit integer

Indicates the maximum number of changes allowed in the netlistwith regards to the number of instances added, deleted, andresized when doing IPO. Connectivity changes (that is, whenconnection to instances are added, deleted, etc) are not



counted. Changes to a particular instance are counted once, forexample, if an instance is first created, and then resized in theoptimization process, it will be counted as one change in thenetlist.

-checkpointCreates a checkpoint of the design in checkpoint.adb fileafter each major step. The timing optimization step may createintermediate checkpoints as there are several importantchanges taking place. The number of times checkpoints aredone depends on the effort level and other options used. Allother steps create a checkpoint at the end of that step.

There is only one checkpoint.adb file created. If a previousfile exists, either from previous session or from previous steps inthe current session, it is overwritten with the new adb formatinformation.

-clock_gateUsed with do_xform_optimize_generic , this argumentuses the Low-Power Synthesis (LPS) engine to explore andinsert clock-gating logic where power savings could be made.Final commitment of the logic is made during power optimization.

Make sure that you use set_clock_gating_options beforeyou run this command if you want specific clock gating optionsused during this step.

-cloneWhen used with do_xform_timing_correction , splits a netinto two nets to improve timing on the critical path. This is doneby duplicating the instance driving the original net. This option isignored if the fix_hold or min_hold options are used.

When used with do_xform_reclaim_area , removesunnecessary clones from the netlist.

-critical_offset floatThis option is similar to the critical_ratio option except thatthe critical_offset number is added to the value of worstslack.



-critical_ratio floatIndicates the range of slack for paths to be considered criticaltoward the end of optimization for timing-driven buffer insertion,cloning, and resizing; fixing design rule violations; and areareclamation. Specify the argument float as a percentage (anumber between 0 and 1) of the worst slack. Only positivenumbers are considered. This option allows a range of worstslack to be considered critical. The critical range considered isdefined as follows.For negative worst slack:worst_slack * (1 - critical_ratio) +critical_offsetFor positive worst slack:worst_slack * (1 + critical_ratio) +critical_offsetDefault: 0

-design_rule_onlyApplies timing corrections to meet the design rules, but no otherchanges such as improving the worst slack are made. Thisoption is useful when the netlist is created or edited outside thesynthesis process and brought in for integration, or when thenetlist was initially synthesized with the -no_design_ruleoption.

-design_rule_have_been_fixedUse this option if design rules on the netlist already have beenfixed. By default, optimization will initially ignore design ruleviolations. Using this option, optimization will honor design rulesfrom the very start. At some point, optimization will still try to fixany remaining rule violations.

-distributedPerforms the optimization in distributed mode. This option can beapplied in conjunction with all other transform command optionsexcept -time_budget and -pks .

-dont_fix_design_ruleTells optimization to observe design rules but not to fix anydesign rule violation. This option enables a faster timingcorrection on a previously optimized netlist where design ruleviolations have been fixed. This option cannot be used with the-design_rule_only option.



-dont_legalize

Prevents the automatic execution of the commanddo_xform_tcorr_eco at the end of optimization. Thisdisables the default behavior when the commandsdo_optimize -pks and do_xform_optimize _slack (forPKS) are run.

-dont_modify_childrenApplies the optimization transform only to the portion of thedesign contained in the current module. In the absence of thisoption, the transforms are applied to the entire design containedin the current module including its hierarchical descendents(children).

-dont_propagate_constantsPrevents propagation of constants during generic optimization.

-dont_reclaim_areaPrevents downsizing and the removal of buffers or cloneinstances to reduce area. By default, area reclamation is donewhen slack fixing ceases to find improvement. This option isuseful when you want prevent area reclamation in parts of thedesign that are not timing critical. This option cannot be usedwith the relcaim_area_only option.

-dont_remove_redundancyPrevents removal of redundancies during generic optimization.

-dont_structurePrevents structuring during generic optimization.

-dont_uniquifyBy default do_optimize will uniquify the design. By applyingthis option the design will not be uniquified. This might be usefulto save run time on structuring multiple instantiated modules.

-effort {low | medium | high}Controls the CPU time spent during the timing optimization step.Default: medium

low Operation is done quickly to meet requirementsthrough easy optimization steps.



-fanin_depth integerExtracts the non critical fan-ins on the critical path. Theinteger value specified gives the level up to which thenon-critical fanins of the critical path are extracted.Default: 0

-fanout_depth integerExtracts the non critical fanouts on the critical path. The integervalue specified gives the level up to which these non-criticalfanouts should be extracted in the critical path.Default: 0

-fix_clock_netPerforms transformations or buffer insertions on clock nets. Bydefault, the clock network is not modified by the timing correctiontransformations.

-fix_constant_portsPerforms buffer insertion on constant net (power or ground)driving output ports. By default, the connections of constant netsto output ports are not modified.

-fix_holdPerforms transformations to fix hold violations regardless ofwhether the transformations worsen slacks on late times (that is,setup violations) as long as they fix hold times. The changes inthe circuit will attempt to minimize the decrease in slacks on latetimes.

-flatten [on | off | auto]Controls the operations employed for optimization of logicequations. If flatten option is set to on , the logic equations areflattened into a sum of products form before applyingoptimization. This generally helps in creating faster and optimalimplementation of the logic, even though it may take up extraarea (gates). For some circuits, this option may result in

medium Extra time is spent searching for alternatemappings and structures to meet all theconstraints.

high Further improvements by applying various time-consuming algorithms.



excessive run time or memory usage. If flatten option is set toauto , only certain flattening operations are performed; some ofthe time consuming steps are skipped. The flattening step maybe disabled entirely by setting the option to off .Default: off .

-footprintSubstitutes cells with higher (lower) drive capability for the cellswith lower (higher) drive, if both cells have the same footprints (inaddition to the same functionality). This assures that there are nochanges in the placement or routing of the cells. This is alsoreferred to as in-place swapping of cells. This option is usefulwhen operating on a netlist that has been already placed and nosignificant changes can be made to the netlist. This optionimplies -resize option.

-forceWhen used with do_optimize , performs all optimization stepsirrespective of the initial state of the design. If the design wasalready mapped, it gets unmapped prior to carrying out all theoptimization steps. If the design has been previously optimized(some or all steps), the default action for do_optimizecommand is to skip over the steps it considers inappropriate.

When used with do_xform_remove_redundancy , unmaps apreviously mapped netlist before applying the transformations.By default, this command does not transform a previouslymapped or optimized netlist. After applying the transformation,the netlist must be remapped.

When used with do_xform_unmap , unmaps cells with adont_modify attribute, such as test cells and IO cells. Bydefault, these cells are not unmapped when usingdo_xform_unmap .

-hierarchicalPerforms mappings, unmappings, structuring, or removesredundancies on the modules in the downward path of thecurrent module. It depends on the command being used. If thisoption is not given, then only the current module is affected bythe command used.



-incrementalIndicates that the design is already well-optimized and that thedesign rule violations have been fixed. In addition, if the globalvariable of auto_slew_prop_selection is set to true ,optimization occurs at the highest slew depth.

-max_area floatPrevents timing optimization from increasing area beyond thespecified value.

-min_holdPerforms transformations to fix hold violations only if they do notworsen negative slacks on late times (i.e. setup time violations).

-minimize {single_output | multiple_output | single_pass }When PLA is extracted or a netlist is flattened (see -flattenoption), this option controls what two-level logic minimizationstrategy is used.single_output (default value) indicates that equation foreach output of module will be minimized independently.multiple_output indicates that equations for all outputs ofmodule will be minimized all together, increasing the chance ofproduct terms of equation being shared among different outputs.The complexity of multiple_output minimization is usuallymuch higher than single_output minimization.single_pass will force BuildGates Synthesis to performminimization in one pass, rather than iteratively, to reduceoptimization effort for fast run time.

-no_design_ruleOptimization will completely ignore all design rules.

-no_partitionPrevents automatic partitioning of the design into smallermodules for optimization, irrespective of the size of the module.Each module boundary should be retained as the partition tooptimize.

-no_pinswapPrevents pin swapping.

-phase_assignmentWhen PLA is extracted or a netlist is flattened to two-level form,



this option allows BuildGates Synthesis to invert the phase ofoutputs, perform minimization on both ON-set and OFF-set ofthe equation, and pick the simpler implementation of logic. It canapply to either single_output or multiple_outputstrategy, depending on the setting of option -minimize . WhenOFF-set of equation is much bigger than ON-set, phaseassignment optimization could be very expensive in terms of runtime.

-pinswap_onlyAllows only pinswap moves.

-pksUses PKS licence. Only use this if you have an unplaced netlistand you want to place the netlist in post placement optimization.

-powerUsed only with the do_xform_optimize_slack command,the -power option performs timing and power trade-offs. Itperforms only timing optimization, but, during optimization—ifthere are two optimization choices with similar timing—thecommand will choose what consumes the least power.

-priority {area | time}Sets area or timing minimization to be the highest priority of thetechnology independent optimization step. If you have a looselyconstrained or unconstrained design, then the priority should beset to area .Default: time

-quickPerforms only one pass of timing correction transformations tomeet constraints, reclaim area and fix design rule violations. Bydefault, the timing correction commands iterate until no furtherimprovement can be achieved.

-reclaim_area_onlyPerforms transformations only to reduce area, without worseningthe worst negative slack. These include replacing cells withsmaller area cells that has the same functionality, and removingunnecessary buffers or clones. This option cannot be used withdont_reclaim_area option.



-reclaim_maximum_areaPerforms area reclamation transforms on any slack that is betterthan the worst slack. By default, area reclamation is not done onany path that can worsen the slack or create negative slack.

-remap_for_timingPerforms timing-driven remapping of the design. After the initialtechnology mapping is done, the do_optimize command maydo remapping of the cells for timing optimization. If this option isnot used then do_optimize command will not remap thedesign.

-resizeIf the library has choice of cells with the same functionality butdifferent drives, replaces a cell with an equivalent cell withdifferent drive if the new cell contributes toward meeting the goalof the transformation.

-restructure_awareEnables the standard optimization engine to performcombinational restructuring on the logic in the Ambitware (ACL)modules. Without this switch, restructuring is achieved only bycomponent swapping using the Datapath engine.

-stop_before_placementThe design is placed after pre-placement optimization and nowwill stop before placement.

-timingPerforms timing-driven mapping on the netlist. By default,area-driven mapping is performed.

-time_budgetUses time budgeting to derive constraints and optimize modulesin the design hierarchy; performs a multi-pass optimization, firstoptimizing in a bottom-up fashion using the time budgetedconstraints and then following with a hierarchical compile (defaultcompile) from the root (top-level) module.

-upsize_onlyAllows only upsizing moves during resizing. Downsizing movesare not allowed.



do_xform_buffer

do_xform_buffer [-quick] [-dont_modify_children] [-no_design_rule][-fix_clock_net] [-dont_reclaim_area | -reclaim_maximum_area] [-max_areafloat ] [-critical_ratio float ] [-critical_offset float ] [-incremental]

The do_xform_buffer command inserts buffers at the non-critical fanouts of the critical netsso that the load driven by the critical net is reduced and the effective timing on the critical pathis improved. It applies buffer transformations.

This command is equivalent to the command do_xform_timing_correction -buffer .

Arguments


Related Information

do_xform_timing_correction



do_xform_buffer_tree

do_xform_buffer_tree [-min_fanout value ] [-non_hierarchical] [-input_ports |-output_ports | -ports | -pins] [-dont_remove_buffers] [ net ]

The do_xform_buffer_tree command causes balanced buffer trees to be inserted in thecurrent module and all sub-modules. Each buffer tree insertion is made only if there is noworsening of the local slack at the buffer tree drive cell. If there is no change of slack or thenet is unconstrained, the buffer tree is inserted.

One usage of buffer tree insertion is when assembling pieces of an unoptimized design, asin a time budgeting flow. For this reason, a form of the command is provided that createsbuffer trees for nets that are connected to module ports or pins only, for greater speed.

Area is not considered. Design rule cost is also not considered, but in practice the design ruleviolations are usually reduced with a buffer tree in place because the sizing and fanout ratiosare controlled in the buffer tree to be optimal for timing, and in most libraries this places theslews, capacitances, and fanouts well within the design rule limits.

By default, any existing buffer tree containing the target net is removed and replaced by a newbuffer tree. Optionally, a buffer tree can be inserted with no existing buffer cells removed, butthis is not recommended in general as the quality of results is higher when the entire buffertree is replaced with a new tree.

The do_xform_buffer_tree step is performed automatically by the do_optimize flow,immediately after the technology mapping (do_xform_map ) step.

foreach i [find -nets] {

do_xform_buffer_tree $i; # may fail second time

}

Note: Inverted loads are not considered part of the buffer tree. The buffer tree is created froma network of non inverting single input/output buffer cells. In the case of a library containingno buffer cells, balanced buffer trees are created from an even number of inverter stages.

This command is not suitable for post-layout optimization, because it does not preserveannotated capacitances, resistances, or SDF delays as it inserts or replaces buffer trees. Anybuffers created by this command will revert to the appropriate wire load model for delaycalculation.

Be careful when using the net form of this command in a Tcl loop, as the command itself willbe deleting and creating nets in the design. For example, do not attempt this code becausethe cached list of nets may become obsolete after the first buffer insertion.



Arguments

-dont_remove_buffersPreserves all buffers in the original design. For a given net, onlynew buffer cells are added. By default, the existing buffer tree isreplaced with a new buffer tree.

-input_ports | -output_ports | -ports | -pinsInserts buffers only on nets connected to input or output ports, orall ports, or all pins. Cannot be given with the net argument. Bydefault, all nets are considered for buffer tree insertion.

-min_fanout valueDo not insert a buffer tree when the number of loads is less thann . Default is 1, which means consider all nets for buffer treeinsertion regardless of fanout.

netThe object ID of a single net in the design that is to be replacedwith a buffer tree. If not given, then all nets are considered forbuffer tree insertion.

-non_hierarchicalInserts buffers in the current module only. The default is to insertbuffers in the current module and all unique children, recursively.

Related Information




do_xform_clone

do_xform_clone [-quick] [-dont_modify_children] [-no_design_rule] [-fix_clock_net][-dont_reclaim_area | -reclaim_maximum_area] [-max_area float ][-incremental] [-critical_ratio float ] [-critical_offset float ]

The do_xform_clone command performs cloning transformations. This command splits upa net into two nets by duplicating the instance driving the original net to improve timing oncritical path.

This command is equivalent to the command do_xform_timing_correction -clone .

Arguments


Related Information




do_xform_fast_optimize

do_xform_fast_optimize [-effort { low | medium | high }] [-resize -buffer] [-one][-critial_ratio float ] [-critial_offset float ]

The do_xform_fast_optimize does a simultaneous resizing and rebuffering. Thealgorithm is fast but the resulting slack may not be optimal.

Arguments

-onePerforms only one pass, doesn’t t iterate.



do_xform_fix_design_rule_violations

do_xform_fix_design_rule_violations [-footprint] [-resize][-buffer][-dont_modify_children] [-clone] [-fix_clock_net] [-incremental][-dont_reclaim_area | -reclaim_maximum_area] [-critical_ratio float ][-critical_offset float ]

The do_xform_fix_design_rule_violations command is another version of thedo_xform_timing_correction command. It provides a tighter control and selection onthe transformations to be performed on the design. The transformations are applied only tothe design rule violators. This command should be applied when one or more transformationshave been applied using do_xform group of commands ordo_xform_timing_correction command with the -no_design_rule option.

If none of the three options, resize , buffer , or clone , are used, then by default all threetransformations are applied to get the best possible results. In effect, the default is the sameas using all the three options.

This command maps a technology specific cell netlist to a technology specific cell netlist.

Arguments


Related Information




do_xform_fix_hold

do_xform_fix_hold [-footprint] [-quick] [-resize] [-buffer][-dont_modify_children] [-no_design_rule] [-minimize] [-fix_clock_net][-dont_reclaim_area] [-max_area float ] [-critical_ratio float ][-critical_offset float ] [-incremental] [-reclaim_maximum_area]

The do_xform_fix_hold command provides a better control when only the hold violatorsare to be transformed. It applies transformations on hold violators. It attempts to fix the holdtimes without trying to fix the setup times. Preserves slack by default.

If neither resize nor buffer option is used, then by default both transformations are applied toget the best possible results. In effect, the default is the same as using both options.


Arguments

-minimizeIndicates that the transformations to fix hold violations should beperformed only if it does not worsen setup requirements.


Related Information




do_xform_fix_multiport_nets

do_xform_fix_multiport_nets [-dont_modify_children] [-fix_clock_net][-fix_constant_ports] [-no_design_rule]

The do_xform_fix_multiport_nets command splits any net connected to more thanone output port into different nets, each driven by a buffer, such that each net is connected toonly one port. It transforms nets connected to multiple ports. This transformation may benecessary to make it easier for some of the placement and floorplanning tools to treat thenetlist properly. This transformation also inserts a buffer on every pass-through net thatdirectly connects input port to an output port.

Arguments


Related Information


set_global fix_multiport_nets



do_xform_footprint

do_xform_footprint [-quick] [-dont_modify_children] [-no_design_rule][-fix_clock_net] [-dont_reclaim_area | -reclaim_maximum_area] [-max_areafloat ] [-incremental] [-critical_ratio float ] [-critical_offset float ]

The do_xform_footprint command applies transformations to the design after place androute. This command substitutes the cells with higher (lower) drive capability for the cells withlower (higher) drive, if both cells have the same footprints (in addition to the samefunctionality). This assures that there are no changes in the placement or routing of the cells.This is also referred to as in-place swapping of cells.

This command is useful when operating on a netlist that has been already placed and nosignificant changes can be made to the netlist.


Arguments


Related Information




do_xform_ipo

do_xform_ipo [-change_limit integer ] [-change_file filename] [-max_area float ][-checkpoint] [-dont_legalize] [-dont_swap_pins] [-dont_resize][-dont_buffer] [-dont_climb_hill] [-dont_downsize]

This command This command preforms ipo optimizations. Only optimizations which areconsidered safe for ipo are performed (pinswapping, resizing and buffering). If the design isplaced, instances will not be moved.

Arguments

See “Arguments for Transform (do_xform_*) Commands” on page 78 for descriptions ofoptional arguments that are shared with other transforms.

-dont_downsizeAllows control of the optimization process so that during resizing,only upsizing moves can be allowed. No downsizing moves areallowed.

-dont_legalizePrevents use of do_legalize as an option during anoptimization transformation.

-dont_swap_pinsPrevents use of do_pin_swap as an option during anoptimization transformation.

-dont_resizePrevents use of use do_resize as an option during anoptimization transformation.

-dont_bufferPrevents use of do_buffer as an option during an optimizationtransformation.

-dont_climb_hillPrevents hill climbing as a method to improve timing.





do_xform_map

do_xform_map [-no_partition] [-effort] [-force] [-hierarchical] [-timing][-critical_ratio float ] [-critical_offset float ] [-distributed][-fanin_depth integer ] [-fanout_depth integer ]

The do_xform_map command maps the generic netlist to the target technology library. It isused for timing driven mapping. Timing is implied when using any of the last three optionsspecified. If the -timing option is used in the absence of any of the other options thentiming-driven mapping is only performed on the critical region as specified by the argumentsof the -critical_ratio , -critical_offset , -fanin_depth , and -fanout_depthoptions whose defaults are all 0.

This command maps a generic cell netlist (ATL) to a technology specific cell netlist.

Arguments


Examples

do_optimize

do_xform_unmap



do_xform_optimize_generic

do_xform_optimize_generic [-checkpoint] [-clock_gate][-flatten { on | auto | off }][-minimize { single_output | multiple_output }] [-phase_assignment][-force] [-no_partition] [-priority { area | time }] [-distributed][-dont_uniquify] [-dont_propagate_constants] [-dont_structure][-dont_remove_redundancy]

The do_xform_optimize_generic command executes the following three technologyindependent transformations: do_xform_propagate_constant,do_xform_structure , and do_xform_remove_redundancy . This command maps ageneric cell netlist (ATL) to a generic cell netlist. For more information, refer to the chaptersOptimizing Before Place and Route and Optimizing with Logic Transforms in theAmbit BuildGates Synthesis User Guide.

Arguments


Related Information

do_optimize

set_current_module

Examples

The following sequence of commands is the same as do_optimize -effort high :

do_xform_optimize_generic

do_xform_map -hier

do_xform_optimize_slack -effort high



do_xform_optimize_slack

do_xform_optimize_slack [-effort { low | medium | high }] [-no_design_rule][-checkpoint] [-max_area float] [-critical_ratio float] [-critical_offsetfloat] [-dont_reclaim_area | -reclaim_maximum_area] [-incremental] [-pks][-distributed] [-power] -restructure_aware[-stop_before_placement] [-time_budget] [-remap_for_timing]

The do_xform_optimize_slack command performs an iteration ofdo_xform_timing_correction and do_xform_restructure transformations. It offersthe same functionality as the do_optimize command except that it expects a mappednetlist as input. It is used instead of the do_optimize command if a netlist is being optimizedtwo or more times.

Note that because the change in the default, larger areas may be seen for the designs. Usethe -reclaim_maximum_area option to revert to the former default.

The transformations are applied to the cells on the critical path in the entire design specifiedby the command set_top_timing_module .

Arguments


Related Information

Refer to the transform commands (do_xform_* ).

do_optimize

set_current_module


Examples

The following commands optimize a netlist, flatten the hierarchy, and then optimizes it again.

read_verilog gate.v

do_build_generic

do_xform_optimize_slack



do_xform_pre_placement_optimize_slack

do_xform_pre_placement_optimize_slack [-effort { low | medium | high }][-design_rule_have_been_fixed] [-no_design_rule] [-checkpoint][-max_area float ] [-critical_ratio float ] [-critical_offset float ][-distributed] [-dont_reclaim_area | -reclaim_maximum_area] [-incremental][-power] [-time_budget] [-remap_for_timing] [-dont_legalize]

The do_xform_pre_placement_optimize_slack command is very similar to thestop_before_placement command. The design is placed after pre-placementoptimization.

Arguments




do_xform_propagate_constants

do_xform_propagate_constants [-dont_uniquify]

The do_xform_propagate_constants command is used to propagate constantsthroughout the design crossing hierarchical boundaries. The constants being propagated arethe logic levels (0 or 1). This command also propagates unconnected property for the netsconnected to those input ports that are not connected (driven) to any driver. The side effectis that it uniquifies all instances unless the -dont_uniquify option is given. By default, thiscommand removes only constant latches. To remove constant flip-flops also, set the globaloption preserve_constant_flops to false .

This command maps a generic cell netlist (ATL) to a generic cell netlist, and a technologyspecific cell netlist to a technology specific cell netlist.

Arguments


Related Information




do_xform_reclaim_area

do_xform_reclaim_area [-footprint] [-resize] [-buffer] [-clone][-dont_modify_children] [-no_design_rule] [-fix_clock_net] [-critical_ratiofloat ] [-critical_offset float ] [-reclaim_maximum_area]

The do_xform_reclaim_area command applies only those transformations that reducearea, without worsening the worst negative slack. These include replacing cells with smallerarea cells that have the same functionality, and removing unnecessary buffers or clones.

If none of the three options, resize , buffer , or clone , are used, then by default all threetransformations are applied to get the best possible results. In effect, it is the same as usingall the three options.


Arguments


Related Information




do_xform_remove_redundancy

do_xform_remove_redundancy [-hierarchical] [-no_partition]

The do_xform_remove_redundancy command is used to remove redundancies from thenetlist. This command maps a generic cell netlist (ATL) to a generic cell netlist.

Arguments


Related Information

do_optimize



do_xform_resize

do_xform_resize [-footprint] [-quick] [-dont_modify_children] [-no_design_rule][-fix_clock_net] [-dont_reclaim_area | -reclaim_maximum_area][-critical_ratio float ] [-critical_offset float ] [-incremental] [-max_areafloat ] -upsize_only

The do_xform_resize command resizes the cells in the netlist. This command indicatesthat if the library has choice of cells with the same functionality but different drives, a cell canbe replaced by an equivalent cell with different drive if the new cell contributes toward meetingthe goal of the transformation.


Arguments


-upsize_onlyAllows control of the optimization process so that during resizing,only upsizing moves can be allowed. No downsizing moves areallowed.

Related Information




do_xform_restructure

do_xform_restructure [-critical_ratio float ] [critical_offset float ][-effort { low | medium | high }] [-max_area float ]

The do_xform_restructure command is used to perform restructuring and remapping ofthe critical path in order to meet the timing constraints.


Arguments


Related Information

do_optimize



do_xform_structure

do_xform_structure [-force] [-hierarchical] [-effort { low | medium | high }][-flatten { on | auto | off }] [-priority { area | time }] [-no_partition]

The do_xform_structure command applies Boolean and algebraic algorithms andtransformations to achieve logic optimization and logic structuring. These transformations aretechnology independent. This command is typically used prior to any technology dependentmapping or optimizations.

This command maps a generic cell netlist (ATL) to a technology generic cell netlist.

Arguments


Related Information

do_optimize




do_xform_timing_correction [-footprint] [-resize] [-upsize_only] [-buffer][-clone] [-dont_modify_children] [-design_rule_only | {-no_design_rule |-dont_fix_design_rule}] [-min_hold | -fix_hold] [-no_pinswap | -pinswap_only][-fix_clock_net] [-max_area float ] [-quick] [-preserve_slack] [-incremental][-critical_ratio float ] [-critical_offset float ] [-dont_reclaim_area |-minimize_area] [-change_limit integer ] [-change_file filename ]

The do_xform_timing_correction command provides various transformationmechanisms to achieve the desired timing for the critical path. It applies timingtransformations to fine tune the design after synthesis. The transformations are applied to thecells on the critical path in the entire design specified by the set_top_timing_modulecommand.

For best results and additional functionality, we recommend that you use the followingcommands instead of do_xform_timing_correction.

do_xform_reclaim_areado_xform_optimize_slackdo_xform_fix_holddo_xform_fix_design_rule_violationdo_xform_footprintdo_xform_ipo

Arguments

See “Arguments for Transform (do_xform_*) Commands” on page 78 for descriptions ofoptional arguments shared by transforms.

Related Information

set_current_module

do_optimize




do_xform_unmap

do_xform_unmap [-hierarchical] [-force] [ list_of_instance_ids |list_of_instance_names ]

This command unmaps the netlist from the technology library. The result of the operation isthat the netlist is back in the generic form and can be mapped again.

This command reverts a technology specific cell netlist to a generic cell netlist (ATL).

Arguments


Related Information

do_optimize

Examples

do_xform_unmap



dump_adb

dump_adb ac_shell_process_id

When the dump_adb command is invoked with the process ID of an ac_shell process, thenthe corresponding ac_shell dumps the .adb (Ambit Synthesis Database) file at the nextmost suitable time allowing the run to continue. You no longer need to use Control-c to stopthe synthesis run to get a snapshot of the state of the design. Using this command you canget a copy of the .adb file at any point during the optimization.

Once the command is invoked the following message appears in the console window and inthe log file:

"Request received to dump ADB at date & time . Will save database atnext suitable time in file current_module .adb.sig. num"

The num variable increments after every successful .adb file dump, starting from 1. Thisenables you to save different snapshots of the design and prevents the snapshots from beingoverwritten.

If the dump_adb command is invoked again before the database is written out, then the tooldisplays the following message in the console and in the log file:

"Received user request to dump ADB. Waiting for suitable time to dumpADB file"

When ac_shell dumps the .adb file, the following message is displayed to indicate that youcan now use the saved adb file to perform other operations:

Database saved in file ’ top_module .adb.sig. num according to userrequest"

The command provides a snapshot of the database during a run.

Arguments

ac_shell_processs_id

Examplesdump_adb ac_shell_processs_id



eval_bottom_up

eval_bottom_up [-skip] [-incr] [-slack float ] [-derive_context] [min_sizeleaf_cell_size ] [-level level_number ]

The eval_bottom_up command first traverses the design tree in a bottom-up fashion andpre-processes all modules to determine which ones meet the conditions specified by theoptions -min_size , -slack and -level . Then it computes the time budgeting for thesemodules. The time budgeting will be done at once for all the pre-selected modules in theabsence of the -incr option. Otherwise it is performed later on. It performs anotherbottom-up tree traversing and visits each pre-selected module. If the -incr option is selectedthen it computes the time budget for each module as it visits them (incrementally). It sets thepointers current_module and top_timing_module , to point to each module visited andthen executes the series of Tcl commands contained in the command’s argument. It placesa set_dont_modify attribute to each instance’s module after it is visited, and before it visitsthe next module. Once it reaches the top module, it clears all the set_dont_modifyattributes for all modules.It is very important to note that the eval_bottom_up command works on both non-uniquifiedand uniquified netlists.

Arguments

-derive_contextThis directs the eval_bottom_up command to perform ado_derive_context operation for all instances instead of ado_time_budget operation.

-incrWithout this option, the eval_bottom_up command performsa time budgeting for all the instances in the design at thebeginning of the operation. With this option, the time budgetingis done incrementally as each instance is being visited.

-level level_numberThis directs the eval_bottom_up command to start to executeits arguments from instances that are at a distance oflevel_number from the top cell (these are the bottominstances) to the top.

-min_size leaf_cell_sizeThis directs the eval_bottom_up command to execute itsarguments on instances that have a greater or equal amount ofcell-instances than the leaf_cell_size number.



-skipIt prevents eval_bottom_up from performing a time budgetingoperation for all the instances in the design.

-slack floatIt performs a worst case setup slack timing analysis eachmodule. It compares the result against the argument given withthe option. If the value of the instance’s worst case setup slack isless than the argument of the -slack option, then it executes theargument of the eval_bottom_up command.

Related Information

set_dont_modify

Examples

■ eval_bottom_up -skip {do_xform_buffer_tree}

Performs a bottom up without doing any time budgeting. It executes ado_xform_buffer_tree at each visited instance.

■ eval_bottom_up {write_assertions [get_name [ get_current_module]]_constraints.tcl}

It will perform the time budget for all modules in the design and will write out constraintsfor each module to files with the naming format: <module_name>_constraints.tcl wherethe string <module_name> corresponds to the actual name of each module.

■ eval_bottom_up -incr -min_size 3000 -slack 0 {do_xform_buffer_tree;do_xform_timing_correction -quick -no_design_rule}

It starts its bottom up from those instances that have more or equal to 3000cell_instances . It performs incremental time budgeting. It will only execute the list ofarguments on those instances whose worst case setup slack is less than 0 (instancesthat have negative slack).

■ eval_bottom_up -incr -level 3 -slack -1 { source fast_procs.tcl }

It starts its bottom up from those instances located 3 levels below the top module. Itperforms incremental time budgeting. It will only execute the commands contained in theTcl file "fast_procs.tcl" on those instances whose slack is less than -1 ns.

■ eval_bottom_up -skip { puts [get_name [get_current_module]] }

It performs a bottom up function from the bottom leaf instances and returns the name ofthe module associated with each instance.



find

find [-blackboxes] [-bus] [-cellrefs] [-clocks] [-dont_modify] [-exact] [-excludenamelist ] [-full_path_name] [-glob | -regexp] [-hierarchical] [-inputs][-instances] [-modules] [-nets] [-nocase] [-noclocks] [-of_cell_typecell_name ] [-of_pin_type { data | clock | output | reset | set }] [-outputs][-pins] [-pla] [-ports] [-registers] [-techlib] [-top] [-scalar] name_list

The find command finds various design objects and prepares the list for other ac_shellcommands. The design objects are found in the design database using glob style patternmatching, unless -regexp option is used. Multiple wildcard matching in a name is permitted.

Typically, the output of find command (list of objects found by this command) is an argumentof another command that accepts a list of objects and performs some task. For example, allinput ports of a module can be set to same arrival time as follows:

set_data_arrival_time 0.2 [find -ports -input *] -clock master_ck

The search for finding objects is carried out in the current module. If the object name hashierarchy specified in it (for example cnt99/* ), then the search is carried out at theappropriate hierarchy level.

Arguments

-blackboxesFilter for -cellref and -instances . Returns only objectsthat are blackboxes.

-busFilter for nets, ports, and instance pins. Returns only buscomponents.

-cellrefsSearches for cell references.

-clocksFilter for -pins and -ports . Returns only clock pins or ports.

-dont_modifyFilter for all objects types. Returns objects with dont_modifyflag set. Refer to set_dont_modify .

-exactSearches only for exact name matches.



-exclude namelistExcludes from the search the names specified in namelist .See the Examples below for clarification.

-full_path_nameReturns the complete path name of the object, not theobject_id . It returns the complete path of the nets, instances,and the instance pins from the current module. It returns theobject name for all other object types.

-hierarchicalSearches the complete database hierarchically from currentmodule.

-inputsFilters for -pin and -port . Returns only input pins or ports.

-instancesSearches only for instances.

-modulesSearches for modules.

name_listSpecifies the names of the objects to search. Pattern matchingand regular expressions may be used to find many objects.

-netsSearches only for net object types.

-nocaseUse this switch in conjunction with the -module or the-techlibs switches to specify. It determines whether a case-insensitive search is performed. It is a useful in searching for theVHDL modules.

-noclocksFilter for -pins and -ports . Returns only nonclock pins orports.

-of_cell_type cell_nameFilter for -instances . Returns only the instances ofcell_name , which can be * .



-of_pin_type data|clock|output|reset|setThis is a filter for -pin . It returns the respective pins for thesequential elements. This option allows you to apply pathexceptions (false paths, multi-cycle paths) across reusedmodules.

-outputsFilter for -pins and -ports . Returns only output pins or ports.

-pinsSearches only for instance pins.

-plaFilter for -cellref and -instances . Returns objects whichare PLA.

-portsSearches only for ports.

-regexpPerforms pattern matching using regular expression rulesinstead of glob style pattern matching by default.

-registersFilter for -instances . Returns only sequential instances.

-scalarFilter for nets, ports, and instance pins. Returns only the scalarcomponents and filters out the bus components. Useful in thecases where there is a name collision between a scalar and buscomponent.

-techlibSearches for technology libraries.

-topFilter for -module . Returns only the top level module.

Object Types and Filters

Valid object types and filters associated with those objects are shown in Object Types andFilters table on page 118. Only the applicable filters will be applied to the objects. If no filtersare listed, each object_id that matches a name in the name_list is returned.



Glob Style Pattern Matching

The following symbols are used for wildcard matching:

*Matches 0 or more occurrence of any character.

?Matches any single character.

[a,b,c]Matches a or b or c .

Regular Expression Pattern Matching

Refer to your Tcl documentation for more information about regular expressions and patternmatching.

The following symbols are used to match regular expressions:

.Any character.

*Zero or more occurrence of preceding character or regularexpression.

+One or more occurrence of preceding character or regularexpression.

^Matches at the start of a string.

$Matches at the end of a string.

\xMatches character x .

[chars]Matches any character from the set.



regexp1 | regexp2Matches anything that matches regexp1 or regexp2 .

Related Information

set_current_module

Examples

➤ Find all input ports

find -ports -input *

or

find -port -input -regexp

➤ Find all inout ports

find -ports -input -output *

➤ Find the complete path names of the nets beginning with the letter A, except the onesbeginning with AB or AC.

find -nets -exclude {AB AC} -full A*

➤ Find all technology libraries that have LCA prefix

find -techlibs LCA*

➤ Find R3 register in all instances

find -instances -registers R3

➤ Find all ports and all modules

find -port -mod *

➤ Find all input ports and all modules

Note: The filter input applies only to ports and not modules

find -port -mod -input *

➤ Find top level module

find -module -top *



➤ Find instances that match add1 or add2

find -instance {add[1.2])

➤ Find all input ports with name beginning with scan N and ending in _d

find -input -port -regexp {^scan[0-9]+.*_d$}

Table 1-1 Object Types and Filters

Object Type Filter

instances blackbox

dont_modify

of_cell_type

pla

registers

ports bus

clocks

input

no_clocks

output

scalar

nets bus

dont_modify

scalar

cells dont_modify

modules dont_modify

nocase

top



pins bus

clocks

input

noclocks

of_pin_type

output

scalar

cellrefs blackboxes

pla

Object Type Filter



get_area

get_area [-cell {combinational | sequential | both} | -net] [-module module ]

The get_area command queries the area of the given mapped module or the currentmodule, and downwards in the hierarchy. It gets the area for a design module.

Unmapped (generic) logic does not count towards the area of a design. There are options forcell area and net area.

Arguments

-cellReturn the combinational or sequential cell area only, or both.The default is both.

-netReturn the net area as determined by the appropriate wireloadmodel.

-module moduleReturn the total area of a module if neither -cell nor -net isspecified. The default is the current_module .

Related Information

get_module_worst_slack

report_area

set_current_module

Examples

■ Set the current module to be topset_current_module top

■ Returns the total area of top and all its childrenget_area

■ Only return the sequential cell area in top and its childrenget_area -cell sequential



■ Only return the net area in top and its childrenget_area -net

■ Return the total area of module buffer2 and its childrenget_area -module buffer2



get_attribute

get_attribute object_id attribute_name

The get_attribute command returns the value set for the specified attribute on thespecified object. You can query tool- and user-defined attributes.

Arguments

object_idThe object identifier of the module, instance, cellref, net, port, orpin you want to query.

attribute_nameThe name of the attribute to query. Refer to the set_attributecommand’s Attributes on page 186 for a list of tool-definedattributes.

Related Information

set_attribute

set_global

delete_attribute

get_info

Examples

Find the value of the flatten attribute for the module A.

get_attribute [find -module A] flatten

The command below queries the attribute my_attribute on the net object my_net for thevalue.

get_attribute [find -net my_net] my_attribute



get_buswidth

get_buswidth object_id

The get_buswidth command returns the width of the specified bus object.

Arguments

object_idThe object identifier associated with a bus.

Examplesget_buswidth 73540

=>4



get_cell_area

get_cell_area cell_id

The get_cell_area command returns the area of the specified cell.

Arguments

cell_idThe object identifier associated with a cell.

Examplesget_cell_area 60979

16.000000



get_current_instance


This command returns the object ID of the instance which has been previously designated asthe current instance by the command set_current_instance .

Related Information

set_current_instance

Examplesget_current_instance



get_current_module

get_current_module

This command returns the object ID of the module which has been designated as the currentmodule previously by the command set_current_module .

Related Information

set_current_module

Examplesget_current_module



get_equivalent_cells

get_equivalent_cells [-exclude_self] cell_id

The get_equivalent_cells command returns a list of names of library cells that have thesame functionality and pin names in non-decreasing order of cell area. Any one of thereturned cell names can be used in a do_rebind call on an instance bound to cellid .

Arguments

-exclude_selfExcludes the name of cellid from the list.

Related Information

do_rebind



get_global

get_global [-default] global_variable_name

The get_global command returns current value for the specified global variable. The valueof any global variable can be obtained using get_global command. The set_globalcommand has a one-to-one correspondence with the get_global and reset_globalcommands. Every variable defined in set_global also applies to get_global andreset_global .

Arguments

-default global_variable_nameReturns the default value for the specified global variable.

Related Information

set_global



get_hdl_file

get_hdl_file module_name

The get_hdl_file command returns the file name corresponding to the module. Thiscommand can be invoked right after reading the HDL files into BuildGates Synthesis, withouthaving to first generate a generic netlist using do_build_generic .

Arguments

module_nameThe name of the module.

Examples

Consider a Verilog module TOPV defined in a file design.v and a VHDL module TOPVHdefined in a file design.vhdl . After the HDL files have been analyzed into BuildGatesSynthesis, get_hdl_file can be used to determine what file the modules belong to.

read_verilog design.v

get_hdl_file TOPV

design.v

read_vhdl design.vhdl

get_hdl_file TOPVH

design.vhdl



get_hdl_hierarchy

get_hdl_hierarchy [ module_name ]

The get_hdl_hierarchy displays the design hierarchy where, for each design, it lists thenames of the designs that are instantiated within, and whether the instantiations areparameterized (using parameters in Verilog or generics in VHDL) or not.

This command can be used to investigate the design hierarchy right after reading the HDLfiles into BuildGates Synthesis, without having to first generate a generic netlist usingdo_build_generic . This is very useful when design data is often organized into tens oreven hundreds of HDL files.

If get_hdl_hierarchy is invoked without any arguments, it will return a TCL list containinginformation for each module that had been read using the read_vhdl or read_verilogcommand.

Arguments

module_nameThe name of the hierarchical module.

Examples

Consider the following VHDL design that consists of three modules: TOP, BOT, and BOTG.

entity BOTG is

generic (WIDTH : natural := 1);

port (O: out bit_vector(WIDTH-1 downto 0));

end;

architecture A of BOTG is

begin

O <= (others => ’1’);

end;

entity BOT is

port (O: out integer);

end;

architecture A of BOT is

begin

O <= 25;

end;



entity TOP is

port (O8: out bit_vector(7 downto 0);

O1: out integer);

end;

architecture A of TOP is

begin

I1 : entity work.BOT port map (O1);

I8 : entity work.BOTG generic map (8) port map (O8);

end;

Assume that the design above is in a VHDL file called design.vhd and has been read inusing the read_vhdl command:

read_vhdl design.vhd

For the VHDL example above, the get_hdl_hierarchy command lists the three modulesin the HDL design pool: TOP, BOT and BOTG.

It also indicates that while BOT and BOTG do not instantiate any other designs, TOPinstantiates both BOT (n represents a non parameterized instantiation) and BOTG (’p’indicates a parameterized instantiation, since design BOTG contains generics).

get_hdl_hierarchy

{TOP {{BOT n} {BOTG p}}} {BOT {}} {BOTG {}}

One can obtain the hierarchy for a specific design, for example, TOP

get_hdl_hierarchy TOP

{TOP {{BOT n} {BOTG p}}}



get_hdl_top_level

get_hdl_top_level

The get_hdl_top_level displays a list containing the names of all top level designs, thatis designs that are not instantiated by any other design.

This command can be invoked right after reading the HDL files into BuildGates Synthesis,without having to first generate a generic netlist using do_build_generic .

Examples

Consider the following VHDL design in file design.vhdl :

entity BOT1 is ....

architecture A of BOT1 is ....

entity BOT2 is ....

architecture A of BOT2 is ....

entity MYDES is ....

architecture A of MYDES is

begin

I1 : entity work.BOT1 port map ...

I8 : entity work.BOT2 port map ...

end;

Then the following set of commands will display the top level module in the design:


get_hdl_top_level

MYDES



get_hdl_type

get_hdl_type module_name

Given a specific design name, the command get_hdl_type returns the language (VHDL orVerilog) in which that specific design was represented.

This command can be invoked right after reading the HDL files into BuildGates Synthesis,without having to first generate a generic netlist using do_build_generic .

Arguments

module_name

The name of the hierarchical module.

Examples

Consider a Verilog module TOPV defined in file design.v and a VHDL module TOPVHdefined in a file design.vhdl . Once the HDL files have been analyzed into BuildGatesSynthesis, get_hdl_type can be used to determine what language the various moduleswere represented in:



get_hdl_hierarchy

{TOPV {}} {TOPVH {}}

get_hdl_type TOPVH

VHDL

get_hdl_type TOPV

Verilog



get_info

get_info object_id [ field ]

The get_info command returns the Tcl data structure associated with the object_id ,or the specific field of that object_id . By default it returns all available fields. It can beused to show attributes.

Arguments

object_idOnly one object_id is accepted.

fieldSpecifies the field associated with the returned object ID.

Related Information

find

get_attribute

set_attribute

Examples

➤ Get the data structure of FD1

find -cellref FD1

35331

get_info 35331

{objecttype cellref} {name FD1} {dont_utilize false} {dont_modify false}{module 17} {pins {35350 35366 35382 35398}}

➤ Pass the value returned by find to get_info

get_info [find -module state1]

{objecttype module} {{name state1} {dont_modify false} views {72690}}

➤ Get the value of the dont_modify attribute of state1

get_info [find -module state1] dont_modify

false

➤ Get the object_id of xf_ncnt[1]

find -net {xf_ncnt[1]}



99557

➤ Get the data structure of xf_ncnt[1]

get_info [find -net {xf_ncnt[1]}]

{objecttype net} {name {xf_ncnt[1]}} {dont_modify false} {bus 99924} {type85799} {module 84385} {connections {102790 91638}}

➤ Get the values of the connections and bus fields.

get_info [find -net {xf_ncnt[1]}] connections

102790 91638

get_info [find -net {xf_ncnt[1]}] bus

99924

➤ Get the data structure of the bus field of xf_ncnt[1] .

get_info [get_info [find -net {xf_ncnt[1]}] bus]

{objecttype bus} {name xf_ncnt} {module 84385} {components {92789 92805 9277392757 99237 99269 99365 99397 99461 99493 99557 99893}}

➤ Get a list of views of module count5 .

set view_list [get_info [find -module count5] views]

➤ Get a list of all port identifiers of module count5 .

foreach view $view_list {

set port_list [get_info $view ports]

}



get_message_count

get_message_count [message_ID] { error | warning | info | info_msg }

The get_message_count command returns the current message count of either thespecified message_ID or the specified message type.

Arguments

message_IDThe ID of the message whose count is returned.

errorGet the count for message type error.

warningGet the count for message type warning.

infoGet the count for message type info.

info_msgGet the count for message type info_msg.

Related Information

set_message_count

set_message_verbosity



get_message_verbosity

get_message_verbosity message_ID

The command get_message_verbosity returns the current message verbosity.

Arguments

message_IDThe ID of the message whose verbosity level will be retrieved.

Related Information

set_global message_verbosity_level



get_names

get_names object_id

Get the names of the objects whose IDs are specified. This command is used for reportingthe names of the objects in the design.

Arguments

object_idThe object_id is the ID of the object whose name is reportedby this command. The object_id is typically obtained usingfind command. If the object_id represents a single object, acorresponding name is returned. If the object_id representsa list of objects, a list of names in the order of objects in theobject_id list is returned.

Related Information

find

Examples

➤ Return the name of all input ports of the current module.

get_names [find -input -ports *]



get_net

get_net [-full_path_name] [-min_fanout integer ] [-max_fanout integer ][ list_of_net_path_or_id ] [ netname ]

The get_net returns net information at the current level of hierarchy. It is useful when findingnets with a pattern matching (wildcard, for example) and then filtering out certain nets basedon other options of the command (that is -min_fanout or -max_fanout ).

By default get_net returns the net IDs at the current level of hierarchy and returns full pathname of the net if -full_path_name is specified.

Arguments

-full_path_nameReturns full path name of net, instead of net ID

list_of_net_path_or_idNet path or ID. Can be a pattern or regular expression. If theargument is not given, it returns all nets under the hierarchy ofcurrent module.

-min_fanout integerReturns net whose number of fanouts is not less than theminimum number specified in integer .

-max_fanout integerReturns net whose number of fanouts is not greater than themaximum number specified in integer .

netnameReturns the ID of the specified net name.

Related Information

report_net

Examples

➤ To get the net ID of i_284 .

get_net i_28494341



➤ To get all nets whose names begin with r under hierarchy of current module and have atleast 300 fanouts. This command can be used to check if there are any high fanout nets.

get_net -min_fanout 300 r*

r_245 r_250

➤ To get full path name of all nets with fanouts less than/equal to 10:

get_net -full_path_name -max_fanout 10

I311/I210/n_230

➤ To get full path name of all nets with fanouts greater than 100:

get_net -full_path_name -min_fanout 100

I311/I210/n_310 I311/I210/n_312



get_parent_instances

get_parent_instances

The get_parent_instances command returns the parent instances of the currentmodule.

Nothing is returned if the current module is the top level module.

Related Information

all_parents

Examplesget_parent_instances

61030 61046 61062 61078



get_tempfilename

get_tempfilename [directory_name] [prefix]

This command returns the temporary file name from the system’s default temporary directory.You can specify the directory name and prefix, if desired.

Arguments

directory_nameThe name of the directory in which to create for the temporaryfile. The default directory name is /var/tmp/ .

prefixPrefix added to the file name.

Examplesget_tempfilename

/var/tmp/CAAa006T3

get_tempfilename /tmp

/tmp/DAAa006T3

get_tempfilename /tmp Run1_

/tmp/Run1_FAAa006T3



help

help [ command | keyword | message_id ]

The help command provides online help for all ac_shell commands. If no arguments aregiven to the help command, the usage syntax is displayed. This is also true for all ac_shellcommands: When a command expects some arguments that are not provided, or incorrectarguments are provided, the usage syntax is displayed.

Arguments

commandSpecified command’s syntax is displayed.

keywordA list of all commands related to the specified keyword aredisplayed. The keyword can be any word, including partial matchto one or more commands.

message_idExplanation of the message is displayed. Most of themessages—errors, warnings, or informative messages, aredisplayed in terse form, with a message-id associated with it.Requesting help with this message-id provides detailedinformation, including possible problems and suggestions forhow to remove the problem.

Exampleshelp

help TCLCMD-187

help global

help do_xform_fix_multiport_net



highlight

highlight list_of_object_ids [-center] [-verbose]

The highlight command highlights schematic instances, nets, and ports, given a list ofobject IDs.

Arguments

-centerCenters schematic on the last object inlist_of_object_ids .

-verbosePrints the name and object ID of each object that is beinghighlighted



issue_message

issue_message [-type {info | error | warning}] message

The issue_message command issues user messages. These messages are logged in a logfile. There may also be no type as an option for this command and the message ID for issuingsuch an information message is user-300 .

Arguments

-infoThe message ID for this message type is user-400 .

-warningThe message ID for this message type is user-200 .

-errorThe message ID for this message type is user-100 .

Examplesissue_message -type error "message"

=> ERROR: message<user-100>

issue_message "message"

=> message <user-300>

issue_message -type info "message"

=>INFO: message <user-400>

issue_message -type warning "message"

=>WARNING: message <user-200>



limit

limit { cpu_seconds | -cycles number } tcl_command

The limit command executes the specified Tcl command and issues a user interrupt aftercpu_seconds have elapsed if the command did not finish by that time.

This command can be used to limit the time spent in a given optimization command. Actualtermination of the tcl_command is at the discretion of the application and is analogous toissuing a user interrupt (^C).

A 0 is returned if the Tcl command completes without exceeding the limit. If the limit wasexceeded, limit will return a positive “magic” number representing the number of cyclesexecuted. This number can be used to reproduce the run using the -cycles numberoption.

Note: CPU times are an approximation made by the operating system. So any script basedon limiting the CPU time can result in non-reproducible results. To reproduce aCPU-time-limited run, use the option -cycles magic_number , with the magic numberreturned by the run you wish to reproduce.

Specifying -cycles 0 is the same as specifying no limit.

Arguments

cpu_secondsAn approximate number of CPU seconds.

-cycles numberA number of CPU cycles.

tcl_commandsA Tcl command.

Examples

The following script automatically replays a previous CPU-time-limited run:

if { $replay } { source $replay_file }

else { set fp [open $replay_file w] }

...

set cmd1 "do_optimize -effort high"

if { $replay } {

limit -cycles $nr1 $cmd1



} else {

set cycles [limit 100 $cmd1]

puts $fp "set nr1 $cycles"

}

...

if { $replay == 0 } { close $fp }



quit

quit

Exits ac_shell process.



read_adb

read_adb [-module module_name ] [-no_cap] [-echo_assertions] [-no_assertions][-no_rc] [-no_res] [-no_sdf] [-no_spf] [-overwrite] filename

The read_adb command reads a previously written Ambit Synthesis database file (ADB)and rebuilds the database for further synthesis and analysis of the netlist. The ADB file is abinary file.

The synthesis data stored by ac_shell in a database can be written out in the ADB formatat any stage during the synthesis process using the write_adb command.

If the module (design) in the ADB file contains references to technology cells, the technologylibrary must be loaded prior to loading the design from the ADB file.

By default, if a database already existed, loading the new database renames the existingmodules.

Arguments

-echo_assertionsEchoes the timing assertions in read_adb , regardless of theset_global echo_commands .

filenameThe .adb file to be read in to ac_shell .

-module module_nameName of the module to be loaded from the entire ADB file. Anadb file can contain several modules. Modules from the file canbe selectively loaded so that ac_shell database does notoccupy unnecessary memory space.

-no_assertionsThis flag will cause the assertions in the ADB being read in to beignored. The default behavior is to write assertions into all ADBsand to apply all the assertions being read in.

-no_capIf the ADB contains any wire capacitances, these values are notrestored.

-no_rcIf the ADB contains any wire resistances or capacitances, these



values are not restored. By default they are restored if present inthe database.

-no_resIf the ADB contains any wire resistances, these values are notrestored.

-no_spfIf the ADB contains any Standard Parasitic Format (SPF)parasitics, these values are not restored. By default a reducedset of values are restored, if present in the database.

-no_sdfIf the ADB contains any delay arc annotations from an SDF file,these values are not restored. By default they are restored ifpresent in the database.

-overwriteOverwrites the existing module if the module is present in thedatabase, otherwise the existing module is automaticallyrenamed maintaining the module’s link.

Related Information

read_alf

read_verilog

read_vhdl

write_adb

Examplesread_adb design_top.adb



read_dc_script

read_dc_script [-ambit ambit_output_file] [-time_scale_factor scaling_factor][-capacitance_scale_factor scaling_factor ][-resistance_scale_factor scaling_factor ][-length_scale_factor scaling_factor ] [-no_apply] [-no_mcp_hold_errors][-voltage_scale_factor scaling_factor ] [-write_only] [-apply_only] [-tcl][-verbose] [-help] write_script_file

The read_dc_script command automatically translates Synopsys Synthesis constraintsinto the Ambit Synthesis constraint format.

Arguments

-ambit ambit_output_fileSpecifies the name of the Ambit Synthesis constraints output file.The default is to print the Synopsys Synthesis constraints to thestandard output device.

-time_scale_factor scaling_factorSpecifies the scaling factor to be applied to all time values in theSynopsys Synthesis script during the translation. The default is1.0.

-capacitance_scale_factor scaling_factorSpecifies the scaling factor to be applied to all capacitancevalues in the Synopsys Synthesis script during the translation.The default is 1.0.

-resistance_scale_factor scaling_factorSpecifies the scaling factor to be applied to all resistance valuesin the Synopsys Synthesis script during the translation. Thedefault is 1.0.

-length_scale_factor scaling_factorSpecifies the scaling factor to be applied to all length values inthe Synopsys Synthesis script during the translation. The defaultis 1.0.

-no_applySpecifies that the translator will only translate the commandsand will not apply them to the current design.



-voltage_scale_factor scaling_factorSpecifies the scaling factor to be applied to all voltage values inthe Synopsys Synthesis script during the translation. The defaultis 1.0.

-write_onlySpecifies that the translator should only write the translatedcommands to the output file and not apply them to the currentdesign.

-apply_onlySpecifies that the translator should only apply the translatedcommands to the current design and not write them to the outputfile.

-tclSpecifies that the Synopsys Synthesis constraints file is in Tclformat (and not in the default dc_shell format).

-verboseSpecifies that the translator should write the line number and thecorresponding Synopsys Synthesis command in the AmbitSynthesis constraints output along with the translated command.

-helpPrints the read_dc_script usage message.

write_script_fileSpecifies the name of the Synopsys Synthesis constraints inputfile. This is a required argument and must be the last specifiedargument.



read_edif

read_edif file_name

The read_edif command reads an EDIF v2.0.0 file.

Arguments

file_nameThe name of the EDIF input file.

Related Information

write_edif

set_global edifin_*

Refer to the EDIF Interface chapter in the HDL Modeling for Ambit BuildGatesSynthesis.

Examplesread_edif my.edif



read_symbol

read_symbol filename

The read_symbol command sets the schematic symbol library search path to filename .If a current list of files is loaded (from a previous read_symbol or read_symbol_updatecommand) the list is set it to filename .

Arguments

filenameThe name of the file to add to the schematic symbol librarysearch list.

Related Information

read_symbol_update

Examples

See read_symbol_update .



read_symbol_update

read_symbol_update filename

The read_symbol_update command appends filename to the schematic symbol librarysearch list. It provides support for loading multiple symbol library files into the schematicviewer.

Arguments

filenameThe name of the file to add to the schematic symbol librarysearch list.

Related Information

read_symbol

Examples

➤ Load schematic symbol libraries; search order is the order in which the libraries are readin.

set SYM_lib_dir ${root_dir}/LIBRARY/SYMBOL

read_symbol $SYM_lib_dir/IBM_SA12E.sym

read_symbol_update $SYM_lib_dir/IBM_SA12E_BC.sym

read_symbol_update $SYM_lib_dir/IBM_SA12E_GA.sym

read_symbol_update $SYM_lib_dir/IBM_SA12E_GROW.sym

read_symbol_update $SYM_lib_dir/IBM_SA12E_IO.sym

read_symbol_update $SYM_lib_dir/IBM_SA12E_SC.sym



read_verilog

read_verilog [-aware_library aware_libname ] verilog_filename

The read_verilog command reads in Verilog design files to ac_shell . When the-aware_library option is used, the verilog modules are stored as components in thespecified AmbitWare library. For more details on AmbitWare libraries, refer to DatapathOption of Ambit BuildGates Synthesis and Cadence PKS.

This command calls the Verilog preprocessor (vpp) and should be followed by the commanddo_build_generic before any constraint or optimization commands are applied.

Arguments

-aware_library aware_libnameReads each component file, checks the syntax, and generatesthe corresponding binary dump file (*.bd ) in the specifiedAmbitWare library. Adds an entry into the existing index file orcreates a new index file in the aware library.

verilog_filenameVerilog design file or files to read into ac_shell . Multiple filenames are separated by blank spaces.

Attributes

buscomp_generator

instance_generator

net_generator

hdl_verilog_vpp_arg

Database Impact

The database contains parse tree of Verilog source when all files are read in successfully.

Related Information

do_build_generic



read_symbol

read_alf

read_library_update

set_aware_library


Examples

The command below loads the Verilog file design.v into the ac_shell .


The command below reads three Verilog designs into the AmbitWare library ZM122200.

read_verilog -aware_library ZM122200 zm_des1.v zm_des2.v zm_des3.v



read_vhdl

read_vhdl [-aware_library aware_libname | -library libname ] vhdl_filenames

The read_vhdl command reads in VHDL design files to ac_shell . When the-aware_library option is used, the VHDL modules are stored as components in thespecified AmbitWare library. For more details on AmbitWare libraries, refer to DatapathOption of Ambit BuildGates Synthesis and Cadence PKS.

This command analyzes the VHDL files, performs basic synthesis subset checking, anddumps the intermediate representation to the directory associated with the specified awareor VHDL library or by default into the VHDL library WORK, if no library is specified.

If the specified library has been explicitly created using the set_vhdl_library command,then the intermediate representation of the VHDL design units is written to the correspondingdirectory. Otherwise, a temporary directory will be created for storing all design units analyzedinto a specific library.

VHDL design units (that is, entities, architectures, packages) can be read in any order withthe following restrictions:

■ Packages must be read before any other units that refer to them.

■ Entities must be read before any of its architectures.

There is no restriction on the order in which entities are read for synthesis.

The following packages are pre-compiled and do not need to be analyzed:

std.standard

std.textio

ieee.std_logic_1164

ieee.numeric_bit

ieee.numeric_std

Arguments

-aware_library aware_libnameReads each component file, checks the syntax, and generatesthe corresponding binary dump file (*.bd ) in the specified awarelibrary. Adds an entry into the existing index file or creates a newindex file in the AmbitWare library.



-library libnameThe name of the VHDL library into which the VHDL files will beanalyzed. Multiple file names are separated by blank spaces.

vhdl_filenameVHDL design file or files to read in. If no library file is specified,the VHDL files will be analyzed into the VHDL library WORK bydefault. Multiple file names are separated by blank spaces.

Attributes

hdl_vhdl_case

hdl_vhdl_read_version

buscomp_generator

hdl_vhdl_preferred_architecture

hdl_vhdl_reuse_units

Related Information

report_vhdl_library

set_vhdl_library

set_aware_library


Examples

The following command analyzes file pack.vhd into a library MYLIB.

read_vhdl -library MYLIB pack.vhd

The following command analyzes file use.vhd into library WORK.

read_vhdl use.vhd



The command below reads three VHDL designs into the AmbitWare library ZM122200.

read_vhdl -aware_library ZM122200 zm_des1.vhd zm_des2.vhd zm_des3.vhd



record_macro

record_macro filename

This command starts the logging of interactive commands into the specified file name.Recording stops when you exit ac_shell . The file can be “sourced” to recreate the session.

Arguments

filenameThe name of the directory and file in which to record the loggedcommands.

Examplesrecord_macro /usr1/tmp/macro_file1



report_area

report_area [-summary] [-block] [-hierarchical] [-cells][{ > | >> } filename ]

The report_area command generates a report on the area of the netlist. The informationcontained in the report is dependent on the options used with the command.

Arguments

{ > | >> } filenameName of the file in which report will be saved. If filename isnot specified, the report is displayed on the standard output.Note that filename must be the last argument in the list.

-summaryArea report is presented in summary form. The summaryinformation contains name of the current module, wire loadmodel used, cell area, net area, and total area.

-hierarchicalArea report is presented for the entire hierarchy below thecurrent module. If this option is not used, the data is presentedonly for the current module.

-cellsArea report is presented on every cell (block) in the currentmodule. The cell report includes summary report for currentmodule, summary report of cumulative design hierarchy, nameand count of cells used, type of cells used, area for each cell,total cell area, net area and total design area. If no options arespecified, then a summary area report will be generated.

-blockProvides a block summary. See the table below.

Block report for module am Current Module Cumulative

Number of combination instances 3 812

Number of noncombinational instances 0 438

Number of hierarchal instances 2 10

Number of blackbox instances 0 1



Related Information

report_design_rule_violations

report_fsm

report_hierarchy

report_timing

set_current_module

Examples

➤ Generate a detailed hierarchical report on each cell and stores the report in filearea.rpt .

report_area -hierarchy -cells area.rpt

➤ Write the report timing data to file my_file.rpt

report_timing > my_file.rpt

➤ Write the area report data to file my_file.rpt , overwriting the timing data.

report_area > my_file.rpt

The my_file.rpt contains both timing and area information.

report_timing > my_file.rpt

report_area >> my_file.rpt

Total number of instances 5 1261

Area of combinational cells 19.00 4181.00

Area of non-combinational cells 0.00 9970.00

Total cell area 19.00 14151.00

Number of nets 471 1721

Area of nets 0.00 0.00

Total area 19.00 14151.00

Block report for module am Current Module Cumulative




report_aware_library [-library library_name ] [-summary filename ][-component pattern ]

The report_aware_library command generates library, summary, and components thatmeet the pattern reports.

Arguments

-component patternSelects a component report of the components specified bypattern .

-library library_nameSelects a report of the aware library library_name .

-summary filenameSelects a summary report, storing the summary in filename .

Related Information

set_aware_library



Examples

The following example generates a report on the library AWLOGIC.

report_aware_library -library AWLOGIC




report_design_rule_violations [-hierarchical] [-ignore_clknet][-current_module_only] [-verbose] [-ignore_dont_modify_nets] [{ > | >> }filename ]

The report_design_rule_violations command generates a report on all the designrule violations in the design. The information contained in the report depends on the optionsused.

Arguments

-current_module_onlyOnly the violations in the current module are reported.

-hierarchicalReports the violations for hierarchical ports.

-ignore_clknetThe clock net violations are not reported.

-ignore_dont_modify_netsDoes not report design rule violations for nets that are setdont_modify .

-verboseReports all design rules for every net and port in the designregardless of whether there were any violations or not.

{> | >>} filenameSpecifies the name of the report file. If filename is notspecified, the report is displayed on standard output. filenamemust be the last argument in the list.

Related Information

report_area

report_fsm

report_hierarchy

report_timing



set_table_style

Examplesreport_design_rule_violations -hierarchical



report_fanin

report_fanin [-level integer ] [-tristate] [-sequential] [-hierarchical] [{> | >>}filename ] [-maxline integer ] list_of_pin_path_or_id

The report_fanin command is used to generate a report on the fanin cone of the specifieddesign objects in the current module. The report generated contains all the pertaininginformation on fanin cone, for example, from pin, to pin, level in the module and the module.All pins and their associated nets on the fanin path are reported with hierarchical names(starting at the current module).

Arguments

-hierarchicalAllows the command to traverse backwards across hierarchyboundaries to generate a report on the fanin cone. By default itwill stop at the input port and it will report on the fanin pathstarting from that port (this is treated as the start point).

-level integerThe number of levels which need to be traversed for generatingthe report.

list_of_pin_path_or_idThe Tcl list of pin or port path names or object identifiers forwhich to start the fanin cone search.

-maxline integerThe number of lines which need to be traversed for generatingthe report.

-output filenameThe report can be written out in a file which can be reviewedlater. The name of the file to be written out is given byfilename .

-tristateInclude the tristates in the fanin path.

-sequentialUsed to include the sequential cells in the fanin path. By defaultthe reporting stops at the encounter of the first sequential cell inthe fanin path.



Related Information

report_fanout

set_table_style



report_fanout

report_fanout [-level integer ] [-tristate] [-sequential] [-hierarchical] [{> | >>}filename ] [-maxline integer ] list_of_pin_path_or_id

The report_fanout command is used to generate a report on the fanout cone of thespecified design objects in the current module. The report generated contains all thepertaining information on fanout, for example, from pin, to pin, level in the module and themodule. All pins and their associated nets on the fanout path are reported with hierarchicalnames (starting at the current module).

Arguments

-hierarchicalAllows the command to traverse forward across hierarchyboundaries to generate a report on the fanout cone. By default itwill stop at output ports and report the fanout path ending at thatport (which is treated as the end point).

-level integerThe number of levels which need to be traversed for generatingthe report. The default value is infinity.

list_of_pin_path_or_idThe Tcl list of pin or port path names or object identifiers forwhich to start the fanin cone search.

-maxline integer

-output filenameThe report can be written out in a file which can be reviewedlater. The name of the file to be written out is given byfilename .

-sequentialUsed to include the sequential cells in the fanout path. By defaultthe reporting stops at the encounter of the first sequential cell inthe fanout path.

-tristateInclude the tristates in the fanout path.



Related Information

report_fanin

set_table_style



report_fsm

report_fsm [-vector vector_name ] [-state_table] [-encoding] [-hierarchical] [{> |>>} filename ]

The report_fsm command generates a report on the finite state machines on the design.The contents of the report include the design name, number of states, inputs, outputs, and soon.

Arguments

{> | >>} filenameThe report is saved in a file specified by filename . If the optionis not used, the data is presented on the standard output.filename must be the last argument in the list.

-vector vector_nameA report on the FSM represented by the state vectorvector_name is displayed. If this option is not used, all FSMsin the current module are reported.

-state_tableA state transition table is extracted in a report form.

-encodingAll state assignments for each selected FSM are reported.

-hierarchicalAll FSMs in any module in the downward path of the currentmodule are displayed.

Related Information

report_area


report_hierarchy

report_timing

set_table_style



Examplesreport_fsm -encoding -state_table





report_globals

report_globals [-tcl_list] [-modified] [-group group_name ] [{ > | >> } filename ]

The report_globals command returns the current and default values for the specifiedglobal variables. If no arguments are specified with the command, the complete list of allglobals will be reported.

Arguments

{> | >>} filenameThe report is saved in a file specified by filename. If the option isnot used, the data is presented on the standard output. Filenamemust be the last argument in the list.

-group group_nameReturns the current and default values of the specified globalvariables belonging to the specified group. Valid values forgroup_name include hdl , aware , ta , opt , pks , dft ,, dist ,dcn , edif , misc , and ui .

-modifiedReturn the current and default values of the specified globalvariables that have been changed from their default value.

-tcl_listReturns the current and default values of the specified globalvariables as a Tcl list.

Related Information

reset_global

set_global

Examples

➤ Get the current and default values of the user interface global variables that have beenmodified from their default values.

report_globals -group ui -modified

+-------------------------------+

| ui |



|-------------------------------|

| Global | Value | Default |

|-------------+-------+---------|

| line_length | 126 | 80 |

+-------------------------------+

➤ Get the current and default values of the user interface global variables.

report_globals -group ui

+-------------------------------------------------------+

| ui |

|-------------------------------------------------------|


|-------------------------+--------------+--------------|

| acsh_prompt | %t[%h]> | %t[%h]> |

| logfile | ac_shell.log | ac_shell.log |

| message_verbosity_level | 7 | 7 |

| line_length | 113 | 80 |

| echo_commands | false | false |

+-------------------------------------------------------+

➤ Get the current and default values of the public test synthesis global variables.

report_globals -group dft

+---------------------------------------------------------+

| dft |

|---------------------------------------------------------|


|-------------------------------------+---------+---------|

| dft_enable_combinational_loop_check | false | false |

| dft_enable_race_condition_check | false | false |

| dft_scan_alphanum_ordering | true | true |

| dft_verbosity_level | 1 | 1 |

| dft_scan_avoid_control_buffering | false | false |

| dft_allow_scan_path_inv | true | true |

| dft_scan_path_connect | chain | chain |

| dft_scan_output_pref | non_inv | non_inv |

| dft_scan_enable_connect | true | true |

| dft_scan_preserve_config | false | false |

+---------------------------------------------------------+



report_hierarchy

report_hierarchy [-inst] [-tcl_list] [{> | >>} filename ]

The report_hierarchy command reports the structural hierarchy as it exists at variousstages in the synthesis process. The hierarchy reported is always that of the netlist inmemory, with the current module as the top of the hierarchy. The report uses the followingsymbols to distinguish hierarchical blocks:

Arguments

-instIncludes the instance name of the module instantiation in theoutput. Modules that are multiply instantiated will include aseparate line of output for each instantiation.

-tcl_listReports the hierarchy in the form of a Tcl list. To use the outputof the Tcl list to generate Tcl code, use a Tcl variable, as shownin the example below.

{> | >>} filenameGenerated report is stored in the file specified by filename . Ifthe filename is not specified then the report is displayed onstandard output. Note that filename must be the lastargument in the list.

Related Information

report_area


report_fsm

b Black box module

g Generic (unmapped) module

o Optimized module

x dont_modify attribute is set for this module

m Module contains a mapped view



report_timing

set_table_style

Examples

The command below will generate a report on the current hierarchy and save it in a filedesign.hier.rpt

report_hierarchy design.hier.rpt

The command below will display instance name of the module instantiation. Sample outputfollows the command.

report_hierarchy -inst

-my_top(g)

-mid1_0 -> my_mid1(m)

-mid1_1 -> my_mid1(m)

-mid2_0 -> my_mid2(g)

The commands below uses the Tcl variable result to save the -tcl_list code into thefile save_tcl_code file.

set result [report_hierarchy -tcl_list]

echo $result > save_tcl_code



report_resources

report_resources [-summary] [-hierarchical] [-module module_name ] [-instance] [{> | >> } filename ]

The report_resources command provides information about the datapath modules in thedesign. By default, it contains information about the architecture, size, format andcorresponding RTL line number of datapath clusters in the datapath modules. The summaryreport contains the information about different arithmetic operators in the datapath module.By default, resources are listed for the current module, but if -module option is used, theresources are separated for the specific module.

Arguments

filenameWrites the report in the summary file.

-hierarchical A report is generated for the hierarchy under the current moduleor the specified module. The hierarchy of the current module orspecified module is traversed and the report is generated foreach datapath module found.

-instanceThe report is generated for each instance of the datapathmodules.

-moduleModule for which all the datapath resources are to be separated.

-summaryGenerates summary report for each datapath module. Thesummary contains module or instance name, type and numberof each arithmetic operator in the module or instance.



report_vhdl_library

report_vhdl_library [-verbose] [ library ] [{ > | >> } filename ]

The report_vhdl_library command lists the mappings between all the defined VHDLlibraries and the directories to which they are mapped. This command can be used to checkwhere BuildGates Synthesis picks up VHDL units such as packages.

Arguments

file_nameThe file to which the report is written.

libraryLists the mapping for the specified VHDL library.

-verboseLists the contents of the VHDL library.

Related Information

set_global hdl_vhdl_read_version

set_vhdl_library



reset_dont_modify

reset_dont_modify [-network] [-hierarchical] list_of_object_ids

The reset_dont_modify command removes the dont_modify attribute set by a previousset_dont_modify command, applied to a design module, instance, or port. Useset_cell_property for applying and removing properties on library cells.

Arguments

list_of_object_idsList of object identifiers. See the set_dont_modify command.

Related Information



set_cell_property

set_dont_modify

Examples

set_dont_modify [find -module my_mod]

reset_dont_modify [find -module my_mod]



reset_failsafe

reset_failsafe

This command restores the name of the file in which to store the database in the event of afatal error to the default location of /tmp/ process_id .

Related Information

set_failsafe

Examplesreset_failsafe



reset_global

reset_global global_variable_name

The reset_global command sets the specified global variable to its default value.

Arguments

global_variable_nameThe name of the global variable to reset.

Related Information

set_global

Examples

The example below resets the VHDL version for writing out VHDL netlists to the default:1993 .

reset_globals h dl_vhdl_write_version



reset_register_type

reset_register_type register_instance_id_list

The reset_register_type command removes the register type constraint imposed bythe previously issued set_register_type command. Subsequent mapping will notenforce mapping to the previously specified register type.

Arguments

register_instance_id_listList of object IDs for the register instances.

Related Information

set_register_type

Examples

The command re set_register_type removes the register type constraint imposed by thepreviously issued set_register_type command. For example, if

set_register_type -latch LD1 -flip_flop FD1 [find -registers *]

was issued, the command below removes the LD1 and FD1 register type constraints.Consequently, subsequent mapping will not enforce mapping to register cells of the sametype as LD1 and FD1.

reset_register_type [find -registers *]



reset_vhdl_library

reset_vhdl_library library_name

The reset_vhdl_library command can be used to remove all VHDL units that have beenanalyzed into a specific library. This is useful if a package was mistakenly analyzed into thewrong library, or if you wish to clear the library of all VHDL units previously analyzed into itand start over.

Arguments

library_nameName of the library from which all analyzed units are to bedeleted.

Related Information

report_vhdl_library

set_vhdl_library

Examples

➤ Reset library MYLIB after a VHDL package from wrongpack.vhd was analyzed into it.

read_vhdl -library MYLIB wrongpack.vhd

reset_vhdl_library MYLIB

➤ Read correct package into MYLIB

read_vhdl -library MYLIB rightpack.vhd



set_attribute

set_attribute object_id { attribute_name attribute_value }

The set_attribute command sets the value set for the specified attribute on the specifiedobject. You can set tool- and user-defined attributes.

The set_attribute command can be used to disable some of the default do_optimizebehavior. You can set the object_id , the attribute_name , and theattribute_value . The corresponding options for do_optimize are -force ,-no_partition , -priority , -flatten , -phase , -multiple_output .

By default, do_optimize partitions the module. If you do not want to partition a particularmodule, then you can use the following command:

set_attribute object_id no_partition true

If you use the do_optimize -no_partition command and you want to partition aparticular module, then use the following:

set_attribute object_id no_partition false

If the following command is used:

set_attribute [find -techlib lca300kv] default_operating_conditions WCCOM

the software treats default_operating_conditions as a user-specified attribute havinga value of WCCOM. This attribute is set on the object lca300kv .

You can use the following command to query the attribute:

get_info [find -techlib lca300kv]

The set_attribute command can be used to set the operating conditions, but it isrecommended that you use the set_operating_conditions command instead.

The set_attribute command is not limited to setting the attributes listed below.User-defined attributes are also valid.

Arguments

attribute_nameThe name of the attribute to set. Refer to the Attributes list belowfor a list of tool-defined attributes.

attribute_valueSets the attribute to this value.



object_idThe ID of the module, instance, cellref, net, port, or pin to modify.

Attributes

The attributes below are defined by the Ambit BuildGates synthesis tool. User-definedattributes are also valid.

flatten {on | off | auto}Controls the operations used for the optimization of logicequations. If the flatten option is set to on, the logic equations areflattened into a sum of products form before applying theoptimization. This helps to create a faster and more optimalimplementation of the logic, even though it may use extra area(gates). If the flatten option is set to auto , only certain flatteningoperations are performed; some of the time consuming steps areignored. The flattening step may be disabled entirely by settingthe option to off . The default option for flatten is off .

force {true | false}Forces this command to carry out all of its steps irrespective ofthe initial state of the design.

no_partition { true | false }Indicates that the design should not be automatically partitionedinto smaller modules for optimization, irrespective of the numberof input pins on the cells in the module. Each module boundaryshould be retained as the partition to optimize.

phase {true | false}Performs phase assignment on module object_id in logicminimization during structuring if the module is flattened into twolevels of logic successfully with option -flatten auto or-flatten on (or attribute flatten) or on PLA hierarchy, if any,that is inferred from constant case statement within the moduleobject_id . Default value is false .

Below are two examples.

Set phase attribute to false on all modules in the designhierarchy except module module_A , then optimize.set_attribute module_A phase truedo_optimize



Apply phase assignment on all modules in the design hierarchyin structuring except module module_B , then optimize using the-phase_assignment option.set_attribute module_B phase falsedo_optimize -phase_assignment

priority {area | time}Sets area or timing minimization to be the highest priority of thetechnology, independent of the optimization step. The defaultpriority is time. If you have a loosely constrained orunconstrained design, then the priority should be set to area.

Related Information

get_attribute

delete_attribute

get_info

set_global

Examples

The set_attribute command can be used to change the default behavior ofdo_optimize . For example, by default, do_optimize partitions the module butset_attribute allows you to prevent the partition of a particular module. The commandbelow prevents the partition of the module module_x1 .

set_attribute module_x1 no_partition true

If you use the do_optimize -no_partition command, you may still partition a particularmodule. The command below allows the partition of the module module_x2 .

set_attribute module_x2 no_partition false

The set_attribute command can also be used to set the user-defined attributes. Thecommand below sets the attribute my_attribute on the net object my_net to a value ofmy_value .

set_attribute [find -net my_net] my_attribute my_value



You can use the get_attribute or get_info commands to query the attribute, as shownbelow.

get_attribute [find -net my_net] my_attribute

or

get_info [find -net my_net]




set_aware_component_property [-library library_name ] dont_utilize {true |false} component_name

The set_aware_component_property command allows the property to be set on anaware component. The only allowed property at this point is dont_utilize . When thisproperty is set on a component, it is not available for use.

Arguments

component_nameName of the component on which the property is to be set.

-library library_nameSelects the name of the aware library to which the componentbelongs. If no library is specified, then the component issearched in all aware libraries (in the order determined by theglobal aware_library_search_order ).

dont_utilize {true | false}

Currently, the only allowed property is dont_utilize .

Related Information

set_aware_library



Examplesset_aware_component_property -library AWARITH dont_utilize true AWARITH_ABS



set_aware_library

set_aware_library library_name library_path

The set_aware_library command maps the logical library name library_name to thephysical path library_path .

Arguments

library_nameName of the aware library.

library_pathSpecifies the path to map to library_name .

Related Information


Examples

The following example maps the logical name of the library AWMYLIBto the existing directory/home/smith/libs/lib1 where the analyzed components physically reside.

set_aware_library AWMYLIB /home/smith/libs/lib1



set_cell_property

set_cell_property property value -lib library_name cell_names

The set_cell_property command sets properties of one or more cells to specifiedvalues. These properties can be dont_modify , dont_utilize , and so on. The value ofthe properties can be set to true or false. Note that set_tech_info, get_tech_info ,and reset_tech_info should be used instead of this command. These are more powerfulmechanisms which can go beyond the functionality of set_cell_property. They can beused to update library information.The set_cell_property command will be phased out in the future.

Arguments

propertyName of a property of the cell which needs to be set.Properties include:dont_modify { true | false }dont_utliize { true | false}objecttype typemodule idpins idAll the properties of a cell can be listed using the commandget_info .

valueNew value of the property.

cell_namesList of cells whose properties will be changed.

-lib library_nameThe library contains a list of properties that will be changed.

Related Information

get_info

set_current_module

Examplesset_cell_property dont_modify true [find -cellref Fifo3]




set_current_instance [ instance_name ]

The set_current_instance command sets the instance given by instance_name tobe the current instance. Design objects referenced by subsequent commands can be foundrelative to this instance. All searches for design objects are started in this instance. If designobjects are referenced hierarchically, instance_name is used as the root (top) of thehierarchy.

The set_current_instance command is used instead of the set_current_modulecommand when a module has multiple instances and each instance requires a separate setof constraints.

Arguments

instance_nameSpecifies the name of the instance to become the currentinstance. If instance_name is not given, the current instanceis set to the top instance of the hierarchy.

Related Information

set_current_module


Examplesset_current_instance MAC/MULT1...# set current instance back to top




set_current_module

set_current_module module_name

The set_current_module command makes the module represented by module_namethe current module. Design objects referenced by subsequent commands can be foundrelative to this module. All searches for design objects are started in this module. If designobjects are referenced hierarchically, module_name is used as the root (top) of thehierarchy.

If a module has multiple instances and each instance requires a separate set of constraints,then the set_current_instance command is used.

Note that when the set_current_module command is used, the current_instanceis reset to the top_timing_module .

Arguments

module_nameName of the module that is being used in the current context.

Related Information


find

get_current_module


Examples

This example sets the mycounter module as the current context. Now the constraints canbe applied to the ports of mycounter .

set_current_module mycounter

To apply constraints to ports of another module either use the set_current_modulecommand with another module name, or use the hierarchical name of the ports.



set_dont_modify

set_dont_modify [-network] [-hierarchical] list_of_object_ids

The set_dont_modify command is used to keep the instances, modules or nets frombeing modified. This is useful when those objects have already been optimized. No furtheroptimization will be done on the specified instances, modules or nets. The command is alsouseful when macros are instantiated from a library. Note: when ports are specified, it isequivalent to specifying the nets connected to these ports.

Once a module is marked for no modifications, the commandsdo_uniquely_instantiate or do_dissolve_hierarchy are ignored for that module.When a net is specified, all the connecting instances are affected by the set_dont_modifyproperty. When an instance pin or port is specified then the net connected to it is marked asdont_modify .

The nets, modules or instances identified by this command are preserved “as is” during thesynthesis process.

Arguments

-networkSpecifies that the dont_modify attribute applies to thecombinational path connected to the given object. This option isvalid with net and port object types.

-hierarchicalThis option is valid only for module, net and port object types.

If this option is specified for modules, all lower levels of hierarchybelow the specified module are also marked dont_modify .If this option is specified for nets or ports, all nets and instancesconnected hierarchically to the specified nets or ports will bemarked dont_modify . If -network is also specified, thenhierarchies will be traversed to mark all nets and instances in thecombination path of specified nets and ports as dont_modify .

If -hierarchy is not specified, then only nets and instancesconnected to the specified nets or ports that are in the same orin the combinational path of (if -network is specified) hierarchywill be marked dont_modify .



list_of_object_idList of object IDs for the instance, module, net, pin, or port to bepreserved. Ports must be either input or inout ports of modulesor output or inout pins of instances. When ports are specified, itis equivalent to specifying the nets connected to these ports

Related Information



reset_dont_modify

set_current_module

Examples

➤ set_dont_modify -hierarchical [find -net rst]

All the highlighted nets in the figure below are preserved. If the hierarchical option wasnot specified the highlighted path in the instance I4 (shown by the dotted boundary),and the nets n1 , n2 would not be preserved.

➤ set_dont_modify -hierarchical [find -mod myRAM]

Preserve the module myRAM and all of its hierarchy. This could be a hand-built RAMmodel which is already optimized.

➤ set_dont_modify [find -inst RAPID_FIFO]

Mark the instance RAPID_FIFO for preservation.

➤ set_dont_modify [find -net n_190]

Put a dont_modify on the net and the two or more instances to which it connects.

rst

I1 I2

I3

I4

n1

n2



➤ set_dont_modify [find -port port_A]

Put a dont_modify on the net connected to the port, but not on the other endinstance.

➤ set_dont_modify -network [find -port port_A]

Put a dont_modify on the net connected to the port and all the other end instances inthe fanout cone stopping at a hierarchical port or a sequential cell.

➤ set_dont_modify -network -hierarchy [find -port port_A]

Put a dont_modify on the net connected to the port and all the other end instances inthe fanout cone without stopping at a hierarchical port.



set_failsafe

set_failsafe filename

This command sets the name of the file in which to store the database in the event of a fatalerror. The specified file name is used instead of the system default location of/tmp/ process_id .

Arguments

filenameThe name of the directory and file in which to store the databasein the event of a fatal error.

Related Information

reset_failsafe

Examplesset_failsafe /usr1/tmp/failsafe_1



set_global

set_global[acsh_prompt string ][auto_slew_prop_selection {true | false}][aware_adder_architecture {ripple | csel | cla | csum | fcla}][aware_implementation_selection {true | false}][aware_dissolve_width integer ][aware_library_search_order logical_names ][aware_merge_operators {true | false}][aware_multiplier_architecture { booth | non-booth | auto}][aware_mux_max_sharing percentage ][aware_mux_min_size integer ][bidi_io_arc {enable | disable}][buscomp_generator string ][capacitance_limit float ][clock_gating_regardless_of_downstream_logic {true | false}][clock_gating_to_be_checked {true | false}][dcl_debug_mode {true | false}][dcl_message_verbosity_level integer ][dcn_bus_allow_conversions{ true | false }][dcn_bus_allowed string][dcn_bus_first_restricted string][dcn_bus_last_restricted string][dcn_bus_max_length integer][dcn_bus_prefix string][dcn_bus_remove_chars string][dcn_bus_replacement_char char][dcn_bus_reserved_words string][dcn_bus_restricted string][dcn_inst_allow_conversion { true | false }][dcn_inst_allowed string][dcn_inst_first_restricted string][dcn_inst_last_restricted string][dcn_inst_max_length integer][dcn_inst_prefix string][dcn_inst_remove_chars string][dcn_inst_replacement_char char][dcn_inst_reserved_words string][dcn_inst_restricted string][dcn_module_allow_conversion { true | false }][dcn_module_allowed string][dcn_module_first_restricted string][dcn_module_last_restricted string][dcn_module_max_length integer][dcn_module_prefix string][dcn_module_remove_chars string][dcn_module_replacement_char char][dcn_module_reserved_words string][dcn_module_restricted string][dcn_net_allow_conversion { true | false }]



[dcn_net_allowed string][dcn_net_first_restricted string][dcn_net_last_restricted string][dcn_net_max_length integer][dcn_net_prefix string][dcn_net_remove_chars string][dcn_net_replacement_char char][dcn_net_reserved_words string][dcn_net_restricted string][dcn_port_allow_conversion { true | false }][dcn_port_allowed string][dcn_port_first_restricted string][dcn_port_last_restricted string][dcn_port_max_length integer][dcn_port_prefix string][dcn_port_remove_chars string][dcn_port_replacement_char char][dcn_port_reserved_words string][dcn_port_restricted string][depth_for_fast_slew_prop { 0 | 1 | 2 | 3 }][dft_allow_scan_path_inv { true | false }][dft_alphnum_ordering {true | false}][dft_enable_combinational_loop_check {true | false}][dft_enable_race_condition_check {true | false}][dft_scan_avoid_control_buffering {true | false}][dft_scan_enable_connect {on | tieoff | floating}][dft_scan_output_pref {non_inv | min_load}][dft_scan_path_connect {chain | tieback | tie0 | tie1 | floating}][dft_verbosity_level integer ][dist_batch_queue name][dist_bits p2[dist_capture_job_histogram {true | false}][dist_default {on | user | off}][dist_embargo_delay time ][dist_enable_final_top_down {true | false}][dist_granularity {medium | fine | coarse}][dist_kill_signal signal ][dist_kill_verbose {on | off}][dist_launch_delay time ][dist_launch_mode {batch | hostlist}][dist_launch_timeout time ][dist_max_failures integer ][dist_max_jobs integer ][dist_max_load percent ][dist_max_restarts integer ][dist_min_cpus integer ][dist_min_jobs integer ][dist_nice integer ][dist_remsh_timeout [ hours ]:[ minutes ]: seconds .[ milliseconds ]][dist_restart_delay hh:mm:ss ][dist_restart_embargo hh:mm:ss ]



[dist_restart_signal {NULL | QUIT | HUP | TERM | USR1 | USR2}][dist_retries integer ][dist_shutoff time ][dist_startup time ][dist_std_file filename ][dist_stop_after_mapping {true | false}][dist_summary_delay time ][dist_timeout time ][dist_uniquify {early | late | none}][dist_verbose integer ][dist_weight nonnegative_integer ][echo_commands {true | false }][edifin_bus_dimension_separator_style string ][edifin_bus_range_separator_style string ][edifin_power_and_ground_representation {net | port| instance | none}][edifin_ground_net_name string ][edifin_ground_net_property_name string ][edifin_ground_net_property_value string ][edifin_ground_port_name string ][edifin_ground_pin_name string ][edifin_ground_instance_name string ][edifin_power_net_name string ][edifin_power_net_property_name string ][edifin_power_net_property_value string ][edifin_power_port_name string ][edifin_power_pin_name string ][edifin_power_instance_name string ][edifout_designs_name string ][edifout_designs_cell_name string ][edifout_designs_library_name string ][edifout_power_and_ground_representation {net | port| instance | none}][edifout_ground_net_name string ][edifout_ground_net_property_name string ][edifout_ground_net_property_value string ][edifout_ground_pin_name string ][edifout_ground_instance_name string ][edifout_ground_cell_name string ][edifout_ground_port_name string ][edifout_power_net_name string ][edifout_power_net_property_name string ][edifout_power_net_property_value string ][edifout_power_pin_name string ][edifout_power_instance_name string ][edifout_power_cell_name string ][edifout_power_port_name string ][edifout_array {true | false }][edifout_properties {true | false }][enable_pinswap {true | false }][estimate_supply_rail_congestion {true | false}][extra_space_for_opt percentage ][failsafe {true | false }]



[fanout_load_limit float ][favor_feedback_cells {true | false }][fix_multiport_nets { true | false }][hdl_common_subexpression_elimination {true | false}][hdl_cse_for_registers {true | false}][hdl_error_on_latch {true | false}][hdl_extract_pla {true | false}][hdl_ff_auto_sync_set_reset {true | false}][hdl_latch_auto_async_set_reset {true | false}][hdl_max_loop_limit integer ][hdl_max_recursion_limit integer][hdl_preserve_unused_registers {true | false}][hdl_undriven_net_value {0 | 1 | x | z | none}][hdl_verilog_out_columns integer ][hdl_verilog_out_compact {true | false}][hdl_verilog_out_declare_implicit_wires {true | false}][hdl_verilog_out_prim {true | false}][hdl_verilog_out_source_track {true | false}][hdl_verilog_out_unconnected_style {none | partial | full}][hdl_verilog_out_use_supply {true | false}][hdl_verilog_vpp_arg string ][hdl_vhdl_case {lower | upper | original}][hdl_vhdl_environment { standard | synopsys| common | synergy}[hdl_vhdl_lrm_compliance {true | false}][hdl_vhdl_preferred_architecture string ][hdl_vhdl_read_version {1987 | 1993}][hdl_vhdl_reuse_units {true | false}][hdl_vhdl_write_architecture {true | false}][hdl_vhdl_write_architecture_name string ][hdl_vhdl_write_bit_type {std_logic | std_ulogic}][hdl_vhdl_write_components {true | false}][hdl_vhdl_write_entity {true | false}][hdl_vhdl_write_entity_name string ][hdl_vhdl_write_packages lib1 . pack_x ...][hdl_vhdl_write_version {1987 | 1993}][hdl_write_gnd_name string ][hdl_write_multi_line_port_maps {true | false}][hdl_write_vdd_name string ][hierarchy_divider character ][ignore_net_area_cost {true | false}][instance_generator integer ][ipl_pin_limit string ][large_fanout_size size ][lib_build_asynch_arc {true | false}][lib_build_timing_cond_default_arc {true | false}][line_length integer ][make_routable_max_over_congestion percentage ][make_routable_max_size percentage ][make_routable_over_congestion_rate percentage ][make_routable_oversize_rate percentage ][map_inversion_through_registers {true | false}]



[map_to_multibit_registers {true | false}][max_capacitance_limit float ][max_points_to_report integer ][max_slew_time_limit float ][message_verbosity_level {[3-9]}][min_capacitance_limit float ][min_slew_time_limit float ][naming_style {vhdl | verilog | none}][net_generator string ][no_buffer_at_integration_level {true | false}][no_of_groute_passes_for_cong integer ][opt_no_new_instances_at_top_level {true | false}][path_style_timing_constraint {true | false}][pks_do_place_option option ][pks_snap_pin_locations {0 | 1}][placement_initialize_auto_pass {true | false}][place_over_utilized {true | false}][preserve_constant_flops [true | false}][pvt_early_path {min | typ | max}][pvt_late_path {min | typ | max}][report_precision integer ][report_timing_format][slew_limit float ][slew_propagation_mode {worst_slew | critical_slew | fast}][slew_time_limit float ][smoothen_area_gap percentage ][smoothen_utilization_only [true | false}][target_technology lib_x ...][time_budget_min_size integer ][time_budget_stop_before_uniquification {true | false}][timing_analysis_type {min_max | bc_wc}][timing_disable_bus_contention {true | false}][timing_disable_floating_bus_check {true | false}][timing_disable_recovery_removal_checks {true | false}][timing_driven_cong_analysis {0 | 1}][topt_no_external_sources_at_outputs {true | false}][use_drive_cell_design_rules {true | false}][use_groute_based_cong_analysis {0 | 1}][use_lef_area {true | false}][wired_logic_resolution {and | or}][write_sdf_force_calculation {true | false}]

The set_global command sets the global variables of ac_shell . These variables areindependent of the design, but affect the overall run procedure and ac_shell policies onvarious global matters which are essentially independent of the design, for example, theVerilog module naming style, message verbosity level, slew limit, and line length in reports.

All global variables have default value when ac_shell starts up. Once a variable is set to anew value, it retains that value for the current ac_shell session unless a subsequent use of



this command sets a new value for the variable. User-specified values for global variables arenot saved in the Ambit Synthesis database (ADB) file.

The value of any global variable can be obtained using get_global command. The valueof any global variable can be set to the default value using reset_global command. Theset_global command has a one-to-one correspondence with the get_global andreset_global commands. Every variable defined in set_global also applies toget_global and reset_global .

Arguments

For complete descriptions of global ac_shell variables, see Command Arguments forset_global on page 203.

Related Information

get_global

reset_global

set_attribute

Examples

set_global target_technology G11

set_global buscomp_generator “%s_%d_bus”

Command Arguments for set_global

The following are all the Ambit BuildGates Synthesis global ac_shell variables, includingthe default values for the arguments and the functionality of each argument. For each of theseglobals, you can retrieve the current setting using the commandget_global global_name , for example get_global hdl_error_on_latch . Thereset_global global_name command returns the setting to the default value. Forexample reset_global hdl_error_on_latch changes the current setting back to thedefault value of false.

acsh_prompt string



The command prompt string for ac_shell .Default: %t[%h]>

auto_slew_prop_selection {true | false}

When set to false , all optimizations are performed in fast slew propagation modeusing the depth specified in the global depth_for_fast_slew_prop .

When set to true , all optimizations are performed in worst slew propagation modeusing a depth increasing from 0 to 1 to 2. When slack reaches 0 or is no longerimproving, the tool increases the slew depth to 1 and repeats the process. Afteroptimization is run with slew depth 2 the tool is finished.

If the -incremental option of a do_xform_* command is specified, optimizationwill always start with depth of 2.

Default: true

aware_adder_architecture {ripple | csum | csel | cla | fcla}

Sets the default adder architecture for (final) adders. The fcla option is onlyavailable with the datapath option.Default: cla for AWCL and fcla for AWDP

aware_dissolve_width positive_integer

Sets the limit for the width of the operator units (such as adders, subtractors,incrementors, decrementors, and comparators) to be dissolved. The value is aninteger indicating the number of bits for the size of a ripple adder. All adders with thegate count less than or equal to the ripple adder of the specified bit width will bedissolved.Default: 4

Note: The dissolve width is based on the literal count of the operator and is influencedby the architecture. For example: a 16 bit adder implemented using the cla architecture,is about the same size as a 24-bit ripple adder, therefore the integer value should be



24.

aware_implementation_selection {true | false}

When set to true, the implementation of datapath components are automaticallyselected based on the constraints. This command is only available with the datapathoption.Default: true

aware_library_search_order logical_names

Sets the order in which aware libraries are searched for components. If two librariescontain a component with the same name, the one found first will be used. Thiscommand is only available with the datapath option.Default: AWARITH AWLOGIC

aware_merge_operators { true | false }

Controls operator merging. When ac_shell is invoked with the datapath option,operator merging is enabled by default. You can disable operator merging with thecommand set_global aware_merge_operators false before callingdo_build_generic . You can also control operator merging using a pragma thatforces merging to stop at the operator on which the property is attached via thepragma. The following Verilog pragma results in a merged implementation of theexpression:assign z = a * //ambit synthesis merge_boundaryb + c;

This may be useful in situations where you do not want the tool to merge someparticular operator with other downstream operators.

The tool does not limit the scope of operator merging to arithmetic expressionsdefined by a single HDL statement. Operator merging is done on the CDFG (ControlData Flow Graph) representation derived from the HDL and can span operators inmultiple HDL statements.Default: true



aware_multiplier_architecture {booth | non_booth | auto}

Sets the default multiplier architecture for multipliers. This command is only availablewith the datapath option.Default: auto

aware_mux_max_sharing positive_integer

Sets the percentage of shared data inputs, above which the multiplexer is dissolvedat the beginning of the do_optimize command and optimized (structured andmapped) within the context of the surrounding logic. The AmbitWare multiplexergenerator uses heuristics to estimate the percentage of unique data inputs for eachmultiplexer function in the RTL description. The If the aware_mux_max_sharingpercentage of unique data inputs is greater than 100, the multiplexer is determinedto be "map-only" and is skipped by structuring.Default: 25

aware_mux_min_size positive_integer

Sets the minimum size, in terms of the number of data inputs, for which a multiplexercan be determined to be "map-only" by the AmbitWare multiplexer generator.Multiplexers that have fewer data inputs than the specified aware_mux_min_sizeare dissolved at the beginning of the do_optimize command and optimized(structured and mapped) within the context of the surrounding logic.Default: 8

bidi_io_arc {enable | disable}

Enables the bidirectional feedback paths in a cell by establishing a feedback path(s)between the cell pin(s) feeding the bidi port and the driven cell pin(s). This variablehas no effect on timing of bidirectional feedback paths involving more than one cell.Default: disable



buscomp_generator string

Choose a scheme to name individual bits of buses. The string argument mustinclude %sto indicate the name of the bus signal, and %dto indicate the bit number.This global must be set before do_build_generic is executed. Relatedcommands are do_blast_busses and do_rename .Default: %s[%d]

capacitance_limit float

Specify maximum capacitance limit on all cells.Default: no limit — infinite

This variable has been replaced with the variable max_capacitance_limit .

clock_gating_regardless_of_downstream_logic {true | false}

This variable controls the treatment of a clock signal based on how it is used in thefanout cone of the clock-gating cell (down stream logic) when data and clock signalsarrive at the inputs. A clock gating check will be performed at the clock gating cellbased on whether or not the signal is expected at the fanout cone of the clock-gatingcell.Default: true

When set to true , the following occurs when both data and clock signals arrive atthe inputs.

Signal ExpectedClockGatingCheck?

Result

Clock — gated signal onlyconnects to the clock pins ofregisters/latches

yes Clock flows through gate; data is blocked.



Tip

To determine whether a pin is clock or data, use the command:get_timing pin_name clkordata

clock_gating_to_be_checked {true | false}

Check whether clock and data signals are connected to any gate. The timing of thedata input is propagated to the clock input of the gate to ensure that there are noglitches.Default: true

dcl_debug_mode {true | false}

Data — clock gating cellconnects to data/preset/clearpins of registers/latches

No Clock signal is converted to data. Bothconverted clock and data signals flow throughgate and take part in down stream timingchecks (if any). The entire fanout cone isconsidered as data logic and optimizationengine optimizes it to meet timing constraints.

Data and clock Yes Data signal is blocked and clock flows through.For signal from a pin:

If the gated signal is only used as data downstream, then the clock signal is converted todata and the optimization works on the logic.

If the gated signal is used down stream as clockor as both clock or data, the signal continues asclock.

Signal ExpectedClockGatingCheck?

Result



Sets debug mode to true or false .Default: false

dcl_message_verbosity_level integer

Controls the level of verbosity of the messages generated in by ac_shell inreporting information, warnings, and errors.Default: 0

dcn_bus_allow_conversion { true | false }

Set to true to allow conversion of the bus. Used to set the conversion rules for thedo_change_name command.Default: false

dcn_bus_allowed string

Specify list of all allowed characters for the bus. Used to set the conversion rules forthe do_change_name command.Default: ][0123456789abcdefghijklmnopqrstuvwxyz

ABCDEFGHIJKLMNOPQRSTUVWXYZ_

dcn_bus_first_restricted string

Specify list of restricted first characters for the bus. Used to set the conversion rulesfor the do_change_name command.Default: $

dcn_bus_last_restricted string



Specify list of restricted last characters for the bus. Used to set the conversion rulesfor the do_change_name command.Default: $

dcn_bus_max_length integer

Specify maximum name length for the bus. Used to set the conversion rules for thedo_change_name command.Default: 32

dcn_bus_prefix string

Specify prefix characters to add to the bus name. Used to set the conversion rulesfor the do_change_name command.Default: none

dcn_bus_remove_chars string

Specify characters to remove from the bus name. Used to set the conversion rulesfor the do_change_name command.Default: none

dcn_bus_replacement_char char

Specify single replacement character to use in the bus. Used to set the conversionrules for the do_change_name command.Default: B

dcn_bus_reserved_words string



Specify string of reserved words to change for the bus. Used to set the conversionrules for the do_change_name command.Default: none

dcn_bus_restricted string

Specify list of all restricted characters for the bus. Used to set the conversion rulesfor the do_change_name command.Default: none

dcn_inst_allow_conversion { true | false }

Set to true to allow conversion of the instance. Used to set the conversion rules forthe do_change_name command.Default: false

dcn_inst_allowed string

Specify list of all allowed characters for the instance. Used to set the conversionrules for the do_change_name command.Default: ][0123456789abcdefghijklmnopqrstuvwxyz


dcn_inst_first_restricted string

Specify list of restricted first characters for the instance. Used to set the conversionrules for the do_change_name command.Default: $

dcn_inst_last_restricted string



Specify list of restricted last characters for the instance. Used to set the conversionrules for the do_change_name command.Default: $

dcn_inst_max_length integer

Specify maximum name length for the instance. Used to set the conversion rules forthe do_change_name command.Default: 32

dcn_inst_prefix string

Specify prefix characters to add to the instance name. Used to set the conversionrules for the do_change_name command.Default: none

dcn_inst_remove_chars string

Specify characters to remove from the instance name. Used to set the conversionrules for the do_change_name command.Default: none

dcn_inst_replacement_char char

Specify single replacement character to use in the instance. Used to set theconversion rules for the do_change_name command.Default: I

dcn_inst_reserved_words string



Specify string of reserved words to change for the instance. Used to set theconversion rules for the do_change_name command.Default: none

dcn_inst_restricted string

Specify list of all restricted characters for the instance. Used to set the conversionrules for the do_change_name command.Default: none

dcn_module_allow_conversion { true | false }

Set to true to allow conversion of the module. Used to set the conversion rules forthe do_change_name command.Default: false

dcn_module_allowed string

Specify list of all allowed characters for the module. Used to set the conversion rulesfor the do_change_name command.Default: ][0123456789abcdefghijklmnopqrstuvwxyz


dcn_module_first_restricted string

Specify list of restricted first characters for the module. Used to set the conversionrules for the do_change_name command.Default: $

dcn_module_last_restricted string



Specify list of restricted last characters for the module. Used to set the conversionrules for the do_change_name command.Default: $

dcn_module_max_length integer

Specify maximum name length for the module. Used to set the conversion rules forthe do_change_name command.Default: 32

dcn_module_prefix string

Specify prefix characters to add to the module name. Used to set the conversionrules for the do_change_name command.Default: none

dcn_module_remove_chars string

Specify characters to remove from the module name. Used to set the conversionrules for the do_change_name command.Default: none

dcn_module_replacement_char char

Specify single replacement character to use in the module. Used to set theconversion rules for the do_change_name command.Default: M

dcn_module_reserved_words string



Specify string of reserved words to change for the module. Used to set theconversion rules for the do_change_name command.Default: none

dcn_module_restricted string

Specify list of all restricted characters for the module. Used to set the conversionrules for the do_change_name command.Default: none

dcn_net_allow_conversion { true | false }

Set to true to allow conversion of the net. Used to set the conversion rules for thedo_change_name command.Default: false

dcn_net_allowed string

Specify list of all allowed characters for the net. Used to set the conversion rules forthe do_change_name command.Default: ][0123456789abcdefghijklmnopqrstuvwxyz


dcn_net_first_restricted string

Specify list of restricted first characters for the net. Used to set the conversion rulesfor the do_change_name command.Default: $

dcn_net_last_restricted string



Specify list of restricted last characters for the net. Used to set the conversion rulesfor the do_change_name command.Default: $

dcn_net_max_length integer

Specify maximum name length for the net. Used to set the conversion rules for thedo_change_name command.Default: 32

dcn_net_prefix string

Specify prefix characters to add to the net name. Used to set the conversion rulesfor the do_change_name command.Default: none

dcn_net_remove_chars string

Specify characters to remove from the net name. Used to set the conversion rulesfor the do_change_name command.Default: none

dcn_net_replacement_char char

Specify single replacement character to use in the net. Used to set the conversionrules for the do_change_name command.Default: N

dcn_net_reserved_words string



Specify string of reserved words to change for the net. Used to set the conversionrules for the do_change_name command.Default: none

dcn_net_restricted string

Specify list of all restricted characters for the net. Used to set the conversion rulesfor the do_change_name command.Default: none

dcn_port_allow_conversion { true | false }

Set to true to allow conversion of the port. Used to set the conversion rules for thedo_change_name command.Default: false

dcn_port_allowed string

Specify list of all allowed characters for the port. Used to set the conversion rules forthe do_change_name command.Default: ][0123456789abcdefghijklmnopqrstuvwxyz


dcn_port_first_restricted string

Specify list of restricted first characters for the port. Used to set the conversion rulesfor the do_change_name command.Default: $

dcn_port_last_restricted string



Specify list of restricted last characters for the port. Used to set the conversion rulesfor the do_change_name command.Default: $

dcn_port_max_length integer

Specify maximum name length for the port. Used to set the conversion rules for thedo_change_name command.Default: 32

dcn_port_prefix string

Specify prefix characters to add to the port name. Used to set the conversion rulesfor the do_change_name command.Default: none

dcn_port_remove_chars string

Specify characters to remove from the port name. Used to set the conversion rulesfor the do_change_name command.Default: none

dcn_port_replacement_char char

Specify single replacement character to use in the port. Used to set the conversionrules for the do_change_name command.Default: P

dcn_port_reserved_words string



Specify string of reserved words to change for the port. Used to set the conversionrules for the do_change_name command.Default: none

dcn_port_restricted string

Specify list of all restricted characters for the port. Used to set the conversion rulesfor the do_change_name command.Default: none

depth_for_fast_slew_prop { 0 | 1 | 2 | 3 }

Controls the number of logic levels that input slew affects output slew when usingfast slew propagation mode. Increasing the depth converges towards worst slewpropagation mode timing. See also slew_propagation_mode global.Default: 0

dft_allow_scan_path_inv {true | false}

Controls whether scan-data can be inverted along the scan path. Allows inversionin the scan path when set to true , prevents inversions when set to false .Inversions in the scan path can occur in two situations:

The scan register’s Q-bar output is selected for the scan data to reduce loading onthe Q output (see the global variable dft_scan_output_pref min_load ).

A scan register was selected with a single, Q-bar, output pin.

When set to false , the scan insertion tool adds an inverter to the scan-data pathimmediately following an inversion. When set to true , any inversions in the scandata path are marked with an asterisk (*) in the scan chain report file.Default: true



dft_enable_combinational_loop_check {true | false}

When set to true , reports any combinational feedback loops in the netlist. You canuse the command check_netlist instead.Default: false

dft_enable_race_condition_check {true | false}

When set to true , calls to the command check_dft_rules issue warnings forany flip-flop with a potential race condition between its data and clock signal.Default: false

dft_scan_alphanum_ordering {true | false}

Controls whether scan connections are made between instances in alphanumericorder. When set to true , connections are made such that instances appear inascending alphanumeric order in the scan-order file. When set to false ,connections are made such that instances appear in arbitrary, netlist order in thescan-order file.Default: true

dft_scan_avoid_control_buffering {true | false}

Controls whether or not the tool buffers scan control signals.Scan control signals, such as scan-mode, tend to have high fanout. By default, thescan insertion tool buffers high fanout signals to avoid maximum signal loadingconditions. Setting this variable to true prevents buffering of the scan controlsignal. For the multiplexed flip-flop scan style, the affected scan control signal is thescan-mode signal.

trueThe tool does not buffer any scan control signals. The scan signal buffering can bedone after synthesis by an external tool.

falseThe tool buffers the scan control signals which can result in extensive buffering of



the scan mode port.Default: false

dft_scan_enable_connect { true | tieoff | floating }

Controls how scan-enable pins are connected at each register.

trueScan-enable pins are connected for normal scan operations throughout thehierarchy.tieoffScan-enable pins are connected to the off state for each scan-register (low for mostflip-flops, high for those with inverted enables).floatingScan-enable pins are not connected to anything. This value is recommended whenusing an external tool to complete the connection.Default: true

dft_scan_output_pref { non_inv | min_load }

Controls which scan register output, Q or Q-bar, is used for the scan data path.non_invSpecifies a preference for the non-inverted (Q) register output pin.min_loadSpecifies a preference for the register output pin with the smallest load. Themin_load setting may decrease the load on the system data path and so minimizethe impact of scan on the timing of the system data path. If desired, correct any scandata inversions occurring as a result of the min_load setting with the set_globaldft_allow_scan_path_inv command. The Cadence® synthesis scan insertiontool can enforce the selected setting only on scan registers that have both a Q anda Q-bar output.Default: non_inv

dft_scan_path_connect { chain | tieback | tie0 | tie1 | floating }



Controls how the scan chain is connected during a synthesis run. Therecommended use model is to use tieback mode prior to the final synthesis run toavoid timing analysis on the scan chains. For the final synthesis run, use chainmode if the tool is connecting your scan chains or use floating , tie0 , or tie1mode if an external tool is connecting your scan chains. Consult your external tooldocumentation to decide whether to use floating , tie0 , or tie1 . (For moredetails on using this variable, see the Test Synthesis for Ambit BuildGatesSynthesis and Cadence PKS.)

This global variable does not affect the scan register control connections. Forexample, scan-enable pins are always connected, regardless of the value set for thisglobal variable.chainInstructs the scan insertion tool to connect the scan registers into scan chain(s)tiebackConnects a scan register’s scan data output pin to its own scan data input pin,emulating the loading effect on the scan data output without connecting the chain,so that optimization accurately reflects the loading that will occur once the scanchain is connected.tie0Connects the scan registers’ scan data input pins to logic 0. If available, a logic 0 netor equivalent library cell is used. Otherwise a constant (1’b0 ) is used.tie1Connects the scan registers’ scan data input pins to logic 1. If available, a logic 1netor equivalent library cell is used. Otherwise a constant (1’b1 ) is used.floatingLeaves the scan registers’ scan data input and output pins unconnected.Default: chain

dft_verbosity_level integer

When integer is set to a number greater than 1 the commandcheck_dft_rules generates more detailed reports.Default: 1

dist_batch_queue name



Sets the name of the LSF batch queue to be used when dist_launch_mode is setto batch . If the value is not null, then batch queue job handling is enabled. There isno default value.

dist_bits p2

Specifies the default number of bits for all ac_shell sessions, where p2 is a powerof 2. The default setting can be overridden on a specific session using theset_dist_bits command.Default: 32 for 32-bit ac_shell and 64 for 64-bit ac_shell

dist_capture_job_histogram {true | false}

When set to true , distributed synthesis generates graph data in the GUI of theactual job distribution.Default: false

dist_default { on | user | off }

Controls whether a command runs in distributed mode.Default: user

dist_embargo_delay time

on Command runs in distributed mode, even if the-distributed option is not specified.

user Command runs in distributed mode only if the-distributed option is specified.

off No command runs in distributed mode, even if the-distributed option is specified.



Prevents jobs from launching on a host for a specific period of time when anotherjob has just been launched. This allows the host load to catch up.Default: 0:30 (30 sec.)

dist_enable_final_top_down { true | false }

If set to true , a final top-down pass of timing optimization is performed. Thistop-down optimization is performed using the do_xform_timing_correctioncommand. This can improve slack for designs with difficulty in meeting timingconstraints.Default: false

dist_granularity { medium | fine | coarse }

Sets the distributed flow granularity. For very large designs, use the coarse value.For smaller designs, fine is recommended.Default: medium

dist_kill_signal signal

Sets the signal used to kill a job. signal is the name or number of a (UNIX/POSIX)signal used to kill all local and remote job processes. Signals SIGHUP, SIGINT ,SIGQUIT, or SIGTERM are recommended.Default: SIGTERM

dist_kill_verbose { true | false }

Determines what information distributed synthesis displays when it kills a job on aremote host. When set to true , distributed synthesis displays the names of themachines on which jobs are currently running, the pid, and host name information.



When set to false , distributed synthesis does not display this information.Default: false

dist_launch_delay time

Sets the maximum delay time between checking for ready jobs. The masterac_shell waits for a this amount of time before launching more jobs. At intervals,it also reports a list of currently running jobs, also see dist_summary_delay.Default: 5:00 (5 min .)

dist_launch_mode { batch | host_list }

Sets the launch mode for remote jobs to batch or host_list . Batch mode usesLSF to run remote jobs, whereas host list mode uses built-in load balancing.Default: host_list

dist_launch_timeout time

Sets the launch idle time-out period. If the master ac_shell cannot launch anyremote jobs within this time period (since the last job was launched), the distributedcommand stops.Default: 30:00 (30 min .)

dist_max_failures integer

Specifies the limit for the number of recoverable errors allowed prior to or during ajob run. When the failure limit is met, the job is rerun, provided the number of retrieshas not yet been exceeded.Default: 2

dist_max_jobs integer



Specifies the maximum number of jobs that can run at one time by a remoteac_shell . At least one job must be running.Default: 4

dist_max_load percent

Jobs are not launched on hosts with a CPU utilization that exceeds this value. Notethat the load on multi-CPU hosts is normalized to a single CPU, as follows:

If the load of a 2 CPU host is 50%, that means that one CPU is busy and the otheris idle. The normalized load in this case is 0% to indicate that one CPU is idle.Default: 15%

dist_max_restarts n

Limits the number of times jobs can be restarted. A value of zero indicates thenumber of restarts is unlimited. If the number of restarts is exceeded, the job will notrun and an error is returned.Default: 0

dist_min_cpus integer

Specifies the minimum number of CPUs that must be accessible to run distributedsynthesis. If the minimum requirement is not met, the -distributed option isignored.Default: 2

dist_min_jobs integer

Specifies the minimum number of jobs that can run in distributed mode. If the widthof the design hierarchy is less than this value, the optimization command is not runin distributed mode. If set to less than 2, the tool issues a warning and prevents the



command from running in distributed mode.Default: 2

dist_nice integer

Specifies the (UNIX/POSIX) nice value used when running remote jobs. This isneeded to run remote jobs at a lower priority on a workstation or when runningremote jobs on the master host. If you set this variable to 0, distributed synthesisdoes not lower the priority of remote jobs.Default: 0

dist_remsh_timeout [ hours ]:[ minutes ]: seconds .[ milliseconds ]

Defines the time-out period for remote shell commands. The master ac_shellinvokes remote shell commands to execute a command on a remote host, forexample, to get the load of a host. Because remote hosts can be busy or off line,remote shell commands are invoked with a time-out option to prevent hanging themaster ac_shell . The command get_global dist_remsh_timeout returnsthe time-out period in the hour:minute:second.millisecond format.Default: 2.0 seconds. On busy networks, a larger value may be appropriate (3 to 4seconds). If a lot of time out warning messages occurs during a distributed run, youmay want to increase the value of dist_remsh_timeout .

Note: While a time-out value of zero is allowed, it is not recommended; it may cause themaster ac_shell to hang or wait indefinitely.

dist_restart_delay hh:mm:ss

Specify the time period to delay the restart of a job stopped by thedist_restart_signal global.Default: 00:00:00

dist_restart_embargo hh:mm:ss



Specify the time period to wait before allowing a host to run another job after a jobwas killed on it. Effectively, this variable takes a host off-line for the time periodspecified.Default: 00:00:00

dist_restart_signal {NULL | QUIT | HUP | TERM | USR1 | USR2}

Allows the master ac_shell to kill a job running on a remote machine. The killrequest can be input one of three way: using the distributed synthesis restartscript , with the kill command from the Unix shell, or with the bkill commandif running in batch mode. For more information on the restart script , refer toRestart Script in the Distributed Processing of Ambit BuildGates Synthesis.

The signals QUIT, HUP, TERM, USR1, and USR2 are "catachable," whichenables the an orderly exit of the remote job. The master ac_shell will reschedulethe killed jobs either on the same or different host.Default: NULL (no restart allowed)

dist_retries integer

Specifies the maximum number of times that distributed synthesis can try to run ajob after the initial job run failed.Default: 2

dist_shutoff time

Sets the shutoff time-out period for a remote job. If a remote job does not finish inthe time-out period, after the final heartbeat has been received by the masterac_shell the remote job is killed. Setting the value to 0.0 turns off this option.Default: 5:00 (5 min .)

dist_startup time



Sets a startup time-out period for a remote job. A remote job should start to run andsend the first heartbeat to the master ac_shell within this time-out period. If a jobdoes not start within this period, it is considered to have failed. The startup time-outperiod starts when the job is launched. Setting the value to 0.0 turns off this option.Default: 0:00

dist_std_file filename

Specifies the name of the remote job log file, which contains the log of the remoteac_shell and additional information, such as the LSF log, when batch mode isused. The name of the log file is unique and contains the job identifier, the name ofthe master host, and the process indentifier on the master ac_shell .Default: .job< job_id> . <mhost> .< mpid> .std

dist_stop_after_mapping { true | false }

When set to true , optimization stops after the mapping phase, and no timingoptimization is done.Default: false

dist_summary_delay time

Sets the time interval between printing summary reports on currently running jobsby the master ac_shell .Default: 0:30 (30 sec.)

dist_timeout time

Sets a time-out for the run time of a remote job. If the run time of a job exceeds thetime-out period, the master ac_shell kills the job and reruns it on another host.The run time of a job starts when the master ac_shell receives the first heartbeat.



Setting the value to 0.0 turns off this option.Default: 0:00

dist_uniquify { early | late | none }

Controls the point at which uniquification occurs during optimization. When thevalue is set to early , uniquification occurs before structuring. When set to late , itoccurs after mapping. Otherwise, no uniquification occurs.Default: early

dist_verbose integer

Determines the level of detail for job messages in the master ac_shell log file. Aminimum number of job messages are provided when the default value is used. Zeromeans no reports.Default: 1

dist_weight nonnegative_integer

Sets the relative size of the job, which can determine the hosts on which the job canrun. A job can run on a host only if the weight of the host is the same or greater thanthe weight of the job. Zero indicates that the job can run on any host.Default: 0

echo_commands { true | false }

Echoes each command prior to its execution on standard output.Default: false

edifin_bus_dimension_separator_style string



Characters used in naming members of bussed ports and nets in EDIF designsbeing read in.Default:[]

edifin_bus_range_separator_style string

Characters used to separate names of bussed ports and nets in EDIF designs beingread in.Default: : (colon)

edifin_ground_instance_name string

Name of the instance that represents ground whenedifin_power_and_ground_representation is set to instance .Default: GND

edifin_ground_net_name string

Name of the ground net when edifin_power_and_ground_representationis set to net .Default: ""

edifin_ground_net_property_name string

Name of the property that nets must have to be interpreted as ground whenedifin_power_and_ground_representation is set to net . Used inconjunction with edifin_ground_net_property_value .Default: default

edifin_ground_net_property_value string



Value of the property that nets must have to be interpreted as ground whenedifin_power_and_ground_representation is set to net . Used inconjunction with edifin_ground_net_property_name .Default: logic_0

edifin_ground_port_name string

Name of the ground port when edifin_power_and_ground_representationis set to port.

Default: GND

edifin_ground_pin_name string

Name of pin of the instance that represents ground whenedifin_power_and_ground_representation is set to instance .

Default: GND

edifin_power_and_ground_representation {net | port | instance |none}

Representation of power and ground in EDIF designs being read in. Allowablevalues are none, net, port, and instance.Default: net

edifin_power_instance_name string

Name of the instance that represents power whenedifin_power_and_ground_representation is set to instance .Default: PWR



edifin_power_net_name string

Name of the power net when edifin_power_and_ground_representation isset to net .Default: ""

edifin_power_net_property_name string

Name of the property that nets must have to be interpreted as power whenedifin_power_and_ground_representation is set to net . Used inconjunction with edifin_power_net_property_value .Default: default

edifin_power_net_property_value string

Value of the property that nets must have to be interpreted as power whenedifin_power_and_ground_representation is set to net . Used inconjunction with edifin_power_net_property_name .Default: logic_1

edifin_power_pin_name string

Name of pin of the instance that represents power whenedifin_power_and_ground_representation is set to instance .Default: PWR

edifin_power_port_name string

Name of the power port when edifin_power_and_ground_representationis set to port.Default: PWR



edifout_array {true | false}

Determines whether the arrays will be represented as single.Default: true

edifout_designs_cell_name string

Name of the cellRef used in the EDIF design construct.Default: ""

edifout_designs_library_name string.

Name of the libraryRef used in the EDIF design constructDefault: ""

edifout_designs_name string

Name used in EDIF design construct.Default: ""

edifout_ground_cell_name string

Name of the cell, an instance of which represents ground whenedifout_power_and_ground_representation is set to instance .Default: GND

edifout_ground_instance_name string

Name of the instance that represents ground whenedifout_power_and_ground_representation is set to instance.Default: GND



edifout_ground_net_name string

Name of the ground net when edifout_power_and_ground_representationis set to net .Default: ""

edifout_ground_net_property_name string

Name of the ground net when edifout_power_and_ground_representationis set to net .Default: ""

edifout_ground_net_property_value string

Value of the property that nets must have to be interpreted as ground whenedifout_power_and_ground_representation is set to net . Used inconjunction with edifout_ground_property_name .Default: logic_0

edifout_ground_pin_name string

Name of pin of the instance that represents ground whenedifout_power_and_ground_representation is set to instance.Default: GND

edifout_ground_port_name string

Name of the ground port whenedifout_power_and_ground_representation is set to port .Default: GND



edifout_power_and_ground_representation {net | port | instance |none}

Representation of power and ground in EDIF designs being written out. Allowablevalues are none , net , port , and instance .Default: net

edifout_power_cell_name string

Name of the cell, an instance of which represents power whenedifout_power_and_ground_representation is set to instance .Default: PWR

edifout_power_instance_name string

Name of the instance that represents power whenedifout_power_and_ground_representation is set to instance .Default: PWR

edifout_power_net_name string

Name of the power net when edifout_power_and_ground_representationis set to net .Default: ""

edifout_power_net_property_name string

Name of the property that nets must have to be interpreted as power whenedifout_power_and_ground_representation is set to net . Used inconjunction with edifout_power_property_value .Default: default

edifout_power_net_property_value string



Value of the property that nets must have to be interpreted as power whenedifout_power_and_ground_representation is set to net . Used inconjunction with edifout_power_property_name .Default: logic_1

edifout_power_pin_name string

Name of pin of the instance that represents power whenedifout_power_and_ground_representation is set to instance .Default: PWR

edifout_power_port_name string

Name of the power port when edifout_power_and_ground_representationis set to port .Default: PWR

edifout_properties {true | false}

Determines whether the properties associated with netlist objects will be written outor not.Default: false

enable_pinswap {true | false}

Enables or disables the pin-swapping algorithm.Default: true

estimate_supply_rail_congestion {true | false}

This variable applies only to designs without rails; it has no effect on designs withrails. When an optimization command is running, true estimates congestion as ifthe rails are present; false prevents estimation of rails during congestion analysis.



(PKS specific)Default = true

extra_space_for_opt percentage

This is the amount by which optimization may overfill a bin. It is expressed as apercentage. (PKS specific)Default: 0

failsafe {true | false}

In case of a system crash, ac_shell has the ability to save the synthesis databasegenerated up to that point. If failsafe mode is not set to true, the database mustbe regenerated by running the commands of the previous session again.Default: false

fanout_load_limit float

Specifies the default fanout load limit used for design rule fixing. The units for fanoutare a function of the default_fanout_load unit specified in the library (usually= 1).Default: no limit — infinite

This variable has been replaced with the variable max_fanout_load_limit .

favor_feedback_cells {true | false}

If set to true , will always prefer mapping to registers with enable input, regardlessof cost, instead of mapping to registers without enable, resulting in the output of theregister feeding back to a MUX in front of the data input of the register. Mapping to



such registers with enable inputs, may adversely impact timing.Default: false

fix_multiport_nets {true | false}

The command is run automatically as part of do_optimize if the variable is set.Default: false

hdl_common_subexpression_elimination {true | false}

Determines whether common sub-expression elimination should be performed onHDL operators before generating the generic netlist. The HDL operators consideredinclude arithmetic operators (for example, +, - , * , abs ), shift operators (for example,<<, >>), relational operators (for example, >,>, =), and user-defined operators.Default: true

hdl_cse_for_registers {true | false}

When set to true and hdl_common_subexpression_elimination is set totrue , registers are also considered for elimination.Default: false

hdl_error_on_latch { true | false }

When set to true , an error is issued if a latch is inferred for a design.Default: false

hdl_extract_pla {true | false}

When set to false , prevents the automatic extraction of PLAs for constant casestatements when do_build_generic is run. For large, non-parallel casex or



casez statements, preventing extraction can reduce run times.Default: true

hdl_ff_auto_sync_set_reset { true | false }

When this argument is set to true, the do_build_generic command usessynchronous set and reset pins, rather than data input pins, to implement allsynchronous set and reset operations for flip-flops.Default: false

hdl_latch_auto_async_set_reset { true | false }

When this argument is set to true, the do_build_generic command usesasynchronous set and reset pins, rather than data input pins, to implement allasynchronous set and reset operations for latches.Default: false

hdl_max_loop_limit integer

Determines the maximum number of iterations for unfolding a loop construct of anytype. If the limit is exceeded an error is issued.Default: 1000

hdl_max_recursion_limit integer

Sets the maximum number of elaborations for recursive instantiations to preventpossible infinite recursions.Default: 1000

hdl_preserve_unused_registers { true | false }



When set to true , the software not remove unused registers (latches and flip-flops)that do not, directly or indirectly, affect any outputs. This can be used, for example,to keep registers inserted for the only purpose of observing internal nets throughscan chains in test mode.Default: false

hdl_undriven_net_value { 0 | 1 | x | z | none}

Undriven nets are connected to the given value. If set to none the undriven nets areleft unconnected.Default: 0

hdl_verilog_out_columns integer

Specify the maximum line length for writing out Verilog netlist in files. Can beoverridden by global hdl_write_multi_line_port_maps .Default: 80

hdl_verilog_out_compact { true | false }

Choose whether to write out compact files for Verilog netlist output. The compactfiles have multiple statements on one line. It may not be very readable. If this variableis set to false , only one statement is written per line.Default: true

hdl_verilog_out_declare_implicit_wires { true | false }

Implicit wires in Verilog do not require a declaration. If set to true the declarationsfor implicit wires are also written.Default: false



hdl_verilog_out_prim { true | false }

When set to true, primitive Verilog operators are written instead of the ATLequivalent componentsDefault: true

hdl_verilog_out_source_track { true | false }

Keep track of the source code (RTL). In various reports, the tool attempts to identifythe sections of code which caused particular effects on the design.Default: false

hdl_verilog_out_unconnected_style { none | partial | full }

Selects the netlisting style for unconnected instance pins.Default: none

hdl_verilog_out_use_supply { true | false }

Choose whether constant signals (1 or 0) be declared as supply signals (supply1or supply0 ). If this variable is set to true , the generated Verilog code will containsupply declarations. If it is set to false then the literal constants 1’b1 and 1’b0are used for connection to power and ground.Default: false

hdl_verilog_vpp_arg string

full C i0 (.UNUSED(UNCONNECTED_3));

partial C i0 (.UNUSED());

none COMP i0 ();



Passes arguments to VPP (Verilog pre-processor). The typical argument passed isthe search path. For example, if this variable is set to -I/home/rtl , ac_shellwould search for Verilog files in /home/rtl . More than one option may be specifiedto this variable by creating one string with all the options to be used. The optionswithin the string must be separated by one or more spaces. Valid options are:

Note: hdl_verilog_vpp_arg replaces vpp_arg .

hdl_vhdl_case { lower | upper | original }

This global causes the VHDL analyzer to store VHDL identifiers and operators inlower case, upper case, or the case given in the source file.Default: original

hdl_vhdl_environment { standard | synopsys| common | synergy}

Specifies the selection of the predefined arithmetic libraries.Default: standard

hdl_vhdl_lrm_compliance { true | false }

When set to true , read_vhdl enforces a more strict interpretation of the VHDLLRM. This variable allows you verify that your VHDL code is compliant with the LRM,such that it is likely to work on other VHDL tools.Default: false

-Idirectory_path specify directory path

-Dmacro=value equivalent to define macro value

-Dmacro equivalent to define macro



The following features are disallowed when set to true , but allowed when set tofalse :

hdl_vhdl_preferred_architecture name

This global sets the name of preferred architecture to use with an entity when thereare multiple architectures.Default: ""

hdl_vhdl_read_version { 1987 | 1993 }

This global specifies the VHDL version to be used when reading VHDL designs. Ifyou change the hdl_vhdl_read_version read version at any time, the softwareautomatically re-maps the IEEE and STD VHDL libraries to the correct directory inthe software release. In this way they pick up the correct versions of standardpackages in these libraries.Default: 1993

hdl_vhdl_reuse_units { true | false }

Treatment of a concatenation as a locally static expression.This allows constructs such as the following:

case expr iswhen "001" & ’1’ => ...

A name X can be used in the definition of a different X:

constant c : integer := 3;function f (c : integer := c) is ...

In VHDL-1987, a function call with globally static arguments istreated as a globally static expression. For instance:

function f(x : integer) return integer;...generic (y : integer := f(3));

Initialization of interface object with function call.



This global specifies whether do_build_generic should load all the analyzedunits from a previous ac_shell session for the defined VHDL libraries.Default: false

hdl_vhdl_write_architecture {true | false}

Specifies whether to write VHDL architectures when write_vhdl is called.Default: true

hdl_vhdl_write_architecture_name string

Sets the name for architectures for all the modules during the VHDL netlistgeneration.Default: netlist

hdl_vhdl_write_bit_type { std_logic | std_ulogic }

Specifies whether the netlist contains std_logic /std_logic_vector ports orstd_ulogic /std_ulogic_vector ports.Default: std_logic

hdl_vhdl_write_components { true | false }

Determines whether any component declarations for technology cells will be writtenout during VHDL netlisting.Default: true

hdl_vhdl_write_entity {true | false}



Specifies whether to write VHDL entities when write_vhdl is called.Default: true

hdl_vhdl_write_entity_name string

Sets the name for entity representing the current module during VHDL netlisting. Forhierarchical designs, this variable only affects the name of the current top-levelmodule, all descendant modules use their own names. If set to the empty string ("" ),the current module name is used as the entity name.Default: ""

hdl_vhdl_write_packages lib1.pack_x ...

Specifies the list of library and package pairs for which the VHDL netlister will writeout library and use clauses before each module that is written out.Default: ieee.std_logic_1164

hdl_vhdl_write_version { 1987 | 1993 }

This global specifies the VHDL version to be used for writing out VHDL netlists.Default: 1993

hdl_write_gnd_name string

Specifies a name to be used for ground net in the netlist.Default: AMBIT_GND

hdl_write_multi_line_port_maps { true | false }

When set to true , a port map can span over more than one line. If set to false , aport map will always be written on one line, ignoring the



hdl_verilog_out_columns limit.Default: true

hdl_write_vdd_name string

Specifies a name to be used for VDD net in the netlist.Default: AMBIT_VDD

hierarchy_divider character

When the design hierarchy is dissolved, the convention for naming new designobjects can be set to any single ASCII character using the hierarchy_dividervariable. It is used as a separator in composing a new name from the hierarchicalname. In Tcl, the separator needs to be a single character so that it can berepresented multiple ways. For example, c is the hierarchy divider character you canhave "c" , c , or {c} .Default: _ (underbar)

ignore_net_area_cost { true | false }

When set to true , net_area_cost is not included in cost functioning during theoptimization.Default: false

instance_generator string

Choose a scheme for naming automatically generated instances. Use of %dindicates sequentially incrementing counter, starting with 0.Default: i_%d

ipl_pin_limit integer



For nets with a fanout less than this global, the timing driven incremental placementmodels each fanout explicitly (PKS specific).

For larger nets, it models only the worst slack pin while calculating instancelocations.Default: 10

large_fanout_size size

During PKS optimization, this global controls the number of fanouts at and beyondwhich a net is considered to have large fanouts. The default is 200, which is thesame number at and beyond which the do_place command considers a net tohave large fanouts that are ignored during placement.

During pre-placement optimization, nets whose number of fanouts are greater thanor equal to large_fanout_size are ignored during DRV fixing. However, if thereare timing violations on these nets, the optimizer attempts to fix them.

After placement, these large_fanout_size nets are buffered with a fast physicalbuffer tree algorithm similar to CTPKS. For any such net that this physical buffer treealgorithm failed to buffer, one of the following actions is performed:

❑ If the net has number of fanouts greater than or equal to 1000, it is marked as alarge-fanout net and is ignored for subsequent DRV fixing or DRV calculations andthe optimizer attempts to fix timing violations.

❑ If the net has number of fanouts less than 1000, it is buffered by the regular DRVfixing algorithm, considering only reducing the number of fanouts (withoutcalculating and trying to fix other DRVs) until this number gets belowlarge_fanout_size .Default: 200

lib_build_asynch_arc { true | false }

When this variable is enabled, delay arcs from set/reset pins to output pins ofsequential library cells are created. Controls the creation of preset/clear to output



arcs on sequential cells in the library. By default, such arcs are not created.Default: false

lib_build_timing_cond_default_arc {true | false}

Controls the creation of the default timing arc. When set to true , the default timingarc is created from the default timing arc delays specified in the library. The defaulttiming arc does not have the WHEN condition. When set to false , the default timingarc from the library is disabled.Default: true

line_length integer

The line length for the messages and reports generated by ac_shell . This variabledoes not control the length of lines for netlist generation. See global variablehdl_verilog_out_columns .Default: 80

logfile filename

Sets the name of the log file. If filename can be opened for writing, then thecurrent log file is closed and filename used. Otherwise the current file is used.Default: ac_shell.log

make_routable_max_over_congestion percentage

While adjusting the placement for routability, this is the maximum amount by whichany bin may be over-utilized and still consider the placement acceptable. Expressedas a percentage. (A value of 10 means that a bin can be 110% utilized.) PKS



specific.Default: 10%

make_routable_max_size percentage

While adjusting the placement for routability, this is the maximum number of binsthat may be over-utilized and still consider the placement acceptable. Expressed asa percentage of the total design area (PKS specific).Default: 6%

make_routable_over_congestion_rate percentage

While adjusting the placement for routability, this is the maximum amount by whichany bin may be routing congested and still consider the placement acceptable.Expressed as a percentage. (A value of 10 means that up to 110% of a bin’s routingresources may be consumed.) PKS specific.Default: 15%

make_routable_oversize_rate percentage

While adjusting the placement for routability, this is the maximum number of binsthat may be congested and still consider the placement acceptable. Expressed as apercentage of the total design area. PKS specific.Default: 10%

map_inversion_through_registers { true | false }

Choose whether ac_shell is allowed to store complementary value in the registerto perform inversions instead of connecting an inverter to the output. If set to true ,and ac_shell determines that the use of complement value of the registerimproves area, the inverter is eliminated and the complement value is stored in the



register.Default: false

map_to_multibit_registers { true | false }

If set to true, will attempt to map sets of registers driving a common bus tomultibit-register cells in the library, if doing so will give better area. Mapping tomulti-bit registers may sometimes impact timing negatively.Default: false

max_capacitance_limit float

Specify maximum capacitance limit on all cells.Default: no limit — infinite

max_fanout_load_limit float

Specifies the default fanout load limit used for design rule fixing. The units for fanoutare a function of the default_fanout_load unit specified in the library (usually= 1).Default: no limit — infinite

max_points_to_report integer

Specify how many points to include in CriticalBegin and CriticalEndpoint messages during optimization. Default number is 1 but there can be manypoints included.Default: 1

max_slew_time_limit float



Specify maximum slew limit for all cells in the library. The tool uses the worse(tighter) of the two limits set in the technology library and set by this variable.Default: no limit — infinite

message_verbosity_level { [3-9] }

Setting a high verbosity level implies that the tool gives out more messages. Hence,a message whose verbosity is less than or equal to the verbosity level of the tool willbe issued and those who have higher verbosity will be suppressed. So, whenspecifying the verbosity in the message file, use a HIGH verbosity number to implymessages which are not to be used as often, and a LOW verbosity number formessages which are more important and should be issued. Messages withverbosity set to 0, 1, 2 will always be issued and messages with verbosity set to 9will hardly ever be issued.

The following guidelines should be used to define the verbosity of a given messagein the message file:

These messages when set to 0, are always issues. So this should be used forinternal warning messages.

Default verbosity level for all messages are generated by ac_shell .Default: 7

min_capacitance_limit float

Specify minimum capacitance limit on all cells.Default: none

min_slew_time_limit float

Specify minimum slew limit for all cells in the library.Default: none

naming_style {vhdl | verilog | none}



This variable determines that the I/O of the object names will take place in eitherVHDL, Verilog, or no naming style. In effect, it reads and prints object names in thespecified naming style. The difference in the three options is the way in which theescaping of the illegal string takes place.

For example, if a user runs a Find on a net with an illegal name, say a%b (withuser ID 12345), the following result will appear:

Verilog Naming Style

find -net 12345

{\a%b\ }

VHDL Naming Style

find -net 12345

{\a%b\ }

NONE Naming Style

find -net 12345

{a%b}

Note the difference in escaping.Default: verilog

net_generator string

Choose a scheme for naming automatically generated internal nets. Use of %dindicates sequentially incrementing counter, starting with 0.Default: n_%d

no_buffer_at_integration_level { true | false }

If set to true , optimization will not insert buffers at levels of hierarchy that do notcontain any primitive cell.Default: false

no_of_groute_passes_for_cong integer



Sets the number of passes of optimization that the wroute global router performswhen using groute based congestion analysis (PKS specific). Value may be anyinteger greater than 0.Default: 2

opt_no_new_instances_at_top_level {true| false}

If set to true , optimization will not insert any new instance at the top most levelin the design hierarchy. This is similar to no_buffer_at_integration_level.Default: false

path_style_timing_constraint { true | false }

When set to true, path exceptions are prioritized so that only the adjustment fromthe path exception with the highest priority is applied. Whenpath_style_timing_constraint is set to false , only the path exceptionssupported before version 3.0 are observed, the rest are ignored. Furthermore, thereis no prioritization on overlapping path exceptions. The false option exists forbackward compatibility with releases prior to 3.0. The default in 4.0 is true . You canavoid problems by always using the default value. Path exceptions are set using theset_false_path, set_path_delay_constraint andset_cycle_addition commands.Default: true

pks_do_place_option option

where option is a quoted string of command line options supported by do_place .The default for the pks_do_place_option variable is " ".

do_place recognizes the value of pks_do_place_option as its command lineoption. Present do_place command line options take precedence should anyconflict arise (PKS specific).

Example: if the variable is set to -net_weight netA netB 5 and the commandline option is -net_weight netB netC 10 , it is equivalent to the command line



option -net_weight netA 5 -net_weight netB netC 10 without setting thevariable.

pks_snap_pin_locations {0 | 1}

Instructs the pin location generation function to snap the pin locations to the nearesttrack location when reading in the pin locations from a def or pdef, or from any otherexternal source. (PKS specific)Default: 0 (retain external pin locations)

placement_initialize_auto_pass {true | false}

This variable is used when the placement setup step in optimization does not meetthe incoming acceptance levels. If true , the acceptance criteria during theplacement setup step are set to the current values. If false , the placement setupstep will fail and optimization will stop. (PKS specific)Default: true

place_over_utilized {true | false}

If set to true , placement will continue even though the utilization is over 100%.Placement quality will be compromised and the resultant placement will not beoverlap-free. (PKS specific)Default: false

preserve_constant_flops {true | false}

If set to false, the do_xform_propagate_constants command will removeconstant flip-flops in additions to constant latches during optimization.Default: true



pvt_early_path { min | typ | max }

The command is used to associate a min , typ or max PVT (process, voltage, ortemperature) corner with early paths. These min , typ or max PVT values are allused to calculate min , typ or max delay and slew values from the library. Delaysand slews of gates and interconnects on early paths are calculated by selecting thecorresponding values from the library.Default: max

pvt_late_path { min | typ | max }

The command is used to associate a min , typ or max PVT (process, voltage, ortemperature) corner with late paths. These min , typ or max PVT values are allused to calculate min or max delay and slew values from the library. Delays andslews of gates and interconnects on late paths are calculated by selecting thecorresponding values from the library.Default: max

report_precision integer

This variable controls the number of digits appearing after the decimal point in thetiming reports; report_timing and report_cell_instance_timing .Default: 2

report_timing_format

Specify the format for report_timing . See command report_timing with-format option for details.

slew_limit float

This variable has been replaced with the variable slew_time_limit .



This variable has been replaced with the variable max_slew_time_limit .

slew_propagation_mode { worst_slew | critical_slew | fast }

Specify the mode of the delay calculation in the timing analyzer. There are threemodes of delay calculation in the timing analyzer which differ in their treatment ofslew calculation and propagation. The fast mode refers to a fast algorithm for slewpropagation which sacrifices some accuracy. The worst_slew mode refers to anaccurate delay calculation algorithm which propagates the worst of all inputs. Thecritical_slew mode refers to an accurate delay calculation algorithm whichpropagates the slew in the critical inputs. This switch does not affect the mode of thetiming analyzer during optimizations, which is always fast .Default: worst_slew

slew_time_limit float

Specify maximum slew limit for all cells in the library. The tool uses the worse(tighter) of the two limits set in the technology library and set by this variable.Default: no limit — infinite

This variable has been replaced with the variable max_slew_time_limit .

smoothen_area_gap percentage

While adjusting the placement for optimization, this is the amount of empty row areathat PKS creates in each bin. Expressed as a percentage of the bin row area. (PKSspecific)Default: 1%

smoothen_utilization_only { true | false }

If true , adjust placement during optimization to eliminate any local utilizationproblems. If false , adjust the placement to address both utilization and congestionproblems. (PKS specific)



Default: trueDefault: false

target_technology lib_x ...

Set target technology library specified by lib_x . Sets the search path for thelibrary; must be a global so that it can be reset from the shell. Multiple target librariesare allowed. The tool default values such as the units for time and capacitance usedin reports and assertions, the slew threshold definitions for specifying slew at ports,and the default operating conditions are picked up from the first library.

For the get_global command, this variable returns the current list of targetlibraries. The target technology libraries are searched in the following order:Cell Definitions: Target libraries are searched sequentially in the order provided.Cells are searched for by name. Search is terminated when a match is found. If twocells have the same name in the libraries, only the first one found is identified.k-factor Derating: For the parameters listed below, the first occurrence in thelibrary list is set as the default value.List: cell drive, cell pin, load, dcl function, mode array.

k-factor Derating — For any parameter, the following values are needed to compute theoperating conditions based on derating:

■ The corresponding k-factor (k_process_wire_cap , k_volt_wire_res , etc).

■ The base or nominal operating condition values at which the parameter wascharacterized.

■ The working operating condition values at which the design is run.

The first two bulleted values are selected from the library which contains the parameter (e.g.wireload model). The third value is selected from the library which contains the designoperating condition.

time_budget_min_size integer

Controls the hierarchical scope at which the optimization will be performed within thedo_optimize -time_budget compile. The value of the variable is the minimumnumber of cell instances which must be present at or beneath the module to becompiled. Increasing the value of this variable will force the time budgeting and



optimization to be run only at higher levels of the design hierarchy.Default: 100

time_budget_stop_before_uniquification { true | false }

Exits the do_optimize -time_budget compile loop prior to the uniquificationand top-level hierarchical compile phase when set to true, which is useful if you wishto experiment with multiple passes of do_optimize -time_budget .Default: false

timing_analysis_type {min_max | bc_wc}

Switches the timing analysis from min/max analysis to bestcase/worstcase. Fordetailed information on analysis, refer to "On and Off Chip Variation Analysis" in theTiming Analysis for Ambit BuildGates Synthesis and Cadence PKS.Default: min_max

timing_disable_bus_contention {true | false}

When set to true , disables the propagation of maximum delay along three statedisable timing arcs and minimum delay along three state enable arcs. These checksare valid only during transient bus contention.Default: false

timing_disable_floating_bus_check {true | false}

When set to true , disables propagation of minimum delay along three state disabletiming arcs and maximum delay along three state enable arcs. These checks areonly valid during floating bus conditions.Default: false



timing_disable_recovery_removal_checks {true | false}

When set to true , recovery and removal checks are disabled in the timing model.Default: false

timing_driven_cong_analysis {0 | 1}

When set to 1, enables a timing-driven global route when doing a wroute globalroute based congestion analysis (PKS specific).Default: 0 (timing driven mode is turned off)

topt_no_external_sources_at_outputs { true | false }

Enables buffering of tristate nets that drive primary output ports when set to true .Default: false

use_drive_cell_design_rules {true | false}

If set to true, design rules, such as fanout_load_limit , slew_limit andmax_capacitance_limit are picked up from the drive cells as well. By default,design rules are not picked up from the drive cells.Default: false

use_groute_based_cong_analysis {0 | 1}

When set to 0, enables a wroute global router based congestion analysis for doingthe congestion analysis. When set to 1, enables a groute-based congestionanalysis. (PKS specific.)Default: 0

use_lef_area {true | false}



When set to true , the optimization code will work on the physical library area ratherthan the default logical library.Default: false

wired_logic_resolution { and | or }

Choose a default resolution function for nets driven by multiple drivers.Default: and

write_sdf_force_calculation {true | false}

Forces the recomputation of delays during write_sdf command and writes triplets(min:typ:max ). Use this option for backward compatibility with 4.0.

Without this option write_sdf uses delays already cached in the system andwrites only values of the triplets specified by the pvt_early_path andpvt_late_path globals. This global is equivalent to using the-force_calculation option of the write_sdf command.Default: false



set_logic0

set_logic0 port_list

The set_logic0 command is used to set ports to logic 0 so that the optimization toolcan better optimize the design.

Arguments

port_listList of ports which are to be set to logic 0.

Related Information


set_logic1

Examples

➤ Set all ports with names matching rst at the beginning to logic 0 .

set_logic0 [find -port rst*]



set_logic1

set_logic1 port_list

The set_logic1 command sets ports to logic 1 so that the optimization tool can do abetter optimization of the design.

Arguments

port_listList of ports which are to be set to logic 1 .

Related Information


set_logic0

Examples

This command will set all ports with preset at the beginning of their name to logic 1.

set_logic1 [find -port preset*]



set_message_count

set_message_count [message_ID | { error | warning | info | info_msg }] integer

The set_message_count command allows you to reset the specified message_ID to thevalue of integer . Or, you may reset the count of the type of message (error, warning, info,or info_msg) to integer . Note: If integer is not specified, zero is assumed.

Arguments

message_IDThe ID of the message whose count will be changed.

errorSet the count for message type error.

warningSet the count for message type warning.

infoSet the count for message type info.

info_msgSet the count for message type info_msg.

integer Count value to set the message_ID or message type. Defaultis zero.

Related Information

get_message_count


Examples

The command below resets to zero the count on the error type of messages.

set_message_count error




set_message_verbosity message_ID {on | off | 0-9}

The set_message_verbosity command controls the level of verbosity of the messagesgenerated by ac_shell in reporting information, warnings, and errors.

You can assign a new verbosity level to each message to filter the ac_shell messagesgiven out by the ac_shell . The messages displayed by the ac_shell have a message IDattached to them. These IDs are used to assign new message verbosity levels. Eachmessage has a default verbosity level assigned to it.

All fatal errors have a verbosity level of 0, 1 or 2. It is recommended that message verbositylevel be set greater than 2.

Note: If message verbosity is set to 9 then it will override all other messages.

Arguments

message_IDThe ID of the message whose verbosity level will be changed.

on | off | 0-9The verbosity level of the message. The message can be turnedon , off , or set as a number between 0 and 9. A lower numberimplies that more messages will be reported.

Related Information

set_global message_verbosity_level

Examples

➤ Turn off the warnings “# delays not supported.”

set_message_verbosity VLOGPT-035 off

➤ Turn warnings “range for parameters ignored” to verbosity 7.

set_global message_verbosity CDFG-345 7



set_port_property

set_port_property -boundary_optimization {true | false} port_list

The set_port_property command allows you to individually specify the specific port of aspecific module that you want to keep isolated from boundary optimization (constantpropagation and so forth). By default, all ports of all modules haveboundary_optimization set to true.

Arguments

-port_listCould be names or IDs of module ports.

Related Information




set_register_type

set_register_type [-exact] [-latch example_latch_cell_name ][-flip_flop example_flipflop_cell_name ] register_instance_id_list

The set_register_type command specifies the latch or flip-flop library cell type forcertain register instances in the design. A latch or flip-flop cell type is represented by anexample latch or flip-flop; any latch or flip-flop that has the same sequential characteristics asthe example latch or flip-flop is considered that type. A latch type, a flip-flop type, or both canbe specified. The subsequent technology mapping enforces mapping to register cells of thesame type for the specified register instances.

The set_register_type command is “sticky” in the sense that subsequent mapping andunmapping/remapping enforce mapping to the specified register type, unless commandreset_register_type is issued or another set_register_type command is issued onthe same register instances.

Example latch or flip-flop cells cannot be multi-bit register, even if the globalmap_to_multibit_registers is turned on.

The register type is ignored in a DFT scan flow where register instances will be mapped toappropriate scan registers based on the chosen scan style.

Arguments

-exactEnforces an exact mapping to the example latch or flip-flop cell.

-latchEnforces mapping to latch cells of the same type as the examplelatch.

-flip_flopEnforces mapping to flip-flop cells of the same type as theexample flip-flop.

register_instance_id_listList of object IDs for the register instances.

Related Information

set_global map_to_multibit_registers



reset_register_type

Examples

The command below enforces mapping to latch cells of the same type as LD1 and flip-flopcells of the same type as FD1 for all register instances in the design.

set_register_type -latch LD1 -flip_flop FD1 [find -registers *]

The command below enforces an exact mapping to FD1 for all register instances whosenames match Q_reg_*.

set_register_type -exact -flip_flop FD1 [find -registers Q_reg_*]



set_table_style

set_table_style -name table_name [-reverse_rows] [-major_sort integer ][-minor_sort integer ] [-max_widths list_of_integers ] [-min_widthslist_of_integers ] [-indent integer ]

The set_table_style command allows you to disable printing of specific columns andallows for specifying the minimum and maximum size of each column. It allows for reversingthe data, for controlling the left indent, and for controlling the sorting of the columns.

Arguments

-indent integerSpecifies the number of spaces to leave on the left for thatparticular table

-major_sort integerSpecifies the column to be used in the major sort. If the columnnumber is negative, it reverses the sort.

-max_widths list_of_integersSpecifies the maximum widths of each column for example, theoption {0,5,7} specifies that first column is to be zero width(deleted) and the second column is to remain and the previouslyspecified width, or the default width if a previous width was notspecified.Each column resizes itself to be between the range of themaximum and minimum widths specified for that column basedon the data in that column.

-min_widthsSpecifies the minimum column width allowed.Each column resizes itself to be between the range of themaximum and minimum widths specified for that column basedon the data in that column.

-minor_sort integerSpecifies the column to be used in the minor sort. It applies toALL rows that have the same values in the major_sort column.If the column number is negative, it reverses the sort.

-name table_nameSpecifies the table that is being controlled. Each table has one of



the following unique names.area_slack1area_slack2inferred_registersreport_area_cellreport_area_cell_hierreport_area_cell_summaryreport_area_summaryreport_case_statsreport_comb_loopreport_library_cellreport_library_headerreport_library_wireloadreport_library_operating_condtionsreport_library_wireload_selectionreport_timingreport_timing_headerreport_timing_summaryreport_timing_prologuereport_faninreport_fanoutreport_fsmreport_fsm_transitionreport_fsm_encoding

-reverse_rowsReverses the data rows. This is useful, for example, if you wantto trace back from an end point and the default report tracesforward from the end point.

Related Information

set_global line_length

Examples

➤ In the main report_library table, allow columns 1-3 (cell name, type, cell area) to bethe default size, and adjusts column 10 (the function column) to have a maximum widthof 40. Sort the table based on column 3 but when two cells have identical area, sort thetable based on column 1 (the cell name)

set_table_style -name report_library_cell -max_widths {,,,0,0,0,0,0,0,40}-major_sort 3 -minor_sort 1



➤ Disable columns 4-9 in the main report_library table:

dont_modify flag

dont_utilize flag

footprint

outputs

inputs

inouts



set_unconnected

set_unconnected port_list

The set_unconnected command sets the ports listed as unconnected. The optimizationphase will remove the logic driven by the input port and the logic driving the output port.

Arguments

port_listList of port names to disconnect from.

Related Information

set_current_module



set_vhdl_library

set_vhdl_library library_name directory_name

The set_vhdl_library command defines a logical VHDL library name and the name ofthe directory used to store the analyzed VHDL units. The following libraries are currentlypreset on starting up ac_shell :

The VHDL library WORKmust be mapped to an existing logical library. To change the mapping,use set_vhdl_library WORK library_name .

Arguments

library_nameThe logical name of the VHDL library

directory_nameThe physical path name to the directory where VHDL units arestored.

Related Information

read_vhdl

report_vhdl_library

Examples

If the VHDL source file has a library(use) clause referring to libraries other than the five listedabove, you can use this command to define those libraries, for example:

set_vhdl_library MYLIB /home/ user_name /libs/ mylib

VHDL units can be analyzed into that library by reading source VHDL files.

AMBIT install_dir /BuildGates/version/lib/tools/vhdl/1993/ambit

IEEE install_dir /BuildGates/version/lib/tools/vhdl/1993/ieee

STD install_dir /BuildGates/version/lib/tools/vhdl/1993/std

TEMP /tmp/?/TEMP

WORK TEMP



read_vhdl -library MYLIB pack.vhd

The analyzed files are sent to /home/ user_name /libs/ mylib .

It is useful to explicitly specify libraries with the set_vhdl_library command because theVHDL units (such as packages) analyzed into such a library are not deleted when you exitfrom the synthesis tool. The VHDL units can be reused in a subsequent invocation of thesynthesis tool.

If an attempt is made to analyze files into a library that has not been created with theset_vhdl_library command, a default directory for that library is created in the /tmparea (the scratch area pointed to by the environment variable AMBIT_TMP_DIR). However,such a library (and the corresponding directory) will be deleted when you exit from thesynthesis tool.

Note: Two different libraries should not be mapped to the same physical directory.



unalias

unalias name

Removes an alias created by the alias command

Arguments

nameThe name of an existing alias

Related Information

alias

Examples

See alias



write_adb

write_adb [-all] [-no_assertions] [-no_acl] [-no_cap] [-no_hierarchical] [-no_rc][-no_res] [-no_sdf] [-no_spf] filename

The write_adb command writes design data stored by ac_shell to the database in theAmbit Synthesis database (ADB) file format. By default, the ADB netlist is a hierarchical netlistof the current module and all instances inside it. In ADB format the data can be loaded quicklyto perform further synthesis or analysis of data when running ac_shell . The read_adbcommand loads data from the .adb file into the ac_shell database.

Tip

If the software terminates abnormally, an ADB recovery file is created in the /TMPfile. To use a directory other than the default /TMP, use the environment variableAMBIT_TMP_DIR. For example: setenv AMBIT_TMP_DIR ./adb_dir .

Arguments

-allDumps all of the modules in the database. The default is to dumpthe current module and the hierarchy below.

-no_aclDoes not dump ACL modules.

-no_assertionsThe assertions are not included in the ADB that is currently beingwritten out. By default the assertions are written into all ADBsand all the assertions read in are applied. When using theread_adb command, this flag causes the assertions in the ADBbeing read in to be ignored. The default behavior is to writeassertions into all ADBs and to apply all the assertions beingread in.

-no_capIf the ADB contains any wire capacitances, these values are notstored.

-no_hierarchicalWrites out only the current module.



-no_resIf the ADB contains any wire resistances, these values are notstored.

-no_rcIf the database contains any wire resistances or capacitances,these values are not stored. By default, they are stored if presentin the database.

-no_sdfIf the database contains any delay arc annotations from an SDFfile, these values are not written. By default, they are stored ifpresent in the database.

-no_spfIf Standard Parasitic Format (SPF) parasitics are present, do notstore the values. By default a reduced set of parasitic values arestored, if present in the database.

filenameName of the ADB output file.

Related Information

read_adb

write_verilog

Exampleswrite_adb -hierarchy mydesign.adb



write_edif

write_edif [-hierarchical] file_name

The write_edif command is used to write out designs in EDIF format.

Arguments

-hierarchicalIf the -hierarchical option is not specified, EDIF is onlywritten out for the current module.

file_nameThe name of the EDIF output file.

Related Information

read_verilog

set_global edifout_*

Refer to the EDIF Interface chapter in the HDL Modeling for Ambit BuildGatesSynthesis.

Examples

Assume that the current module is TOP which has the following hierarchical structure

report_hierarchyTOP(g)

MIDDLE(g)BOTTOM(g)

The following command writes out an EDIF description of all the three modules: TOP, MIDDLE,and BOTTOM

write_edif -hierarchical out.edif



write_verilog

write_verilog [-hierarchical] [-equation] verilog_file_name

This command writes out a netlist stored in the database in Verilog format. The netlist istypically generated by the do_build_generic command or do_optimize command.

If the netlist is written out after do_build_generic command it contains instances of ATLand XATL cells. For gate level verification of this netlist, the Ambit Synthesis Verilog Librarymust be used for simulation.

If the netlist is written out after you use the do_optimize command then it containsinstances of cells in the target technology library. To verify this netlist, a Verilog library of thetarget technology must be used for simulation.

Note: If you get assign statements in the output you must use the commanddo_xform_fix_multiport_nets or set_global fix_multiport_nets .

Arguments

-hierarchicalIndicates that the netlist should be written out as a hierarchicalnetlist. If this option is not used, the command writes out a netlistfor the current module and any implied hierarchy created byBuildGates Synthesis, such as ACL modules.

verilog_file_nameFile in which the Verilog netlist will be saved.

-equationCauses the verilog output to be written without reference to atl,xatl, or library cells. Instead, each combinational or tristate cellinstance is represented with an equation, and a simulation modelfor each sequential cell is written out.

Attributes

hdl_verilog_out_columns

hdl_verilog_out_compact

hdl_verilog_out_source_track



hdl_verilog_out_use_supply

Related Information

do_build_generic

do_optimize

read_verilog

write_assertions

Examples

➤ Save the hierarchical netlist in the file counter.v.net

write_verilog -hierarchy counter.v.net



write_vhdl

write_vhdl [-hierarchical] [-equation] [-no_wrap] vhdl_file_name

The write_vhdl command writes out a VHDL netlist. The resulting netlist preserves theoriginal VHDL types of the ports of the current module being written. As the internalrepresentation of the module is in terms of bits, any required wrapper functions to convertbetween the port types and the internal bit type are also generated. This enables you to do acomparison of the netlist with the original VHDL description through simulation or verification.

All of the submodules will have equivalent std_logic or std_logic_vector ports. If themodule being written did not originate from a VHDL source file, then all ports are written outin terms of equivalent std_logic ports.

Arguments

vhdl_file_nameFile to which the VHDL netlist will be written.

-hierarchicalIndicates that the netlist should be written out as a hierarchicalnetlist. If this option is not used, the command writes out a netlistfor the current module and any implied hierarchy created byBuildGates Synthesis, such as ACL modules.

-no_wrapWrites the current module with equivalent std_logic orstd_logic_vector representation (that is, do not preservethe original VHDL port types).

-equationCauses the vhdl output to be written without reference to atl, xatl,or library cells. Instead, each combinational or tristate cellinstance is represented with an equation, and a simulation modelfor each sequential cell is written out.

Related Information

set_global hdl_vhdl_write_version



Examples

Assume that you have a hierarchy of VHDL entities:

report_hierarchy

-TOP(g)

-MIDDLE(g)

-BOTTOM(g)

In the write_vhdl below, the entity TOPwill have its port types preserved while MIDDLEandBOTTOM will have std_logic ports.

set_current_module MIDDLE

MIDDLE

report_hierarchy -MIDDLE(g) -BOTTOM(g)

write_vhdl -hierarchical netlist.vhd

In the write_vhdl below, both the entities MIDDLE and BOTTOM will have std_logicports.

write_vhdl -hierarchical -no_wrap netlist.vhd



2CTPKS Commands

This chapter provides a listing of the CTPKS commands available with the Cadence®

Physically Knowledgeable Synthesis (PKS) tool. CTPKS provides clock tree synthesisfunctionality to PKS.

Note: Because CTPKS works simultaneously on the logic design and the physical design,most CTPKS commands are only relevant when given at the top level (corresponding to theentire physical design).

This chapter describes the following CTPKS commands (in functional order):

■ set_clock_tree_constraints on page 284

■ get_clock_tree_constraints on page 286

■ get_clock_tree_objects on page 287

■ set_attribute on page 289

■ do_build_clock_tree on page 294

■ do_build_physical_tree on page 297

■ report_clock_tree on page 299

■ report_clock_tree_violations on page 305

■ reset_clock_tree_constraints on page 307


Command Reference for Ambit BuildGates Synthesis and Cadence PKSCTPKS Commands

set_clock_tree_constraints

set_clock_tree_constraints [-pin list_of_pins ] [-min_delay value ] [-max_delayvalue ] [-max_skew value ] [-max_leaf_transition value ] [-max_tree_transitionvalue | -max_tree_transition value ] [-self_heat][-physical_tree]

The set_clock_tree_constraints command specifies the clock tree constraints for aspecific source (or multiple sources if more than one pin is specified).

Note that, the actual max slew for the leaf pins of the clock tree will be the smallest of themax_leaf_transition, the max_tree_transition, the global variable slew_time_limit or the limitspecified in the library.

Note that, the actual max slew for the non-leaf pins of the clock tree will be the smallest of themax_tree_transition, the global variable slew_time_limit or the limit specified in the library.

Arguments

-pin list_of_pinsSpecifies the pin of an instance or an input port as the root of theclock tree.

-min_delay valueSpecifies the minimum acceptable clock leaf pin insertion delay.

-max_delay valueSpecifies the maximum acceptable clock leaf pin insertion delay.

-max_skew valueSpecifies the maximum acceptable difference between any twoclock leaf pin insertion delay (max_skew is smaller or equal tomax_delay and min_delay).

-max_leaf_transition valueSpecifies the maximum acceptable transition time at any leaf pinof the clock tree.

-max_tree_transition valueSpecifies the maximum acceptable transition time at any pin ofthe tree, even leaf pins.

-self_heatCalculates wire self heat effects on the nets in the clock tree.Checks are made for wire self heat violations and build clock



trees that minimize or eliminate the number of wire self heatviolations.

-physical_treeSpecifies that the constraints are for thedo_build_physical_tree command for non-clock signals.

Database Impact

Clock tree constraints are saved in .adb files.

Related Information

get_clock_tree_constraints on page 286

reset_clock_tree_constraints on page 307

Examplesset_clock_tree_constraints -min_delay 0.1 -max_delay 1.0 -max_skew 0.3 -max_tree_transition 0.3 -pin [find -port clk]

set_clock_tree_constraints -self_heat -pin clock -min_delay 0.5 -max_delay 1.0-max_skew 0.4



get_clock_tree_constraints

get_clock_tree_constraints [-pin list_of_pins ][-physical_tree]

The get_clock_tree_constraints command displays the constraints on all clock treesor on a specific clock tree.

Arguments


-physical_treeSpecifies that the constraints to be reported are for thedo_build_physical_tree command for non-clock signals.

Database Impact

None

Related Information

do_build_clock_tree on page 294

do_build_physical_tree on page 297

set_clock_tree_constraints on page 284

reset_clock_tree_constraints on page 307

Examplespks_shell> get_clock_tree_constraints -pin [find -ports clk]

Info: Clock clk: min_delay 0.000000, max_delay 3.000000, max_skew 0.

100000, max_leaf_transition 0.030000 <CTPKS-111>



get_clock_tree_objects

get_clock_tree_objects [{-leaf_only|-tree_only}] [-pin list_of_pins ][-no_gated] [-buffer] [-inverter]

The get_clock_tree_objects command returns a list of objects in the form specified bythe selected argument.

Arguments

{-leaf_only|-tree_only}Returns a Tcl list of object ID’s that are part of the clock tree.Selecting leaf_only returns only leaf instances. Selectingtree_only returns only tree elements (pins, instances, andnets).

-pin list_of_pins

Returns clock tree objects from the root pins of clock treesspecified by list_of_pins . You can invoke this command onany module in the hierarchy. If given by name, the root pin shouldbe the complete path name as seen from thetop_timing_module . If given by ID, the ID should be returnedby a find command executed from the top_timing_module(see example below). If no pin is given, the pins on the clock treeconstraints that have been set will be used.

-no_gatedReturns clock tree objects seen from the root pin up to the veryfirst cells that are neither buffers nor inverters. Inputs ofcombinational cells are reported as leaves.

-buffer|-inverter

Returns a list of IDs from the library cells usable for the clocktree. Selecting buffer returns the buffer IDs. Selectinginverter returns the inverter IDs.

Database Impact

None



Related Information

None

Examplesset clock_root [find -hier -pin u1/u2/i_234/Y]

set my_list [get_clock_tree_objects -pin $clock_root]

issue_message "list of cells available for clock tree:[get_names [get_clock_tree_objects -buffer -inverter]]"



set_attributeset_attribute [ cell_id ct_dont_utilize {true|false}][ pin_id ct_no_leaf {true|false}][ object_id ct_preserve {true|false}][ object_id ct_preserve_tree {true|false}][ pin or port id ct_leaf {rising|falling}][ library cell pin id ct_leaf {rising|falling}][ pin_id ct_excluded {true|false}]

Arguments

cell_id ct_dont_utilize {true|false}Allows you to declare which cells you do not want to use inCTPKS. Selecting true tells CTPKS to ignore the cells specifiedby cell_id . Selecting false tells CTPKS to use the cellsspecified by cell_id .

pin id ct_no_leaf {true|false}Allows the tree to be considered even through a sequentialgating element which would leaf.

object_id ct_preserve {true|false}Preserves an instance in the final tree. This option is only usefulon buffers and inverters. Selecting true preserves an instance(specified by object_ids ) in the final tree. Selecting falseremoves an instance (specified by object_ids ) from the finaltree.

object_id ct_preserve_tree {true|false}Preserves a portion of the tree starting from an instance in thefinal tree. Selecting true preserves the portion of the treestarting from the instance (specified by object_id ) in the finaltree. The instance is then treated as a gating component. Asubtree is built from the output of the instance. Selecting false orany other value, removes the instance when building the clocktree.

pin or port id ct_leaf {{rising|falling} | "{rising | falling}{value | min_value max_value}"}Treats the specified instance pin (input pin or output port) as leafpins when these pins would have otherwise been internal to thetree. If a single value is associated to the edge, it is used tomodel the insertion delay of the downstream clock tree from thispin. If a pair of values are passed, the first value models the



minimum insertion delay while the second value models themaximum insertion delay of the downstream logic.

library cell pin id ct_leaf {rising|falling}Treats all instances of the specified cell pin as a leaf pin whenthis pin would have otherwise been internal to the tree. CTPKSwill not trace through this pin. Using a value other than risingor falling is treated as if no attribute was set.

pin_id ct_excluded {true|false}Prevents CTPKS from considering some input pins as leaf pinsin the generated buffer subtree. Excluded pins are connecteddirectly to the output pin at the root of the generated buffersubtree. If the pin is an output pin, the pin has to belong to agated component that has several outputs.

Database Impact

None

Related Information


do_build_physical_tree on page 297

Examplesset_attribute [find -cellref ssnid6] ct_dont_utilize true

set_attribute [find -inst i_47] ct_preserve true

set_attribute [find -inst i_47] ct_preserve_tree true

set_attribute [find -pin gated_component/A0] ct_leaf rising

set_attribute [find -pin i_273/A] ct_leaf "rising 1.27 1.35"

set_attribute [find -pin decoder/Y3] ct_excluded true

define_structure

Note: The define_structure command has been added to this chapter only forreference. This command is included with Cadence’s Clock Tree Generator tool and providessignificant information that supports several CTPKS commands mentioned in this chapter.



define_structure{

{ from_pin | from_iopin }[ drive_booster ][ noninverting_tree

[ to_rising_clock_pins ][ to_falling_clock_pins ][ to_pin ] ...

][ inverting_tree

[ to_rising_clock_pins ][ to_falling_clock_pins ][ to_pin ] ...

]} ...

Syntax of Individual Optionsfrom_pin ' component_name ' ' output_pin_name '

from_iopin ' input_iopin_name '

drive_booster ' cell_name ' [ ' cell_name ' ]

noninverting_tree [ { ' cell_name ' ... parent_fanout } ... ]

inverting_tree [ { ' cell_name ' ... parent_fanout } ... ]

to_rising_clock_pins [ { 'cell_name' ... parent_fanout } ... ]

to_falling_clock_pins [ { 'cell_name' ... parent_fanout } ... ]

to_pin ' component_name ' ' pin_name ' [ ' cell_name ' ... ]

Command Context

The define_structure command is optional for each clock tree command set(specify_tree /set_constraints command pair) you use in the constraints file.

Description

Use this command to define the clock tree structure. If you use this command, you mustdefine the structure for every subtree of the overall clock tree topology.

You cannot use both the define_cells command and the define_structure commandfor the same clock tree.

You specify the subtrees with the from_pin and from_iopin options, and you can specifythe subtrees in any order.



Each subtree specification must start with either the from_pin or the from_iopin option.These options specify the given subtree root.

The drive_booster option allows you to specify that the given subtree root should havetwo inverters or one or two buffers connected directly to it to boost its drive.

The polarity of the drive_booster must always be noninverting. Thus, you can specify onebuffer cell, two buffer cells, or two inverter cells. Specifying one inverter cell, or one buffer celland one inverter, will cause an error.

The noninverting_tree option lets you specify the noninverted subtree topology fromthe given root to the clock pin subtree, gating pins, and block pins.

The inverting_tree option lets you specify the inverted subtree topology from the givenroot to the clock pin subtree, gating pins, and block pins.

The to_rising_clock_pins option lets you specify the buffer subtree topology to rising-edge triggered clock pins (the subtree does not include gating pins or block pins).

The to_falling_clock_pins option lets you specify the buffer subtree topology to falling-edge triggered clock pins (the subtree does not include gating pins or block pins).

The to_pin option lets you specify the padding in front of a gating pin or block pin.

Note: The to_pin option can only be used to specify padding in front of input pins togating components or input pins to blocks with the TLF insertion_delay construct foran internal clock.

If you specify an inappropriate subtree topology option (for example, if you use only theinverting_tree option for a particular subtree that has only noninverted paths to clockpins), you will see an error message.

If you omit a necessary subtree topology option (for example, if the subtree has bothnoninverted and inverted paths to clock pins and you specified only thenoninverting_tree option), you will see an error message.

Arguments

component_name Specifies the component name.

output_pin_name Specifies the name of an output component pin.

input_iopin_name Specifies the name of an input I/O pin.



cell_name Specifies the cell name of a buffer or inverter.

parent_fanout Specifies the number of fanouts associated with the parent of thepreviously specified buffer or inverter.

Examples

define_structurefrom_pin 'CKPAD1' 'Z'

noninverting_tree 'CKBUF' 'CKBUF' 1 'CKBUF' 'CKBUF' 'CKBUF' 2to_rising_clock_pins 'CKBUF' 1 'CKBUF' 4 'CKBUF' 6to_pin 'CKNAND1' 'A'to_pin 'CKNAND2' 'A'to_pin 'CKNAND3' 'A'to_pin 'IPBLOCK' ' CK' ' CKBUF' ' CKBUF'

from_pin 'CKNAND1' 'Z'inverting_tree 'CKINV' 1

to_rising_clock_pins 'CKBUF' 4from_pin 'CKNAND2' 'Z'

inverting_tree 'CKINV' 1to_rising_clock_pins 'CKBUF' 4

from_pin 'CKNAND3' 'Z'inverting_tree 'CKINV' 1

to_rising_clock_pins 'CKBUF' 4

In this example, the noninverting buffer tree connected to pin CKPAD1 Z drives the CKBUFwhich is at the root of the to_rising_clock_pins tree as well as the three gating pins(CKNAND1 A, CKNAND2 A, and CKNAND3 A) and the CKBUFpadding in front of the block pin(IPBLOCK CK). The to_pin 'IPBLOCK' 'CK' 'CKBUF' 'CKBUF' statement specifiesthat two CKBUFs should be in front of the IPBLOCK CKpin to equal out delays. (The IPBLOCKhas no from_pin statement because the tree does not go through this block.)

The schematic diagram for the noninverting tree connected to CKPAD Zis as shown below.Note that the tree contains repeaters.

The first, third, and fourth levels of buffers are considered repeaters and the clock treegenerator distributes them evenly along the estimated routing path between the nonrepeatingcells.

CKPAD1

To rest of tree



do_build_clock_tree

do_build_clock_tree [-pin list_of_pins ] [-save_structure filename ][-use_structure filename ] [-noplace] [-no_gated {rising | falling}] [-power][-fast] [-move_gated]

The do_build_clock_tree command generates a clock tree using parameters that wereset by the set_clock_tree_constraints command. If no constraint is set, the commandhas no effect. This command requires that all the modules that contain a clock net areuniquified. The command will fail otherwise.

Arguments

-pin list of pinsSpecifies the pin of an instance or an input port as the root of theclock tree. Without -pin , CTPKS will run on all clock treespreviously specified with the set_clock_tree_constraintscommand.

-save_structure filenameWrites the clock tree structure to a file whose syntax is identicalto the syntax of define_structure on page 290.

-use_structure filenameLoads the clock tree structure you want to use from a file. CTPKSapplies the semi-automatic mode to this structure. If thefrom_pin or from_iopin specified in the file matches theclock pin being treated by CTPKS, the corresponding treestructure is used. The syntax is similar to the syntax ofdefine_structure on page 290.

-noplaceSpecifies that incremental Qplace will not be invoked. Someinserted buffers or inverters may be illegally placed.

-no_gated {rising | falling}Specifies that the clock tree stops at the first cells downstreamfrom the root that are neither buffer nor inverter. If the active edgeat this point is not specified, the edge given on the command lineis taken.

-powerWhen this switch is activated, the lowest consuming clock tree is



selected when design rules and timing constraints are met. Theconsumption is measured on all clock objects (buffers + leaves).Note that a low power license is required.

-fastThis switch tells the tool to do a quick job. It picks only the fastestcell from all available buffers and inverters and builds a clock treewith it. The number of internal trials is also reduced. Theresulting clock tree is, in most cases, not to be used as is.

-move_gatedSpecifies that the gating components may be moved to optimizeperformances.

Attributes

See set_attribute on page 289.

Database Impact

Buffers and/or inverters have been added. The clock propagation mode has been set topropagated.

The + USE CLOCK property is added in a DEF on all clock nets.

The +SHIELNET property is propagated to all clock nets if it it present on the subtree root net.

The NONDEFAULTRULE, layer usage table, R and C LEF multiplier information is propagatedto all clock nets if it it present on the subtree root net.

Related Information



Examplespks_shell> set_clock_tree_constraints -min_delay 0.1 -max_delay 1.0 -max_skew 0.3-max_tree_transition 0.3 -pin [find -port clk]

pks_shell> do_build_clock_tree -save_structure tc1.struct



Warning: Clock Propagation Mode is ideal <CTPKS-105>

Info: Setting clock propagation mode to propagated. <CTPKS-104>

Clock tree root clk Clock TreeConstraints Actual Area

Number of Inserted Instances 3 15.000

Max. transition time at leaf pins 0.300 0.117

Min. insertion delay to leaf pins 0.100 0.145

Max. insertion delay to leaf pins 1.000 0.206

Max. skew between leaf pins 0.300 0.061

Number of violations 0

Number of buffers 2 10.000

Number of inverters 1 5.000

Number of gated/pad/preservedinstances

0 0.000

Total number of instances 3 15.000



do_build_physical_tree

do_build_physical_tree list_of_objects [-noplace] [-fast]

The do_build_physical_tree command creates a balanced tree starting from the givenobjects specified by list of objects . All buffers and inverters in the down stream treeare removed and replaced by the new tree. The tree stops at any cell that is not a buffer or aninverter. The attributes ct_preserve , ct_leaf , ct_excluded , ct_preserve_tree ,and ct_dont_utilize are taken into account when building the tree. When there is nophysical tree constraint at root, the smallest alternative tree (respecting design rules) is kept.

Arguments

list_of_objectsNames of the objects that may include nets, input ports, andpins.

-noplaceSpecifies that incremental Qplace will not be invoked. Someinserted buffers or inverters may be illegally placed.

-fastThis switch tells the tool to do a quick job. It picks only the fastestcell from all available buffers and inverters and builds a clock treewith it. The number of internal trials is also reduced.

Attributes

See set_attribute on page 289.

Database Impact

Buffers and/or inverters have been added.

Related Information

report_clock_tree on page 299

set_attribute on page 289




Examplespks_shell> do_build_physical_tree in1

Physical tree root in1 Physical TreeConstraints Actual Area

Number of Inserted Instances 3 15.000








0 0.000




report_clock_tree

report_clock_tree [-format { list_of_columns } ] [{-depth_first_search |-breadth_first_search}] [{-increasing_latency | -decreasing_latency}][{-leaf_only | -tree_only}] [-no_gated {rising | falling}] [-physical_tree][-tcl_list] [-pin root_pin ] [{> | >> file_name }]

The report_clock_tree command generates a report that displays (in a text table) theclock tree structure from its root component to all its leaf cells. If both edges of the clock areused, the report appears in two parts; one for the rising edge and the other for the falling edge.Excluded pins always appear in both parts. Also, when a cell has insertion delay, it appearson two lines; one with the actual physical report and the other with a virtual pin in which theinsertion delay has been added to the latency.

Arguments

-format { list_of_columns }Specifies the report format (must type curly braces):

pin_name : Hierarchical pin name.

cellref : Cell type.

edge : ^ (rising) or v (falling).

latency : Delay from root pin on the considered edge.

violation : Displays one or several characters in case ofviolation:T: indicates a max transition violation on the pin.L : indicates that the latency (delay) on the pin violates theconstraint.C: indicates a maxcapacitance violation on the net connected tothe pin.F: indicates a fanout violation on the pin.S: indicates a max sink violation on the net connected to the pin.W: indicates a wire self heat violation on the net connected to thepin.

slew : Slope of signal on the considered edge.

predecessor_pin : Hierarchical pin name preceeding.

level : Number of cells in the tree from the root.



increment : Delay from predecessor pin.

x_y : X and Y location of the pin.

fanout : Number of successor in the tree (with betweenbrackets the number of leaf pins: 10(6L) ).

load : Total capacitance on the net.

-depth_first_search

Generates a report that displays the pins in the order in whichthey are found by going as far in the tree as possible. Leaf pinsconnected to the same branch appear together.

-breadth_first_search

Generates a report that displays the pins by level order (from theroot). Pins (leaf or not) of the same level appear together.

{-increasing_latency | -decreasing_latency}

Specifies the order in which the pins should appear whendepth_first_search or breadth_first_search do notfully determine it. The input and ouput of a cell always appear ontwo consecutive lines, only output latency is considered forordering.

-leaf_only

Generates a report that will not display intermediate cells(buffers, inverters, and gating cells).

-tree_only

Generates a report that will not display leaf cells (flip-flops). Thefanout column should be used to see the number of leaf cells.

-no_gated {rising | falling}

Generates a report that will consider each input (of non bufferand non inverter cell) as a leaf pin. If no edge is specified, eachpin of the tree is shown in both the rising edge and falling edge



section unless the active edge can be derived for the timingmodel. If an edge is specified, it is used as an active edge for thepins whose active edge can not be derived from the timingmodel. If clock tree constraints exist on the root pin, the reportwill display constraints and flag violations in the violation column.

-physical_treeGenerates a report that will consider each input (of non bufferand non inverter cell) as a leaf pin. Each pin of the tree is shownin both the rising edge and falling edge section. This switch isused in conjunction with the do_build_physical_treecommand or in order to detect a gated clock. If physical treeconstraints exist on the root pin, the report will display constraintsand flag violations in the violation column.

-tcl_list

Generates a report (Tcl list) that can be used by another Tclscript.

-pin root_pin

Specifies the root pin of the clock tree to display.

{> | >> file_name}

Specifies file redirection.

Database Impact

None

Related Information

None



Examplespks_shell> report_clock_tree

Report report_clock_tree Options

Module tc1

Timing LATE

Slew Propagation FAST

Operating Condition slow

PVT Mode worst_case

Tree Type balanced

Process 1.00

Voltage 2.25

Temperature 125.00

time unit 1.00 ns

capacitance unit 1.00 pF

resistance unit 1.00 kOhm










0 0.000




pin rising

clk edge

pin_name cellref edge latency slew violation level fanout

clk ^ 0.00 0.00 0 1

i_43/A INVX8 ^ 0.00 0.00 1

i_43/Y INVX8 v 0.06 0.07 1 1

i_44/A INVX8 v 0.06 0.07 2

i_44/Y INVX8 ^ 0.14 0.12 2 3(2L)

i_1330/A INVX8 ^ 0.15 0.12 3

i_1330/Y INVX8 v 0.21 0.03 3 2(2L)

dffn_bi/CKN DFFNX1

v 0.21 0.03 4

dff_bb/CK DFFX1 ^ 0.14 0.12 3

pin falling

clk edge




pin_name cellref edge latency slew violation level fanout

clk v 0.00 0.00 0 1

i_43/A INVX8 v 0.00 0.00 1

i_43/Y INVX8 ^ 0.05 0.09 1 1

i_44/A INVX8 ^ 0.05 0.09 2

i_44/Y INVX8 v 0.14 0.10 2 3(2L)

i_1330/A INVX8 v 0.15 0.10 3

i_1330/Y INVX8 ^ 0.20 0.04 3 2(2L)

dff_bi/CK DFFX1 ^ 0.20 0.04 4

dffn_bb/CKN DFFNX1

v 0.15 0.10 3



report_clock_tree_violations

report_clock_tree_violations [-pin list_of_pins ] [-no_gated {rising | falling}]

The report_clock_tree_violations command generates a report that provides anexhaustive list of clock tree violations.

Arguments

-pin list_of_pinsSpecifies the pin of an instance or an input port as the root of theclock tree. Without -pin , CTPKS will report on all clock treespreviously specified with the set_clock_tree_constraintscommand.

-no_gated {rising | falling}Generates a report that will consider each input (of non bufferand non inverter cell) as a leaf pin. If no edge is specified, eachleaf pin is considered as both a rising edge and a falling edge pinunless the active edge can be derived for the timing model. If anedge is specified, it is used as an active edge for the pins whoseactive edge can not be derived from the timing model. Thisswitch is used in conjunction with thedo_build_physical_tree command.

Database Impact

None

Related Information





Examplespks_shell> report_clock_tree_violations -pin clk

Clock tree clk Clock TreeConstraints Actual Area









0 0.000


Clock Tree Violations Summary Violations

No. of self heat violations 0

No. of max. clock skew violations: 0

No. of max. load capacitance violations: 0

No. of max. rise transition time violations: 0

No. of max. fall transition time violations: 0

No. of min. rise required time violations: 0

No. of min. fall required time violations: 0

No. of max. rise required time violations: 0

No. of max. fall required time violations: 0



reset_clock_tree_constraints

reset_clock_tree_constraints [-pin list_of_pins | -all] [-physical_tree]

The reset_clock_tree_constraints command removes previously set clock treeconstraints.

Arguments


-allSpecifies that all constraints are to be removed.

-physical_treeSpecifies that the constraints to be removed are for thedo_build_physical_tree command for non-clock signals.

Database Impact

Constraints are removed.

Related Information


get_clock_tree_constraints on page 286

Examplesreset_clock_tree_constraints -pin [find -port clk]

reset_clock_tree_constraints -all

reset_clock_tree_constraints -pin [find -port reset] -physical_tree





3Distributed Synthesis Commands

This chapter describes the commands and global variables used with Cadence® distributedsynthesis.

■ check_batch on page 310

■ check_dist on page 312

■ check_host on page 313

■ get_host_info on page 314

■ get_job_info on page 317

■ get_weight_batch_option on page 323

■ kill_job on page 324

■ remove_host on page 325

■ remove_job on page 326

■ report_job on page 327

■ reset_dist_bits on page 328

■ reset_dist_point on page 329

■ reset_dist_weight on page 330

■ set_dist_bits on page 331

■ set_dist_point on page 332

■ set_host_config on page 334

■ set_host_list on page 337

■ set_dist_weight on page 338

■ set_weight_batch_option on page 339


Command Reference for Ambit BuildGates Synthesis and Cadence PKSDistributed Synthesis Commands

check_batch

check_batch { queue | " "} { test_number | -all } [-debug] [-force] [-silent][-timeout time ] [-verbose] [-weight integer ]

The check_batch command checks a batch queue by running the rac_shell script indiagnostic mode.

For more information about the rac_shell script, see Appendix A, “Testing DistributedSynthesis,” of the Distributed Processing of Ambit BuildGates Synthesis manual.

Arguments

-debug Displays detailed debug information.

-force Forces rac_shell tests to run, even on hosts that areembargoed.

queue | " " Checks the LSF batch queue or the current batch queue. (Seealso the dist_batch_queue global variable.)

-silent Displays the minimum amount of information for each test.

test_number | -all Runs the specified rac_shell test or all tests.

-timeout time Specifies an optional timeout limit for each test, indays - hh : mm: ss . mmm format.

-verbose Displays detailed log information printed for each test.

-weight integer Uses the weight value to test the LSF Batch options that youhave set with the set_weight_batch_options command.You must have already used set_weight_batch_option toset the weight to integer before using this option.

Related Information

check_host

set_weight_batch_option



Examplesrac_shell batch -batch_queue queue -test n



check_dist

check_dist [-force] [-print] [-silent]

The check_dist command verifies the settings of the distributed global variables andreturns the number of errors detected. For example, if dist_max_jobs is set to 6 anddist_min_jobs is set to 8, an error is returned.

Arguments

-force Forces all of the tests to run, even on hosts that are embargoed.

-print Displays more detailed log information for each test.


Related Information

check_batch

check_host



check_host

check_host { host | -all } { test_number | -all } [-debug] [-force] [-silent][-timeout time ] [-verbose]

The check_host command checks one or all of the hosts in a host list by running therac_shell script in diagnostic mode.

For more information about the rac_shell script, see Appendix A, “Testing DistributedSynthesis,” of the Distributed Processing of Ambit BuildGates Synthesis manual.

Arguments

-debug Displays detailed debug information.

-force Forces rac_shell tests to run, even on hosts that areembargoed.

host | -all Checks host or all of the hosts that are currently in the host list.


test_number | -all Runs the specified rac_shell test, or all tests.

-timeout time Sets a timeout period for each test, in days - hh : mm: ss . mmm.

-verbose Displays detailed log information for each test.

Related Information

set_host_list

Examplesrac_shell catbert -test 2



get_host_info

get_host_info { host | -all [-force] } { attribute ... }

Returns information about the hosts in your host list or LSF batch queue. You can specify oneor all hosts for which you want to return information. You can also specify one or all attributesfor those hosts.

Arguments

attribute Requests the value of the specified attribute or, if noattribute is specified, all attributes of the specified hosts. Youspecify an attribute by its name. (See below for a list ofattributes.)

-force Requests the current value of attributes that can change duringa job run. Otherwise, get_host_info returns the last knownvalue of the attribute. The -force option also forcesget_host_info to return information on embargoed hosts.

host | -all Requests information for host or for all the hosts that arecurrently in the host list.

Attributes

access Returns the access to the host. If 0 is returned, the host cannotbe accessed. This attribute is dynamic. You must use the-force option to return the current value.

cpus Returns the number of CPUs on the host.

embargo Returns on if the host cannot run jobs; returns off if the host canrun jobs. This attribute is dynamic. You must use the -forceoption to return the current value.

embargo_time Returns the temporary embargo time, inhours : minutes : seconds . If this value is nonzero, itrepresents the time period for which this host cannot run aremote job. (See also the dist_embargo_delay globalvariable.)

embargo_secs Returns the temporary embargo time, in seconds.



jobs Returns the total number of jobs that ran on the host.

load Returns the normalized load, between 0 and 100 percent. Thisattribute is dynamic. You must use the -force option to returnthe current value.

max_load Returns the maximum load allowed for the host.

memory Returns the memory size of the host, in MBytes.

name Returns the given host name.

named Returns the short name of the host.

name_domain Returns the long host name, including the domain name.

nice Returns the nice value for jobs on this host.

release Returns the version number of Envisia distributed synthesis thatyou are running.

rlogin_ok Returns the remote access permission to the host.

ruser_ok Returns the remote access permission from the master to thishost.

speed Returns the clock speed of the CPU, in MHz.

swap Returns the swap space, in MBytes.

weight Returns the weight of the host (the relative size of the jobs thatthe host can handle). The size of the jobs that the host canhandle increases as the weight increases, beginning with 1. Aweight of 0 indicates that the host can run any job. There is noupper limit on the weight of a host.

Related Information

set_host_config

set_host_list



Examples

➤ To return all attributes for a host:

get_host_info fireflyfirefly {name firefly} {namedomain firefly} {cpus 1} {embargo off} {jobs 1} {kind{SunOS sun4u}} {load 1} {load_time -28.737} {memory 512} {release v4.0} {rloginOK} {ruser OK} {speed 440} {swap 1025}

➤ To return the value of a specific attribute:

get_host_info firefly speed

➤ To return the numbers of CPUs for all hosts (a line of information is printed for each hostonly if the dist_verbose global variable is nonzero):

get_host_info -all cpus -force

The -force option updates the attribute value:

➤ To find the total number of accessible hosts:

get_host_info -all access

➤ To return the total number of CPUs that are currently running and accessible:

get_host_info -all cpus

➤ To return the recent load of all hosts:

get_host_info -all load

➤ To determine the current, actual load of all hosts, including embargoed hosts:

get_host_info -all load -force

➤ To determine the version of Envisia distributed synthesis that you are running:

get_host_info firefly releasev4.0

➤ To find out how many hosts are capable of running a job of a certain weight:

get_host_info -all weight



get_job_info

get_job_info { job_id | -last_top | -all } attribute

Returns the attribute values for a specific job, the top job, or all jobs.

Arguments

attribute Specifies the attribute whose value you want to return. (Seebelow for a list of job attributes.)

job_id | -last_top | -allReturns the attribute information for a specific job (job_id ), thetop job (-last_top ), or all jobs (-all ).

Attributes

batch Returns 1 if the job is a batch job, otherwise 0.

batch_id Returns the LSF job ID of a batch job.

batch_queue Returns the name of the LSF batch queue to which the job wassubmitted.

cells Returns the number of primitive and modifiable instances in thejob module.

child_ids Returns a list of job IDs for this job’s child jobs.

children Returns the number of child jobs.

cpu_secs Returns the CPU time for the job, in seconds.

cpu_time Returns the CPU time for the job, indays - hours : minutes : seconds .

depth Returns the level of the job in the job hierarchy, calculated fromthe top job.

done_at Returns the time at which the job completed, indays-hours : minutes : seconds .



done_at_secs Returns the time at which the job completed, in seconds.

exit_status Returns the job exit status. A value of 0 indicates that the jobfinished correctly. A non-zero value indicates that an erroroccurred.

exit_at Returns the time at which the job completed, indays-hours : minutes : seconds .

exit_at_secs Returns the time at which the job completed, in seconds.

failures Returns the number of recoverable errors in the most recentattempt to run.

family_ids Returns a list of all job IDs below a job or a top job.

height Returns the number of remote job levels below and including thisjob.

height_all Returns the number of all job levels below and including this job.

host Returns the name of the host on which the job was launched.(See also the rhost job attribute.)

instances Returns the number of modifiable instances in a job module.

job_id Returns a unique job identifier for the job. This attribute valuemust be 1 or greater.

job_secs Returns the entire job time, in seconds.

job_time Returns the entire job time, indays - hours : minutes : seconds .

launched_at Returns the moment at which the job was launched, indays - hours : minutes : seconds .

launched_at_secs Returns the moment at which the job was launched, in seconds.

listed_at Returns the time at which the job was listed to run, indays - hours : minutes : seconds .

listed_at_secs Returns the time at which the job was launched, in seconds.



kind Returns the job type: structured , mapped, bottomup , orbottomupskip .

module Returns the ID of the module to be optimized by the job, or 0 ifthe ID is not available.

most_jobs Returns the maximum number of jobs that actually ran in parallelat any time during the distributed run.

name Returns the full name of the job module.

name_truncated Returns the truncated name of the job, if it exceeds the namelimit.

name_path Returns the hierarchical path name of the job, specified by jobname.

new_at Returns the job creation time, indays - hours : minutes : seconds .

new_at_secs Returns the job creation time, in seconds.

nice Returns the nice value for the job. (See also the dist_niceglobal variable.)

ordinal Returns the order (number) of the job in the run list.

ordinal_ids Returns the list of dependent job IDs, in ascending ordinal order.

parent_id Returns the job ID of the primary parent job.

parent_ids Returns the list of all parent jobs, beginning with the primaryparent.

parents Returns the number of parent jobs.

path Returns the location of the job in the hierarchy, specified byjobid . For example, 1-12-13 .

pid Returns the process ID of the job on the local host.

queued_at Returns the moment the job was queued to batch queue, indays - hours : minutes : seconds .



queued_at_secs Returns the moment when the job was queued to the batchqueue, in seconds.

remote_ids Returns a list of all remote job IDs below the top job.

re_used Returns the module reuse count. A value of 0 indicates a uniquemodule (no module reuse).

rhost Returns the name of the remote host where the job ran.

rpid Returns the process ID of the job on the remote host.

run Returns the run number. The first retry is run number 2.

run_secs Returns the run time, in seconds. (The run time is the elapsedtime between the start and the exit time of the job.)

run_time Returns the run time, in days - hours : minutes : seconds .

shutoff Returns the shut-off timeout period, in seconds

size Returns the size of the job.

started_at Returns the launch time, indays - hours : minutes : seconds .

started_at_secs Returns the launch time, in seconds.

startup Returns the start-up timeout period, in seconds.

startup_secs Returns the startup time, indays - hours : minutes : seconds .

startup_time Returns the startup time, in seconds.

status Returns one of the following job status values: created ,listed , waiting , ready , launched , queued , starting ,running , exit , done , interrupted , killed , failure ,error , or deleted .

timeout Returns the run-time timeout period, in seconds.

top_id Returns the job ID of the top job in the distributed run.



total_cpu_secs Returns the total CPU time of the job and its dependent jobs, inseconds.

total_cpu_time Returns the total CPU time of the job and its dependent jobs, indays - hours : minutes : seconds .

total_run_secs Returns the total run time of the job and its dependents, inseconds.

total_run_time Returns the total run time of the job and its dependent jobs, indays - hours : minutes : seconds .

total_size Returns the total job size of the job and its dependents.

type Returns one of the following job types: top , remote , master , orlumped .

wait_secs Returns the total wait time before a job is launched, in seconds.

wait_time Returns the total wait time before a job is launched, indays - hours : minutes : seconds .

weight Returns the weight of the job. When the weight is greater than 0,the host must have a weight that is equal to or greater than thejob weight. There is no upper limit on the weight that you canassign to a job. When the weight is 0, the job can run on any host.

width Returns the maximum number of remote jobs that can run inparallel.

width_all Returns the maximum number of all jobs that can run in parallel.

Examples

➤ To return a list of all the jobs:

get_job_info -all

➤ To return a list of job_ids below the job specified, including the specified job_id :

get_job_info 2 family_ids

➤ To return the value of a specific attribute:

get_job_info 2 cells

➤ To return the job_ids of all top jobs:



get_job_info -all top_ids

➤ To return the job_ids of all remote jobs:

get_job_info -all remote_ids



get_weight_batch_option

get_weight_batch_option integer

The get_weight_batch_option command gets the LSF batch options associated withthe weight attribute.

Arguments

integer Specifies the weight of the host on the batch queue.

Related Information




kill_job

kill_job { job_id ... | -last_top | -all } [-force] [-hierarchical] [-signal sig ][-silent] [-verbose]

The kill_job command lets you kill all processes when a failure is detected. This commandsends a signal to a specific job, to a job and all of its children, or to all jobs. By default, thesignal SIGTERM is used, and the signal is sent only to jobs that are launched, started, orrunning.

Arguments

-force Sends a signal to all jobs for which the local or remote pid isavailable.

-hierarchical Kills all child jobs of the specified job.

job_id | -last_top | -allKills the specified job (job_id ), the most recent top job(-last_top ), or all currently running jobs (-all ).

-signal sig The name or number of a UNIX/POSIX signal used to kill all localand remote job processes. Signals SIGHUP, SIGINT , SIGQUIT,or SIGTERM are recommended, but others can be used.Note: SIGKILL and SIGSTOP are ignored.Default: SIGTERM

-silent Does not display the signals that the command sends to theremote processes. The value of the dist_kill_verboseglobal variable determines whether this is the default.

-verbose Displays all signals that the command sends to kill the remoteprocesses. The value of the dist_kill_verbose globalvariable determines whether this is the default.

Related Information

remove_job

Exampleskill_job -last_top -hierarchical -force

kill_job -all -force



remove_host

remove_host { host | -all }

The remove_host command permanently removes one, several, or all hosts from the hostlist. In removing the host from the host list, this command also removes all information aboutthat host.

Arguments

host | -all Removes the specified host or all hosts from the host list.

Related Information

set_host_list

Examplesremove_host host

remove_host -all



remove_job

remove_job { job_id | -last_top | -all } [-hierarchical]

The remove_job command permanently removes all information about the specified job. Alljob information exists only during the ac_shell run. It is lost upon exit.

Arguments

-hierarchical Removes all child jobs of the specified job.

job_id | -last_top | -allRemoves the specified job (job_id ), the most recent top job(-last_top ), or all currently running jobs (-all ).

Related Information

kill_job



report_job

report_job { job_id | -last_top | -all } [-hierarchical] [-parents]

The report_job command generates a report on one or several jobs.

Arguments

-hierarchical Generates a report on the child jobs of the specified job.

job_id | -last_top | -allGenerates a report on job_id , the most recent top job, or alljobs.

-parents Generates a report on the parent jobs of the specified job.

Related Information

get_job_info



reset_dist_bits

reset_dist_bits list_of_module_name_or_ids

The reset_dist_bits command is equivalent to set_dist_bits 0 . This is the defaultsetting and sets the distributed synthesis ac_shell to 32 bits.

Arguments

list_of_module_name_or_idsResets the -bits value or module IDs to 32 bits.

Related Information

set_dist_bits



reset_dist_point

reset_dist_point [-hier] { list_of_modules | -all}

The reset_dist_point command (formerly the reset_distribution_pointcommand) reverses the effect of a previous set_dist_point command. That is, themodules that you specify are no longer explicitly set to be distribution points; the distributedsynthesis tool determines whether they are distribution points. By default, the size of amodule determines whether it can become a distribution point.

Arguments

-hier Resets the entire hierarchy, starting from the modules specifiedin the list_of_modules .

list_of_modules | -allResets the specified module names or module IDs, or allmodules in the hierarchy, starting from the current module.

Related Information

set_dist_point



reset_dist_weight

reset_dist_weight list_of_module_names_or_ids

The reset_dist_weight command (formerly the reset_weight command) sets theweight attribute of the specified modules to 0. A module with a weight of 0 can run on anyhost.

You can set the weight of a module to indicate its size relative to other modules in your design.The higher the weight, the larger the module. When the distributed synthesis tool allocatesjobs, it compares the weight of the job to the weight that you have assigned to the hostmachines. A job is launched only on hosts whose weights are equal to or greater than theweight of the job.

Arguments

list_of_module_names_or_idsResets the specified module names or module IDs.

Related Information

set_dist_weight



set_dist_bits

set_dist_bits { non-negative_power_of_2 | list_of_module_names_or_ids }

The set_dist_bits command allows the -bits value for a distributed systhesis job to bespecified on the module in the design to either 32- or 64-bits. The -bits size of the job cannever exceed the -bits size of the master ac_shell .

Arguments

non-negative_power_of_2 | list_of_module_names_or_ids

Sets the -bits value or lists the module names or ids.

Related Information

reset_dist_bits



set_dist_point

set_dist_point { on | off | auto } [-hier] list_of_modules

The set_distribution_point command (formerly the set_distribution_pointcommand) the controls whether a module, either in a list of modules or within the hierarchyof a listed modules, can become a distribution point. The list of modules can include modulenames or modules IDs.

By default, the size of a module determines whether it can become a distribution point.

Important

It is good practice to call reset_distribution_point for the modules that youwant to set, before you call set_distribution_point . That way, you can besure that you do not define conflicting distribution points for those modules.

Arguments

-hier Marks the entire hierarchy, starting from the modules specified inthe list_of_modules .

list_of_modules The module names or module IDs to set.

on | off | auto Determines whether a module can be a distribution point, asfollows:

Related Information

reset_dist_point

Examples

➤ Mark only the specified modules as distribution points:

on Sets the module as a distribution point, no matterwhat its size.

off Sets the module to not be a distribution point, nomatter what its size.

auto Sets the module as a distribution point, accordingto its size.



reset_dist_point -hier [get_current_module]

set_dist_point on [get_current_module]

➤ Mark some modules and the entire hierarchy below those modules as distribution points.Allow the tool to mark the distribution points for the remaining parts of the hierarchybased on size.

reset_dist_point -hier list_of_module_names_or_IDs

set_dist_point on same_list_of_module_names_or_IDs

➤ Mark some modules as distribution points and send those modules to go out as remotejobs. Allow the tool to mark distribution points based on size for the remaining parts ofhierarchy. For example, if a child module is large enough to go out as separate job, itshould do that, even if its parent (or some other ancestor) is marked as distribution point.

reset_dist_point -hier list_of_module_names

set_dist_point on list_of_module_names



set_host_config

set_host_config { host ... | -all } { attribute ... | -auto [-force] }

Configures the host machine by modifying the individual attributes of the host. Theconfiguration of a host is defined by a list of attributes. One or all hosts can be configuredautomatically.

Use get_host_info to query the host status and check the values of the attributes for ahost.

Arguments

attribute Configures the specified host attribute . (See below for adescription of the host attributes.)

-auto Configures the critical host attributes automatically: cpus ,embargo , and rlogin_ok .

-force Launches a remote ac_shell on the specified host, even if thehost is embargoed or overloaded. Use the -force option withthe -auto option. If the -force option is not used, only lightlyloaded hosts and hosts which have not been embargoed areconfigured.

host | -all Configures a specific host or all hosts currently in the host list.The host must be present in the current host list. (See alsoset_host_list .)

Attributes

cpus integer Specifies the number of CPUs on the host.Default: 1

Important

The cpus attribute must be set for correct distributed operation.

embargo { on | off } When set to on , prevents remote jobs from running on the host.

kind string Specifies the machine type.Default: The result from the csh command uname -srpi .



max_load percent Specifies the maximum load allowed on the host. (See also thedist_max_load global variable.)

memory MBytes Specifies the memory size of the host, in MBytes.

name_domain name Specifies the full host name, including the domain name. Forexample, ra.Cadence.com .

nice integer Specifies the nice value for remote jobs on the host. It must bea non-negative value. (See also the dist_nice global variable.)

rlogin_ok { ok | no | unknown }Sets the permissions for remote access to the host. This attributemust be set for correct distributed operation.

ruser_ok { ok | no | unknown }Sets the permission for access to the host from the master host.This attribute must be set for correct distributed operation.

speed MHz Specifies the CPU speed, in MHz.

swap MBytes Specifies the swap space, in MBytes

user name Specifies your account name on this host.

weight integer Specifies the weight of the host (the relative size of the jobs thatthe host can handle). The size of the jobs that the host canhandle increases as the weight increases, beginning with 1. Aweight of 0 indicates that the host can run any job. There is noupper limit on the weight of a host.

Related Information

get_host_info

Examples

➤ To set the number of CPUs of a host:

set_host_config firefly cpus 2

➤ To remove an embargo on a host:

set_host_config firefly embargo off



➤ To remove the embargo on all hosts:

set_host_config -all embargo off

➤ To retrieve the critical configuration attributes (cpus , rloginok and ruserok ) for thehost:

set_host_config firefly -auto timeout

An ac_shell is launched on the specified host. The timeout limits the total run timeof the automatic configuration; 0 means no timeout. The default is 2:00 (2 minutes).

➤ To launch a remote ac_shell on all hosts to retrieve the critical configuration attributes:

set_host_config -all -auto timeout

timeout is an optional run-time timeout value for each remote ac_shell . The default is2:00 (2 minutes).

➤ To set the embargo switch for all hosts to on :

set_host_config -all -embargo on



set_host_list

set_host_list host ...

The set_host_list command adds one or more hosts to the existing host list.

Arguments

host Specifies the name of the host to add to the host list.

Related Information

check_host



set_dist_weight

set_dist_weight integer list_of_module_names_or_ids

The set_dist_weight command sets the weight attribute of the specified modules. Youcan set the weight of a module to indicate its relative size. The higher the weight, the largerthe module.

When the distributed synthesis tool allocates jobs, it compares the weight of the job to theweight of the host machines. A job is launched only on a host whose weights is equal to orgreater than the weight of the job.

When you set the weight of a module to 0, it can run on any host.

Arguments

integer Specifies the weight of the module.

list_of_module_names_or_idsSpecifies one or more module names or module IDs whoseweight you want to set.

Related Information

set_host_config


reset_dist_weight




set_weight_batch_option integer any_LSF_bsub_option_string

The set_weight_batch_option command sets the LSF Batch options based on theweight attribute.

Arguments

integer Specifies the weight of the host on the batch queue

any_LSF_bsub_option_stringSpecifies the LSF Batch options whose weight attribute you wantto set.

Related Information

get_weight_batch_option


Command Reference for Ambit BuildGates Synthesis and CadencePKS

4PKS Commands

This chapter provides a listing of the Cadence® physically knowledgeable synthesis (PKS)commands available with the PKS tool.

This chapter describes the following PKS commands:

■ check_design on page 344

■ check_libraries_and_design_compatibility on page 345

■ check_library on page 346

■ create_blockage on page 348

■ create_placement_area on page 350

■ delete_blockage on page 352

■ do_extract_route_parasitics on page 353

■ do_generate_estcap on page 354

■ do_initialize_floorplan on page 355

■ do_place on page 356

■ do_placement_spread on page 361

■ do_reset_floorplan on page 362

■ do_route on page 363

■ do_snap_instance_to_row on page 369

■ do_xform_tcorr_eco on page 370

■ generate_supply_rails_on_rows on page 372

■ get_cluster_names on page 373

■ get_current_congestion on page 374



■ get_current_utilization on page 375

■ get_library_layer_capacitance on page 376

■ get_library_layer_offset on page 377

■ get_library_layer_resistance on page 378

■ get_library_layer_usage on page 379

■ get_logic_0_net on page 380

■ get_logic_1_net on page 381

■ get_min_porosity_for_over_block_routing on page 382

■ get_min_wire_length on page 383

■ get_physical_info on page 384

■ get_pin_location on page 385

■ get_route_availability on page 386

■ get_special_netpins on page 387

■ get_steiner_capacitance on page 388

■ get_steiner_channel_width on page 389

■ get_steiner_length on page 390

■ get_steiner_resistance on page 391

■ read_def on page 392

■ read_layer_usages on page 394

■ read_lef on page 395

■ read_lef_update on page 396

■ read_pdef on page 397

■ remove_placement_area on page 399

■ remove_supply_rails_on_rows on page 400

■ report_block_halo on page 401

■ report_floorplan_parameters on page 402

■ report_placement_area on page 404



■ report_preroute_parameters on page 405

■ report_supply_rails_on_rows on page 406

■ reset_dont_move on page 407

■ set_block_halo on page 408

■ set_dont_move on page 409

■ set_floorplan_parameters on page 410

■ set_layer_usages_table on page 413

■ set_lef_multiplier on page 415

■ set_library_layer_offset on page 417

■ set_library_layers_cap_multiplier on page 418

■ set_library_layers_res_multiplier on page 419

■ set_library_layer_usage on page 420

■ set_logic_0_net on page 422

■ set_logic_1_net on page 423

■ set_min_porosity_for_over_block_routing on page 424

■ set_min_wire_length on page 425

■ set_net_physical_attribute on page 426

■ set_physical_instance on page 429

■ set_pin_location on page 430

■ set_power_stripe_spec on page 432

■ set_preroute_parameters on page 434

■ set_route_availability on page 436

■ set_special_netpin on page 437

■ set_steiner_channel_width on page 438

■ set_steiner_mode on page 439

■ set_supply_rails_on_rows on page 441

■ write_def on page 443



■ write_layer_usages on page 445

■ write_pdef on page 446



check_design

check_design filename

The check_design command reports the cells of the design that don’t exist in the physicallibrary or have different pin names..

Arguments

filenameName of the file that stores the report.

Database Impact

None

Related Information

check_libraries_and_design_compatibility

check_library

Examplescheck_design design.rpt





The check_libraries_and_design_compatibility command checks thecompatibility between physical and logical libraries to anticipate possible stoppages duringoptimization. It also checks the compatibility between the physical libraries and the designand pin name inconsistencies. The return values are TCL_ERROR and TCL_OK. TheTCL_ERRORvalue states that there is an incompatibility between libraries and the design andoptimization will stop. The TCL_OKvalue states that the libraries and design are compatibleand optimization will proceed.

Database Impact

None

Related Information

check_design

check_library

Examplescheck_libraries_and_design_compatibility



check_library

check_library [-logical] [-physical] [-power] filename

The check_library command verifies the different properties associated with the designlibraries, such as the power properties and the compatibility between the physical and logicallibraries. This command also checks to see if pin names are the same.

Arguments

filenameName of the file that stores the report.

-logicalReports the cells of the logical libraries that don’t exist in thephysical libraries.

-physicalReports the cells of the physical libraries that don’t exist in thelogical libraries and reports pin name problems.

-powerIdentifies libraries that contain power information.

If you specify check_library -power filename , thecommand checks whether the cell has a power model andreports the names of cells that do not have a power model.Names are printed to the screen if a filename is not specified.You need an LPS license to run the command with thisargument.

If you specify check_library -power -logical- physical filename , the command checks for a powermodel and then continue with a check for logical and physicalmodels. Results are printed into the specified file. You need bothan LPS and PKS license to run the command this way.

Related Information

check_design




Examplescheck_library -logical library_log.rpt

check_library -physical library_phy.rpt

check_library library.rpt



create_blockage

create_blockage { lx ly ux uy } [ layername ]

The create_blockage command creates a user-defined routing blockage in a specifiedlayer or in all layers.

Note: The curly braces must be typed around the required coordinates. See examples below.

Arguments

layernameName of the layer containing the routing blockage. If layernameis not specified, a routing blockage is created on all routinglayers.

lxThe lower left x coordinate.

lyThe lower left y coordinate.

uxThe upper right x coordinate.

uyThe upper right y coordinate.

Database Impact

None

Related Information

delete_blockage

Examplescreate_blockage {10 20 30 30}

Creates a blockage on all layers for a specified bbox [note: This will by definition cause botha placement and a routing blockage for that region; thus modeling keepouts].



create_blockage {10 20 30 30} metal1

Creates a blockage only on metal1 [note: depending on the place/route blockage layersspecified using set_preroute_parameters , this may or may not define a place/routeblockage].



create_placement_area

create_placement_area [-name name ] lx ly ux uy

The create_placement_area command allows you to create a named placement area.The placement areas work in conjunction with DEF rows. Use the placement areas to limitthe region where you want the cells to be placed. Useful for:

■ Low utilization design

Such as forcing QP to a cluster in the middle.

■ Part of a semi-hierarchical flow

■ Avoiding thin strips of row area (around macros)

The command generates an error if:

■ The specified box intersects the chip die box.

■ The specified name already exists.

The command generates a warning if:

■ The specified box intersects another placement area.

■ The specified box is adjusted to account for the rows along the edges. Supports bothhorizontal and vertical rows.

Arguments

-name nameName of the placement area.

lxThe lower left x coordinate.

lyThe lower left y coordinate.

uxThe upper right x coordinate.

uyThe upper right y coordinate.



Database Impact

None

Related Information

remove_placement_area

report_placement_area

Examplescreate_placement_area -name a1 100. 200. 1000. 1100.



delete_blockage

delete_blockage x y

The delete_blockage command deletes all user created blockages that lie on top of thepoint specified in the command.

Arguments

x yThe x and y coordinates.

Database Impact

None

Related Information

create_blockage

Examplesdelete_blockage 120 87



do_extract_route_parasitics

do_extract_route_parasitics wdb_name

The do_extract_route_parasitics command reads in a Wroute database, thatcontains either global and or detailed routing of the design, extracts the parasitics from therouting segments, and annotates them to the nets in the design for timing analysis use. Afterextraction, the routing information is disposed of.

The Wroute database contains physical library information (LEF), design netlist information(DEF), and global and or detailed routing information. The Wroute database has to beconsistent with ADB or in-core design data at the time of extraction. Otherwise, parasiticscannot be extracted and annotated correctly. As an example, the ADB saved right before orafter do_route is consistent with the WDB that is saved at the end of do_route . If one ofthem has been changed after saving, they can potentially become inconsistent.

Arguments

wdb_nameThe name of the Wroute database.

Database Impact

After extraction, the routing information is disposed of.

Related Information

None

Examplesdo_extract_route_parasitics wdb_name



do_generate_estcap

do_generate_estcap

The do_generate_estcap command generates the budgets and the estcaps for all netsand stores them as attributes in PDMNet. When you do a write_def the est cap is writtenout in the nets section of the DEF.

Note: If any optimization is done after issuing the above command, the est caps mightchange for the nets and the values stored in the net are meaningless. So you might have toissue the command once again to make sure that you have the correct est cap values beforeexecuting a write_def .

Database Impact

None

Related Information

None

Examplesdo_generate_estcap



do_initialize_floorplan


The do_initialize_floorplan command is used to initialize the die box and otherfloorplan parameters based on the floorplan parameters set using theset_floorplan_parameters command or using the read_def or read_pdefcommands. This command also initializes the pin positions based on the pin locations fromread_def or read_pdef commands or from the pin indices set by the user.

Database Impact

None

Related Information

report_floorplan_parameters

Examplesdo_initialize_floorplan



do_place

do_place [-area_util {l|b|r|t|u}] [-block {true | false}][-block_keep_out_x distance ] [-block_keep_oute_y distance ][-buffer_space site ] [-clock_buffer_site site ] [-cong_max_util util ][-cong_mode2 {true | false}] [-cut_ratio float ][-def_name list_of_file_names ] [-def_out_name file_name ][-eco {true | false}] [-fixed_placed_cell {true | false}][-free_track_percent_1 0-1] [-free_track_percent_2 0-1][-free_track_percent_3 0-1] [-free_track_percent_4 0-1][-free_track_percent_5 0-1] [-free_track_percent_6 0-1][-free_track_percent_7 0-1] [-free_track_percent_8 0-1][-free_track_percent_9 0-1] [-groute_analysis report_filename ][-groute_num_opt_pass num [auto tune]] [-incremental {true | false}][-incr_size size ] [-llc_ignore_layer_1 {true | false}][-llc_ignore_layer_2 {true | false}] [-llc_ignore_layer_3 {true | false}][-llc_ignore_layer_4 {true | false}] [-llc_ignore_layer_5 {true | false}][-llc_ignore_layer_6 {true | false}] [-llc_ignore_layer_7 {true | false}][-llc_ignore_layer_8 {true | false}] [-llc_ignore_layer_9 {true | false}][-llc_prewire_keep_out {true | false}] [-mega_cell_keep_out_x distance ][-mega_cell_keep_out_y distance ][-net_weight tcl_or_net_name_list integer_weight ][-output_full_def {true | false}] [-pin {concurrent|refine}][-pin_layer {left|bottom|right|top} layer_name ][-pin_same_side {true | false}] [-place_area {l|b|r|t}][-route_top_layer_limit [0 to 9]] [scan_reorder][-spare_cell cell_name_list ] [-timing_driven {true | false}][-timing_weight weight ]

The do_place command creates the initial placement of the design.

Arguments

-area_util {l|b|r|t|util}Defines the row utilization for an area {l=left, b=bottom, r=right,t=top, util=utilization}. The l , b, r , and t options are regioncoordinates, float in micron. The util option=utilization,0 < u < 1. Utilization is defined as the ratio of the instance areaand the available area for placement in the given region. Thedefault value is " ".

-block {true | false}Places the blocks. The default value is false.

-block_keep_out_x_distanceDefines the minimum horizontal distance (in microns) between



block and core cell, or two blocks. The default value is 0, ifplaceBlock is false, else the default is Row_height .

-block_keep_out_y_distanceDefines the minimum vertical distance (in microns) betweenblock and core cell, or two blocks. The default value is 0, ifplaceBlock is false, else the default is Row_height .

-buffer_space siteProvides space (site in microns) around instances connectedby nets specified in -buffer_nets .

-clock_buffer_site siteReserves n-sites (integer or floating number) around every corecomponent connected to nets marked +USE CLOCKfor the clockbuffers to be inserted later on during clock tree synthesis. Thedefault value is 0.

-cong_max_util utilDefines the maximum local utilization. util =float and the rangeis from 0-1. The default value is auto tune.

-cong_mode2 {true | false}Use when the design has region constraints or is timing-driven.

-cut_ratio floatDefines the ratio between the cuts in the horizontal directionversus the cuts in the vertical direction. This is used to adjustconnection densities in either direction. The default value is 1.0.01 < r < 100.

-def_name list_of_file_namesDefines additional DEF file names (no default).

-def_out_name filenameName of the output DEF file.

-eco {true|false}Makes minor placement modifications for the engineeringchange order (ECO). The default value is false.



-fixed_placed_cell {true | false}Fixes all the placed components if true. The default value is false.

-free_track_percent_1 0-1Defines the percentage of free routing tracks for layer 1specifiedby the user-defined value from 0-1 (.5 = 50%). The default valueis auto tuned. The 1 in this command can be replaced with thevalues [1-9] depending upon which layer is specified.

-groute_analysis report_file_namePerforms groute to generate the congestion map. Analysis isturned off using " ".

-groute_num_opt_pass numDefines the number of optimization passes in groute. num is aninteger value. The default value is auto tune.

-incremental {true | false}Makes incremental placement and optimizations based onexisting placement. The default value is false.

-incr_size sizeUses the number of instances as a starting point for incrementalplacement. Incremental size is in number of instances.

-llc_ignore_layer_1 {true | false}Turns the legal location check off (true) for specified layer 1. Thedefault value is auto tune. The 1 in this command can bereplaced with the values [1-9 ] depending upon which layer youspecify.

-llc_prewire_keep_out {true | false}

Places core cells away from prewires with appropriate designrule. The default value is false.

-mega_cell_keep_out_x distanceProvides space (<num> in microns) in the horizontal directionaround the macro cells.

-mega_cell_keep_out_y distanceProvides space (<num> in microns) in the vertical directionaround the macro cells.



-net_weight tcl_or_net_name_list integer_weightAssigns weight on the nets specified bytcl_or_net_name_list to give priority for placement inminimizing their wire length.

-output_full_def {true | false}Outputs a complete DEF instead of a DEF with only placementinformation.

-pin [concurrent | refine]Performs pin placement only. Used only with the Cadence ultraplacer. The default value is false. The concurrent option placesall cells and pins together and ignores initial placement. Therefine option states that all cells must be pre-placed (otherwisequits), only pins are re-placed.

-pin_layer {left|bottom|right|top} layernameDesignates a layer name for pins on the left, bottom, right, andtop sides. Used only with the Cadence ultra placer.

-pin_same_side {true | false}Places pins to their original side. Used only with the Cadenceultra placer. The default value is false.

-place_area {l|b|r|t}Places instances within the left, bottom, right, or top boundingbox areas. Used only with the Cadence ultra placer.

-route_top_layer_limit 0-9Limits the top routing layer to the specified value. Used only withthe Cadence ultra placer. The default value is 0.

-scan_reorderDisconnects the scan chain (if any) before placement andreconnects them based on the scan element’s physical locationafter placement. See Test Synthesis for Ambit BuildGatesand Cadence PKS for more information.

-spare_cell cell_name_listSpecifies the spare cells to be placed randomly.

-timing_driven {true | false}Performs timing-driven placement. The default value is false.



-timing_weight weightPlaces weight on the timing-driven placement effort. Sacrificeswire length to meet timing. The default value is automaticallygenerated.

Database Impact

None

Related Information

None

Examples

See the PKS User Guide (Appendix B) for information about how to use the ultra placer insidePKS.



do_placement_spread

do_placement_spread

The do_placement_spread command moves cells off of blockages, such as power stripesand macros. This helps eliminate overlaps between cells and placement blockages. It alsopredefines the placement for the final QP-eco.

Database Impact

None

Related Information

None

Examplesdo_placement_spread



do_reset_floorplan

do_reset_floorplan -rows -instances

The do_reset_floorplan command may be issued after loading a design.

Arguments

-rowsRemoves all user rows in the database and uses the floorplanparameters to generate cell rows.

-instancesSpecifies that all standard cells are to be unplaced. Thiscommand does not affect the placement of hard blocks or padcells.

Database Impact

None

Related Information



set_floorplan_parameters

Examplesdo_reset_floorplan -rows -instances



do_route

do_route [-assign_routing_direction {true | false}][-def_name list_of_file_names ] [-def_out_name def_name [wdb_name.def]][-discourage_planar_routing {true | false}] [-follow_pins][-ggrid_max_size 16] [-ggrid_min_size 5][-ggrid_mode {user | align | uniform}] [-ggrid_opt_size 10][-groute_num_opt_pass num [auto tune]][-ignore_unplaced_component {true | false}] [-incremental {true | false}][-no_follow_pins] [-output_db_name wdb_name [design_name.wdb]][-output_full_def {true | false}] [-pin_access_mode{normal|offGrid|upViaEnclosure|upVia|upViaReserve|narrowPin}][-route_area {lx|ly|ux|uy}] [-route_bottom_layer_limit value ][-route_select_net [~] list_of_net_names ][-route_select_net_first {true | false}][-route_top_layer_limit value ][-select_net_layer_range {layer:layer | layer}][-straighten_net net_name_list ] [-timing_driven {true | false}][-use_max_xy_spacing {true | false}][-use_range_rule obstruction | pin | obstruction+pin]

The do_route command invokes Wroute to do a global routing on the design and saves theglobal routing information in the Wroute database. The user can specify timing-driven usingthe synthesis timing engine.

Arguments

-assign_routing_direction {true | false}

When true, the router automatically assigns routing directions inthe channels between blocks to take advantage of availablerouting tracks (default value is false). This variable is useful, forexample, if channel congestion between blocks occurs becausethe preferred routing tracks are perpendicular to the orientationof the channel. In this case, this variable lets the router reassignthe preferred routing direction in the channel.

-def_name list_of_file_namesName of the DEF file(s) that Wroute reads.

-def_out_name def_name [wdb_name.def]Specifies the name of the DEF file that Wroute writes to.

-discourage_planar_routing {true | false}



Eliminates the use of planar routing over blocks (default value isfalse).

-follow_pinsRemoves existing power rails (if applicable) and generates newones. See Appendix D of the PKS User Guide.

-ggrid_max_size 16Sets the maximum gcell grid size in tracks. ggrid size has asignificant effect on QOR (quality of results). It is recommendedyou use a smaller ggrid size unless your design has a largenumber of obstacles or is memory constrained. See-ggrid_min_size and -ggrid_opt_size for more options.

-ggrid_min_size 5Sets the minimum gcell grid size in tracks. ggrid size has asignificant effect on QOR (quality of results). It is recommendedyou use this ggrid size unless your design has a large numberof obstacles or is memory constrained. See-ggrid_max_size and -ggrid_opt_size for more options.

-ggrid_mode {align | uniform | user}

Sets the global routing grid generation mode. The global routinggrid partitions the routing portion of a standard cell design intorectangles called gcells. The arguments for this variable set thegrid as follows:

align generates a global routing grid that aligns with thechannels and macro block boundaries in your design. This optionimproves routing quality for block-based designs because, byaligning the grids, the global router can route more effectively inempty gcells in the channel area.

uniform generates a uniform global routing grid.

user uses the global routing grid defined in the DEF file.

-ggrid_opt_size 10Sets the optimal gcell grid size in tracks. ggrid size has asignificant effect on QOR (quality of results). It is recommendedyou use a smaller ggrid size unless your design has a large



number of obstacles or is memory constrained. See-ggrid_max_size and -ggrid_min_size for more options.

-groute_num_opt_pass num

Sets the number of optimization passes in groute, specified bythe value num. If no value is given for num, the default value isauto tune .

-ignore_unplaced_component {true | false}

Specifies not to route to the pins of uplaced components (defaultvalue is false).

-incremental {true | false}

When set to true, the router runs global routing in incrementalmode, during which it deletes and globally reroutes the nets withviolations (default value is false).

-no_follow_pinsRemoves existing power rails (if applicable). See Appendix D ofthe PKS User Guide.

-output_db_name wdb_name [design_name.wdb]Specifies the router’s output database. The database is in binaryform. To save your design into a router database without runningrouting, specify the database name with this variable and set allthe routing variables to false . The router will save your designinto database format without making any routing passes. Thisvariable is useful, for example, if you are routing several differentfloorplans or placements. You can use this variable to save eachdatabase that the router creates to a different routing binary.Then you can load the best results from the saved database.

-output_full_def {true | false}When true, outputs a full DEF file instead of a DEF file containingonly placement information (default value is true).

pin_access_mode {normal | offGrid | upViaEnclosure |upVia| upViaReserve | narrowPin}Sets the option for processing pin geometries. The arguments forthis variable are:



normal – The router processes the pin geometries as it did inprevious versions of the software. This is the default value for thisenvironment variable.

offGrid – The router shrinks the pin geometries by one-halfthe wire width. The reminder of the pin geometry is valid for therouter to make a connection using a regular wire. The routerchecks the connection using a one-half wire width plus spacingrule.

upViaEnclosure – The router shrinks the pin geometries byone-half a via width. The remainder of the pin geometries is validfor the router to make a connection using a via that is fullyenclosed by the pin. The router checks the connection using aone-half via width plus spacing rule.upVia – The router does not shrink the pin, so the full size of thepin geometry is valid for the router to make a connection using avia. The router checks the connection using a one-half via widthplus spacing rule.

upViaReserve – The router shrinks the pin geometries by one-half the wire width. The remainder of the pin geometries is validfor making a connection using a via. The router checks theconnection using a one-half via width plus spacing rule.

narrowPin – The router does not shrink the pin geometries.The full size of the pin geometries is valid for making aconnection using a regular wire. The router checks theconnection using a one-half via width plus spacing rule.

-route_area {lx ly ux uy}

Routes the specified area. The coordinates for the area are indatabase units. If no arguments are given, the full chip is routed.

-route_bottom_layer_limit [0]

Limits the bottom routing layer to the specified value. A value of0 disables this argument. Routing below the specified layer isallowed, but at a very high cost. Thus, the wire length below thespecified layer is kept short. For example, in a design with six



layers, a value of 4 requests that the router start routing at thefourth layer.

-route_select_net [~] list_of_net_nameswhere ~ represents negation.Using ~ routes all but the specified nets.No ~ routes only the specified nets.

-route_select_net_first {true | false}Routes the selected nets first, followed by all other nets. Thedefault value is false.

-route_top_layer_limit [0]

Limits the top routing layer to the specified value. A value of 0disables this argument. A value of n means the placer usesrouting resources from layer 1 to layer n .

-select_net_layer_range {layer:layer | layer}Routes the selected nets on the specified layer range.

-straighten_net net_name_list

Straightens the selected nets specified by net_name_list .The default value is [ ].

-timing_driven {true | false}Turns on timing-driven routing when set to true (default value istrue). To perform timing-driven routing, the router decides theorder in which to route the constrained nets based on their timingcriticality, and routes them accordingly. The most timing-criticalnets are routed first to achieve the shortest routes.The router modifies its routing priorities as appropriate during therouting process. For example, if the router places a net low on thepriority list to start, but later realizes that the net must be routedmore directly to meet timing constraints, it will reroute the net.The router also considers the layer RC values when determininghow to route the timing-critical nets.

-use_max_xy_spacing {true | false}

Uses the maximum values of x and y for spacing checks (defaultvalue is false).



-use_range_rule obstruction | pin | obstruction+pin

Specifies the clearance distance used for spacing rule checksusing one or more of: pin, obstruction, or obstruction+pin(default).

Database Impact

None

Related Information

None

Examplesdo_route -timing_driven true -ggrid_mode align



do_snap_instance_to_row

do_snap_instance_to_row -all

The do_snap_instance_to_row command takes all instances that have placementsoutside of row definitions and snaps them into a row. When an instance is snapped to a row,it is in a semi-legal location, meaning that the instance is placed to fit entirely inside the row.If the row is smaller than the instance, the lower-left corner of the instance is snapped to thelower-left corner of the row. Instances are not snapped to multi-height rows. By default, it willonly snap instances completely outside of any row.

Arguments

-allSpecifies all instances including those that overlap with rows.

Database Impact

None

Related Information

None

Examplesdo_snap_instance_to_row -all



do_xform_tcorr_eco

do_xform_tcorr_eco [-opt_passes num] [-fix_design_rule] [-reclaim_area]

The do_xform_tcorr_eco command performs 1 pass of placement spreading and QP-eco followed by a loop of opt_passes iterations of TC/QP-eco.

where the TC command is do_xform_timing_correction-quick -incremental -resize-dont_fix_design_rules -dont_reclaim_area

This command is typically used as a cleanup step after obtaining the results fromdo_optimize . It results in a legal placement of the design.

Arguments

-opt_passes <num>Defines the number of optimization passes. The default value is1.

-fix_design_ruleTurns on fixing design rules during timing correction.

-reclaim_areaTurns on reclaim area during timing correction.

Database Impact

None

Related Information

None

Examplesdo_xform_tcorr_eco -opt_passes 0

Only performs legalization on the design.

do_xform_tcorr_eco -opt_passes 1 -reclaim_area

Performs legalization and reoptimization including area reclaiming on the design.



.



generate_supply_rails_on_rows


The generate_supply_rails_on_rows command removes any existing supply rails onrows, then generates new rails over the rows.

Database Impact

None

Related Information

remove_supply_rails_on_rows

report_supply_rails_on_rows

set_supply_rails_on_rows

Examplesgenerate_supply_rails_on_rows



get_cluster_names

get_cluster_names [-children] [-root]

The get_cluster_names command returns the name of either the root cluster, thechildren, or both. This command works with the current top timing module.

Arguments

-childrenName of the cluster’s children.

-rootName of the root cluster.

Database Impact

None

Related Information


Examplesget_cluster_names -children

get_cluster_names -root

get_cluster_names -children -root



get_current_congestion

get_current_congestion

The get_current_congestion command returns two numbers. The first measureshorizontal congestion in the design, and the second measures vertical congestion.

Database Impact

None

Related Information

None

Examplesget_current_congestion



get_current_utilization

get_current_utilization

The get_current_utilization command returns the current standard cell rowutilization of a design by dividing the current total standard cell area by the effective sites inthe design computed after accounting for all.

Database Impact

None

Related Information

None

Examplesget_current_utilization



get_library_layer_capacitance

get_library_layer_capacitance [-hor] [-ver] layername

The get_library_layer_capacitance command reports the capacitance of thehorizontal and vertical layers.

Arguments

-horReports the capacitance of the horizontal layers.

-verReports the capacitance of the vertical layers.

layernameName of the metal layer in question.

Database Impact

None

Related Information

get_library_layer_resistance

get_library_layer_usage

set_library_layers_cap_multiplier

set_library_layers_res_multiplier

Examplesget_library_layer_capacitance -hor M1

get_library_layer_capacitance -ver M1



get_library_layer_offset

get_library_layer_offset layername

The get_library_layer_offset command returns the offset value for a given routinglayer (specified in the physical library). Only routing layers may have offsets, so the layernameis the name of a routing layer. The offset value is in user units (similar to LEF data).

Arguments

layernameName of the routing layer.

Database Impact

The offset value is retrieved from the database that stores physical library data.

Related Information

set_library_layer_offset

Examplesget_library_layer_offset M1




get_library_layer_resistance [-hor] [-ver] layername

The get_library_layer_resistance command reports the resistance of the horizontaland vertical layers.

Arguments

-horReports the resistance of the horizontal layers.

-verReports the resistance of the vertical layers.

layernameName of the metal layer in question.

Database Impact

None

Related Information





Examplesget_library_layer_resistance -hor M1

get_library_layer_resistance -ver M1




get_library_layer_usage [-hor] [-ver]

The get_library_layer_usage command provides the layer usage in the horizontal andvertical directions.

Arguments

-horReports the layer usage in the horizontal direction.

-verReports the layer usage in the vertical direction.

Database Impact

None

Related Information

None

Examplesget_library_layer_usage -hor M1

get_library_layer_usage -ver M1



get_logic_0_net

get_logic_0_net

The get_logic_0_net command gets the name of the tie low net used in write_def todump the connectivity associated with the tie lows.

Database Impact

None

Related Information

get_logic_1_net

Examplesget_logic_0_net



get_logic_1_net

get_logic_1_net

The get_logic_1_net command gets the name of the tie high net used in write_def todump the connectivity associated with the tie high.

Database Impact

None

Related Information

get_logic_0_net

Examplesget_logic_1_net



get_min_porosity_for_over_block_routing


The get_min_porosity_for_over_block_routing command returns the currentvalue set by set_min_porosity_for_over_block_routing

Database Impact

None

Related Information

set_min_porosity_for_over_block_routing

Examplesget_min_porosity_for_over_block_routing



get_min_wire_length

get_min_wire_length

The get_min_wire_length command gets the current value of the minimum wire lengthvariable..

Database Impact

None

Related Information

set_min_wire_length

Examplesget_min_wire_length



get_physical_info

get_physical_info [-instance|-pin] [-location] [-size] [-center] object

The get_physical_info command queries the physical instance information.

Arguments

-instanceDefines the object as an instance.

-pinDefines the object as a pin.

-locationReturns the x,y coordinates of the object location. Operatessimilarly to the -center option when you use the -pin option.

-sizeReturns the x,y coordinates for the width and height of theinstance. Not valid with the -pin option.

-centerReturns the x,y coordinates of the object center. Operatessimilarly to the -location option when you use the -pinoption.

objectDefines an object’s name or ID.

Database Impact

None

Related Information

set_net_physical_attribute

Examplesget_physical_info -instance -location -size -center object



get_pin_location

get_pin_location pin_name [-side] [-index]

The get_pin_location command gets the side, the index, or both assigned to thepin_name .

Arguments

pin_nameName of the pin whose side and index are displayed.

-sideDisplays the side assigned to the pin.

-indexDisplays the index of the pin.

Database Impact

None

Related Information

set_pin_location

Examplesget_pin_location clk

Displays the side and the index assigned to the clk pin.

get_pin_location clk -side

Displays the side assigned to the clk pin.



get_route_availability

get_route_availability -layer layername

The get_route_availability command provides the raw routing layer percentage thatis used by the congestion analysis engine after considering preroutes. The default value is100% for each routing layer.

Arguments


Database Impact

None

Related Information

set_route_availability

Examplesget_route_availability -layer metal4

Gets the raw routing layer (metal4 ) percentage used by the congestion analysis engine afterconsidering preroutes.



get_special_netpins

get_special_netpins -type {power|ground}

The get_special_netpins command gets a list of the special pins in the current modulethat are of the type specified by the -type option.

Arguments

-type power|groundDetermines the special pins type. The special pins type isdefined as either power or ground.

Database Impact

None

Related Information

set_special_netpin

Examplesget_special_netpins -type power



get_steiner_capacitance

get_steiner_capacitance list_of_net_name_or_id

The get_steiner_capacitance command gets the total steiner wire capacitance of thespecified nets. If more than one net is passed, the capacitances are returned as the sum ofthe capacitances of the individual nets. If a net is listed more than once, the capacitance isadded for each occurrence of the net in the list.

Note: There are no -horizontal or -vertical options.

The resultant capacitance does not include pin capacitance, only wire capacitance. You canget the pin capacitance using the get_timing or report_net commands.

Arguments

list_of_net_name_or_idSpecifies the net or list of nets or ids.

Database Impact

None

Related Information

get_steiner_length

get_steiner_resistance

get_timing

report_net

Examplesget_steiner_capacitance list_of_net_name_or_id



get_steiner_channel_width


The get_steiner_channel_width command returns the current value (the default valueis 0, which means set_steiner_channel_width is off).

Database Impact

None

Related Information

set_steiner_channel_width

Examples



get_steiner_length

get_steiner_length [-horizontal|-vertical] list_of_nets

The get_steiner_length command reports the sum of the steiner wire lengths for all netsspecified in list_of_nets .

Arguments

list_of_netsName of the network using either the full hierarchical name of anet(s) or an ID (wildcards are supported).

-horizontalReports the sum of the horizontal length for the given net(s).

-verticalReports the sum of the vertical length for the given net(s).

Database Impact

None

Related Information

None

Examplesget_steiner_length -horizontal Gnd Vdd

get_steiner_length -vertical Vdd



get_steiner_resistance

get_steiner_resistance list_of_net_name_or_id

The get_steiner_resistance command gets the total steiner wire resistance of thespecified nets. If more than one net is passed, the resistances are returned as the sum of theresistances of the individual nets. If a net is listed more than once, the resistance is added foreach occurrence of the net in the list.

Note: There are no -horizontal or -vertical options.

Arguments

list_of_net_name_or_idSpecifies the net or list of nets or ids.

Database Impact

None

Related Information

get_steiner_capacitance

get_steiner_length

get_timing

report_net

Examplesget_steiner_resistance list_of_net_name_or_id



read_def

read_def [-do_not_strip_top_level_delimiter] [-hier_delimiter char ][-ignore_dist_cells] [-ignore_pwrgnd_pads] [-ignore_cover] filename

The read_def command reads a Design Exchange Format (DEF) file and reads in only cellplacement and IO placement information. All other information in the DEF file is ignored.

Arguments

filenameName of the file to be read.

-do_not_strip_top_level_delimiterForces the DEF reader to ignore the top-level delimiter character(if it exists in the input DEF) in situations where the Verilog is aflat Verilog and has the delimiter as a part of the name.

Example:The flat Verilog name is: /a/b/cThe DEF name is: /a/b/c

In the example above, the Verilog name is a flat name; thereforeread_def should not strip the first / character. By default,read_def strips the top-level delimiter to find the instanceinternal to the PKS database.

-hier_delimiter charSpecifies the delimiter character to be used with instance and pinnames. The default value is / .

-ignore_dist_cellsForces the read_def to ignore filler cells when reading the inputdef file.

-ignore_pwrgnd_padsForces the read_def to ignore physical only pads, such aspower and ground pads.

-ignore_coverForces the read_def to ignore cover macros.



Database Impact

The database is modified when a DEF file is loaded.

Related Information

write_def

Examplesread_def DesignFile.def

Reads design cell placement information and also reads the IOs from the DEF file(DesignFile.def ).

read_def -hier_delimiter / temp.def

Designates the / character as the hierarchy delimiter for instance and pin names in the DEFfile (temp.def ) .



read_layer_usages

read_layer_usages filename

Important

This command performs operations similar to those found in othercommands. If this command is used, the following commands are disabledand will have no effect:

❑ set_lef_multiplier

❑ set_layer_usages_table

❑ set_net_physical_attribute

The read_layer_usages command reads the layer usages table that contains wire lengthrange definitions. See Appendix A of the PKS User Guide for more information about layerusages tables.

Arguments

filenameName of the wire length usage table file.

Database Impact

Changes the default layer usages table (both clock and non clock data).

All capacitance values will change.

Related Information

set_layer_usages_table


write_layer_usages

Examplesread_layer_usages <usages.txt>



read_lef

read_lef filename

The read_lef command reads in the physical library data contained in the LEF file. Notethat the LEF file can be read only once during each pks_shell session, otherwise a warningis issued.

Arguments

filenameName of the LEF file.

Database Impact

None

Related Information

read_lef_update

Examplesread_lef abc.lef



read_lef_update

read_lef_update filename

The read_lef_update command reads in the physical library data contained in the LEFfile and adds this data to the data read in by the previous read_lef operation. Thiscommand can only be used after the read_lef command is issued.

Arguments

filenameName of the LEF file.

Database Impact

None

Related Information

read_lef

Examplesread_lef_update abc_ext.lef



read_pdef

read_pdef [-flow] [-Release Status ] pdef_file_name

The read_pdef command reads a PDEF file conforming to the V2.0 syntax. Additionalconstructs from the IEEE-P1481 syntax include:

■ Support for RECT, ROW_ORIENT, ORIGIN, and CONTENTS_LOCATION attributes onclusters.

■ Support for PIN construct and LOC attributes for pins.

■ Support for WireLoad attributes.

Arguments

pdef_file_nameName of the source PDEF file.

-flowMaintains file integrity between the ADB and PDEF files. Use thisoption after loading an ADB file. If the PDEF file contains CELLinformation, this information must correspond to instances in theADB file at the time the command is issued. For example, if yourun the optimize command first, it may change the netlist andtherefore potentially invalidate the CELL information.

-Release StatusSets the design state to a placed status if there is any CELL LOCinformation in the PDEF file. Any subsequent use of thedo_optimize command is launched in the PKS mode. If youdon’t want to use this mode, reload the design (minus theread_pdef command).

Database Impact

The database is modified when a PDEF file is loaded.

Related Information

write_pdef



Examplesread_pdef -flow -Release Status <pdef_file_name>




remove_placement_area [-by_name name ] [-by_position { x y } ] [-all]

The remove_placement_area command removes a specified placement area.

Arguments

nameName of the placement area.

-by_nameRemoves a placement area based on its name.

-by_position x yRemoves a placement area based on its location specified by thex, y coordinate pairs used.

-allRemoves all placement areas.

Database Impact

Can cause significant timing changes in ECO due to unplacable areas.

Related Information



Examplesremove_placement_area -by_name a1

remove_placement_area -by_position [3524. 2480.}

remove_placement_area -all





The remove_supply_rails_on_rows command removes any supply rails that are lyingon rows.

Database Impact

None

Related Information




Examplesremove_supply_rails_on_rows



report_block_halo

report_block_halo list_of_instance_names

The report_block_halo command reports the block halo that has been set around all ofthe macro blocks in the design. If no block halo is set, the default is reported.

Arguments

list_of_instance_namesName of the instance being checked.

Database Impact

None

Related Information

set_block_halo

Examplesreport_block_halo blockA/i_10




report_floorplan_parameters [-tcl_list]

The report_floorplan_parameters command reports information about the floorplan.To change and control these parameters, use the set_floorplan_parameterscommand.

Arguments

-tcl_listReports a tcl list of floorplan parameters.

Database Impact

None

Related Information





ExamplesThe output file for report_floorplan_parameters .

ac_shell[2]> report_floorplan_parameters

+---------------------------------------------+

| FloorplanParameter | Value | Source |

|------------------------+----------+---------|

| InitialBoundingBox<lx> | -603.600 | PDEF |

| InitialBoundingBox<ly> | -900.640 | PDEF |

| InitialBoundingBox<ux> | 604.800 | PDEF |

| InitialBoundingBox<uy> | 901.680 | PDEF |

| IoCoreSpacing<left> | 0.000 | Default |

| IoCoreSpacing<bottom> | 0.000 | Default |

| IoCoreSpacing<right> | 0.000 | Default |

| IoCoreSpacing<top> | 0.000 | Default |

| InitialAspectRatio | 1.000 | Default |

| FixedAspectRatio | N | Default |

| InitialHeight | 0.000 | Default |

| InitialWidth | 0.000 | Default |

| MaxHeight | - | Default |

| MaxWidth | - | Default |

| InitialRowUtilization | 80.000% | Default |

| MaxRowUtilization | 95.000% | Default |

| RowSpacing | 0.000 | Default |

| AbutPairsOfRows | N | Default |

| FlipAlternateRows | N | Default |

+---------------------------------------------+





The report_placement_area command lists all of the placement areas in the database.Placement areas with no names will contain a ? in the name string.

Database Impact

None

Related Information



Examplesreport_placement_area

Format: lower left upper right

---------- -----------

(x) (y) (x) (y)

1) a1 ---> [190.00 120.00 936.00 540.00] <PHY-451>.

2) a2 ---> [1287.00 1688.00 2290.00 2485.00] <PHY-451>.

3) a3 ---> [2530.00 1688.00 3524.00 2485.00] <PHY-451>.



report_preroute_parameters

report_preroute_parameters [-tcl_list]

The report_preroute_parameters command provides you with a report to view thepreroute parameters that have been set.

Arguments

-tcl_listReports the tcl list preroute parameters.

Database Impact

None

Related Information

set_preroute_parameters

Examples





The report_supply_rails_on_rows command outputs the supply rail specifications currentlybeing used. Among other things, the output will indicate whether the specifications werederived automtically from the LEF library, or were input by the user through theset_supply_rails_on_rows command.

Database Impact

None

Related Information




Examplesreport_supply_rails_on_rows



reset_dont_move

reset_dont_move instance_list

The reset_dont_move command removes the attribute placed on an instance(s) by theset_dont_move command.

Arguments

instance_listLists the hierarchical names (wildcards accepted) or object ids ofthe instance(s).

Database Impact

None

Related Information

set_dont_move

Examplesreset_dont_move blockA/i_10 blockB/i_40



set_block_halo

set_block_halo instName [-left lval] [-right rval] [-top tval] [-bottom bval]

The set_block_halo command defines the region around a macro reserved for routing.This command internally creates placement areas which cause the rows to adhere to theblock halo. This only applies values for macro cells as specified in the LEF file. This is anoverriding value; this value is in affect even if the global defaults are changed. This onlyaffects optimization space and should not result in a timing change.

NOTE: Specifying block halos will snip rows in the database for all macros which have at leastone non-zero halo value.

Arguments

instNameName of the instance.

-left lvalThe halo distance on the left side. The default value is 0.

-right rvalThe halo distance on the right side. The default value is 0.

-top tvalThe halo distance on the top side. The default value is 0.

-bottom bvalThe halo distance on the bottom side. The default value is 0.

Database Impact

Effects placement resources.

Related Information

report_block_halo

Examplesset_block_halo top/block/macroInst -left 10 -right 10 -top 25 -bottom 30



set_dont_move

set_dont_move instance_list

The set_dont_move command identifies the instances that will not be moved duringoptimization. The instances will not be moved, but can be deleted or resized in-place unlessyou also assert a set_dont_modify on them. The instances are written out with the+FIXED attribute in the DEF file. This property is not an attribute and can not be viewed bythe get_info or get_physical_info commands. This property is preserved in an ADBfile.

Note: The recommended usage is to use this command after the related instances havealready been placed using do_place , or after reading the PDEF or DEF file.

To remove the attribute on an instance, use the reset_dont_move instance_listcommand.

Arguments

instance_listLists the hierarchical names (wildcards accepted) or object ids ofthe instance(s).

Database Impact

None

Related Information

reset_dont_move

get_physical_info

Examplesset_dont_move blockA/i_10 blockB/i_40




set_floorplan_parameters [-abut_row_pairs|-no_abut_row_pairs][-aspect_ratio_initial float ] [-bbox_initial float float float float ][-by_tracks] [-fixed_floorplan | -no_fixed_floorplan][-flip_alternate_rows | -no_flip_alternate_rows] [-height_initial float ][-lr_io_to_core_distance { float | float float }][-tb_io_to_core_distance { float | float float }] [-lr_block_halo float ][-tb_block_halo float ] [-max_height float ] [-max_row_utilization float ][-max_width float ] [-report_only] [-row_spacing float ][-row_utilization_initial float ] [-width_initial float ]

The set_floorplan_parameters command sets floorplan specification parameters forthe root cluster.

Arguments

-abut_row_pairsKeeps flipped row pairs together. Used with theflip_alternate_rows command.

-aspect_ratio_initialDefines the aspect ratio for the initial floorplan. This is used inconjunction with row_utilization ,io_to_core_distance , and row_spacing to determine theinitial floorplan. Note that the aspect ratio = width/height.

-bbox_initialDefines the initial bounding box of the design. It defines whichbounding box to use when the design is initially converted into aplaced state. If specified, the other parameters in this block arenot used: aspect_ratio_initial , height_initial , andwidth_initial .

-by_tracksIndicates that the io_to_core_distance , row_spacing ,lr_block_halo , and tb_block_halo values are to beinterpreted in terms of tracks of the lowest routing layer in eachdirection.

-flip_alternate_rowsCauses every other row to be oriented opposite the onepreceding it (such as: North, flipped South, North, flipped South,and so on).



-height_initialDefines the height of the initial floorplan. Givenrow_utilization_initial , io_to_core_distance , androw_spacing , the width of the design is calculated.

-lr_io_to_core_distanceDefines the left and right io-to-core distance. The io-to-coredistance is the distance between the die box of a given edge andthe rows that are used for the core cell placement. The defaultvalue is 6 metal pitches using the lowest vertical routing layer.

-tb_io_to_core_distanceDefines the top and bottom io-to-core distance. The io-to-coredistance is the distance between the die box of a given edge andthe rows that are used for the core cell placement.

-lr_block_haloDefines the amount of block halo on the left/right sides. Thedefault value is 0.

-tb_block_haloDefines the amount of block halo on the top/bottom sides. Thedefault value is 0.

-max_heightDefines the maximum height that the design can grow. Sets thelimit of growth for a particular floorplan.

-max_row_utilizationDefines the maximum row utilization allowed. This is a constraintthat the tool will attempt to maintain during optimization. If themaximum row utilization is exceeded, a “grow” on the design isattempted.

-max_widthDefines the maximum width that the design can grow. Sets thelimit of growth for a particular floorplan.

-report_onlyReports the set and derived values if those options are issued.Will not change any of the specification parameters in thedatabase. Recommended if you are unsure of the relationshipsbetween values.



-row_spacingDefines the space between the rows created in the core. Therows start in the lower left of the core area and are stepped bythe core site height plus the row_spacing . The last row is atleast the io-to-core distance from the upper right, but may bemore than this minimum distance.

-row_utilization_initialDefines the row utilization used when creating the initialfloorplan. The final utilization may be different depending on theoptimizations done, but it will never be more than themax_row_utilization .

-width_initialDefines the width of the initial floorplan. Givenrow_utilization_initial , io_to_core_distance , androw_spacing , the height of the design is calculated.

Database Impact

None

Related Information



Examples




set_layer_usages_table -name table_name filename

Important


❑ read_layer_usages

❑ set_library_layers_cap_multiplier

❑ set_library_layers_res_multiplier

❑ set_library_layer_usage

The set_layer_usages_table command reads named layer usages tables. Thiscommand is used to load tables for use by set_net_physical_attribute .

The layer usages table specifies how nets will be routed by specifying what percentage ofeach wire will be routed on each layer. See Appendix A of the PKS User Guide for moreinformation about layer usages tables.

Arguments

-name table_name filenameLoads tables for use by the set_net_physical_attributecommand. The data is read from the file specified and atable_name is generated and associated with the layer usagestable that was read. The table_name is used as an argument forthe set_net_physical_attribute command, for example:set_net_physical_attribute -layer_usages_tabletable_name -all . The table_name can not be overwritten. Iftable_name already exists, an error message is issued andthe data is ignored.

Database Impact

None



Related Information


write_layer_usages

Examples



set_lef_multiplier

set_lef_multiplier -name multiplier_name -layer layer_name [-capacitance c ][-edge_capacitance e] [-resistance r ] [-via_resistance v ]

Important






The set_lef_multiplier command builds multiplier tables that effect the capacitanceand resistance values of the LEF file. The data is associated with the multiplier_name .The various layers must be specified using separate commands (SEGV). Thevia_resistance applies to the via with the given -layer as the lower layer. If applied tothe top layer, an error message is generated and the table will not be changed. If thecommands specify a new layer with the same table_name , the data is cumulative. If thelayer and data have already been specified, they are overwritten.

Arguments

-name multiplier_nameThis is how the multiplier will be referenced byset_net_physical_attribute . This is a required field.

-layer layer_nameThis is the layer that the multipliers will be applied to. This is arequired field.

-capacitance cThe value c is a float and the capacitance for the specified layerwill be multiplied by this c value. This is an optional field.

-edge_capacitance eThe value e is a float and the edge capacitance for the specifiedlayer will be multiplied by this e value. This is an optional field.



-resistance rThe value r is a float and the resistance for the specified layerwill be multiplied by this r value. This is an optional field.

-via_resistance vThe value v is a float and the via_resistance for thespecified lower layer will be multiplied by this v value.

Related Information


Examples



set_library_layer_offset

set_library_layer_offset layername offset_value

The set_library_layer_offset command sets the offset value for a given routing layer.Only routing layers may have offsets, so layername is the name of the routing layer.

Arguments


offset_valueThe offset value for a given routing layer is in user units(similar to LEF data).

Database Impact

The offset value is stored in the database that stores physical library data.

Related Information

get_library_layer_offset

Examplesset_library_layer_offset M1 0.5




set_library_layers_cap_multiplier multiplier_value

Important





The set_library_layers_cap_multiplier command defines the multiplier value thatlibrary layer capacitances are multiplied by. This command may be used several times in onesession.

Arguments

multiplier_valueSets the multiplier value. As a rule the multiplier value should beequal to or greater than 1.0.

Database Impact

multiplier value is stored in the physical library database.

Related Information



Examplesset_library_layers_cap_multiplier 1.05




set_library_layers_res_multiplier multiplier_value

Important





The set_library_layers_res_multiplier command defines the multiplier value thatlibrary layers and via resistances are multiplied by. This command may be used several timesin one session.

Arguments

multiplier_valueSets the multiplier value. As a rule the multiplier value should beequal to or greater than 1.0.

Database Impact

multiplier value is stored in the physical library database.

Related Information



Examplesset_library_layers_res_multiplier 1.05



set_library_layer_usage

set_library_layer_usage layer_name -hor in_hor_dir -ver in_ver_dir

Important





The set_library_layer_usage command defines the probabilities of routing inhorizontal and vertical directions for a given layer. Use this command only after reading thephysical library. If this command is not issued, default values are used. Layer usage valuesare not stored when writing out the ADB file. The layer usage values may need to be redefinedafter reading back the ADB file.

NOTE: When using the set_library_layer_usage command, make sure that thehorizontal and vertical values add up to 1.0. If these values do not add up to 1.0, they willautomatically be normalized to 1.0 and new values will be calculated, resulting in inaccuratedata. You will notice the change in values after accessing this information. For example, fromreport_timing .

Arguments

layer_nameName of the routing layer for which routing probabilities inhorizontal and vertical directions are being defined.

-hor in_hor_dirDefines the probability of routing in a horizontal direction for agiven layer.

-ver in_ver_dirDefines the probability of routing in a vertical direction for a givenlayer.



Database Impact

The probabilities of routing in the horizontal and vertical directions for a given layer areupdated into the database that stores physical library data.

Related Information

None

Examplesset_library_layer_usage M1 -hor 0.1 -ver 0.3

set_library_layer_usage M2 -hor 0.3 -ver 0.5

set_library_layer_usage M3 -hor 0.5 -ver 0.7



set_logic_0_net

set_logic_0_net net_name

The set_logic_0_net command sets the net name associated with the pins that are tiedlow in the design.

Arguments

net_nameName of the net.

Database Impact

None

Related Information

set_logic_1_net

Examplesset_logic_0_net Gnd



set_logic_1_net

set_logic_1_net net_name

The set_logic_1_net command sets the net name associated with the pins that are tiedhigh in the design.

Arguments

net_nameName of the net.

Database Impact

None

Related Information

set_logic_0_net

Examplesset_logic_1_net Vdd



set_min_porosity_for_over_block_routing

set_min_porosity_for_over_block_routing val

The set_min_porosity_for_over_block_routing command defines the percentageof routable tracks that can be used for over the block routing. Porosity is the total unblockedtrack length in the horizontal direction / total track length in the horizontal direction. Thevertical direction is similar. For a 4-layer design, if a macro has obstacles in only layer 1/2,then its porosity measure is > 50 in each direction. So setting the value to 50 would allow thesteiner router to route over the block instead of detouring around it.

Arguments

valThe percentage of routable tracks (0-100). The default value is100.

Database Impact

None

Related Information


Examplesset_min_porosity_for_over_block_routing 50



set_min_wire_length

set_min_wire_length value

The set_min_wire_length command sets the minimum wire length value used duringoptimization. In other words, if a net length is calculated to be less than this value, for timing(RC calculation) purposes its wire length is treated as <value> . The intention is to build aminimum tolerance for cell movements (such as overlap removal) later on without alteringachieved timing. Units are in microns.

Arguments

valueThe minimum wire length value.

Database Impact

None

Related Information

get_min_wire_length

Examples




set_net_physical_attribute [-layer_usages_table table_name ][-lef_multiplier multiplier_name ] [-non_default_rule rule_name ]{[-non_clock_tree_nets] | [-clock_tree_nets] | [-all] | [-net list_of_nets ]}

Important






The set_net_physical_attribute command allows you to change the waycapacitance and resistance (RC) are calculated for a specific net or class of nets.

There are three ways to change the RC calculation for a net:

■ -layer_usages_table

■ -lef_multiplier

■ -non_default_rule

There are four ways to apply the changes to a design:

■ -non_clock_tree_nets

■ -clock_tree_nets

■ -all

■ -net

Note: If one of the four options above is not selected, this command is ignored. If more thanone option is selected, only one option will be used and in the priority listed above.

Arguments

-layer_usages_table table_nameApplies the table_name to the nets specified. The



table_name must already be defined using theset_layer_usages_table command. Alayer_usages_table may not be changed once it is created;a new named table must be created.

-lef_multiplier multiplier_nameApplies the named multiplier to the nets specified. The namedmultiplier must already be defined using theset_lef_multiplier command. lef_multipliers maybe changed after they are applied. The change will take effect assoon as the named multiplier is changed.

-non_default_rule rule_nameApplies the named rule to the nets specified. The named rulemust be specified in the LEF file.

-allApplies to all nets in the design. Overwrites informationpreviously set with the -net option.

-clock_tree_netsApplies to all clock tree nets. Overwrites information previouslyset with the -all , -net , or -clock_tree_nets options.

-non_clock_tree_netsApplies to all non clock tree nets. Overwrites informationpreviously set with the -net option.

-net list_of_netsApplies only to the supplied list of nets. Overwrites informationpreviously set with the -all , -net , -clock_tree_nets , or-non_clock_tree_nets options.

Database Impact

None

Related Information

None



Examplesset_net_physical_attribute -layer_usages_table BASE -lef_multiplier ONE -all

set_net_physical_attribute -layer_usages_table CLOCK -clock_tree_nets

set_net_physical_attribute -non_default_rule WIDE_WIRE_1 -net CLK_PLL

set_net_physical_attribute -lef_multiplier ONEp5 -non_clock_tree_nets

Group layer_usages_table lef_multiplier non_default_rule

-------- ------------------ -------------- ------------

CLK_PLL CLOCK ONE WIDE_WIRE_1

clock_tree_nets CLOCK CLOCK -

non_clock_tree BASE ONEp5 -

This result is exactly the same as using :

set_net_physical_attribute -layer_usages_table BASE -lef_multiplier ONEp5-non_clock_tree_nets

set_net_physical_attribute -layer_usages_table CLOCK -lef_multiplier ONE-clock_tree_nets

set_net_physical_attribute -non_default_rule WIDE_WIRE_1 -net CLK_PLL



set_physical_instance

set_physical_instance [-xpos x ] [-ypos y ] [-xtrans xt ] [-ytrans yt ] instance

The set_physical_instance command sets the absolute or relative position of aninstance. Note that the object must be placed.

Important

This command has no effect if the instance is not placed.

Arguments

-xpos xSets the absolute x position of the instance.

-ypos ySets the absolute y position of the instance.

-xtrans xtTranslates the instance on the x-axis by the xt amount.

-ytrans ytTranslates the instance on the y-axis by the yt amount.

Database Impact

None

Related Information

get_physical_info

Examplesset_physical_instance -xpos 10 i_1



set_pin_location

set_pin_location pin_name [-new {[-side side ] [-index number ] | [-locationlocation ] [-layer layername ] [-box {lx | ly | ux | uy}]}]

The set_pin_location command sets one of the following: pin side, pin index, pin layer,pin location, or pin geometry. If you are using the set_pin_location command in arelease prior to the 4.0 release, the old set_pin_location command is still available foruse (see below). Note that the old command syntax will be removed in the next major release.

set_pin_location pin_name [-place {left|right|top|bottom}] [-index]

Arguments

pin_nameName of the pin whose side has to be set.

-newA mandatory option needed to utilize the new command syntax.If the -new option is not used, the default is to use the oldset_pin_location syntax. The -new option and oldcommand syntax will be removed in the next major release.

-sideDefines the side that the pin is assigned. Can be one of thefollowing: {left | right | bottom | top}. This is mandatory but cannotbe used in conjunction with the -location option.

-indexDefines the relative index for the pin on the side it has beenassigned. Any number greater than 1. This is specified alongwith the -side option.

-location {x y}Defines the location for the pin. This is mandatory but cannot beused in conjunction with the -side option.

-box {lx | ly | ux | uy}Defines the geometry for the pin.

-layer layernameDefines the layer of where the pin is placed.



Database Impact

None

Related Information

get_pin_location

Examplesset_pin_location clk left (old syntax)

set_pin_location clk -new -side left (new syntax)

Sets the location of the clk pin to the left side of the die and sets the relative order to be thelast pin on the respective side.

set_pin_location clk left 19 (old syntax)

set_pin_location clk -new -side left -index 19 (new syntax)

Sets the location of the clk pin to the left side of the die and also sets the relative order to bethe 19th pin on the left side.

set_pin_location clk -box {0 0 100 100} (new syntax)

Sets the pin geometry to be a rectangular box with origin {0,0} and height and width 100relative to the pin location.

set_pin_location clk -location {10000 20999} (new syntax)

Sets the pin location to {10000, 20999}.

set_pin_location clk -layer M1 (new syntax)

Sets the pin location in the M1 layer.



set_power_stripe_spec

set_power_stripe_spec -direction {vertical|horizontal} -layer name -width W[-start_from SF] [-stop_from EF] [-number_stripes NS] [-stripe_spacing SP][-net_spacing DS] [-net_name name1 name2 ...] [-delete_def_routes]

The set_power_stripe_spec command allows the user to generate power stripes for oneor several power nets. This command describes the rules of how to generate power stripes;it does not describe the power stripes themselves. This command is useful when modelingPG related blockages for congestion with grow on.

More than one set_power_stripe_spec command may be issued in one session. It willnot check the intersect of power stripes defined by different commands. Creating powerstripes with this command will not prevent the design from growing.

Arguments

-direction {vertical|horizontal}Defines the direction of the power stripe(s). This option ismandatory.

-layer nameDefines the power stripe(s) layer name. This option is mandatory.

-width WDefines the width of the power stripe. This option is mandatory.

-start_from SFDefines the distance to the middle of the first power stripe fromthe left side of the row bounding box (identifies where to startcreating the power stripes). If start_from and/or stop_fromare not defined, the default value of 100 microns is used. Zero isa valid value for these two parameters.

-stop_from EFDefines the distance to the middle of the last power stripe fromthe right side of the row bounding box (identifies where to stopcreating power stripes). The default value is 0.

-number_stripes NSDefines how many power stripes to create. If there is not enoughspace to create NSstripes, than the maximum number of stripesfitting into the space defined by SF and EF is created. Thedefault value is 1. If NS is not defined, the tool creates as many



stripes as possible to fill space defined by start_from andstop_from parameters.

-stripe_spacing SPDefines the distance between the power stripes. This option ismandatory if you are creating more than one power stripe. If SPis not defined, the default value of 200 microns is used. If SP iszero, only one stripe is created (the value of thenumber_stripes parameter is ignored if it is more than one).

-net_spacing DSDefines the distance between power stripes of the twoneighboring nets in the list of net names. This option ismandatory if you create power stripes for more than one net. Ifthis option is not defined, only power stripes for the first net in thelist is created.

-net_name name1 name2...Defines the list of net names of where to create power stripes. Atleast one net name should be specified.

-delete_def_routesDeletes the power stripes that were created based on the DEFinformation that if there are power stripes created based on theinformation from DEF, they should be deleted before creatingpower stripes.

Database Impact

None

Related Information

None

Examples



set_preroute_parameters

set_preroute_parameters [-min_place_obstacle_size float ][-min_route_obstacle_size float ][-place_obstacle_layers {layName1 layName2 ..}][-route_obstacle_layers {layName1 layName2 ..}][-use_pads_for_place_obstacles {0|1}] [-use_pads_for_route_obstacles {0|1}]

The set_preroute_parameters command sets a placement blockage (rows will be cut)if an obstacle exists in any of the specified place_obstacle_layers , and is at least ofmin_place_obstacle_size . It can also set a routing blockage (steiner router detoursaround it) if an obstacle exists in all of the specified route_obstacle_layers , and is atleast of min_route_size . If your design has area pads and you wish to affect placement/routing, set the use_pads_for * variables.

Arguments

-min_place_obstacle_size floatSets the minimum size of a pre-route or blockage that will beseen as a placement obstruction. Default is 6 metal1 pitches.

-min_route_obstacle_size floatIdentifies the minimum size of a pre-route or blockage that will beseen as a routing obstruction. Default is 6 metal1 pitches.

-place_obstacle_layers {layName1 layName2 ..}Specifies the list of layers to be seen as placement obstructions.Default is the lowest two routing layers.

-route_obstacle_layers {layName1 layName2 ..}Identifies the list of layers that will be seen as routingobstructions. The default requires that all layers must be in anarea for the area to be considered a routing obstruction.

-use_pads_for_place_obstacles <0|1>Tells PKS to use pads (IO or Area) as placement obstacles. Thedefault is 1 (true).

-use_pads_for_route_obstacles <0|1>Tells PKS to use pads (IO or Area) as routing blockages. Thedefault is 1 (true).



Database Impact

None

Related Information

None

Examples



set_route_availability

set_route_availability -layer layername val

The set_route_availability command sets the raw routing layer percentage that isused by the congestion analysis engine after considering preroutes. Note that setting thisvalue only has an effect during the congestion analysis within PKS. This value is not used asa guide for do_route .

Arguments


valSets the routing layer percentage that is used by the congestionanalysis engine after considering preroutes.

Database Impact

None

Related Information

get_route_availability

Examplesset_route_availability -layer metal4 20

Makes 20% of the routing layer (metal4 ) available to the congestion analysis engine afterconsidering preroutes (which means 80% of the routing layer is occupied by preroutes).



set_special_netpin

set_special_netpin -type {power|ground} list_of_pin_names

The set_special_netpin command assigns a list of pin names to a special pin connectedto a special net of the same name. The type option specifies the special pin type.

Arguments

list_of_pin_namesName of a list of pins separated by spaces.

-type power|groundDefines the special pin type. The type options are power orground .

Database Impact

None

Related Information

get_special_netpins

Examplesset_special_netpin -type ground list_of_pin_names



set_steiner_channel_width

set_steiner_channel_width float

The set_steiner_channel_width command enhances the steiner router blockavoidance by detouring preferably along sides of the macro that are free of routingobstructions within the specified distance. Timing will be reset if the number is set to adifferent value.

Arguments

float

Database Impact

None

Related Information


Examples



set_steiner_mode

set_steiner_mode {0|1|2}

The set_steiner_mode command provides three modes to control the Steiner routingfunctionality in your design. The mode should be set at the beginning of your script.

Note: All three modes are effective, but it’s recommended you evaluate each mode on yourcomplex floorplan to obtain the optimal results.

Arguments

set_steiner_mode 0Creates a wire length minimal steiner tree construction.However, the order in which sinks get connected may lead tolarger delay changes due to small cell displacements. Usingmode 0 is also susceptible to large slack jumps (see figurebelow).

The figure above shows that minimizing the Steiner tree is notalways the optimal choice. Assume S (Fig. 1) moves slightly tothe left (Fig. 2), the resulting tree in Fig. 2 is in fact optimal froma wire length perspective, but the delay to pin D has becomesignificantly worse. Care must be taken when usingset_steiner_mode 0 .

set_steiner_mode 1Each source and sink RC is computed based on the Manhattandistance separating the source and sink in addition to the routesegments connecting the 2 points. This mode is slightly morepessimistic than mode 0, but is more robust to smallperturbations (the exception is for nets with multiple drivers).

A

B C

D

S

set_steiner_mode 0

A

B C

D

S

Fig. 1 Fig. 2



Less susceptible to large slack jumps due to small celldisplacements.

set_steiner_mode 2Invokes a new timing-conscious Steiner tree router. Whenconnecting sinks, it makes a locally optimal choice by connectingthe sinks to an existing tree, therefore minimizing the maximumdelay to any sink. This mode is only available with the 4.0 releasesoftware.

Database Impact

None

Related Information

None

Examplesset_steiner_mode 2




set_supply_rails_on_rows [-location float -width float -supply {power | ground}-layer string ] | [-derived]

The set_supply_rails_on_rows command sets the specifications for the power andground rails that run through the cell rows. If this command is not used, the specifications areautomatically extracted from the LEF library. The supply rail specifications are used duringrouting congestion analysis to account for routing resources occuppied by the supply rails.

Arguments

-locationProvides the location of the center line of the rail from the bottom(horizontal rows) or left side (vertical rows) of each cell.

-widthProvides the width of the rail.

-supplyProvides the use of the rail.

-layerProvides the name of the layer that the rail lies on.

-derivedIndicates that the supply rail specifications are to be derivedautomatically from the LEF library. If this option is given, allexisting supply rail specifications are deleted.

Database Impact

None

Related Information






Examplesset_supply_rails_on_rows -locaton 9.7 -width 0.2 -layer metal1 -supply power

set_supply_rails_on_rows -derived



write_def

write_def [-placement {all|cell|io}] [-netlist][-groups {number_of_groups | cells_per_group} num] [-hier_delimiter char ][top_level_delimiter] [-no_pin_placement] [-number_of_groups num ][-cells_per_group num ] filename

The write_def command writes a Design Exchange Format (DEF) view of the currentmodule when physical cell placement information is known for the design. The defaultoperation provides cell placement coordinates, IO pin placement information, and netlistinformation. The output is determined by setting the desired command options.

Arguments

filenameName of the DEF file.

-placement {all|cell|io}Outputs the x,y coordinates for all cell and IO pins, cells only, orIO pins only in the design.

-netlistOutputs cell placement and netlist information for all netsconnecting the cells.

-hier_delimiter charDefines the character that is used as the delimiter for thehierarchical names. The default value is /.

-top_level_delimiterControls whether the delimiter for the top-level hierarchy is usedin the DEF file. The default value is false . If true , the delimitercharacter used is based on the -hier_delimiter option.

-groupsOutputs cell group associations and placement proximity usingDEF group statements. The number of groups and groupselections are controlled by either the -number_of_groupsswitch or the-groups_per_cell switch. An error message is issued if youspecify both switches. The default number of groups is 7 .

-number_of_groups integerDetermines the number of groups to be created in DEF. The



block is partitioned into rectangular or square groups of equalsize. This option is useful only when group information is outputin DEF.

-cells_per_group integerDetermines the maximum limit for the number of cells per group.The number of groups in DEF will be the number of cells in thedesign divided by the specified cells_per_group . This optionis useful only when group information is output in DEF.

Database Impact

None

Related Information

read_def

Exampleswrite_def full.def

Writes all DEF information to the full.def file.

write_def -placement all DesignName.def

Writes the cell and IO placement information to the DesignName.def file.

write_def -netlist DesignName.def

Writes the cell and IO placement information and all netlist information in the design to theDesignName.def file.

write_def -groups -number_of_groups 10 DesignName.def

Writes a list of the 10 cell groups, the cells within each group, and the relative groupplacement to the DesignName.def file.



write_layer_usages

write_layer_usages [-name table_name ] filename

The write_layer_usages command allows you to view the layer usages tables stored inthe system. If the -table option is used, only the named table is written into the specifiedfilename . If the -table option is not used, all loaded layer usages tables are written out.This includes the default tables for the clock nets and non clock nets. Use this commandanytime after issuing the read_layer_usages command.

Arguments

-name table_nameStates that only the specified table data is written to the specifiedfilename . If not used, all loaded tables and default values arewritten to the specified filename .

filenameName of the file that will contain the layer and contact usagesinformation.

Database Impact

None

Related Information

read_layer_usages



Exampleswrite_layer_usages LayerUsages.report



write_pdef

write_pdef [-version {IEEE 1481-1998 | 2.0}] [-bbox_rect] [-location_ieee_1481][-proprietary_avant_location] [-xoffset float ] [-yoffset float ]pdf_filename

The write_pdef command writes a PDEF file conforming to v2.0 syntax. Additionalconstructs from the IEEE-P1481 syntax include:

■ Support for RECT, ROW_ORIENT, ORIGIN, and CONTENTS_LOCATION attributes onclusters.

■ Support for PIN constructs and LOC attributes for pins.

■ Support for WireLoad attributes.

Arguments

-version {IEEE 1481-1998 | 2.0}Writes the pdef file in IEEE 1481-1998 standard format or 2.0standard format.

-bbox_rectRepresents the cluster bounding box in RECTconstruct. Defaultis to represent the cluster bounding box in X_BOUNDS andY_BOUNDS constructs.

-location_ieee_1481Represents the object orientation and location defined by IEEE1481-1998. The default value is to represent object orientationand location defined by PDEF 2.0.

-proprietary_avant_locationSpecific to Avant! customers only. Represents the objectorientation and location.

-xoffset floatAdds coordinates to instance and pin locations, and xboundaries and rect of clusters.

-yoffset floatAdds coordinates to instance and pin locations, and yboundaries and rect of clusters.



pdef_filenameName of the PDEF file.

Database Impact

None

Related Information

None

Exampleswrite_pdef pdef file name



5Low Power Synthesis (LPS) Commands

The following chapter contains all the ac_shell command line commands and argumentsrelated to the Low Power Synthesis (LPS) option for Ambit® BuildGates® Synthesis andCadence® PKS:

■ do_xform_optimize_power on page 449

■ get_clock_gating_options on page 452

■ get_power on page 454

■ get_sleep_mode_options on page 456

■ read_tcf on page 458

■ report_power on page 461

■ report_tc_stats on page 464

■ set_clock_gating_options on page 467

■ set_sleep_mode_options on page 475

■ Low Power Options for Existing BuildGates Synthesis Commands on page 477


Command Reference for Ambit BuildGates Synthesis and Cadence PKSLow Power Synthesis (LPS) Commands

do_xform_optimize_power

do_xform_optimize_power [-effort {no_gatelevel_opt | low | medium | high}][-no_design_rule][-critical_ratio {0.0-1.0}] [-critical_offset float ][-fix_clock_net]

The do_xform_optimize_power command analyzes and commits sleep mode and clockgating logic to the design. This command also performs gate-level optimizations to improveaverage power consumption in the design.

If you have a timing-optimized netlist, use this command instead of do_optimize -power .

Prerequisites

If you want to use sleep-mode analysis to optimize the power, run the following commandsfirst:

1. set_sleep_mode_options

2. do_build_generic -sleep_mode

If you want to lower power consumption with clock-gating logic, run the following commandsfirst:

1. set_clock_gating_options

2. do_xform_optimize_generic -clock_gate

Arguments

-critical_offset floatThis option is similar to the critical_ratio option except thatthe floating number is added to the value of worst slack. Onlypositive numbers are valid.

-critical_ratio { 0.0 - 1.0 }Specifies the range of slack for paths to be considered for thetiming-driven power optimization. The ratio is expressed as apercentage of the worst slack. This allows a range of worst slackto be considered critical by the command. Only positive numbersare considered. The default value for is 0. The critical ranges thiscommand considers are calculated as follows:

For negative worst slack:



(worst_slack * (1 - critical_ratio) + critical_offset, worst_slack)

For positive worst slack:

(worst_slack * (1 + critical_ratio)+ critical_offset, worst_slack)

-effort {no_gatelevel_opt | low | medium | high}The effort level specifies the scope of the power optimization thatyou want. In general, the higher the level, the larger the scopeand the longer the run time of the optimization. The default levelis medium. Note that, if before running this command, you hadclock-gating or sleep-mode logic inserted in the design,do_xform_optimize_power commits/decommits the logicbased on potential power savings.

Choose one of the four effort levels:

Note: It is a good idea to use the medium or high effort level throughout the flow. Use thelow effort level at the end of the flow.

no_gatelevel_opt Commits/Decommits only the sleep mode andclock gating logic inserted when runningdo_build_generic -sleep_mode anddo_xform_optimize_generic-clock_gate . It does not perform gate-levelpower optimization.

low Performs gate-level transformations, such asresizing, pin swapping, and restructuring, tominimize power consumption without worseningthe current slack. This effort level isrecommended for post-timing optimized designs.

medium The medium effort level performs the same gate-level transformations as the low effort level, butdoes more iterations without worsening the timingconstraints.

high This effort level performs the gate-level poweroptimizations at the highest level. It does moreiterations then the low and medium effort levelsto minimize the power consumption.



-fix_clock_netPerforms transformations on clock nets. By default, the clocknetwork is not modified by the power optimizationtransformations.

-no_design_ruleIgnores design rules when optimizing the power.

Related Information

■ do_build_generic


Example

See the gate-level power optimization only flow.



get_clock_gating_options

get_clock_gating_options [-tcl]

The get_clock_gating_options command displays the current settings you have forclock gating.

Prerequisites

None

Arguments

-tclOutputs a list of all clock gating options that you have set usingthe set_clock_gating_options command. By default(without specifying -tcl ), options are shown in a tabular formatwith the keywords SET/NOT SET or values for each option.

Related Information



Examples

Here is an example of the type of output you would get usingget_clock_gating_options -tcl :

-drv 2 -control test -observe -no_latch -force {78867} -ignore {79251}

If you run the get_clock_gating_options command without the -tcl argument, theoutput would look like this:

+--------------------------+

| Clock-Gating Options |

|--------------------------|

| Options | Value |

|-------------+------------|

| -drv | 2 |

| -control | test |

| -observe | SET |



| -no_timing | SET |

| -no_latch | SET |

| -pref_map | NOT SET |

| -commit_all | NOT SET |

| -force | 78867 |

| -ignore | 79251 |

+--------------------------+



get_power

get_power [-instance { list_of_instances }]

The get_power command goes down the hierarchy and returns the total power for thespecified instances of the current module. If you do not use this option with this command,the command returns the power numbers for the current instance.

Prerequisites

You should have a toggle count format (TCF) file read into the database before you run theget_power command. Without a TCF file, the tool uses default toggle counts for eachprimary input and sequential cell output, performs probabilistic analysis on the rest of thedesign incrementally, and generates the power.

Arguments

-instance {list of instances }Specifies the instances that you want to obtain the power for.Instances must be separated by a space. See the Examplessection for details.

Related Information


■ get_current_instance


Examples

Example 1:

get_power

0.234

Example 2:

get_power -instance B

0.119



Example 3:

get_power -instance {A/B/C/I1 A/B/C/I2 A/B}}

This command will go down the hierarchy as shown in Figure 5-1 and return the followingvalues:

{3.45E-04 5.27E-04 0.119}

Figure 5-1 Instance Hierarchy

Note: The power values are shown in the unit you have specified in your technology library.Also, the precision of the power value is three digits. So, if you have a total power of 0.00345 ,it is displayed as 0.345E -2.

I1 I2A

B



get_sleep_mode_options

get_sleep_mode_options [-tcl]

The get_sleep_mode_options command displays the current settings you have for sleepmode.

Prerequisites

None

Arguments

-tclOutputs a list of all sleep mode options you have set using theset_sleep_mode_options command. By default (withoutspecifying -tcl ), options are shown in a tabular format with thekeywords SET/NOT SET or value for each option.

Related Information



Examples

Here is an example of the type of output you would get using get_sleep_mode_options-tcl :

-no_dissolve -timing_driven full -remove {106019}

If you run the get_sleep_mode_options command without the -tcl argument, theoutput would look like this:

+-----------------------------+

| Sleep Mode Options |

|-----------------------------|

| Options | Value |

|----------------+------------|

| -no_dissolve | NOT_SET |

| -timing_driven | full |

| -remove | 106019 |



+-----------------------------+



read_tcf

read_tcf tcf_name

The read_tcf command reads toggle counts from the specified file and puts assertions intothe database, so they can be used for power estimation and optimization.

If you plan to run power analysis or optimization, it is recommended that you read in a togglecount format (TCF) file. If you do not use a TCF file for power estimation or optimization, thetool uses default toggle count values at the primary input and sequential outputs andperforms probabilistic analysis after that.

Prerequisites

You must have read in a netlist before you can use this command.

Arguments

tcf_nameSpecifies the file containing the toggle counts that you want touse. There are no restrictions on file names or length of thefilename and the toggle count file does not have to use a .tcfsuffix.

Examples

Example 1:

Here is an example of a flat TCF file:

tcffile () {

tcfversion : "1.0";

generator : "BGPower Verilog PLI";

genversion : "1.0";

date : "Wed Aug 9 16:45:44 2000";

duration : "1.501000e+05";

unit : "ns";

instance () {

net () {

"p_22gat_10_" : "0.587916 739";

}



pin () {

"i_12/Z" : "0.566029 747";

"n_n1/B" : "0.516522 475";

"hier1/i_0/Z" : "0.773700 478";

"hier1/n_n0/Z" : "0.433971 747";

"hier1/n_n0/A" : "0.517588 521";

"hier1/n_n0/D" : "0.516522 475";

"hier1/i_0/A" : "0.487675 488";

"hier1/i_0/B" : "0.492405 493";

"n_n1/A" : "0.504664 506";

}

}

Example 2:

Here is an example of a hierarchical TCF file:

tcffile () {

tcfversion : "1.0";

generator : "BGPower Verilog PLI";

genversion : "1.0";

date : "Wed Aug 9 16:20:07 2000";

duration : "1.501000e+05";

unit : "ns";

instance() {

net() {

"p_22gat_10_": "0.587916 739";

}

instance("n_n1") {

pin() {

"B" : "0.516522 475";

"A" : "0.504664 506";

}

}

instance("i_12") {

pin() {

"Z" : "0.566029 747";

}

}

instance("hier1") {

instance("i_0") {

pin() {



"Z" : "0.773700 478";

"A" : "0.487675 488";

"B" : "0.492405 493";

}

}

instance("n_n0") {

pin() {

"Z" : "0.433971 747";

"A" : "0.517588 521";

"D" : "0.516522 475";

}

}

}

}

}

For more details about either example, see Chapter 2 in the Cadence Low PowerSynthesis User Guide.



report_power

report_power [-instance { list_of_instances }] [-net { list_of_nets }][-maxcount nworst ] [-hier] [{>|>>} filename ]

The report_power command obtains the power consumption information for specifiedobjects in your design.

By default, the report_power command provides the total power of the current instance.

Prerequisites

Before you use report_power , the top timing module must be correctly set because thepower for each net is computed by using the assertions set with respect to the top timingmodule. It is not necessary to set it to a specific module, but it must be set to manipulate onlythe power assertions.

Arguments

{>|>>} filenameThe generated report is stored in the file specified byfilename . If the filename is not specified, the report isdisplayed in standard output. The filename must be the lastargument included with this command.

Specifies where you would like the power report saved forviewing later. If you do not use this option with this command, thepower report will be immediately displayed on the screen, but isnot saved.

-hierTraverses through the hierarchies below the current module. Itreports power of those hierarchies based on the other optionsyou specify, such as -instance , and -net .

-instance {list_of_instances }Reports the power for each instance in the specified instance list.It is non-hierarchical, unless you also use the -hier option. Ifyou do not specify any instances with this option, the defaultaction is to report the power for each instance in the specified orcurrent module.



If you have more than one instance, separate instance nameswith a space. See the Examples section for more details.

-maxcount nworstLimits the number of entries in the report to the specified numberthat have the worst (highest) power value. If you do not specify anworst value, the default reported is 5.

For example, report_power -instance -maxcount 10 willgive you a report of the 10 worst power values for all instances inyour design.

-net {list_of_nets }Reports net statistics, such as the signal probability, toggle rate,net capacitance, and the total power of each of the nets in thespecified net list. If you do not specify any net names with thisoption, the default action is to report the power for each net in thecurrent module.

If you have more than one net, separate net names with a space.See the Examples section for more details.

Related Information


Examples

This usage of the report_power command in the gate-level power optimization flow:

read_alf lib.alf


do_build_generic

source timing_constraint_file .tcl

read_tcf tcf_file

do_optimize -power

report_power

generates this output:+--------------------------------------------+

| Report | report_power |

|---------------------+----------------------|

| Options | |

+---------------------+----------------------+

| Date | 20000907.143101 |



| Tool | ac_shell |

| Release | v4.0-eng |

| Version | Sep 6 2000 08:06:12 |

+---------------------+----------------------+

| Module | top |

| Operating Condition | NOM |

| Process | 1.000000 |

| Voltage | 3.300000 |

| Temperature | 25.000000 |

+--------------------------------------------+

+----------------------------------------------------------------------------------------------------------+

| top |

|----------------------------------------------------------------------------------------------------------|

| | Library | Internal | Leakage | Net | Total |

| | | Cell | | | |

|--------------+----------------+--------------+--------------+--------------+--------------+--------------|

| Module | Instance | Cell | Power (mW ) | Power (mW ) | Power (mW ) | Power (mW ) |

|--------------+----------------+--------------+--------------+--------------+--------------+--------------|

| | | | 0.0140 | 0.0000 | 0.0218 | 0.0358 |

+----------------------------------------------------------------------------------------------------------+



report_tc_stats

report_tc_stats [-prob | -td] [-type {assert | noassert | all}][-instance { instance_name }] [-range { n1 n2 ... }][-tcl_list default_table_format ]

The report_tc_stats command reports the number of nets falling into the bins based oneither signal probability or transition density.

Prerequisites

None

Arguments

-instance instance_nameReports the statistics of a particular instance. There is no needto use this argument if statistics are needed for the whole design.

-prob | -tdReports statistics based on signal probability (-prob ) ortransition density (-td ). If you do not specify either argument,the default behavior is -td and a warning is issued to state this.Note that no warning is issued if you specify the -tcl_listargument with this command.

-range {n1 n2 ... }Provides the range of signal probability or transition density. Ifrange values are not provided, the tool uses the default values.

These are the default values:

-tcl_list default_table_formatSpecifies the Tcl output format. If no format is specified, thedefault output is table format.

-prob (0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9)

-td (0.0001 0.00005 0.00001 0.00005 0.001 0.0050.01 0.05 0.1 0.5)



-type {assert | noassert | all}Specifies which nets to report.

Choose one of the following:

Examples

Here is what the output for the report_tc_stats command looks like:

Transition Density (td)

Statistics For Nets

|--------------------------------|

| td | #nets |

|-------------------+------------|

| 0.000000-0.000050 | 11 |

+-------------------+------------+

| 0.000050-0.000100 | 2 |

+-------------------+------------+

| 0.000100-0.000500 | 0 |

+-------------------+------------+

| 0.000500-0.001000 | 6 |

+-------------------+------------+

| 0.001000-0.005000 | 137 |

+-------------------+------------+

| 0.005000-0.010000 | 16 |

+-------------------+------------+

| 0.010000-0.050000 | 1 |

assert Reports nets that have a signal probability ortransition density asserted by the user.

noassert Reports nets that have a signal probability ortransition density compiled by the software.

all Reports both types of nets, as specified with theassert and noassert options.This is thedefault action for this command.

If no type is specified, a warning is issued, unlessyou have specified the -tcl_list argumentwith the command.



+-------------------+------------+

| 0.050000-0.100000 | 0 |

+-------------------+------------+

| 0.100000-0.500000 | 0 |

+-------------------+------------+

| 0.500000-> | 0 |

+--------------------------------+



set_clock_gating_options

set_clock_gating_options [-control { signal_name }][-observe][-minsize reg_bank_size ][-auto_test_port][-domain {all|dft_domain|clock_net}][-drv size ][-obs_style {port|register|reg_module}][-same_polarity][-no_latch][-no_timing][-ignore list_of_instances ] [-force list_of_instances ][-pref_map] [-default][-remove][-xor_depth xor_depth ][-ctrl_before_latch]

The set_clock_gating_options command lets you set various clock gating functionsfor inserting clock gating and for clock gating logic commitment during gate-level poweroptimization.

Changing and Viewing Option Settings

This command will not overwrite any options previously set by this command. For example, ifyou used the command as follows:

set_clock_gating_option -drv 2

set_clock_gating_option -no_latch

Running the get_clock_gating_options command shows that both options remain set:

-drv 2 -no_latch

Note: Options are preserved even after you run the do_remove_design -all command,which removes the design.

To reset the clock-gating options to the software defaults, useset_clock_gating_options -default .

Support for Multiple Clock Domains

To support multiple clock domains controlled by different test signals, theset_test_mode_setup command was modified, along with theset_clock_gating_options command. See the set_test_mode_setup on page 522command for more information.

For more information about multiple clock domains, see Chapter 3 of the Low PowerSynthesis Option of Ambit BuildGates Synthesis and Cadence PKS document.

Prerequisites

Your design must be loaded.



Arguments

-auto_test_portAutomatically sets test_mode pins at the top module for all theclock domains when inserting DFT logic during clock gating, ifclock domains under DFT settings do not have a correspondingtest_mode pin defined.

Note that, if the -auto_test_port option is not set and thecondition described in the previous paragraphs exists, thesoftware issues a warning message.

The name of the added test_mode pins is made from the globaldft_test_mode_port_name_prefix setting, followed by anumeric. By default, the global is set to TEST_MODE. So, if thatglobal was set to the default, the first test_mode pin added wouldbe called TEST_MODE_1.

-control { signal_name }Specifying this option makes the clock controllable when thesignal is active, if the signal is present and the -domain optionis set to all . The signal can be either a port or internal node. Ifyou specify the signal, it should be specified as aset _test_mode option or this argument will not work. Seeset_test_mode_setup on page 522 for more information.

If the -domain option is set to either dft_domain orclock_net , then the clock is made controllable (controllabilitylogic is inserted) by associating the test_mode pin with thecorresponding clock as defined by the set_test_mode_setupcommand. See the Examples section of theset_clock_gating_options command that showstestmode1 associated with clk1 .

If this association between the test_mode pin and clock does notexist with set_test_mode_setup and-auto_test_port set, the tool performs as detailed in theauto_test_port argument description.

Because of the gated logic, it might not be possible to control theclock signal feeding the set of registers affecting clock gating,which can affect design testability. Using this argument gives youthat control.



-ctrl_before_latchAdds logic to control the gated clock before latching the signal.Controlling the gated block before latching the signal preventsglitches on the gated clock signal even if the test_enable signalhas glitches.

-defaultSets all values for this command to the default values andremoves any attributes set by -force and -ignore .

The default values for the set_clock_gating_options are asfollows:

-domain {all|dft_domain|clock_net}Lets you choose how you would like gating signals grouped for

Option Default Value

-drv NOT SET

-xor_depth 5

-control NOT SET

-observe NOT SET

-no_timing NOT SET

-no_latch NOT SET

-pref_map NOT SET

-same_polarity NOT SET

-commit_all NOT SET

-remove NOT SET

-auto_test_port NOT SET

-domain all

-obs_style port



controllability, observability, or both. The default is all .Choose one of the following:

-drv sizeIf specified, gating logic is cloned whenever it is driving morethan the number of registers specified with the size variable.Note that LPS only clones the gate that gates the clock.

-force {list_of_instance_ids }Inserts and forcibly commits clock gating on the specified flip-flops.

If you specify this argument with theset_clock_gating_options command before runningdo_xform_optimize_generic -clock_gate , clock-gatinglogic for the instances specified is not inserted. If this argument

all Groups all gating signals into one observabilitylogic. This is the default for -domain when the-observe option is also set for this command.

Makes all clocks controllable by a singletest_mode pin. This is the default for -domainwhen the -control option is also set for thiscommand.

dft_domain Groups all gating signals of clock domains thatare associated with the same test_mode signaltogether in the same observability logic, if youalso have -observe set for this command.

Makes all clocks controllable using the sametest_mode pin, if you also have -control set forthis command.

clock_net Groups gating signals driven by the same clocksignal under DFT settings. This option is onlyrelevant for observable domains.

For a detailed description of the three differentways the tool can trace the clock net back throughthe design, see Chapter 3 of the Low PowerSynthesis Option of Ambit BuildGates Synthesisand Cadence PKS document.



is specified for set_clock_gating_options after runningdo_xform_optimize_generic -clock_gate and beforedo_optimize -power , clock-gating logic for the specifiedinstances is not committed.

-ignore {list_of_instance_ids }Does not insert/commit clock gating logic for the specifiedinstances. If you specify this argument with theset_clock_gating_options command before runningdo_xform_optimize_generic -clock_gate , clock-gatinglogic for the instances specified is not inserted. If this argumentis specified for set_clock_gating_options after runningdo_xform_optimize_generic -clock_gate and beforedo_optimize -power , clock-gating logic for the specifiedinstances is not committed.

-minsize reg_bank_sizeProviding this variable means that any register bank larger thanthe specified size will be clock gated. By default, the registerbank is clock gated based on the estimated power savings it canproduce.

It is recommended that you let the tool decide the minimumregister size based on the power estimation.

-no_latchDoes not latch the enable signal. The clock-gating logic does notcontain any latches. By default, the enable signal is latched.If you use -no_latch and want timing constraints to be takeninto consideration when performing clock gating, you’ll need toset the timing constraints because LPS analyzes the clockinformation to perform clock gating with no latches.

-no_timingIf set, clock gating will not consider timing. This means that, evenif the clock-gating logic causes a timing violation, the logic will becommitted.

-observeMakes all gated signals observable. Each of the gating signals isadded to an XOR tree and the output of the XOR tree isconnected to either a port or observability register.



Note that the XOR tree can span through several modules. Allobservability signals in a module corresponding to a clockdomain under DFT settings are put into an XOR tree in thatmodule and a single observability signal crosses the moduleboundary, when necessary.

Clock gating makes the gating signals unobservable, so settingthis argument adds the extra logic to make the signalsobservable again.

This option only works if -control is set.

Note: This option may cause module changes because a new port may be added for theobservable signal.

-obs_style {port|register|reg_module}Lets you specify how the observability domain is created.Choose one of the following:

port Creates a port in the top module for eachobservability domain and its logic is connected tothis port through an XOR tree. This is the defaultfor -obs_style .

register Feeds the observability logic to an observabilityregister that is inserted in the scan chain. This islimited by the -xor_depth value, with a defaultvalue of 5.

By default, the register is clocked with the invertedsignal of the physical clock net driving theregisters in that observability domain. The registeris inserted at the outermost hierarchy that has thecorresponding clock signal. The -same_polarityoptions changes this default.

Note that the logic can span across modulesexcept where the clock signal is not present.

If you select this option, you must also select-obs_domain clock_net .



-pref_mapPreferentially maps the clock gating logic to cells that have theattribute is_clock_gating_cell . If no such cells exist, thecommand maps to the normal cells with clock gatingfunctionality.

-removeRemoves all inserted clock-gating logic.

-same_polaritySets the clock polarity for the observability register to that of thedriving registers in the clock-gating domain. By default, the clockpolarity of the observability is opposite to the driving registers ofthe clock-gating domain. This default provides an additional halfcycle to allow the signal to propagate through the XOR tree.

Note that, if you select this option, you must also select-obs_style register or -obs_style reg_module .

-xor_depth xor_depthAdds a register whenever the depth of the XOR tree is equal tothe depth specified with this option. This ensures that themaximum depth of the XOR tree is limited to the value specifiedhere. The default depth value is 5.

Related Information




reg_module Completes the observability logic for anobservability domain in the register in thatmodule. This avoids the observability portcreation in any hierarchical module.Note that, if you select this option, you must alsoselect -domain clock_net .



Examples

This is an example of how you can use the -control option:

set_test_mode test1 1 -clock [find -port clk1]

set_test_mode test2 1 -clock {[find -port clk2][find -port clk3]}

set_test_mode test3 0 -clock clk4

set_clock_gating_options -control

In this example, all clock-gating logic driven by clk1 , either directly or after propagationthrough buffers, inverters, clock splitters, and pre-existing gating logic, is made controllableby test1 . clk2 and clk3 are controllable by test2 and clk4 by test3 .



set_sleep_mode_options

set_sleep_mode_options [-timing_driven {none | partial | full}][-no_dissolve][-remove {list_of_instances}][-default]

The set_sleep_mode_options command lets you choose settings for the sleep modelogic commitment for the gates of the current module.

Note: Set these options anytime before running gate-level power optimization.

Prerequisites

You must run do_build_generic -sleep_mode before using theset_sleep_mode_options command.

Arguments

-defaultSets all options for this command to the default settings.

-no_dissolveDoes not dissolve the hierarchy of a gating module when it iscommitted during sleep mode. Unless you specify this argument,the gating module’s hierarchy is dissolved when the module iscommitted during sleep mode.

-remove {list_of_instances}Removes the inserted sleep-mode logic for the specifiedinstances. If no instances are specified, all inserted sleep-modelogic is removed.

-timing_driven {none | partial | full}Determines what degree timing is considered when committingsleep mode logic.Choose one of the following:

none Does not consider timing when committing thesleep mode gating logic. Only power isconsidered.



Related Information




partial Commits all modules based on power, but thenruns timing optimization to improve slack. If thetiming constraints are not met, the command triesto improve the slack by decommitting gatedmodules.

full Commits each gating module if committing it willnot violate a timing constraint.



Low Power Options for Existing BuildGates Synthesis Commands

Some low power options are built into existing BuildGates Synthesis commands. Please seethe appropriate command documentation for more information about the low powerfunctionality.

■ check_library -power

■ do_build_generic -sleep_mode

■ do_optimize -power

■ do_xform_optimize_generic -clock_gate

■ do_xform_optimize_slack -power



6Test Synthesis Commands

This chapter describes the commands that you can use with the test synthesis tool.

■ check_dft_rules on page 480

■ display_scan_chains on page 482

■ do_xform_connect_scan on page 483

■ do_remove_scan_order_data on page 486

■ get_scan_chain_info on page 487

■ read_scan_order_file on page 489

■ report_dft_assertions on page 490

■ report_dft_registers on page 491

■ reset_dft_compatible_clock_domain on page 493

■ reset_dft_internal_clock_domain on page 494

■ reset_dft_transparent on page 495

■ reset_dont_scan on page 496

■ reset_dont_touch_scan on page 497

■ reset_must_scan on page 498

■ reset_scan_data on page 499

■ reset_test_mode_setup on page 500

■ set_dft_compatible_clock_domain on page 501

■ set_dft_internal_clock_domain on page 503

■ set_dft_transparent on page 505

■ set_dont_scan on page 506

■ set_dont_touch_scan on page 507


Command Reference for Ambit BuildGates Synthesis and Cadence PKSTest Synthesis Commands

■ set_lssd_aux_clock on page 508

■ set_lssd_scan_clock_a on page 509

■ set_lssd_scan_clock_b on page 510

■ set_max_scan_chain_length on page 511

■ set_must_scan on page 512

■ set_number_of_scan_chains on page 514

■ set_scan_data on page 515

■ set_scan_mode on page 518

■ set_scan_style on page 520

■ set_test_scan_clock on page 521

■ set_test_mode_setup on page 522

■ write_atpg_info on page 524

■ write_scan_order_file on page 525



check_dft_rules

check_dft_rules [> | >> filename ]

This command is used to check DFT rules for each flip-flop in the design. The flip-flops thatpass check_dft_rules check are later automatically mapped to scan flip-flops andincluded in a scan chain during scan connection. The flip-flops that fail check_dft_rulesare excluded from scan chains. Checks for the DFT rule violations listed in Table 6-1 onpage 480. To maximize fault coverage, you should try to fix any DFT rule violations so that allflip-flops can be included in a scan chain. To better understand the costs and benefits of fixingDFT rule violations, see the section “Avoiding DFT Rule Violations” in the Cadence TestSynthesis User Guide.

You should run check_dft_rules whenever you make changes to your DFT assertions.Otherwise, your assertions are not propagated through the design.

The error message produced by this command gives the RTL file name and line number atwhich the DFT violation occurred. If you are working in the GUI, you can triple-click the errormessage itself to view that section of RTL code. You can fix the violation by editing the RTLcode directly in the window.

This command has no effect on the design database.

Table 6-1 Checking for DFT Rule Violations

DFT Rule Violation Check for Violation With

Combinational feedback loops

set_global dft_enable_combinational_loop_check true

check_dft_rules

Race conditions set_global dft_enable_race_condition_check true

check_dft_rules

Uncontrollable asynchronous signals

Gated clocks and derived clocks

Register’s clock port connected to tied lines

Multiple sequential control functions

check_dft_rules

Clocks feeding the data path

Not checked



The output of this command can be directed to a file using > or >>.

Arguments

None

Related Information

check_netlist

set_test_mode_setup

set_global dft_enable_combinational_loop_check

set_global dft_enable_race_condition_check

set_dont_scan

Bus conflicts or floating conditions

Not checked

Table 6-1 Checking for DFT Rule Violations

DFT Rule Violation Check for Violation With



display_scan_chains

display_scan_chains [-pks] [-chain n] [ module_name ]

Displays the scan chains in the schematic viewer following test synthesis. You should openthe schematic viewer to the appropriate module prior to invoking this command.

If you want to display the scan chains for the current module, you can use the following Tclcommand:

display_scan_chains [get_names[get_current_module]]

You can traverse the hierarchy in the schematic viewer by clicking on a module instance,repeat the Tcl command to view the scan chains for the newly displayed module.

This command has no effect on the design database.

Arguments

-chain n Displays only the specified scan chain.Default: All scan chains

module_name Specifies the name of the module whose scan chains you wantto display.Default: Current module

Note: The module_name argument is ignored when you also specify the -pksargument because the PKS window shows only the flattened top-level design.

-pks Displays the scan chain in the PKS window.Default: Schematic viewer

Examplesdisplay_scan_chains mymod

display_scan_chains [get_names [get_current_module]]



do_xform_connect_scan

do_xform_connect_scan [-scan_file file_name ] [-pks] [-preserve_config]

This command configures and connects scan flip-flops into scan chains. The commandworks at the "current module" level and all lower hierarchies referred to in the current module.The design must be mapped before connecting scan chains in a design.

All flip-flops that pass DFT rule check (through check_dft_rules command) are convertedto scan flip-flops and are connected up into scan chians. The flip-flops that do not pass DFTrule check are automatically excluded from scan chains. The flip-flops in the lower modulehierarchies are also automatically reconfigured and connected, unless the lower module istagged with dont_modify or dont_touch_scan . The scan style used for scan flip-flops iscontrolled by the set_scan_style command.

Scan configuration:

Unless the -preserve_config option is used, all scan flip-flops are first configured intodifferent chains based on the DFT assertions, such as

■ Maximum scan chain length

■ Number of scan chains

■ Sets of compatible clock domains (when mixing different clock domains in a single chainin mux scan style)

■ Fixed scan segments (i.e. scan segments belonging to modules marked dont_modifyor dont_touch_scan ).

When using the -pks option, the placement information about scan flip-flops is used toconfigure the chains to minimize wire length due to routing the scan data shift path. Thedesign must be placed before -pks option can be used in scan connection.

Scan data connection:

Scan flip-flops are connected up according to the global setting on thedft_scan_path_connect global variable, which can be one of the following:

■ chain : connect scan flip-flops in chain mode (DEFAULT)

■ tieback : tie scan-in of a flip-flop to its own scan-out pin

■ floating : leave the scan-in of flip-flop unconnected



Under chain mode, the folllowing two additional globals control how the chains will beconnected.

■ dft_scan_output_pref : This global controls whether to use normal or invertedoutput (Q or Q-bar) of scan flip-flop for scan connection.

The possible settings are:

non_inv : use non-inverted (Q) output (DEFAULT)

min_load : use the output with least load

■ dft_allow_scanpath_inv : This global controls if inverters should be inserted inscan path to compensate for logic inverion when connecting from inverted output or toinverted scan-input.

The possible settings are:

on : inversion in scan path is allowed. (DEFAULT)

off : inversion in scan path is not allowed. When connecting from inverted output(Qbar) or to inverted scan-input, an inverter must be inserted to compensate forlogic inversion on the data path.

Under chain mode, the chains would get connected to the specified scan-in and scan-out pins(using set_scan_data command). If the scan-out of a chain is shared with a functionaloutput pin, a multiplexor, controlled by the scan-enable signal, would be inserted to share thepin between functional output and scan output.

In mux scan style, if scan flip-flops triggered by different edges of a clock, or by different clockdomains are to be connected in the same chain, then lock-up latches would be automaticallyinserted to prevent clock-skew problems.

Scan control connection:

Unless the -preserve_config option is used, the scan mode signal (scan-enable signal)is connected according to the setting of global variable dft_scan_enable_connect .

The allowed settings are:

on : connect scan-enable pin of flip-flop to the specified top level scan-enable signal.

tieoff : connect scan-enable pin of flip-flop to its inactive value (power/ground).

floating : leave scan-enable unconnected.



Arguments

-scan_file file_nameSpecifies the file name for the scan order file.Default: top_module .scan and top_module .scan.flat-name

-pks Orders and connects each chain according to the proximity offlip-flops and the placement information from the PKS tool.Note: The -pks option requires a Cadence® PhysicallyKnowledgable Synthesis (PKS) software license. The designmust be placed before performing placement-based scan chainordering using the do_place command.

-preserve_config This option is used to preserve the analyzed configuration ofexisting scan chains in mapped netlists during PKS based scanreordering (-pks option). Any additional configurationassertions that you specify, such asset_number_of_scan_chains orset_max_scan_chain_length , are ignored. The-preserve_config option is the default mode used by thedo_place -scan_reorder command.

Related Information

set_global dft_scan_path_connect

dft_scan_enable_connect { true | tieoff | floating }

set_number_of_scan_chains

set_max_scan_chain_length

set_dont_touch_scan

set_dont_modify

do_optimize

do_place

Examplesdo_xform_connect_scan -pks



do_remove_scan_order_data


You can delete active scan order data with the do_remove_scan_order_data command,so that subsequent add and connect cycles can freely configure and assign scan order usingonly the user constraints set. You may find this technique useful for error recovery orwhenever a change in hierarchy could benefit from regenerating an initial file. (See theCadence Test Synthesis User Guide.)

Related Information

read_scan_order_file

do_xform_connect_scan

Examplesdo_remove_scan_order_data



get_scan_chain_info

get_scan_chain_info { [-test_setup] | [-scan_setup] | [-count] | [-enable] |[-clock [ scan_chain_index ]] | [-length [ scan_chain_index ]] |[-in [ scan_chain_index ]] | [-out [ scan_chain_index ]] | [-name]}

The get_scan_chain_info command returns the information on scan chains that youmay need to generate ATPG information.

Arguments

-test_setup Returns a list of sublists, where each sublist consists of a port IDand its active level that needs to be set during test mode(throughout the test session). In the -name option is used, thecommand returns the pin name rather than the id .

-scan_setupGets the required drive value at the asynchronous pins duringscan-shift mode. This option returns a list of pin IDs and theirrequired logic values. In the -name option is used, the commandreturns the pin name rather than the id .

-count Gets the total number of scan chains.

-enable Gets the scan-enable pin ID and its active value. In the -nameoption is used, the command returns the pin name rather thanthe id .

-clock scan_chain_indexGets the pin ID of the scan clock port of the specified chain andits active edge. The active edge is reported as 0 for negativeedge, 1 for positive edge. In the -name option is used, thecommand returns the pin name rather than the id .

Valid values for scan_chain_index are 1 through thenumber of scan chains. Default: 1

-length scan_chain_indexGets the length of the specified chain. Valid values forscan_chain_index are 1 through the number of scanchains. Default: 1



-in scan_chain_indexGets the pin ID of the scan input port of the specified chain. Validvalues for scan_chain_index are 1 through the number ofscan chains. Default: 1. In the -name option is used, thecommand returns the pin name rather than the id .

-out scan_chain_indexGets the pin ID of the scan output port of the specified chain.Valid values for scan_chain_index are 1 through thenumber of scan chains. Default: 1. In the -name option is used,the command returns the pin name rather than the id .

Examplesget_scan_chain_info -count

get_scan_chain_info -name -in 1

get_scan_chain_info -test_setup




read_scan_order_file file_name

The read_scan_order_file command reads a scan order data file and initializes thescan order data access functions. The scan order file controls the configuration and specificordering of instances and scan chains throughout the hierarchy. In this mode, all other scanconfiguration assertions, such as set_number_of_scan_chains andset_max_scan_chain_length will be ignored.

The test synthesis tool creates a scan order data file when you call thedo_xform_connect_scan or do_optimize command. You can create or edit a scanorder data file to define the order in which registers are connected into scan chains.

Arguments

filename Specifies the name of the scan order data file.

Related Information

write_scan_order_file


Examplesread_scan_order_file new.scan_order



report_dft_assertions

report_dft_assertions [-module { module_id | module_name }

Displays the current settings of the DFT assertions and constraints. When you do not use the-module option, report_dft_assertion displays the DFT assertions for the currentmodule and all the modules below it.

Arguments

-module { module_id | module_name }Reports DFT assertions for the specified module.

Related Information

check_dft_rules

Examplesreport_dft_assertions max_scan_chain_lengthInfo: Module ’seqdes’: maximum scan chain length: 10 <USER-400>



report_dft_registers

report_dft_registers [-scan] [-nonscan][-latch][> | >> file name]

By default, the report_dft_registers command reports whether all register instancesare scanned or non-scanned, and the clock domain in which they exist. For non-scannedregisters, it indicates the reason for their exclusion from scan. You can request informationabout only the scanned registers or only the non-scanned registers.

In addition non-scannable latch instances can be reported using the -latch option.

The output can be directed to a file using > or >>.

You would use this command after running check_dft_rules .

Arguments

-scan Reports only the scan registers.

-nonscan Reports only the non-scan registers.

-latch Reports only the latch instances

Related Information

check_dft_rules

Examplecheck_dft_rulesreport_dft_registers -scan

Scan register instances: ======================== ireg_reg_4 -> [clock-domain 0] ireg_reg_3 -> [clock-domain 0] ireg_reg_5 -> [clock-domain 0] ireg_reg_2 -> [clock-domain 0] ireg_reg_1 -> [clock-domain 0] submod2i/creg_reg_4 -> [clock-domain 0] submod2i/creg_reg_3 -> [clock-domain 0] submod2i/creg_reg_2 -> [clock-domain 0] submod2i/creg_reg_1 -> [clock-domain 0] submod2i/bottom2i/breg_reg_0 -> [clock-domain 0] submod2i/bottom2i/breg_reg_1 -> [clock-domain 0] submod2i/bottom2i/breg_reg_2 -> [clock-domain 0] submod2i/bottom2i/breg_reg_3 -> [clock-domain 0] submod2i/bottom2i/breg_reg_4 -> [clock-domain 0] submod2i/bottom2i/breg_reg_5 -> [clock-domain 0]



submod2i/bottom2i/breg_reg_6 -> [clock-domain 0] submod2i/bottom2i/areg_reg_0 -> [clock-domain 0] submod2i/bottom2i/areg_reg_1 -> [clock-domain 0] submod2i/bottom2i/areg_reg_2 -> [clock-domain 0] submod2i/bottom2i/areg_reg_3 -> [clock-domain 0] submod2i/bottom2i/areg_reg_4 -> [clock-domain 0] submod2i/bottom2i/areg_reg_5 -> [clock-domain 0] submod2i/bottom2i/areg_reg_6 -> [clock-domain 0] submod1i/do_reg_0 -> [clock-domain 0] submod1i/do_reg_1 -> [clock-domain 0] submod1i/do_reg_2 -> [clock-domain 0] submod1i/do_reg_3 -> [clock-domain 0] submod1i/do_reg_4 -> [clock-domain 0] submod1i/do_reg_5 -> [clock-domain 0] submod1i/do_reg_6 -> [clock-domain 0]

Info: Total Scannable register count: 30 <DFT-340>.

30



reset_dft_compatible_clock_domain


This will remove all the previous settings of the commandset_dft_compatible_clock_domain .

Related Information

set_dft_compatible_clock_domain

Examplereset_dft_compatible_clock_domain



reset_dft_internal_clock_domain

reset_dft_internal_clock_domain { <pin_or_net_id> | -net <net> | -pin <pin> }

The command can be used to undo a previous specification of an internal clock as a separateDFT domain. See set_dft_internal_clock_domain .

Arguments

Either one of <pin_or_net_id> , -net <net> , or -pin <pin> should be specified as:

<pin_or_net_id> Must be an existing top-level clock port or net-ID, or uniquifiedinstance output pin or net-ID.

<net> { <name> | <hiername> | <ID> }

<pin> { <name> | <hiername> | <ID> }

<name> Should be an existing top-level clock port/pin name.<hiername> Must be an existing internal hierarchical outputpin name. <ID> Must be of a top clock port or internal instanceoutput pin (uniquified).

Clocks are specified cumulatively by the set_dft_internal_clock_domaincommand. To remove any of the previous settings, use thereset_dft_internal_clock_domain command. This data will apply toset_current_module .

Related Information

set_dft_internal_clock_domain



reset_dft_transparent

reset_dft_transparent [-module { module_id | module_name }] -instance{ instance_id | instance_name } output_port_id | output_port_name [-all]

Removes the virtual connectivity information specified for a black-boxed module, which youpreviously defined with set_dft_transparent .

Arguments

-module { module_id | module_name }When you specify an instance name, specifies the module for theinstance that you want to reset. You do not need to specify themodule for an instance ID.Default: Current module

-instance { instance_id | instance_name }Specifies the instance for which you want to remove theconnectivity data.

-all Specifies that you want to remove the connectivity data for allmodule instances that were previous defined byset_dft_transparent .

Related Information

set_dft_transparent

Examplereset_dft_transparent -all



reset_dont_scan

reset_dont_scan [-module { module_id | module_name }] [-instance{ list_of_instance_id | list_of_instance_name }]

Reverses the effect of the set_dont_scan command. This command allows the specifiedregisters to be included in the scan chain if those registers pass the DFT rule checks.

You need to rerun check_dft_rules before you connect the scan chain, to propagate thechanges through the circuit.

Arguments

-module { module_id | module_name }Specifies the module that you want to reset. All registers in themodule hierarchy that pass DFT rule checking are included in thescan chain.

-instance { list_of_instance_id | list_of_instance_name }Specifies one or more instances that you want to reset. Allregisters in the instance hierarchy that pass DFT rule checkingare included in the scan chain.

Related Information

set_dont_scan

check_dft_rules

Examplesreset_dont_scan 75939 75027check_dft_rules



reset_dont_touch_scan

reset_dont_touch_scan [ module_id | module_name ]

Reverses the effect of a set_dont_touch_scan command. That is, after you call thiscommand, the test synthesis tool may modify and reconfigure existing scan chains inside thismodule in subsequent scan connection runs (do_xform_connect_scan ).

You need to rerun check_dft_rules before you connect the scan chain, to propagate theeffects of this command.

Arguments

module_id Specifies the ID of the module that you want to reset.

module_name Specifies the name of the module that you want to reset.

Related Information

set_dont_touch_scan

Examplesreset_dont_touch_scan submod1

Info: module ’submod1’ cleared of DONT_TOUCH_SCAN mode.

check_dft_rules



reset_must_scan

reset_must_scan [-module { module_id | module_name }] [-instance{ list_of_register_instance_id | list_of_register_instance_name }]

Reverses the effect of a set_must_scan command. That is, the test synthesis tool insertsinto a scan chain only those registers that pass DFT rule checking.


Arguments

-module { module_id | module_name }When you specify an instance name, specifies the module for theinstance that you want to reset. You do not need to specify themodule for an instance ID.Default: Current module

-instance { list_of_register_instance_id | list_of_instance_name }Specifies the module instances that you want to reset.

Related Information

set_must_scan

check_dft_rules

Examplesreset_must_scan -module submod1check_dft_rules



reset_scan_data

reset_scan_data [-module module_id | module_name ] [-clock clock_port_id |clock_port_name ]

Resets the scan-data port assertions to their default settings. The test synthesis tool assignsdefault names or propagates the names applied at the top-timing module (if specified).

Arguments

-clock [ clock_port_id | clock_port_name ]Specifies the clock domain for which you want to reset the scandata port assertions. The clock must be the top timing moduleclock port.

-module module_id | module_nameSpecifies the module for which you want to reset the scan dataport assertions.

Related Information

set_scan_data

Examplesreset_scan_data

reset_scan_data -module m1

reset_scan_data -module m1 -clock clk

check_dft_rules



reset_test_mode_setup

reset_test_mode_setup -module { module_id | module_name } input_port_id |input_port_name

Reverses the effect of a previous set_test_mode_setup command. That is, it clears theinput port of the test mode signal.


Arguments

-module { module_id | module_name }When you specify an input port name, specifies the top-levelmodule for the input port that you want to reset. You do not needto specify the module for an input port ID, unless it is differentfrom the current module.Default: Current module

input_port_id | input_port_nameSpecifies the input port for the test mode signal.

Related Information

set_test_mode_setup

Examplesreset_test_mode_setup -module top scan_enable

Info: Module ’top’ cleared of test mode ’scan_enable = 1’ during entire testsession.

check_dft_rules




set_dft_compatible_clock_domain [ <list_of_clocks> | -sameclock | -all]

This command specifies the compatible clocks whose affected scan flip-flops can be mergedinto a single scan chain using lockup latches in between. Specifying clock A and clock B ascompatible and subsequently clock B and clock C is the same as specifying that clock A, clockB, are clock C are compatible. By default, no clocks (including different phases of the sameclock) are assumed compatible if the command is not specified.

Arguments

Either one of <list_of_clocks> , -same , or -all should be specified as:

<list_of_clocks> One or more of: <clock> [-rise | -fall]

Specifies a particular clock domain. <clock> should be theexisting top-level clock port name or ID. -rise denotes risingedge, and -fall denotes falling edge. When no edge is specified,both domains are assumed to be compatible, if present.

-sameclock Specifies that both edges of each clock are compatible, e.g., ifboth edges of clocks A and B are present (4 domains total), thisis equivalent to the following commands:

set_dft_compatible_clock_domain A

set_dft_compatible_clock_domain B

-all Specifies that all clocks are compatible. This setting supersedesall prior invocations of this command.

The settings of set_dft_compatible_clock_domain are cumulative (except for the-all option). Use the reset_dft_compatible_clock_domain command to remove allprior compatibility settings.

Related Information


Exampleset_dft_compatible_clock_domain clkA clkB clkC



set_dft_compatible_clock_domain [-sameclock | -all]

Check_dft_rules



set_dft_internal_clock_domain

set_dft_internal_clock_domain { <pin_or_net_id> | -net <net> | -pin <pin> }

If there are different internal clock domains logically connected to the same clock input portin test mode, you need to specify the internal clocks even if all the flip-flops belong to thesame logical clock domain.

Note: A data lockup latch will be inserted between the clock domains during scan chainconnection if you specify set_dft_compatible_clock_domain -sameclock . Thisinsures that the scan chain shifs correctly.

All the flip-flops driven by the specified pin are treated as belonging to a separate clockdomain. Such flip-flops must pass all DFT rules, including clock rules such that thoseflip-flop’s clock ports can be driven by a primary input under test mode conditions.

Arguments

Either one of <pin_or_net_id> , -net <net> , or -pin <pin> should be specified as:

<pin_or_net_id> Existing top-level clock port/net ID or internal uniquified instanceoutput pin/net ID. Nonuniquified internal instance output pin/netID is not allowed.

<net> { <name> | <hiername> | <ID> }

<pin> { <name> | <hiername> | <ID> }

<name> Should be an existing top-level clock port/pin name.<hiername> Must be an existing internal hierarchical outputpin name. <ID> Must be of a top clock port or internal instanceoutput pin (uniquified).

Clocks are specified cumulatively by the set_dft_internal_clock_domain command.To remove any of the previous settings, use the reset_dft_internal_clock_domaincommand. This data will apply to set_current_module .

Related Information



reset_dft_internal_clock_domain



Exampleset_dft_internal_clock_domain -net clock_net_A

set_dft_internal_clock_domain -net clock_net_B

set_dft_internal_clock_domain -pin u1/out

set_dft_internal_clock_domain -pin u2/out

IN OUT

IN OUT

CLOCK

U1

U2

clock_net_A

clock_net_B



set_dft_transparent

set_dft_transparent -module { module_id | module_name } [-instance{ instance_id | instance_name }] -from { input_port_id | input_port_name }[-invert] output_port_id | output_port_name

Lets you specify the functional connectivity within a blackboxed module, from an input port toan output port. Otherwise, when your design has blackboxed modules, thecheck_dft_rules command cannot detect whether a direct path exists from a primaryinput to the flip-flops, clock, and set/reset pins of the module, and it reports a DFT violation.

You should use this command only for blackboxed modules, or modules for which you haveprovided no functionality.

Arguments

-module { module_id | module_name }When you specify an instance name, specifies the blackboxedmodule for the instance that you want to set. You do not need tospecify a module for an instance ID.Default: Current module

-instance { instance_id | instance_name }Specifies the blackboxed instance for which you want to specifythe connectivity.

-from { input_port_id | input_port_name } { output_port_id |output_port_name }Specifies the input and output ports that represent a direct paththrough the module or instance.

-invert Specifies that the path is inverted. By default, theset_dft_transparent command assumes that the pathrepresents a direct connection.

Related Information

reset_dft_transparent

Examplesset_dft_transparent -instance [find -hier -instance pll_ins] -from REF CKout



set_dont_scan

set_dont_scan [-module { module_id | module_name }] [-instance{ list_of_instance_id | list_of_instance_name }]

Excludes from the scan chain all of the registers in the specified module or instance hierarchy.You can use this command before or after uniquification of your design (withdo_xform_propagate_constants ). By default, the test synthesis tool tries to includeall registers that pass DFT rule check in the scan chain.

This command determines whether a register is included in the scan chain, so it affects thewiring of the scan chain. This command can affect the area of the design because anyregisters excluded from the scan chain could be mapped to smaller, non-scannable cells.


Arguments

-module { module_id | module_name }Excludes all registers in the specified module hierarchy from thescan chain.

-instance { list_of_instance_id | list_of_instance_names }Excludes all registers in the specified instance hierarchy from thescan chain.

Related Information

reset_dont_scan

check_dft_rules

report_dft_assertions

Examplesset_dont_scan 75939 75027 77859check_dft_rules



set_dont_touch_scan

set_dont_touch_scan [ module_id | module_name ]

Prevents modification or reconfiguring of existing scan chains inside the specified module (ascan-specific equivalent to set_dont_modify on the module). All existing scan chains inthe indicated module are analyzed for suitability and compatibility with scan chains beingconstructed from the top level and are connected accordingly. Any existing module chaincontaining a flip-flop that violates DFT rules will be excluded from connection to outer(top-level) chains.


Arguments

module_id Specifies the ID of the module that you want to leave unchanged.

module_name Specifies the name of the module that you want to leaveunchanged.

Related Information

reset_dont_touch_scan

check_dft_rules

Examplesset_dont_touch_scan submod1

Info: Module ’submod1’ set to DONT_TOUCH_SCAN mode.

check_dft_rules



set_lssd_aux_clock

set_lssd_aux_clock clock

This command sets the auxilliary clock for aux_clocked_lssd scan style. In theaux_clocked_lssd scan style, a regular edge-triggered D-flip-flop is replaced by anaux_clocked_lssd scan cell that has one edge triggered System Clock input andlevel-sensitive scan clocks, scan_clock_a , scan_clock_b and aux_clock .

Arguments

clock { name | hiername | ID }

Required argument. name should be a top-level input port, if itexists. If not, it will be created. hiername must be an existinginstance output pin (may be non-uniquified). ID must be the IDof a top-level input port, or an existing instance output pin (mustbe uniquified).

The clock active edge is assumed to be rising-edge, where applicable. This commandoverrides any previous command setting specified, and applies to the current module.

Related Information

set_scan_style

set_lssd_scan_clock_a

set_lssd_scan_clock_b

Exampleset_lssd_aux_clock aux_test_clock




set_lssd_scan_clock_a clock

This command sets the LSSD scan_clock_a in clocked_lssd or aux_clocked_lssdscan style. In the clocked LSSD scan style, a regular edge-triggered D-flip-flop is replaced bya clocked_lssd scan cell that has one edge triggered System Clock input andlevel-sensitive scan clocks, scan_clock_a and scan_clock_b .

Arguments




Related Information

set_scan_style <clocked_lssd | aux_clock_lssd>


Exampleset_lssd_scan_clock_a clockA




set_lssd_scan_clock_b clock

This command sets the LSSD scan_clock_b for clocked_lssd or aux_clocked_lssdscan style. In the clocked_lssd scan style, a regular edge-triggered D-flip-flop is replacedby a clocked LSSD scan cell that has one edge triggered System Clock input andlevel-sensitive scan clocks, scan_clock_a and scan_clock_b .

Arguments




Related Information

set_lssd_aux_clock {clocked_lssd | aux_clock_lssd}


Exampleset_lssd_scan_clock_b clockB




set_max_scan_chain_length positive_integer

Specifies the maximum length of any scan chain in the current module. If necessary, the testsynthesis tool creates additional scan chains to keep each scan chain at or below the requiredmaximum length. By default, there is no limit to the maximum length of a scan chain.

When both maximum length and set_number_of_scan_chains are specified, maximumlength always takes precedence. When the maximum length for a scan chain is exceeded bythe length of an existing chain inside a set_dont_modify or set_sont_touch_scanmodule, a warning is issued and this dont_touch chain will be placed in a top level chainby itself.

For the recommended use model for this command, see the Cadence Test Synthesis UserGuide.

Arguments

positive_integer Specifies the maximum number of registers allowed in a scanchain.

Related Information


Examplesset_max_scan_chain_length 20



set_must_scan

set_must_scan [-module module_id | module_name }] [-clock { clock_port_id |clock_port_name }] [-rise | -fall ] list_of_register_instance_id |list_of_register_instance_name

Forces a register to be included in a scan chain, even if the register does not pass all DFTrules. If the register fails the clock controllability rule, you must also specify the clock domainto which the register belongs.

You need to rerun check_dft_rules before you connect the scan chain, to propagate theeffects of this command.

Caution

When you use this command, some flip-flops that do not pass DFT rulesmay get placed in scan chains. As a result, the scan shifting operationmay fail in simulation and on the tester. Please use this command rarely,and only when you understand the implications of its use.

Arguments

-module { module_id | module_name }Identifies the module associated with the register instances thatyou want to include in the scan chain. Default: current module.

-clock { clock_port_id | clock_port_name }Specifies the clock domain to which the register belongs. Theclock_port_id or clock_port_name must be the toptiming module’s clock port. You specify this option only if theregister fails the clock controllability rule.

-rise | -fall Specifies the clock edge of the clock domain, when you alsospecify the -clock option. Default: -rise .

list_of_register_instance_id | list_of_register_instance_nameSpecifies the register instances that you want to include in thescan chain. This argument is required.

Related Information

reset_must_scan



check_dft_rules

Examplesset_must_scan -module submod1 docheck_dft_rules




set_number_of_scan_chains positive_integer

Specifies the number of scan chains to create for the current module. Meeting a specifiedmaximum length takes priority over meeting the specified number of scan chains when bothparameters are specified. By default, the tool creates one scan chain for each clock domain.

You cannot use this command to set a smaller number of scan chains than the number ofincompatible clock domains or sets of domains, see the command“set_dft_compatible_clock_domain” on page 501. For example, if you setset_number_of_scan_chains 5 , but your design has 10 compatible clock domaingroups, the test synthesis tool ignores this command and creates 10 scan chains. The toolissues a warning message indicating that the number of scan chains was increased.

For the recommended use model for this command, see the Cadence Test Synthesis UserGuide.

Arguments

positive_integer Specifies the number of scan chains desired.Default:1 scan chain for each clock domain

Related Information


Examplesset_number_of_scan_chains 3



set_scan_data

set_scan_data [-clock clock [-rise | -fall]] scan_in scan_out [-sharedout][-enable scan_enable ]

Specifies the names for the input and output scan data ports. You can use this command tospecify the following:

■ Name for a port that the test synthesis tool creates

■ Name of an existing port

Use -sharedout option if the output port is to be shared with a functional port using amux.

■ Clock domain to which you want to associate the specified port names

Do not use set_scan_data during preliminary synthesis runs (i.e., on lower level modules).Let the test synthesis tool use default names for the scan data ports. In higher-level synthesisruns, the tool discards information that you have set with this command during previoussynthesis runs.

During the final synthesis run of the entire design (when the tool connects the scan chains),use set_scan_data to specify the desired scan data port names for each clock domain.

If a clock domain has multiple scan chains, you can invoke this command multiple times togive a different name to each scan chain data port. Otherwise, the tool would use default portnames for the extra scan chains.

The situations in which the tool does not use the names specified by this assertion are asfollows:

■ If you set this assertion multiple times and use the -clock option in some, but not all,assertions, the tool ignores the names given without the option and uses default namesin their place. For example:

set_scan_data -clock cka -fall sdia sdoaset_scan_data sdib sdob *This assertion ignored*set_scan_data -clock ckc -fall sdic sdoc

■ If you use the same port names for two different clock domains, the tool uses the portname for the clock domain specified first, and ignores the second invocation. Forexample:

set_scan_data -clock cka -fall sdia sdoaset_scan_data -clock ckb -rise sdia sdoa *This assertion ignored*



Arguments

[-clock clock [-rise | -fall]]

This is optional for specifying the clock domain. The clock shouldbe an existing top-level clock port name or ID. Hierarchical/internal clock names or IDs are not allowed.

scan_in { name | hiername | ID } Required for specifying scandata input. name should be top-level port/pin name, if it exists. Ifnot, the port will be created. hiername must be the name of anexisting instance output pin (can be non-uniquified). ID can beID of an existing top-level input port, or hierarchical instanceoutput pin (must be uniquified).

scan_out { name | hiername | ID } Required for specifying scandata output. name shou ld be top-level port/pin name, if it exists.If not, the port will be created. hiername must be the name ofan existing i nstance input pin (can be non-uniquified). ID canbe ID of an existing top-level output port, or hierarchical instanceinput pin (must be uniquified).

-enable scan_enable { name | hiername | ID }

Optional. This is used to designate a chain-specific scan-enableport/pin for the muxscan scan style. If this option is specified, theset_scan_mode command is required for specifying the activepolarity of the scan-enable signal. name must be a top-level port,if it exists. If not, the port will be created. hiername must be anexisting instance output pin (can be non-uniquified). ID must bethe ID of an existing top-level input port, or uniquified instanceoutput pin.

If this command is not used, the scan connection function will create or re-use the defaultscan port names BG_scan_in , and BG_scan_out . The settings from the set_scan_datacommand are cumulative, and apply to the current module set. To undo these settings, usethe reset_scan_data command.

Related Information

set_scan_mode




check_dft_rules

Examplesset_scan_data -clock cka -fall sdia sdoa

set_scan_data sin sout



set_scan_mode

set_scan_mode [-default] scan_enable {0 | 1}

Specifies the name of the input port that activates scan mode (scan shifting), and whether itis active-high (1) or active-low (0). A separate input port to activate scan mode is required bythe multiplexed flip-flop (muxscan ) scan style. If you do not call this command, the toolcreates a default port named BG_scan_enable , which is active-high.

If the port already exists, you must ensure that any logic connected to the port is not neededin system mode. If the named port does not already exist, the test synthesis tool adds thescan mode port to the netlist when you call do_xform_connect_scan

This assertion is propagated to all child modules.

Arguments

[ -default ] Optional. Indicates that the scan_enable specified is thedefault shift control for all scan chains. To specify chain-specificshift control pins, use -enable option in set_scan_datacommand.

scan_enable { name | hiername | ID }

Designates the port/pin used to control scan-shifting for themuxscan scan style. name should be a top-level input port, if itexists. If not, it will be created. hiername must be an existinginstance output pin name (can be non-uniquified). ID must bethe ID of an existing top-level input port or internal instanceoutput pin (but must be uniquified).

{0 | 1} Sets the active polarity desired for the scan enable signal.

The scan_scan_mode command is not cumulative. Each command overrides the previoussettings for the current module.

Related Information

set_scan_style

set_scan_data

check_dft_rules



Examplesset_scan_mode scan_enable 1

set_scan_mode jtag_instance/SE 1



set_scan_style

set_scan_style [muxscan | clocked_scan | clocked_lssd | aux_clocked_lssd]

Selects a scan style for the current module and all child modules. Currently, the test synthesistool supports the multiplexed flip-flop scan style, muxscan, clocked_scan,clocked_lssd, and aux_clocked_lssd .

You must set the appropriate scan style before running check_dft_rules since the DFTrules varies with different scan styles. If no scan style is set, the tool assumes muxscan styleby default.

For information about the muxscan scan style, see the section “Multiplexed Flip-Flop ScanStyle” in the Cadence Test Synthesis User Guide.

Arguments

muxscan Specifies the multiplexed flip-flop scan style.

clocked_scan Specifies clocked scan style.

clocked_lssd Specifies the clocked lssd scan style.

aux_clocked_lssd Specifies the auxiliary scan style.

Related Information

check_dft_rules

Examplesset_scan_style muxscan

set_scan_style clocked_scan

set_scan_style clocked_lssd

set_scan_style aux_clocked_scan



set_test_scan_clock

set_test_scan_clock clock

This command sets the scan_clock for clocked_scan style.

Arguments


Required argument. name should be a top-level input port, if itexists. If not, it will be created. hiername must be an existinginstance output pin (may benon-uniquified). ID must be the ID ofa top-level input port, or an existing instance output pin (must beuniquified). The clock active edge is assumed to berising-edge, where applicable. This command overrides anyprevious command setting specified, and applies to the currentmodule.

Exampleset_test_scan_clock clockA

set_scan_style clocked_scan



set_test_mode_setup

set_test_mode_setup [-module { module_id | module_name }] {input_port_id |input_port_name} { 0 | 1 } -scan_shift [-clock {clock_pin_name | id}]

Specifies the input port and constant value that is assigned during a test session. The testsignal is asserted for the entire test session, unless you specify -scan_shift in which caseit is assumed to be asserted only during the scan_shift operation..

The check_dft_rules command ensures that this environment exists which checking forDFT rule violations.

Arguments

0 | 1 Specifies the value for the test mode signal.

input_port_id | input_port_nameSpecifies the input port for the test mode signal.

-module { module_id | module_name }When you specify an input port name, specifies the top-levelmodule for the input port on which you want to set this assertion.You do not need to specify the module for an input port ID.Default: Current module

-scan_shift Specifies that you want to assert the test signal only during thescan shift session. If you do not specify this option, the test signalis asserted for the entire test session, including the scan shiftsession.

-clock { clock_pin_name | id}

During low-power synthesis this option can be used to specifythat this test mode be used to bypass low-power clock gatinglogic for flip-flops clocked by the identified clock pin.

Related Information

reset_test_mode_setup



Examplesset_test_mode_setup -module top test_mode 1Info: Test mode for module ’top’ set to ’test_mode = 1’ during entire test session.

set_test_mode -scan_shift reset_L 1

check_dft_rules



write_atpg_info

write_atpg_info [-mentor | -syntest | -logicvision]

Creates an interface file containing the scan chain information in a format readable by thedesignated third-party ATPG tool. The third-party ATPG tool uses this interface file togenerate appropriate test patterns. The file extension given to this interface file is determinedby the selected third-party tool.

The interface file is useful only to the third-party tool if the test synthesis tool has connectedthe scan chain. Therefore, you should use this command only if the test synthesis toolconnects the scan chains; that is, if you have set the dft_scan_path_connect globalvariable to chain .

The test synthesis tool does not currently add information about asynchronous controls ortest mode ports to the interface file. If needed, you must add this information manually.

Arguments

-mentor Creates an interface file in the format used by Mentor GraphicsATPG tool.

-syntest Creates an interface file in the format used by SyntestTechnologies ATPG tool.

-logicvision Creates an interface file in the format used by the Logic VisionATPG tool.

Exampleswrite_atpg_info -mentor

write_atpg_info -syntest



write_scan_order_file

write_scan_order_file [-hier | -flat ] filename

Generates a scan order file containing the scan chain information in the format specified. Ifyou do not include a filename, the default filename isset_current_module_name .scan (hierarchical format) orset_current_module_name .scan.flat (flat format).

If you do not specify either -hier or -flat , write_scan_order_file creates hier file.

Arguments

-hier filename Creates only a hierarchical scan order file, organized by themodules with the design hierarchy.

-flat filename Creates only a flat scan order file, which contains a list of thecomplete scan chain in the top-level module that uses fullhierarchical path names, down to each register.

Related Information


Exampleswrite_scan_order_file -hier init.scan_order


Command Reference for Ambit BuildGates Synthesis and Cadence PKSTiming Analysis Commands

7Timing Analysis Commands

This chapter contains information about the following Ambit® BuildGates® synthesis andCadence® physically knowledgeable synthesis (PKS) commands that are used in timinganalysis:

■ check_timing on page 532

■ do_cppr_analysis on page 535

■ do_derive_context on page 537

■ do_time_budget on page 539

■ do_xform_timing_correction on page 542

■ get_cell_drive on page 543

■ get_cell_pin_load on page 545

■ get_clock on page 546

■ get_clock_propagation on page 548

■ get_clock_source on page 549

■ get_constant_for_timing on page 551

■ get_dcl_calculation_mode on page 552

■ get_dcl_functional_mode on page 553

■ get_dcl_functional_mode_array on page 554

■ get_dcl_level on page 555

■ get_derived_clock on page 556

■ get_drive_pin on page 557

■ get_fanin on page 559

■ get_fanout on page 561



■ get_load_pin on page 563

■ get_module_worst_slack on page 564

■ get_operating_parameter on page 565

■ get_scale_delays on page 567

■ get_slack on page 568

■ get_tech_info on page 569

■ get_time_borrow_limit on page 574

■ get_timing on page 575

■ get_top_timing_module on page 578

■ libcompile on page 579

■ load_dcl_rule on page 580

■ read_alf on page 581

■ read_ctlf on page 583

■ read_library_update on page 584

■ read_ola on page 586

■ read_sdf on page 587

■ read_spf on page 591

■ read_spef on page 593

■ read_stamp on page 594

■ read_tlf on page 596

■ remove_assertions on page 598

■ report_annotations on page 600

■ report_cell_instance_timing on page 602

■ report_clocks on page 604

■ report_functional_mode on page 608

■ report_library on page 609

■ report_net on page 611



■ report_path_exceptions on page 615

■ report_port on page 617

■ report_timing on page 622

■ reset_clock_gating_check on page 636

■ reset_clock_root on page 638

■ reset_constant_for_timing on page 639

■ reset_disable_cell_timing on page 640

■ reset_disable_timing on page 641

■ reset_external_delay on page 643

■ reset_functional_mode on page 645

■ reset_input_delay on page 646

■ reset_tech_info on page 648

■ reset_time_borrow_limit on page 653

■ reset_wire_load on page 654

■ reset_wire_load_selection_table on page 655

■ set_begin_tag on page 656

■ set_clock on page 657

■ set_clock_arrival_time on page 660

■ set_clock_gating_check on page 661

■ set_clock_info_change on page 664

■ set_clock_insertion_delay on page 668

■ set_clock_propagation on page 672

■ set_clock_required_time on page 674

■ set_clock_root on page 676

■ set_clock_uncertainty on page 678

■ set_constant_for_timing on page 682

■ set_cycle_addition on page 683



■ set_data_arrival_time on page 689

■ set_data_required_time on page 690

■ set_dcl_calculation_mode on page 692

■ set_dcl_functional_mode on page 693

■ set_dcl_level on page 694

■ set_default_slew_time on page 695

■

■ set_disable_cell_timing on page 696

■ set_disable_timing on page 697

■ set_drive_cell on page 699

■ set_drive_resistance on page 703

■ set_external_delay on page 705

■ set_false_path on page 708

■ set_fanout_load on page 713

■ set_fanout_load_limit on page 714

■ set_functional_mode on page 715

■ set_input_delay on page 716

■ set_max_delay on page 718

■ set_min_delay on page 719

■ set_num_external_sinks on page 720

■ set_num_external_sources on page 721

■ set_operating_condition on page 722

■ set_operating_parameter on page 724

■ set_path_delay_constraint on page 726

■ set_port_capacitance on page 730

■ set_port_capacitance_limit on page 732

■ set_port_wire_load on page 734



■ set_scale_delays on page 735

■ set_slew_limit on page 737

■ set_slew_time on page 738

■ set_slew_time_limit on page 740

■ set_tech_info on page 741

■ set_time_borrow_limit on page 747

■ set_top_timing_module on page 749

■ set_wire_capacitance on page 750

■ set_wire_load on page 752

■ set_wire_load_mode on page 755

■ set_wire_load_selection_table on page 756

■ set_wire_resistance on page 757

■ unload_dcl_rule on page 758

■ write_assertions on page 759

■ write_constraints on page 761

■ write_gcf_assertions on page 763

■ write_library_assertions on page 765

■ write_rspf on page 766

■ write_sdf on page 767

■ write_spf on page 773



Command Descriptions

This section contains descriptions for the timing analysis commands.



check_timing

check_timing[-early] [{> | >> } file_name ]

The check_timing command performs a variety of consistency and completeness checkson the timing constraints specified for a design. Run this command after setting all constraintsbut before executing the do_optimize command or any timing analysis commands, suchas report_timing , to verify that the timing environment is complete and self-consistent.

The checks include arrival time and required time (or external delay) for each clock in amultiple clock system. Clock connectivity, as opposed to data connectivity, is also checked forgated clock analysis. For more information about gated clock checks, see Using GatedClocks in Timing Analysis for Ambit BuildGates Synthesis and Cadence PKS.

This command can be used on generic or mapped netlists.

Important

The check_timing command must be run before any commands that run timinganalysis. Error messages and warnings are displayed when errors occur. Table 7-1on page 533 lists the check_timing errors and warnings. For best results, reruncheck_timing after resolving each error or warning. Redirecting the output to afile is the quickest run method.

Arguments

-earlyReports the early timing inconsistencies along with the late. Bydefault, only the late timing inconsistencies are reported.

file_nameThe name of the output file. Defaults to stdout.

Related Information

check_netlist


Examplescheck_timing > timechk.log



cat timechk.log

--> WARNING: Clock not found at pin ’I/A_reg/CP’, where clock is expected. <TA-101>.

--> WARNING: No required or external delay assertion found at port ’out’ <TA-109>.

--> WARNING: No arrival time assertion found at port ’in’ <TA-104>.

--> WARNING: No arrival time assertion found at port ’clkA’ <TA-104>.

Table 7-1 check_timing Error and Warning Messages

MessageNumber Message Text Comments

TA-100

Data signal where clock isexpected

Typically indicates a problem with generatedclocks or with the set_clock_rootassertion. A generated clock can be modeledwith a set_clock_root command followedby a set_false_path command or a singleset_clock_info_change command.

TA-101Clock not found where clockis expected.

Indicates that no clock signal is defined at theclock pin. Typically accompanies TA-100 errormessage.

TA-102 Multiple signals arrive atpin.

Indicates that a single data signal wastriggered by different clocks.

TA-103

Required time assertiondoes not match any incomingsignal.

The triggered signal does not arrive by therequired time assertion. Check for badconstraints. Use the set_external_delaycommand instead of theset_data_required_time command.

TA-104 No arrival time assertionfound.

TA-105 No arrival time assertionfound for signal.

TA-106 Arrival time assertionwith no clock informationfound at port.

The clock was not specified when theassertion was given. Do not mix theasynchronous @ clocks with regular clocks.

TA-107,TA-108

No drive assertion found atport.

TA-109,TA-110

No required or externaldelay assertion found.

TA-111 Data gating clock at pin’ pin_name ’ <TA-111>.

A warning that the clock is a gated clock.Also see TA-552.



TA-116

Clock not propagatedbeyond pin.

The clock is not propagated because it isconnected to a black box or an output port.Typically indicates a problem with the designlibrary (cells not found in library) or a black-boxphase-locked loop (PLL). You can fix the PLLproblem with aset_clock_insertion_delay commandapplied to the PLL output.

TA-552 Clock clipping at pin’ gclkout ’ is possible dueto incompatiblefrequencies between clocksignal on ’ clk_in ’ anddata signal on ’ data_in ’

A warning that clock clipping can occur on agated clock.

Table 7-1 check_timing Error and Warning Messages , continued

MessageNumber Message Text Comments



do_cppr_analysis

do_cppr_analysis[-slack_limit slack_limit ] [-critical] [-early | -late]

The do_cppr_analysis command removes delay pessimism from paths that have aportion of the clock network in common. Common path pessimism removal (cppr) is theprocess of computing delay adjustments through a clock network to remove the pessimismintroduced at various checks. All timing checks compare a latest arriving signal against anearliest arriving signal. If both signals share a portion of the clock network, then for thecommon clock network, a pessimism equal to the difference in maximum and minimum delayvalues is introduced.

For additional information, see “Common Path Pessimism Removal” in the Timing Analysisfor Ambit BuildGates Synthesis and Cadence PKS manual.

Arguments

-slack_limit slack_limitRemoves clock pessimism only from paths whose slack is worsethan the specified slack limit. This option can be used as anefficiency measure to reduce CPU and memory usage.

-criticalStops the common path pessimism removal process at eachendpoint, as soon as the most critical path to that endpoint hasits pessimism removed. This option can be used as an efficiencymeasure to reduce CPU and memory usage.

-early | -lateSpecifies pessimism removal from either early or late data paths.By default, the command removes pessimism from both earlyand late paths.

Related Information

set_global pvt_early_path

set_global pvt_late_path

set_operating_condition



Examplesdo_cppr_analysis -slack_limit 3.2



do_derive_context

do_derive_context[list_of_ instances ]

The do_derive_context command builds the characteristics of the design from itsenvironment constraints. A context-based optimization approach requires that constraints forlower level modules be derived from the higher level modules. This is one of the fundamentalcapabilities for performing top-down hierarchical synthesis. The constraints set at the top levelof the design are pushed down the hierarchy so that each of the lower level modules areoptimized using the correct set of constraints. Later, as the higher level modules are groupedtogether, the optimized modules are all connected correctly with respect to each other.

The do_derive_context command derives the worst condition for modules among all theinstances specified in the list of instances, in a similar manner to that performed by the timebudgeting procedure.

The context is derived by extracting three types of constraints from the surroundingenvironment of the instances in the instance list. The name of the instances can behierarchical and are related to the current module:

■ Interface timing constraints

The interface timing constraints include timing information about clock definitions, arrivaltime on input ports, required time on output ports, and identification of multicycle andfalse paths.

■ Electrical constraints

The electrical constraints include port capacitance and resistance, number of drivers,and load for every port of every instance.

■ Logic value constraints

These include the logic constants that block timing analysis.

Note: The derived context information is stored in the database. The commandwrite_assertions must be executed to store the constraints in a file.

Arguments

list_of_instancesList of instance names for which the context is derived. If theinstance name is specified by a hierarchical path name, thecontext is derived only for that instance in the hierarchy.



The instance name is relative to the current module. The currentmodule must be unique in the context of the top timing module.If not, execute the do_uniquely_instantiate command.

If the instance list is not provided, the default is the currentmodule.

Related Information


do_optimize

write_assertions

do_time_budget

Examplesdo_derive_context [find -inst *]

do_derive_context blkA/xbar



do_time_budget

do_time_budget[-top list_of_top_instances ] | [ list_of_instances ]

Time budgeting is the process of splitting the combinational delay requirements acrossmodule boundaries to allocate slack across all modules in a fair manner. Thedo_time_budget command generates realistic time estimates for the modules specified inthe instance list. The segments of paths entirely contained in the instance list are consideredto be changeable, while all other paths are considered to be fixed.

The do_time_budget command does the following:

■ Writes assertions on the instances in the database. The commandwrite_assertions or write_adb can be used to save the result of time budgeting.

■ Finds the worst constraints for a module from all those available (if the module is used inmany contexts under the top timing module).

■ Accepts the dont_modify flags on instances and modules in the computation ofconstraints.

The reference of the hierarchical instances starts from the current module as specified by theset_current_module command. The current module must be unique in the scope of thetop timing module as set by the set_top_timing_module command.

Note: The time budgeting algorithm handles both positive and negative slacks.

A “changeable” path or block is one that can be modified during synthesis to meet timingconstraints, whereas a “fixed” one cannot be modified. Normally you specify as fixed the hardmacros or other blocks that you do not want the optimizer to touch. There are two ways tospecify such fixed blocks:

■ Use the dont_modify switch for such instances

■ Use the -top option only for blocks that can be modified

if you issue the command without any options

do_time_budget

then all instances (except those having the dont_modify switch) are assumed to bechangeable. And Ambit BuildGates synthesis creates budgets for all the instances.

If you want to create the budgets only for specific modules, use

do_time_budget {inst1 inst2 ...}

For example, if you want only a specific instance (inst1 ) to be changeable and all



others fixed, you would use

do_time_budget inst1

Note: The above commands still assume that all the instances except those markeddont_modify are changeable.

Arguments

list_of_instancesList of instances for which time budgeting is to be performed. Theinstances in the instance_list must all be hierarchicalentities. If the instance_list is not specified then the defaultis to generate budgets for all instances within the current module.The time budget assumes that only the delay arcs (paths)entirely within the specified instances can be optimized. Theothers are considered to be fixed.

Depending on the number of instances in the current module,omitting the instance list can result in long run times.

-top list_of_top_instancesCreates a top timing module from which to start the synthesis.The listed instances are considered part of the top context. Onlythose sub-designs that exist under the list of top instances aresynthesized. The time budget assumes that only the delay arcs(paths) within and between the specified top instances can beoptimized. The others are considered to be fixed.

The default assumes that everything under the top timing modulecan be changed. The dont_modify switch for instances andmodules overrides this.

Related Information

set_current_module


do_derive_context

set_dont_modify



Examples

The circuit is shown in Figure 7-1 on page 541. The following command performs timebudgeting on the instances X1, X2, and X3, assuming that all delay arcs contained withinthese instances are changeable and all others are fixed. The paths p2 , p4 , and p6 arechangeable and the others are treated as fixed. This is because the top contains only p2 , p4 ,and p6 , while p1 , p3, p5 are outside the boundaries of the top context.

do_time_budget -top {X1 X2 X3}

The effect of the following command is different from the earlier one because now thecommand assumes only paths in and between X1 and X2 instances to be changeable andX3 to be fixed. As a result, the time budgeting algorithm derives a new set of constraints sinceonly the paths p2 and p4 are changeable while the others are fixed.

do_time_budget -top {X1 X2}

Figure 7-1 do_time_budget Example

X1 X2 X3

p2

p4

p6

p1 p3p5

X5X4




See do_xform_timing_correction on page 108.



get_cell_drive

get_cell_drive[-library library_name ] -cell cell_name[-from_pin from_pin_name ] [-from_pin_rise] [-from_pin_fall][-rise] [-fall] [-early | -late]-pin pin_name

The get_cell_drive command returns the resistance value at the specified output port ofa cell in the library. For a library having nonlinear delay models, the returned value is theresistance as seen at the specified output pin if the output pin were to drive the input pinhaving the worst capacitance of the same cell. (In other words, the resistance is linear at thepoint as if the cell is driving itself.)

The returned value is a real (floating point) number. The units of resistance are the same asthe units used in the technology library. By default, the worst resistance found in rising, falling,from-pin rising, from-pin falling, early and late modes is returned.

Arguments

-cell cell_nameName of the cell whose output port is specified by the -pinargument.

-pin pin_nameName of the output port whose resistance will be returned. Ifthere is more than one path terminating at the pin_name , thelargest resistance seen among all paths is returned.

-library library_nameName of the library where the cell can be found. By default, thetarget library.

-riseReturns the resistance corresponding to rising edge only.

-fallReturns the resistance corresponding to falling edge only.

-from_pin from_pin_nameSpecifies the input port name as the starting point of the path forwhich the resistance is returned.



-from_pin_riseReturns the resistance corresponding to rising signal at the frompin only.

-from_pin_fallReturn the resistance corresponding to falling signal at the frompin only.

-early | -lateReturns the resistance corresponding to early (hold) or late(setup) modes only.

Related Information

get_cell_pin_load

set_global target_technology

Examples>get_cell_drive -cell BUFA -from_pin A -pin Z

1.920189

>get_cell_drive -cell BUFA -from_pin A -from_pin_fall -pin Z

1.368688



get_cell_pin_load

get_cell_pin_load[-library library_name ] -cell cell_name -pin pin_name

The get_cell_pin_load command returns the value of the capacitive load at the specifiedpin of a cell in the library. The returned value is a real (floating point) number. The units of theload are the same as the units used in the library.

Arguments

-library library_nameName of the library where the cell can be found. By default, thetarget library is searched for the cell.

-cell cell_nameName of the cell whose pin is specified by the -pin argument.

-pin pin_nameName of the pin whose capacitive load will be returned.

Related Information

get_cell_drive


Examplesget_cell_pin_load -cell IV -pin z



get_clock

get_clock[ clock_name ] [-period | -waveform | -lead | -trail]

The get_clock command returns the information of clocks defined in the database throughthe set_clock command.

Arguments

clock_nameIf the clock name is specified, the information for that clock isreturned. By default, a list of all currently defined clocks isreturned and all other command line options are ignored.

-periodReturns the period of the specified clock.

-waveformReturns the waveform of the specified clock in the form of{ lead , trail } .

-lead Returns the leading edge of the specified clock.

-trailReturns the trailing edge of the specified clock.

Related Information

set_clock

get_clock_source

Examples

The following command defines the clock named CLOCK.

ac_shell[1]>set_clock CLOCK -period 4.0 -wave {0 2.0}

This command gets clock-related information for CLOCK.

ac_shell[2]>get_clock -period CLOCK

4.0



The following command gets the name of all the defined clocks.

ac_shell[2]>get_clock

CLOCK



get_clock_propagation


The get_clock_propagation command returns the value of the clock propagation mode(ideal or propagated ) associated with the current top timing module.

Note: Because this command returns the clock propagation mode associated with a design,a design must be loaded before this command can be used.

Related Information

set_clock_propagation

Examplesac_shell[2]>get_clock_propagation

ideal



get_clock_source

get_clock_source[-port_only] [ clock_name ]

The get_clock_source command returns the list of clock names (sources) for thedefined clock clock_name in the database. The clock sources can be specified through theset_clock_root command.

Note: In releases prior to 4.0.8, this command returned clock object ids instead of names.

Arguments

clock_nameIf the clock name is specified, the clock sources (input ports orinstance output pins) set on the named clock are returned. If thisoption is omitted, all clock sources specified in the currentdatabase are returned.

-port_onlyReturns only the clock sources that are input ports.

Related Information

set_clock

get_clock

set_clock_root

get_derived_clock

Examples

Define the clock CLK

ac_shell[1]>set_clock CLK -period 4 -waveform {0 2}

Define the clock source clk_in

ac_shell[2]>set_clock_root -clock CLK clk_in

Get the clock source for clock CLK

ac_shell[3]>get_clock_source CLK

clk_in





get_constant_for_timing

get_constant_for_timingpin_name

The get_constant_for_timing command queries the design database for the state ofthe specified pin or the state propagated through the combinational logic cone to that pin. Thereturned value is 0 for logic 0, 1 for logic 1, or X if no constant has been set.

Note: Constants on hierarchical ports are not computed.

Tip

The get_constant_for_timing command returns the state for one pin only. Ifyou want to know the state on all pins that have a constant set, use the -typeconstant option of report_port as shown:

report_port -type constant

Use the -tcl_list option if you want to process the list in Tcl.

Arguments

pin_nameSpecifies the name of the single pin to query for pin state. Thepin must be an instance pin or primary IO port.

Related Information

set_constant_for_timing

reset_constant_for_timing

report_port

Examplesac_shell[8]>set_constant_for_timing 0 J_block/zbuf0/A

ac_shell[9]>get_constant_for_timing J_block/zbuf0/A

0



get_dcl_calculation_mode


The get_dcl_calculation_mode command returns the current DCL calculation mode.

Calculation modes defined in the DCL library allow the vendor library developer to modelthree process conditions (best_case , nominal_case , and worst_case ) within onelibrary. You choose the mode with the set_dcl_calculation_mode command.

Note: Temperature, process multiplier, and voltage are set independently of the calculationmode using the set_operating_parameter command.

Related Information

set_dcl_calculation_mode

set_operating_parameter

get_operating_parameter

load_dcl_rule

Examplesac_shell[6]>get_dcl_calculation_mode

worst_case



get_dcl_functional_mode

get_dcl_functional_modeinstance

The get_dcl_functional_mode command returns the current DCL functional mode onthe specified hierarchical instance. The value returned is a TCL list where the currentfunctional mode group for the instance is the first element in the list and the current functionalmode value is the second element in the list.

Functional modes defined in a DCL library allow the library developer to model the timing arcsand timing checks for a technology cell in a variety of ways. For instance, a scan flip-flop couldhave functional modes defined for normal flip-flop behavior and for scan behavior where, foreach mode, different timing arcs and checks are defined.

Arguments

instanceThe hierarchical instance for which the DCL functional modeneeds to be obtained.

Related Information

get_dcl_functional_mode_array

set_dcl_functional_mode

load_dcl_rule

Examples

The following example shows that the current functional mode group for instance A1/B3/C2is latch_type and the value is transparent .

>get_dcl_functional_mode A1/B3/C2

{latch_type transparent}




get_dcl_functional_mode_array-cell cellname

The get_dcl_functional_mode_array command returns the DCL functional modearray on the specified library cell. This array lists all of the functional modes available for thelibrary cell by group. The array is returned as a hierarchical TCL list.

Functional modes defined in a DCL library allow the vendor library developer to model thetiming arcs and timing checks for a technology cell in a variety of ways. For instance, a scanflip-flop could have functional modes defined for normal flip-flop behavior and for scanbehavior where, for each mode, different timing arcs and checks are defined.

Arguments

-cell cellnameSpecifies the library cell for which the DCL functional mode arrayneeds to be obtained.

Related Information

load_dcl_rule



Examplesac_shell[18]>get_dcl_functional_mode_array -cell ram_8_8

{

{rw { read write}} {latch_type {latching transparent}}

}



get_dcl_level

get_dcl_level-perfLevel

The get_dcl_level command returns the current level being used in DCL based delay andslew calculations. At this time, only the performance level can be returned.

DCL supports two performance levels for delay calculation. One performance level targetsfaster run time with less accurate timing while the other targets more accurate timing withslower run time.

Refer to the DCM library vendor documentation for information about the characteristics ofeach performance level in their library and whether or not they are both supported. Use thefaster performance in terms of run time for initial synthesis. For final timing correction, use themore accurate level.

Arguments

-perfLevelReturns the current performance level.

Note: The DCL standard contains other types of levels which, if supported in the future, willbe accessible via other arguments. These other types include temperatureScope ,voltageScope , functionalModeScope , and wireloadModelScope .

Related Information

set_dcl_level

load_dcl_rule

Examplesac_shell[19]>get_dcl_level -perfLevel

1



get_derived_clock

get_derived_clock[-full_path_name] [ instance_path_or_id ]

The get_derived_clock command reports the derived clock sources for all sequentialinstances or for the specified instance.

The derived clocks are found by traversing backwards from the clock pin of sequentialinstances until reaching an output of a non-single-input-single-output combinational instance,or a sequential output (divided clock, for example), or a primary input port.

Note: If the clock: true attribute is not present in the library, the input pin on a RAM/ROMwith setup/hold timing check is also treated as clock pin.

Arguments

instance_path_or_idSpecifies a sequential instance by path or object identifier. If noinstance_path_or_id is specified, derived clocks for allsequential instances (ff and latch ) are reported.

-full_path_nameReturns a list of full path names for derived clocks. If this optionis not specified, pin object identifiers are returned.

Related Information

set_clock_info_change

Examplesac_shell[22]>get_derived_clock -full_path_name

TCLK3

COREP_P2/BEP_P2/I14P/Q

COREP_P2/BEP_P2/I25P/Q

CS



get_drive_pin

get_drive_pin[-hierarchical] [-full_path_name] net_path_or_id

The get_drive_pin command returns a list of drive pins that drive a given net within thecurrent module.

Note: For multiple driver situations get_drive_pin returns a list of pin identifiers.

Arguments

net_path_or_idSpecifies the net for which you want to know the driver pin. Thenet can be specified by full path name or object ID.

-hierarchicalEnables traversal across a hierarchy if the given net crosses ahierarchy boundary.

-full_path_nameReturns the full path name for the drive pin, rather than the pinobject identifier. By default, object identifiers are returned.

Related Information

get_load_pin

Examples

For the circuit shown in Figure 7-2 on page 558:

ac_shell[10]>get_names [get_drive_pin [find -net w00]]

out

ac_shell[11]>get_drive_pin -full_path_name w00

I_block/out



Figure 7-2 get_drive_pin Example

I_block J_block

w00out



get_fanin

get_fanin[-level integer ] [-tristate] [-sequential] [-hierarchical] [-full_path_name]list_of_pin_path_or_id

The get_fanin command returns a Tcl list of all begin points (output pins and input ports)in the fanin cone.

The -tristate and -sequential options give you finer control of the gate type to beincluded in the fanin cone.

The command can take a hierarchical path name as well as pin object identifier. Specifying ahierarchical name is useful when a module is not uniquely instantiated.

Arguments

list_of_pin_path_or_idStarts the fanin cone search from the specified Tcl list of pins orports specified by path names or object identifiers.

-level integerLimits the search to the number of logic levels specified.

-hierarchicalAllows the search to cross hierarchy boundaries. The defaultsearch stops at input ports and returns the port as the startingpoint.

-full_path_nameReturns the hierarchical path name for the starting points,starting from the current module. By default, pin object identifiersare returned.

-tristateIncludes tristate cells in the fanin path. By default, tristates areexcluded.

-sequentialIncludes sequential cells in the fanin path. By default, sequentialcells are excluded.



Related Information

get_fanout

do_extract_fanin

do_extract_fanout

Examplesac_shell[23]>get_fanin -hierarchical -full_path_name out*

J_block/C_reg/Q J_block/D_reg/Q

The following Tcl script Iterates over all the begin points of the fanin cone of net req

foreach i [get_fanin [find -net req]] {

puts "Found fanin [get_names $i]"

}



get_fanout

get_fanout[-level integer ] [-tristate] [-sequential] [-hierarchical] [-full_path_name]list_of_pin_path_or_id

The get_fanout command returns a Tcl list of all endpoints (input pins and output ports) inthe fanout cone.

The -tristate and -sequential options give you finer control of the gate type to beincluded in the fanout cone.

The command can take a hierarchical path name as well as pin object identifier. Specifying ahierarchical name is useful when a module is not uniquely instantiated.

Arguments

list_of_pin_path_or_idStarts the fanout cone search from the specified Tcl list of pinsor ports specified by path names or object identifiers.

-level integerLimits the search to the number of logic levels specified.

-hierarchicalAllows the search to cross hierarchy boundaries. The defaultsearch stops at output ports and returns the port as the endingpoint.

-full_path_nameReturns the hierarchical path name for the starting points,starting from the current module. by default, the pin objectidentifiers are returned.

-tristateIncludes tristate cells in the fanout path. By default, tristates areexcluded.

-sequentialIncludes sequential cells in the fanout path. By default,sequential cells are excluded.



Related Information

get_fanin

do_extract_fanin

do_extract_fanout

Examples

The following command returns the names of endpoints of the fanout cone of any portswhose names begin with characters in .

get_fanout -full_path_name [find -port in*]

The following Tcl script Iterates over all the endpoints of the fanout cone of net req .

foreach i [get_fanout [find -net req]] {

puts "Found fanout[get_names $i]"

}



get_load_pin

get_load_pin[-hierarchical] [-full_path_name] net_path_or_id

The get_load_pin command returns a list of load (sink) pins for the given net within thecurrent module and in the sub-modules.

Note: For multiple load situations the get_load_pin command returns a list of pinidentifiers.

Arguments

net_path_or_idSpecifies the net for which you want to know the load pin. Thenet can be specified by full path name or object ID.

-hierarchicalEnables traversal of the design hierarchy when the given netconnects to an output port.

-full_path_nameReturns a list of full path names of load (sink) pins. By default theobject identifiers are returned.

Related Information

get_drive_pin

get_fanout

get_fanin

Examplesget_load_pin -full_path_name [find -net out]




get_module_worst_slack[-clknet_too] [-early | -late]

The get_module_worst_slack command returns the worst slack time for the module andall of its children. The module that is set as the current module is searched for the worst slacktime on its paths.

If there are negative slack paths in the module, the returned value is the most negative value.If there are no negative slack paths in the module, the returned value is the least positive slackvalue.

Arguments

-clknet_tooIncludes clock nets while searching for the worst slack time on allpaths in the module. By default, slack time on clock nets is notconsidered.

-early | -lateIndicates whether the worst slack time should be considered onearly arrivals (hold) or late arrivals (setup) of signals. If neitheroption is specified, the default is to obtain worst slack time for latearrivals on signals.

Related Information

set_current_module

Examplesget_module_worst_slack -early




get_operating_parameter{-process | -voltage | -temperature} [-pvt {min | typ | max}]

The get_operating_parameter command is used to query the process, voltage, andtemperature currently being used for delay calculation.

Only one of the parameter options can be specified per command.

Arguments

-processReturns the process multiplier.

-voltageReturns the operating voltage.

-temperatureReturns the operating temperature.

-pvt {min | typ | max}Returns the operating parameter for a particular PVT (process,voltage, temperature) corner. You can choose one, two, or threePVT corners. If you choose more than one corner, enclose thelist in curly braces ({} ) and separate the values by spaces. Bydefault, the typ value is returned.

Related Information



load_dcl_rule

Examplesac_shell[8]>get_operating_parameter -voltage -pvt {min max}

3.100000 3.500000

ac_shell[9]>get_operating_parameter -process

1.000000

ac_shell[10]>get_operating_parameter -temperature



25.000000



get_scale_delays

get_scale_delays[-cell | -net] [-pvt {min | typ | max}]

The get_scale_delays command returns the value of the delay scaling factor for aspecific PVT corner (min, typ, or max) for cells or nets.

Arguments

-cellReturns the delay scaling factor on cells.

-netReturns the delay scaling factor on nets.

If neither -cell nor -net is specified, the scaling factor for cellsis returned. You cannot specify both -cell and -net in thesame command.

-pvt {min | typ | max}Returns the delay scaling factor for a particular PVT (process,voltage, temperature) corner. You can choose one, two, or threePVT corners. If you choose more than one corner, enclose thelist in curly braces ({} ) and separate the values by spaces. Bydefault, the max PVT corner delay scaling factor is returned.

Related Information

set_scale_delays

Examples

The following commands return delay scaling factor for nets.

ac_shell[7]>get_scale_delays -net -pvt min

0.950000

ac_shell[8]>get_scale_delays -net -pvt max

1.050000

The following command returns cell delay scaling factor for the max PVT corner.

ac_shell[9]>get_scale_delays

1.050000



get_slack

get_slack[-early | -late] net_or_pin_id

The get_slack command returns the slack of the given net or pin. The late mode slack isthe worst case required time minus the worst case arrival time.

Arguments

net_or_pin_id

{-early |-late}

-earlyReports the amount of time that the signal misses or passes thehold check. If the signal changes before the required hold time,it is early. Early slack is calculated as arrival time minus requiredtime. If the signal arrives after the required hold time, there is noviolation and the slack is positive. This is the opposite of lateslack.

-lateReports the amount of time that the signal misses or passes thesetup check. If the signal changes after the required setup time,it is late. Late slack is calculated as required time minus arrivaltime. If the signal arrives before the required setup time, there isno violation and the slack is positive. Late check reports are thedefault.

Related Information


get_area

Examplesac_shell[6]>get_slack [find -net out]

-2.000000



get_tech_info

get_tech_info{([-library list_of_library_names ]{[-default_wire_load] | [-default_wire_load_selection] |[-default_operating_conditions] |[-default_fanout_load] | [-default_max_capacitance] |[-default_max_fanout] | [-default_max_transition] |[-input_threshold_pct_rise] | [-input_threshold_pct_fall] |[-output_threshold_pct_rise] | [-output_threshold_pct_fall] |[-slew_lower_threshold_pct_rise] | [-slew_lower_threshold_pct_fall] |[-slew_upper_threshold_pct_rise] | [-slew_upper_threshold_pct_fall]}[-pvt {min | typ | max}])|([-library list_of_library_names ]-cell list_of_cell_names{[-dont_modify] | [-dont_utilize] |[-scaling_factors] |[-input_threshold_pct_rise] | [-input_threshold_pct_fall] |[-output_threshold_pct_rise] | [-output_threshold_pct_fall] |[-slew_lower_threshold_pct_rise] | [-slew_lower_threshold_pct_fall] |[-slew_upper_threshold_pct_rise] | [-slew_upper_threshold_pct_fall]}}[-pvt {min | typ | max}])|([-library list_of_library_names ]-cell list_of_cell_names-pin list_of_pin_names{[-fanout_load] | [-max_fanout] |[-max_transition] | [-max_capacitance]}[-pvt {min | typ | max}])}

The get_tech_info returns the data for the specified library parameters in the namedtarget libraries. The data can come either from the library itself or the overrides (assertions)as previously specified with the set_tech_info command.

Arguments(any level)

-library list_of_library_namesReports data for the named libraries. Default is all librariesspecified with the set_global target_technologycommand.

-pvt { min | typ | max}Returns the value for the environment corner of interest. You canspecify one PVT corner at a time. The default is typ .



Arguments(library level)

-default_wire_loadReturns the default wire-load model for the library.

-default_wire_load_selectionReturns the default wire-load selection table for the library.

-default_operating_conditionsReturns the default operating conditions for the library.

-default_fanout_loadReturns the value of the default fanout load for all pins on all cellsin the library.

-default_max_capacitanceReturns the value of the default maximum capacitance for allpins on all cells in the library.

-default_max_fanoutReturns the value of the default maximum fanout for all pins onall cells in the library.

-default_max_transitionReturns the value of the default maximum transition time for allpins on all cells in the library.

-input_threshold_pct_rise floatResets the value of the default input threshold percent for therising edge for all cells in the library.

-input_threshold_pct_fall floatReturns the value of the default input threshold percent for thefalling edge for all cells in the library.

-output_threshold_pct_rise floatReturns the value of the default output threshold percent for therising edge for all cells in the library.

-output_threshold_pct_fall floatReturns the value of the default output threshold percent for thefalling edge for all cells in the library.



-slew_lower_threshold_pct_rise floatReturns the value of the default lower threshold percent for theslew time of the rising edge for all cells in the library.

-slew_lower_threshold_pct_fall floatReturns the value of the default lower threshold percent for theslew time of the falling edge for all cells in the library.

-slew_upper_threshold_pct_rise floatReturns the value of the default upper threshold percent for theslew time of the rising edge for all cells in the library.

-slew_upper_threshold_pct_fall floatReturns the value of the default upper threshold percent for theslew time of the falling edge for all cells in the library.

Arguments(cell level)

-cell list_of_cell_namesReports assertions on the named cells. Required argument forcell and pin level assertions.

-dont_modifyReturns true or false . If true , the cell is not modified inoptimization or time budgeting.

-dont_utilizeReturns true or false . If true , the cell is not used inoptimization.

-scaling_factorsReturns the name of the derating table used for scaling.

-input_threshold_pct_rise floatReturns the value of the default input threshold percent for therising edge for the listed cells.

-input_threshold_pct_fall floatReturns the value of the default input threshold percent for thefalling edge for the listed cells.



-output_threshold_pct_rise floatReturns the value of the default output threshold percent for therising edge for the listed cells.

-output_threshold_pct_fall floatReturns the value of the default output threshold percent for thefalling edge for the listed cells.

-slew_lower_threshold_pct_rise floatReturns the value of the default lower threshold percent for theslew time of the rising edge for the listed cells.

-slew_lower_threshold_pct_fall floatReturns the value of the default lower threshold percent for theslew time of the falling edge for the listed cells.

-slew_upper_threshold_pct_rise floatReturns the value of the default upper threshold percent for theslew time of the rising edge for the listed cells.

-slew_upper_threshold_pct_fall floatReturns the value of the default upper threshold percent for theslew time of the falling edge for the listed cells.

Arguments(pin level)

-pin list_of_pin_namesReports assertions on the named pins. Required argument forpin level assertions.

Note: The pin assertions apply to a specific pin type. If the correct pin type is not specified,an error is flagged.

-fanout_loadReturns the value of the fanout load for the named pins. Thisoption can be specified only for an input pin.

-max_fanoutReturns the value of the maximum fanout for the named pins.This option can be specified only for an output pin.



-max_transitionReturns the value of the maximum transition time for the namedpins. This option can be specified for both input and output pins.

-max_capacitanceReturns the value of the maximum capacitance for the namedpins. This option can be specified only for an output pin.

Related Information

set_tech_info

reset_tech_info

write_library_assertions


Examples

These examples follow those of set_tech_info .

ac_shell>get_tech_info -library lib1 -default_fanout_load1.411100

ac_shell>get_tech_info -cell FD2ESSA -dont_utilizetrue

ac_shell>get_tech_info -library lca300kv -cell B2I -pin Z1 Z2 -pvt min -max_fanout

3.000000



get_time_borrow_limit

get_time_borrow_limit -pin pin_list -clock list_of_clocks

The get_time_borrow_limit command returns the limit on time that can be borrowed byone cycle from the next cycle as previously specified with the set_time_borrow_limitcommand. You can query for borrow limits on pins or waveforms.

Arguments

-pin pin_or_instance_listReturns the borrow time limit for a single pin on a latch.

You can alternatively give one latch instance name. whichreturns the assertion for the clock pin of the instance.

-clock list_of_clocks

Returns the borrow limit for the specified list of ideal clocknames.

Related Information

reset_time_borrow_limit

set_time_borrow_limit

Analyzing Latch-based Designs in the Timing Analysis for Ambit BuildGates Synthesisand Cadence PKS manual.

Examples>get_time_borrow_limit -pin l1/q

3.0



get_timing

get_timing[-early | -late] [-rise | -fall] pin_path_or_id{arrival | required | edge | slack | slew | stolen| cell | net | instance | pin | clkordata | clkordatapin | phase | load| pinload | wireload | fanout | hpin}

The get_timing command retrieves timing information for the specified pin property on thegiven pin. The pin can be specified by object ID or hierarchical name. Only one pin is allowedper command.

Arguments

pin_path_or_idSpecifies the port or pin for which timing information is to bereturned. The port or pin can be specified by object ID orhierarchical name.

-early | -lateSpecifies analysis type, either early or late. The default is late.

-rise | -fallSpecifies the edge, either rise or fall. The default is the edge withthe worst timing.

arrivalReturns the arrival time of the worst slack causing path at thegiven pin.

requiredReturns the required time of the worst slack causing path at thegiven pin.

edgeReturns the edge of the worst slack causing path at the given pin.Rising edge is ^ , falling edge is v.

slackReturns the worst slack at the given pin.

slewReturns the propagated slew at the given pin.



stolenReturns the slack stolen at the given pin (only visible on theoutput of transparent latches).

cellReturns the cell of the given pin’s instance.

netReturns the hierarchical name of the net connected to given pin.

instanceReturns the hierarchical name of the given pin’s instance.

pinReturns the pin name of the given hierarchical pin.

clkordataTells you whether the specified path is of type clock or of typedata. The default behavior for get_timing is to returninformation about the most critical path. This behavior can bechanged by use of the -rise or -fall option.

clkordatapinTells you whether the specified pin expects a clock or data signal.This information is currently derived from the library, except in thecase of output ports. Output ports are considered of type DATAif there is a delay constraint asserted on the port. This behavioris consistent with the check_timing command. This option isnot path dependent.

phaseReturns the phase of a pin in the same format asreport_cell_instance_timing .

loadReturns the total capacitive load on a given pin.

pinloadReturns the total capacitive load from pins on a given pin,including its own load.

wireloadReturns the total capacitive load from the wire on a given pin.



fanoutReturns the total fanout on a given pin.

hpinReturns the full hierarchical name of the pin. Equivalent to-full_path_name option of get_fanin , get_fanout , orfind .

Related Information

report_timing

report_cell_instance_timing

report_net

report_port

set_global slew_propagation_mode

report_precision

Examplesac_shell[18]>get_timing i00/Z arrival

1.23

ac_shell[19]>get_timing i00/Z net

n001

ac_shell[20]>get_timing in edge

^

ac_shell[21]>get_timing clkC clkordata

CLOCK

ac_shell[22]>get_timing clkC phase

CLK2(C)(P)



get_top_timing_module

get_top_timing_module

The get_top_timing_module command returns the object ID of the module which wasdesignated as the top timing module by the set_top_timing_module command.

Related Information


get_names

Examplesac_shell[12]>get_top_timing_module

67841

ac_shell[13]>get_names 67841

top



libcompile

libcompile (UNIX command) [-help] [-version] [-expire] [-queue] [-ipformat][-debug] [-verbosity level ] [-logfile file_name ]library_file_name output_file_name

The libcompile command converts Synopsys Liberty (.lib ) libraries into AdvancedLibrary Format (.alf ) a format readable by Ambit BuildGates synthesis. For moreinformation, see Using Synopsys .lib Libraries in the Timing Analysis for AmbitBuildGates Synthesis and Cadence PKS manual.

Note: You must execute the libcompile command from the UNIX prompt, not fromac_shell .



load_dcl_rule

load_dcl_rule

The load_dcl_rule command loads a binary Delay and Power Calculation Module(DPCM) into memory. The DPCM is an executable shared library that is linked to anapplication (like Ambit BuildGates synthesis) at runtime. DPCM is often abbreviated as DCM.After loading the DCM, all timing calculations are performed using delay tables and equationsdefined in the DCM.

Note: Before a DCM can be loaded, certain environment variables must be set beforeac_shell is invoked. The following list shows an example.

setenv DCMRULEPATH /dcl_libs/sample_dcm

setenv DCMRULESPATH /dcl_libs/%RULENAME

setenv DCMTABLEPATH /dcl_libs/

Refer to the DCL library vendor documentation for information about how to set thesevariables.

Related Information

Using IEEE 1481 Delay and Power Calculation System (DCL) Libraries in the TimingAnalysis for Ambit BuildGates Synthesis and Cadence PKS manual.

read_ola

set_dcl_level





Examplesac_shell>load_dcl_rule

Info: Library ’MY_DCM’ was loaded from file ’./DCL_OLA_Libs/DCMinterface_SOL’

<TCLCMD-701>.



read_alf

read_alf{ alf_library_name |([-min min_lib_name ] [-typ typ_lib_name ] [-max max_lib_name ][-name merged_lib_name ]}}

The read_alf command reads the Ambit library format (ALF) file. The binary .alf files arepreviously compiled from .lib format using the libcompile utility. For more details, see“Using Synopsys .lib Libraries” in the Timing Analysis for Ambit BuildGates Synthesisand Cadence PKS manual.

This command can be used two ways.

■ To read an ALF library into the database, use this form

read_alf a lf_library_name

The above command loads the library data from alf_library_name into the typfield.

■ To create and read a merged library from single operating point libraries, use this form

read_alf [-min min_lib_name ] [-typ typ_lib_name ] [-max max_lib_name ][-name merged_lib_name ]

The -min , -typ , -max options let you create a merged library from libraries for only oneoperating point. The libraries to be merged must contain data in the typ field. Themerged library is read into the database immediately. See examples.

The -name option changes the name of the merged library to a new name. For example,-name merged_lib_name changes the merged library name to merged_lib_name .

Arguments

alf_library_nameName of the ALF library. This name can be a fully qualified filename or a relative file name. If the AMBIT_SLIB_PATHenvironment variable is set, the search is performed in the orderspecified.

-min min_lib_nameUses typ data from library min_lib_name to populate themin field of the merged library.

-typ typ_lib_nameUses typ data from library typ_lib_name to populate thetyp field of the merged library.



-max max_lib_nameUses typ data from library max_lib_name to populate themax field of the merged library.

-name merged_lib_nameChanges the new merged library name tomerged_lib_name .

Related Information

read_adb

read_library_update

read_verilog

read_vhdl

Examples

The following command reads the LSI Logic G11 library.

ac_shell>read_alf lca_G11.alf

The following example populates typ values from the respective single operating pointlibraries into the min , typ , max fields of the combined library named merged.alf .

ac_shell>read_alf -min min.alf -typ typ.alf -max max.alf -name merged_lib

Suppose min.alf contains 0.02 , typ.alf contains 0.03 , and max.alf contains 0.04the resultant triplet in merged_lib is (0.02:0.03:0.04) .



read_ctlf

read_ctlfOBSOLETE: Use read_tlf instead.

Important

The read_ctlf command is no longer supported. Obtain a .tlf source file withversion 4.3 or higher and use read_tlf .

Related Information

read_tlf

“Using Cadence TLF Libraries” in the Timing Analysis for Ambit BuildGates Synthesisand Cadence PKS manual.



read_library_update

read_library_update[-library library_name] [-pvt {min | typ | max}][-wireloads] [-scaling_factors] [-operating_conditions] [-cells]filename

The read_library_update command replaces existing technology library data with newdata. This command updates wire load, operating conditions, and cell-specific information inthe library.

If none of the three options (wireloads , operating_conditions , cells ) are specified,all wire-load models, operating conditions, and cells from libname are used to update thelibrary.

Note: The read_library_update command has been enhanced to update scaling factorgroups to the target library similar to a wire-load models update. The -scaling_factorsoption can be used to set a new scaling factors group for a cell or to change the scaling factorsgroup of a cell within a library.

Arguments

-library library_nameSpecifies the name of the library to be updated. If this option isnot used, the target library specified by set_globaltarget_technology is updated.

-pvt {min | typ | max}Replaces library data for a particular PVT (process, voltage,temperature) corner. You can choose one, two, or three PVTcorners. If you choose more than one corner, enclose the list incurly braces ({} ) and separate the values by spaces. By default,the library is updated for all three PVT corners.

filenameSpecifies the name of the ASCII file that contains the new data.The file can be .tlf , .alf , or .lib file types. Requiredargument.

-wireloadsThe wire-load models from the file are used for updating thewire-load models in the library. If a wire-load model alreadyexists in the library then it is overwritten by the one from the file.



-scaling_factorsThe scaling factor groups from the file are used for updating thescaling factor groups in the library. If a scaling factor groupalready exists in the library then it is overwritten by the one fromthe file.

-operating_conditionsIndicates that the operating conditions specified in the filefilename are used to update the library.

-cellsAdds cells from the file filename to the library. If the cellalready exists in the library an error is reported.

Related Information

read_adb

read_alf

read_tlf

read_verilog

read_vhdl


Examples

The following command adds cells in library file memgen.lib to the library previouslyspecified by set_global target_technology .

read_library_update -cells memgen.lib

The first command loads TLF library lib1.tlf and the second command appends allinformation from TLF library lib2.tlf to lib1.tlf .

ac_shell[10]>read_tlf lib1.tlf

ac_shell[11]>read_library_update lib2.tlf



read_ola

read_ola

The read_ola command loads an OLA into memory in the form of a DCM (compiledmodule) and initializes it for use in Ambit BuildGates synthesis. Upon loading the OLA library,all timing calculations are performed using the OLA delay tables and equations. Thesynthesis properties and functions are also derived from the OLA library.

Note: Before an OLA library can be loaded, certain environment variables must be set beforeac_shell is invoked. The following list shows an example.

setenv DCMRULEPATH /dcl_libs/sample_dcm

setenv DCMRULESPATH /dcl_libs/%RULENAME

setenv DCMTABLEPATH /dcl_libs/

Refer to the OLA library vendor documentation for information about how to set thesevariables.

See “Using OLA v1.0.2 Libraries” in the Ambit Timing Analysis User Guide for moreinformation.

Related Information

load_dcl_rule

set_dcl_level




Examplesread_ola



read_sdf

read_sdf[-continue_on_error][-min |-typ | -max][-store_as_min | -store_as_typ | -store_as_max][-scale float ][-worst_case_mismatched_conds]sdf_filename

The read_sdf command reads a Standard Delay Format (SDF) file. After the physicaldesign has been done, the post-layout delay data needs to be backannotated for furthertiming analysis. This command reads SDF files into the design.

The default behavior is to read all the MTM information in the SDF, and store it as it ispresented in the SDF. For example:

read_sdf SDF

The -min | -typ | -max options are used for pulling the values only from a given MTM field.For example:

read_sdf -max SDF1

read_sdf -typ SDF2

read_sdf -min SDF3

In the example session, the first read_sdf loads the SDF1 max value into the BG max field.It leaves the min and typ fields unannotated. The next command gets the typ data fromanother SDF which still leaves the min field unannotated. The third command completes theannotation by picking up the min value from yet another SDF.

SDF Command BG

(1:2:3) read_sdf (no options) (1:2:3)

SDF1 SDF2 SDF3 Commands BG

(2.8:2.9:3) N/A N/A read_sdf -max (::3)

N/A (2.0:2:2.1) N/A read_sdf -typ (:2:3)

N/A N/A (1:1.1:1.2) read_sdf -min (1:2:3)



Caution

Partially annotated SDFs can give unexpected results. Makesure you fully annotate min/typ/max.

Tip

The -min | -typ | -max and -store_as_min | -store_as_typ |-store_as_max options provide a powerful mechanism for reading and storingMTM values from multiple SDF files,. However they should be used carefully, seeCaution above.

Arguments

sdf_filenameThe name of the SDF file that has the backannotation data.

-scale floatScales all values in the SDF file by the given number.

-continue_on_errorIf an error occurs, usually the read_sdf command stopsreading the file. By specifying this option, you can attempt tocontinue reading the file if it is possible. Use caution if youcontinue because some annotations could be missing due to theerrors. Use the report_annotations command to findmissing annotations. If the file is corrupted, you need to obtain anew SDF file.

-min | -typ | -maxSpecifies only one field, either the min , typ , or max numbers,from the SDF file to be applied to the arc.

Note: By default this number is applied to all three delay values in the timing system. Tooverride this use one of the -store_as_* options.

-store_as_min | -store_as_typ | -store_as_maxMust be used with one of the options -min | -typ | -max . Thistells the system to store the specified value into a specific valuein the timing system. These options must be compatible withpvt_early_path and pvt_late_path globals.



For example, if you want to load the minimum values from anSDF file, but ignore the other two values, then you would use oneof the following sets of commands:

set_global pvt_early_path min

set_global pvt_late_path min

read_sdf -min -store_as_min

or

set_global pvt_early_path typ

set_global pvt_late_path typ

read_sdf -min -store_as_typ

or simply

read_sdf -min -store_as_max

since pvt_early_path and pvt_late_path are set to max by default.

If you want to use the minimum SDF values for early paths and the typical SDF valuesfor late paths, use the following commands:


set_global pvt_late_path typ


read_sdf -typ -store_as_typ

or


set_global pvt_late_path max


read_sdf -typ -store_as_max

Note: This option assumes that you have previously annotated the design from anotherSDF file with all three values or that you will eventually fill in all values with subsequentread_sdf -store_as_* commands. Behavior of the timing analysis is not definedunless all three fields are annotated.

-worst_case_mismatched_condsSpecifies that the SDF file contains conditional delays that do notmatch the conditional delays in the library. When this option isspecified, the mismatched condition is compared to the defaultconditional delay and the worst delay is used. By default,mismatched conditional delays in the SDF file are ignored.



Related Information

read_adb

read_alf

read_pdef

read_verilog

read_vhdl

Examples

The following command scales all delay values in the file typ.sdf by 2.

ac_shell[5]>read_sdf -scale 2 typ.sdf

These commands store the min values from min.sdf in the min delay of the timing system,and so on for typ and max values. This method is useful when setting up a model forsimultaneous worst case, best case analysis.

ac_shell[5]>read_sdf -min -store_as_min min.sdf

ac_shell[6]>read_sdf -typ -store_as_typ typ.sdf

ac_shell[7]>read_sdf -max -store_as_max max.sdf

Note: The default timing analysis type is min_max , for best-case/worst-case you mustset_global timing_analysis_type bc_wc. For more information about best-case/worst-case analysis, see On and Off Chip Variation Analysis in the Timing Analysis forAmbit BuildGates Synthesis and Cadence PKS manual.



read_spf

read_spf[-left_bus_delimiter char -right_bus_delimiter char ] [-verbose]file_name

The read_spf command lets you read in a parasitics file in Standard Parasitics Format(SPF). The SPF file can be in detailed or reduced form. Internally a detailed SPF is reduced.The reduced file is stored in the database and used for delay calculation. You can write outthe reduced file by issuing the write_spf command.

For flow information and details about delay calculation with parasitics, see Reading SPF andSPEF Files in Timing Analysis for Ambit BuildGates Synthesis and Cadence PKS.

Note: Parasitics stitching is not supported. Parasitics are supported only for the full flatdesign.

Arguments

-left_bus_delimiter char -right_bus_delimiter charSpecifies the left bus delimiter and the right bus delimiter. Bothof these options are required for SPF versions 1.3 and older.These options are ignored for SPF versions newer than 1.3

-verbosePerforms various checks such as resistance loops in detailedparasitics and the completeness of parasitics data and reportsthem. This option lets you check the correctness of the parasiticsfile.

file_nameSpecifies the name of the SPF file to read.

Related Information

read_spef

write_spf

Examples

This command reads in a version 1.4 detailed SPF file named new.dspf .

read_spf new.dspf



This command reads in a version 1.3 reduced SPF file named old.rspf .

read_spf old.rspf -left_bus_delimiter \[ -right_bus_delimiter \]

Tip

Some delimiter characters like square brackets and curly braces must be escapedcharacters (preceded by \ ) for proper Tcl interpretation. See above example.



read_spef

read_spef[-verbose] file_name

The read_spef command lets you read in a parasitics file in Standard Parasitics ExchangeFormat (SPEF). The SPEF file can be in detailed or reduced form. Internally a detailed SPEFis reduced. The reduced file is stored in the database and used for delay calculation.

For flow information and details about delay calculation with parasitics, see Reading SPF andSPEF Files in Timing Analysis for Ambit BuildGates Synthesis and Cadence PKS.

Note: Parasitics stitching is not supported. Parasitics are supported only for the full flatdesign.

Arguments

-verbosePerforms various checks such as resistance loops in detailedparasitics and the completion of parasitics specified and reportsthem.

file_nameSpecifies the name of the SPEF file to read.

Related Information

read_spf

write_spf

Examplesread_spef -verbose spiffy.spef



read_stamp

read_stamp(-model model_file model_data_file ) |({[-min min_model_data_file ] | [-typ typ_model_data_file ] |[-max max_model_data_file ]} -model model_file [-name merged_name ])

The read_stamp command reads in a timing model in the Synopsys Stamp format.

The first usage associates one model data file with the model. In this case the model data fileis assumed to contain typ data.

read_stamp -model model_file model_data_file

The second usage lets you associate data from one or more model data files to the samemodel.

read_stamp {[-min min_model_data_file ] | [-typ typ_model_data_file ] |[-max max_model_data_file ]} -model model_file [-name merged_name ]

Arguments

model_fileSpecifies the name of the Stamp model to load.

model_data_fileSpecifies the name of the data file associated with the Stampmodel. This model data file is assumed to contain typ data.

-min min_model_data_fileSpecifies the name of the min data file associated with theStamp model.

-typ typ_model_data_fileSpecifies the name of the typ data file associated with theStamp model.

-max max_model_data_fileSpecifies the name of the max data file associated with theStamp model.

-name merged_lib_nameChanges the new merged library name tomerged_lib_name .



Related Information

set_functional_mode

reset_functional_mode

report_functional_mode

Using Synopsys Stamp Models in the Timing Analysis for Ambit BuildGates Synthesisand Cadence PKS manual.

Examples

This example loads the data from cpu.data into the typical field of the library.

read_stamp -mod cpu.mod cpu.data



read_tlf

read_tlf[-silent] [-password password ] { tlf_library_name |(-min min_lib_name -typ typ_lib_name -max max_lib_name-name merged_lib_name }}

The read_tlf command reads in an encrypted or unencrypted Timing Library Format (TLF)library in compiled (.ctlf ) or uncompiled (.tlf ) format. TLF version 4.3 or higher issupported. This command can be used two ways.

■ To read a TLF library into the database, use this form

read_tlf [-silent] [-password password] tlf_library_name

If the library has complete triplets of data (min/typ/max values), then all three fields areloaded simultaneously.

■ To create and read a merged TLF library from single operating point libraries, use thisform

read_tlf [-silent] [-password password]-min min_lib_name -typ typ_lib_name -max max_lib_name-name merged_lib_name

The -min , -typ , -max options let you create a merged library from libraries for only oneoperating point. The libraries to be merged must contain data in the typ field. Themerged library is read into the database immediately. See examples.

The -name option changes the name of the merged library to a new name. For example,-name merged_lib_name changes the merged library name to merged_lib_name .

Arguments

-silentSuppresses the message which says that the library has beensuccessfully loaded.

-password passwordPasses the key password for an encrypted TLF library.

-min min_lib_nameUses typ data from library min_lib_name to populate themin field of the merged library. This option is required whenusing the -name option.

-typ typ_lib_nameUses typ data from library typ_lib_name to populate the



typ field of the merged library. This option is required whenusing the -name option.

-max max_lib_nameUses typ data from library max_lib_name to populate themax field of the merged library. This option is required whenusing the -name option.

-name merged_lib_nameChanges the name of the merged library tomerged_lib_name . This option requires the use of -min ,-typ , -max options.

Related Information

“Using Cadence TLF Libraries” in the Timing Analysis for Ambit BuildGates Synthesisand Cadence PKS manual.

Examples

The following example picks up min values from the min.tlf library and populates them tothe min fields of the merged library with name merged_lib . If min values are not present inmin.tlf then typ values are used. The typ values are picked up from the typ.tlf libraryand populated to the typ fields of the merged library. Likewise maxvalues are picked up fromthe max.tlf library and populated to max fields. If max values are not present in max.tlf,then typ values are used.

read_tlf -min min.tlf -typ typ.tlf -max max.tlf -name merged.tlf

Suppose min.tlf contains (0.01:0.02:0.03) as the ( min : typ : max) pin-to-pin delayfor some cell, typ.tlf contains (0.04:0.05:0.06) for the corresponding delay, andmax.tlf contains (0.07:0.08:0.09) , the resultant triplet in merged.tlf is(0.01:0.05:0.09) .



remove_assertions

remove_assertions[-arrival | -required][-type {input_delay | external_delay | arrival | required | clock_root}]list_of_pins

The remove_assertions command removes the specified assertions on the given list ofpins. The impact on the database is to remove certain assertions, there is no change to thenetlist.

Currently only assertions of the types listed can be removed. The default removes allassertions (of the types allowed).

Arguments

list_of_pins

-arrival | -requiredThese options are for backward compatibility and are equivalentto -type arrival and -type required .

-type input_delay | external_delay | arrival | required | clock_rootRemoves only the assertion specified. When no options areprovided, the default is to remove all assertions listed below.

input_delayRemoves only assertions previously given by theset_input_delay command.

external_delayRemoves only assertions previously given by theset_external_delay command.

arrivalRemoves only assertions previously given by theset_data_arrival command.

requiredRemoves only assertions previously given by theset_data_required command.



clock_rootRemoves only assertions previously given by theset_clock_root command.

Related Information

write_assertions

set_input_delay

set_external_delay

set_data_arrival_time

set_data_required_time

set_clock_root

Examples

This example writes the existing assertions, then removes some and writes a new assertionsfile.

ac_shell[18]>write_assertions assert.txt

ac_shell[19]>cat assert.txt

set_current_module {top}

set_top_timing_module {top}

set_clock_propagation ideal

set_input_delay -clock clkA -lead -early -rise 0.000 {in}

set_external_delay -clock clkA -lead -late -rise 0.000 {out}

#end of assertions for module top

Now remove assertions on ports in and out :

ac_shell[20]>remove_assertions [find -port in out]

ac_shell[21]>write_assertions assert2.txt

ac_shell[22]>cat assert2.txt

set_current_module {top}

set_top_timing_module {top}

set_clock_propagation ideal

#end of assertions for module top



report_annotations

report_annotations[-missing_resistances] [-missing_capacitances] [-missing_rc][-missing_delays] [-max_missing integer ] [-tcl_list]

The report_annotations command reports the coverage of the annotations on a design.These annotations include SDF delay arc annotations, wire resistances, and wirecapacitances.

You can limit the search for annotations to a specific area of the design by specifying thecurrent_module and current_instance commands before issuing thereport_annotations command.

Using the -missing _* options you can get a detailed report of all delay arcs and wires thatare missing annotations. You can use the information in a Tcl program.

Arguments

-missing_resistancesReports the nets that are missing resistances. By default, only asummary of the coverage is reported.

-missing_capacitancesReports the nets that are missing capacitances. By default, onlya summary of the coverage is reported.

-missing_rcReports the nets that are missing both resistances andcapacitances. By default, only a summary of the coverage isreported.

-missing_delaysReports the arcs that are missing SDF annotations. By default,only a summary of the coverage is reported.

-max_missing integerLimits the number of missing annotations to the numberspecified. The default is 1000.

-tcl_listFormats the information for use in a Tcl program.



Related Information

report_net

Examplesreport_annotations -missing_capacitances



report_cell_instance_timing

report_cell_instance_timing[-early | -late] [-tcl_list] list_of_cell_instances

The report_cell_instance_timing reports information about the timing context of alibrary cell instance. Timing information on all pins of the instance are reported, followed byall the delay arcs between those pins.

Note: Internal pins (pins inside the instance boundary) are also reported.

The report contains three tables:

■ The first table in the report contains information about the pins of the instance.

The propagated slew is the delay that is propagated to the next stage.

■ The second table contains information about the arcs through the instance.

The slew out is the slew calculated from the timing model. This slew is not necessarilythe slew propagated.

■ The third table contains information about the timing checks, if present, on the cell.

Only checks that are from the library are shown in this table. Automatic checks, such asclock gating setup and hold, are not reported.

Arguments

list_of_cell_instancesA cell instance or list of cell instances. Use curly braces ({} ) toenclose the list and separate the instance names withwhite-space.

-early | -lateReports the early timing (hold) or late timing (setup). The defaultis -late .

-tcl_listProduces the report in a Tcl list instead of a human-readablereport. This option can be used to integrate timing with customTcl functions or to customize report generation.



Related Information

report_timing

get_timing

report_net

report_precision


Examplesac_shell[16]report_cell_instance_timing reg01

Instance reg01 of LD1|------------------------------------------------------------|| Pin | Propagated | Arrival | Required | Slack | Phase| | Slew | | | ||-------+------------+---------+----------+-------+----------|| Q ^ | 0.09 | 0.66 | 1.78 | 1.12 | CLK(D)(P)|| Q v | 0.06 | 0.65 | 1.77 | 1.12 | CLK(D)(P)|| QN ^ | 0.02 | 0.66 | | | CLK(D)(P)|| QN v | 0.03 | 0.71 | | | CLK(D)(P)|| D ^ | 0.03 | 1.25 | 0.08 | -1.17 | CLK(D)(P)|| D v | 0.03 | 1.31 | 0.07 | -1.24 | CLK(D)(P)|| G ^ | 0.00 | 0.04 | 1.16 | 1.12 | CLK(C)(P)|| G v | 0.00 | 2.03 | 5.25 | 3.22 | CLK(C)(P)|+------------------------------------------------------------++-----------------------------------------------------------+| Instance reg01 of LD1 ||-----------------------------------------------------------|| Arc | Slew | | | ||---------------+---------------+-------+-------+-----------|| From | To | In | Out | Load | Delay | Phase ||-------+-------+-------+-------+-------+-------+-----------|| D ^ | QN v | 0.03 | 0.03 | | 0.62 | CLK(D)(P) || D v | QN ^ | 0.03 | 0.02 | | 0.59 | CLK(D)(P) || D ^ | Q ^ | 0.03 | 0.09 | 0.12 | 0.58 | CLK(D)(P) || D v | Q v | 0.03 | 0.07 | 0.12 | 0.57 | CLK(D)(P) || G ^ | QN ^ | 0.00 | 0.02 | | 0.62 | CLK(C)(P) || G ^ | QN v | 0.00 | 0.03 | | 0.67 | CLK(C)(P) || G ^ | Q ^ | 0.00 | 0.09 | 0.12 | 0.62 | CLK(C)(P) || G ^ | Q v | 0.00 | 0.06 | 0.12 | 0.61 | CLK(C)(P) |+-----------------------------------------------------------++-----------------------------------------------------------+| Instance reg01 of LD1|-----------------------------------------------------------|| | Pins | | | | Phase|-------+---------------+-------+-------+--------+----------|| Check | Sig | Ref | Slack | Delay | Adjust | Sig | Ref||-------+-------+-------+-------+-------+--------+-----+----|| HOLD | D ^ | G v | 3.22 | 0.01 | 4.00 | CLK(D)(P)| CLK(C)(P)| HOLD | D v | G v | 3.29 | 0.01 | 4.00 | CLK(D)(P) | CLK(C)(P) || SETUP| D ^ | G v | 0.73 | 0.05 | 0.00 | CLK(D)(P) | CLK(C)(P) || SETUP| D v | G v | 0.53 | 0.19 | 0.00 | CLK(D)(P) | CLK(C)(P) |+-----------------------------------------------------------+



report_clocks

report_clocks[-description] [-arrival_points] [-clock_to_data] [-data_to_clock][-phase_shift_table] [-uncertainty_table] [-adjustment_table][-delay_adjustment_table] [-source_insertion] [-insertion][-total_shift_table] [-clocks ideal_clock_name | ideal_clock_name_list ][-tcl_list] [{> | >>} filename ]

The report_clocks command reports information about clocks and clock assertions. Itreports information about all ideal clocks, clock arrival points, clock uncertainties, whereclocks are converted to data, and where data is converted to clocks.

By using the -description , -arrival_points , -clock_to_data , -data_to_clock ,-uncertainty_table , and the *_table options, you can specify different parts of thereport. If one of these options is supplied, only the section that the option corresponds to isreported. If other options are supplied, those sections are also reported.

The information can be formatted for use in a Tcl program, by the -tcl_list option.

Arguments

-descriptionReports only the description of the ideal clock.

-arrival_pointsReports only the clock arrival points. A clock arrival point is thepin where set_clock_root or set_clock_arrival_timehas been asserted.

The data is reported differently if set_clock_root is usedinstead of set_clock_arrival_time . Ifset_clock_arrival_time is used the early/late rise/fallfields are displayed along with the Ideal clock name and theplace where the clock is attached. If set_clock_root is usedonly the Ideal clock name and the attachment point aredisplayed, the rise/fall early/late fields are left empty.

-clock_to_dataReports only the clock to data change points. A clock to datachange point is where the set_clock_info_changecommand has been used to convert any clock signals to datasignals.



-data_to_clockReports only the data-to-clock change points. A data-to-clockchange point is where the set_clock_info_changecommand has been used to convert any data signals to clocksignals.

-phase_shift_tableReports two tables that detail the phase shift between idealclocks. One table shows the phase shifts in late mode and theother in early mode.

Note: If specific ideal clocks are requested with the -clocksideal_clock_name_list option, then only the relationships between those clocksare reported.

-uncertainty_tableReports two tables (late mode and early mode) that detail theuncertainty between ideal clocks as specified by theset_clock_uncertainty command.


-adjustment_tableReports two tables that detail the early and late cycleadjustments between ideal clocks as set by theset_cycle_addition command.


-delay_adjustment_tableReports two tables that detail the early and late path delayadjustments between ideal clocks as set by theset_path_delay_constraint command with-clock_from -clock_to options.


-source_insertionReports the source insertion delays specified on ideal clocks.



-insertionReports the network insertion delays specified on ideal clocks.The values in the table are in min:typ:max format.

-total_shift_tableReports two tables (late mode and early mode) that detail thetotal relationship between ideal clocks.


-clocks ideal_clock_name | ideal_clock_name_listRequests information on a specific ideal clock. If a list is given,only information about those clocks is reported. You can usewildcards in the names. By default, all ideal clocks are reported.

-tcl_listProduces the report in a Tcl list, not a human-readable report.This is useful for integrating timing with custom Tcl functions andalso for customizing report generation.

{> | >>} filenameSpecifies the name of the file in which report is saved. Thefilename argument must be the last argument in the list. If thefilename is not specified, the report is displayed on the standardoutput without being saved. Since the report is often large, textmay be lost if you do not save the report to a file.

Related Information

set_clock_root

set_clock_insertion_delay


set_clock_uncertainty

Examplesac_shell[5]>report_clocks

+--------------------------------+| Clock Descriptions |



|--------------------------------|| Clock | Period | Lead | Trail || Name | | | ||-------+--------+-------+-------|| A | 15.00 | 0.00 | 7.50 || B | 10.00 | 2.00 | 8.00 |+--------------------------------++-----------------------------------------------+| Total Clock To Clock Relationship ||-----------------------------------------------|| From | To | L->L | L->T | T->L | T->T ||-------+-------+-------+-------+-------+-------|| A | A | 14.76 | -0.48 | 14.28 | 14.04 || A | B | -1.20 | -6.44 | 8.32 | -1.92 || B | A | 2.84 | -7.40 | 7.36 | 2.12 || B | B | 6.88 | -3.36 | 6.40 | 6.16 |+-----------------------------------------------+

ac_shell[2]>report_clocks -uncertainty_table+-----------------------------------------------+| Clock To Clock Uncertainty (Late) |

|-----------------------------------------------| | From | To | L->L | L->T | T->L | T->T | |-------+-------+-------+-------+-------+-------| | iclk1 | iclk1 | 0.00 | 0.00 | 0.00 | 0.00 | | iclk1 | iclk2 | 1.70 | 1.70 | 1.70 | 1.70 | | iclk2 | iclk1 | 0.00 | 0.00 | 0.00 | 0.00 | | iclk2 | iclk2 | 0.00 | 0.00 | 0.00 | 0.00 | +-----------------------------------------------+ +-----------------------------------------------+ | Clock To Clock Uncertainty (Early) | |-----------------------------------------------| | From | To | L->L | L->T | T->L | T->T | |-------+-------+-------+-------+-------+-------| | iclk1 | iclk1 | 0.00 | 0.00 | 0.00 | 0.00 | | iclk1 | iclk2 | -2.70 | -2.70 | -2.70 | -2.70 | | iclk2 | iclk1 | 0.00 | 0.00 | 0.00 | 0.00 | | iclk2 | iclk2 | 0.00 | 0.00 | 0.00 | 0.00 | +-----------------------------------------------+




report_functional_mode [-cell cell_name ] [ instance_list ]

The report_functional_mode command reports status (active or inactive) of all modesin the instance list.

The following form of the command reports a list of mode groups and modes forcell_name .

report_functional_mode -cell cell_name

Without arguments, the command reports status of all modes in all instances.

report_function_mode

Arguments

-cell cell_nameSpecifies the name of the cell.

instance_listSpecifies the list of instances for which the functional modestatus needs to reported.

Related Information

set_functional_mode


Examples

The following command reports the status of all modes in all instances.


The following command reports the status of all modes in cell named RAM.

report_functional_mode -cell RAM

The following command reports the status of all modes in instances A1/B3/C2 and A1/B2/C2.

report_functional_mode {A1/B3/C2 A1/B2/C2}



report_library

report_library[-library library_name ] [-cells [ pattern ]] [-wireloads][-operating_conditions] [-tcl_list] [{> | >>} filename ]

The report_library command generates a report about the technology library used in thedesign.

Arguments

-library library_nameReports contents of the specified library. By default, contents ofthe library set by set_global target_technology arereported.

-cells [ pattern ]Reports information about all cells in the library. If a pattern isspecified, only the cell names in the library that match the patternare reported. See examples.

-wireloadsReports information on all the wire-load models in the library.

-operating_conditionsReports information on all the operating conditions in the library.

If none of the three options (-cells , -wireloads ,-operating_conditions ) are specified, the report containsinformation about all the cells, wire-load models and operatingconditions.


{> | >>} filenameSpecifies the name of the file in which report is saved. Thefilename argument must be the last argument in the list. If thefilename is not specified, the report is displayed on the standardoutput without being saved. Since the report is often large, textmay be lost if you do not save the report to a file.



Related Information

report_timing

set_table_style


Examples

The following command reports contents of the technology library to the file namedlibrary.rep :

ac_shell[18]>report_library library.rep

This command reports all cells matching the string AO* in library lca300kv :

ac_shell[24]>report_library -library lca300kv -cells AO*



report_net

report_net[-min_fanout int ] [-max_fanout int ] [-wire_resistance_not_annotated][-wire_capacitance_not_annotated] [-clock clock_name [-lead | -trail]]{-net list_of_net_name_or_id | -pin list_of_pin_name_or_id }[-old] [-tcl_list] [-output filename | {> | >>} filename ]

The report_net command reports the net information on the current module. Theinformation includes the net name, the number of source pins, sink pins and bidirectional pinson the net, the wireload model. the wire capacitance and wire resistance, and totalcapacitance.

Electrical information such as pin capacitance, wire capacitance, wire resistance and thewireload model with which the net is associated are also included. If wire capacitance and/orwire resistance are backannotated from post-layout information, such as an SDF file, they areindicated in the Wireload Model (WLM) column accordingly. If any attributes are set on the net,they are also indicated in the attribute column

The -pin option reports the net that is connected to the specified pin (or port). Both -netand -pin cannot be specified at the same time. The net (or pin) names can be hierarchicalnames which are unique relative to the top timing module.

Note: The top timing module must be set (by the set_top_timing_module command)before report_net can be used.

This command only searches for the defined nets and does not modify any object indatabase.

Arguments

-net list_of_net_name_or_idReports the set of nets on the list of net names. This argumentcannot be specified at the same time as -pin . If neither -net or-pin is specified, all nets are listed by default.

-pin list_of_pin_name_or_idReports the set of nets to which the pins on the listlist_of_pin_name_or_id are connected. This argumentcannot be specified at the same time as -net .

-min_fanout integerReports the net whose number of fanouts is greater than theminimum number specified by integer .



-trailOnly show the paths triggered by the trailing edge of thespecified clock. Must be used with -clock .

-leadOnly show the paths triggered by the leading edge of thespecified clock. Must be used with -clock .

-oldProduces the table in 3.0 format (without information about theinterconnect delay model).

-clock clock_nameOnly show the paths triggered by the specified ideal clockclock_name .

-max_fanout integerReports the net whose number of fanouts is less than themaximum number specified by integer .

-wire_resistance_not_annotatedReports the net for which the resistance information has notbeen backannotated. This is usually used for checking andreporting any nets whose resistance has not yet been annotated.

-wire_capacitance_not_annotatedReports the net for which the capacitance information has notbeen backannotated. This is usually used for checking andreporting any nets whose capacitance has not yet beenannotated.

-tcl_listProduces the report in Tcl list form instead of a tabular format.This is useful for extracting information from the report in a Tclprogram.

-output filename | {> | >>} filenameDumps the report to the specified file instead of to the standardoutput. The filename argument must be the last argument inthe list.



Related Information

report_path_exceptions

report_timing

set_current_module

Examples

The format of the report is the same for all examples. The format is shown in the first example.

The following command reports information about net named in .

ac_shell[9]>report_net -net inNet Name : inNumber of Sources : 1Number of Sinks : 2Number of Bidis : 0Wireload Model : 0Net Capacitance : 0.00Total Capacitance : 0.02

+----------------------------------------------------------------------------------------+

| Source |

|----------------------------------------------------------------------------------------|

| Pin | Reduced Net | Driver Load | Slew | |

|-------------------------------+--------------+-----------------+---------------+-------|

| Name | Dir | Cell | Cap | Model | Model | Ctotal | Rise | Fall | Phase |

|-------+-------+-------+-------+--------------+--------+--------+-------+-------+-------|

| in | IN | top | 0.00 | Elmore Delay | CTOTAL | 0.02 | 0.05 | 0.04 |@(D)(P)|

+----------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------+

| Sinks for pin in |

|----------------------------------------------------------------------------------------|

| Pin | Reduced Ne | Delay | Slew |

|-----------------------------------------+------------+---------------+---------------+-|

| Name | Dir | Cell | Cap | Parameters | Rise | Fall | Rise | Fall | Phase |

|-----------------+-------+-------+-------+------------+-------+-------+-------+-------+-|

| I_block/B_reg/D | IN | FD1QA | 0.01 | 0.00 | 0.00 | 0.00 | 0.05 | 0.04 | @(D)(P) |

| I_block/A_reg/D | IN | FD1QA | 0.01 | 0.00 | 0.00 | 0.00 | 0.05 | 0.04 | @(D)(P) |

+----------------------------------------------------------------------------------------+



The following command reports the net to which the pin interesting_pin is connected.

report_net -pin interesting_pin

This command reports all the nets in the current module.

report_net -net *

The following command reports all nets with a fanout greater than 16.

report_net -net * -min_fanout 16



report_path_exceptions

report_path_exceptions[-tcl_list] [{> | >>} filename ]

The report_path_exceptions command generates a report about the path exceptionsthat you have specified using the set_false_path , set_path_delay_constraint andset_cycle_addition commands.

A path can have more than one path exception. When the globalpath_style_timing_constraint is set to true , multiple path exceptions that match agiven path are prioritized. The adjustment on the path is from the path exception with thehighest priority. Table 7-4 on page 774 ranks path exception priorities from highest to lowest.

Important

When the global path_style_timing_constraint is set to false , only thepath exceptions supported before version 3.0 are observed, the rest are ignored.Furthermore, there is no prioritization on overlapping path exceptions.The falseoption exists for backward compatibility with releases prior to 3.0. The default in 4.0is true . You can avoid problems by always using the default value.

Arguments

> | >> filenameRedirects the output to the named file. If this option is omitted,the default is stdout.

-tcl_listProduces the report in Tcl list form instead of a tabular format.This is useful for extracting information from the report in a Tclprogram.

Related Information

report_timing

report_area


report_hierarchy



report_fsm

set_current_module

Examples

The following report shows that a false path has priority over cycle addition on the same path.

ac_shell[19]>report_path_exceptions

+---------------------------------------------------------------------+

| From | To | Early | Late |

|-----------------+-----------------+---------------+-----------------|

| I_block/A_reg/Q | J_block/D_reg/D | false | false |

| I_block/A_reg/Q | J_block/D_reg/D | | add 2 ignored |

+---------------------------------------------------------------------+



report_port

report_port[-type ([input] | [source_insertion] | [insertion] |[clock_root] | [uncertainty] |[arrival] | [required] | [external] | [clk_arrival] |[clk_required] | [port_cap] | [fanout_load] |[num_external_sinks] | [num_external_sources] |[fanout_load_limit] | [port_wire_load] |[drive_resistance] | |[drive_cell] | [slew_time] |[slew_limit] | [constant] | external_detail | drive_resistance_detail)][-tcl_list][-pins port_name_id_list ]

The report_port command reports timing assertions on ports and pins. The default (if noparameters are supplied) is to report all timing assertions on all ports of the current module.A specific port can be specified with either an object ID, a name, or a list of IDs or names.

Specific assertions can be queried by using the -type option.

The -tcl_list option formats the information for use in a Tcl program.

Arguments

-type { assertion_type | assertion_type_list }This option specifies the assertions to be reported. By default, allassertions are reported. The following are validassertion_type values:

inputReports the input delay assertions as set byset_input_delay .

source_insertionReports the source insertion delay as set byset_clock_insertion_delay -source .

insertionReports the network insertion delay as set byset_clock_insertion_delay .

clock_rootReports the clock root as set by set_clock_root .



uncertaintyReports the clock uncertainty as set byset_clock_uncertainty .

arrivalReports arrival time assertions as set by set_input_delay .

requiredReports required time assertions as set byset_data_required_time .

externalReports external delay assertions as set byset_external_delay .

clk_arrivalReports clock arrival time assertions as set byset_clock_insertion_delay .

clk_requiredReports clock required time assertions as set byset_clock_required_time .

port_capReports port capacitance assertions as set byset_port_capacitance .

fanout_loadReports fanout load assertions as set by set_fanout_load .

num_external_sinksReports external sink assertions as set byset_num_external_sinks .

num_external_sourcesReports external source assertions as set byset_num_external_sources .

fanout_load_limitReports fanout load limit assertions as set byset_fanout_load_limit .



port_wire_loadReports port wire-load model assertions as set byset_port_wire_load .

drive_resistanceReports drive resistance assertions as set byset_drive_resistance .

drive_cellReports drive cell assertions as set by set_drive_cell .

slew_timeReports slew time assertions as set by set_slew_time .

slew_limitReports slew time limit assertions as set byset_slew_time_limit .

constantReports constant assertions as set byset_constant_for_timing .

external_detailReports detail about the output ports with external delayassertions.

drive_resistance_detailReports detail about the input ports with drive resistanceassertions.


-pins port_name_id_listSpecifies the pins or ports to be reported. Pins can be specifiedby name or object ID in a Tcl list.

Related Information

report_net



report_timing

Examplesac_shell[28]>report_port+----------------------------------------------------------------------------------------+| | | | | Early | Late ||-----------------+-------+------------------+------------+---------------+--------------|| Pin Name | Dir | Assertion | Clock Name | Rise | Fall | Rise | Fall||-----------------+-------+------------------+------------+-------+-------+-------+------|| I_block/u000/A | IN | slew_time | CLK1(C)(P) | 1.60 | 1.60 | 1.60 | 1.60|| J_block/D_reg/D | IN | arrival | CLK1(D)(P) | | 0.07 | | || J_block/D_reg/D | IN | drive_resistance | CLK1(D)(P) | 1.20 | 1.20 | 1.20 | 1.20 || clkA | IN | clk_arrival | CLK2(C)(N) | 2.00 | 0.00 | 2.00 | 0.00 || clkA | IN | slew_time | CLK1(C)(P) | 1.30 | 1.30 | 1.30 | 1.30 || clkB | IN | clk_arrival | CLK2(C)(P) | 0.00 | 2.00 | 0.00 | 2.00 || clkB | IN | slew_time | CLK1(C)(P) | 1.30 | 1.30 | 1.30 | 1.30 || clkC | IN | clk_arrival | CLK2(C)(P) | 0.05 | 0.07 | 0.05 | 0.07 || clkD | IN | clk_arrival | CLK2(C)(N) | 3.00 | 0.50 | 3.00 | 0.50 || in | IN | drive_cell | *(D)(P) | BUFA | BUFA | BUFA | BUFA || out | OUT | external | CLK1(C)(N) | | | 1.00 | 1.00 |

+----------------------------------------------------------------------------------------+ +------------------------------------------------------------+ | Pin | Dir | Assertion | Value | | Name | | | | |-------+-------+--------------------+-----------------------| | out | OUT | port_cap | ( 3.20 : 3.20 : 3.2 ) | | out | OUT | num_external_sinks | 4 | | out | OUT | port_cap_limit | 4.00 | | in | IN | slew_limit | 1.50 | | in | IN | port_cap_limit | 2.00 | | clkA | IN | port_cap_limit | 2.00 | | clkB | IN | port_cap_limit | 2.00 | | clkC | IN | port_cap_limit | 2.00 | | clkD | IN | port_cap_limit | 2.00 | +------------------------------------------------------------+

The following example from a different design shows that input , source_insertion andclock_root assertion type options report the assertions in the same format as arrival .

ac_shell[6]>report_port -type clock_root source_insertion input -pin clk in

+---------------------------------------------------------------------------+

| | | | | Early | Late

|-------+-------+------------------+-----------+---------------+------------|

| Pin | Dir | Assertion | Clock | Rise | Fall | Rise | Fall

| Name | | | Name | | | |

|-------+-------+------------------+-----------+-------+-------+-------+----|

| clk | IN | clock_root | CLK(C)(P) | | | |

| clk | IN | source_insertion | *(D)(P) | 2.50 | 2.50 | 2.50 | 2.50

| in | IN | input | CLK(D)(P) | 3.00 | 3.00 | 3.00 | 3.00

+---------------------------------------------------------------------------+

The last example shows that the insertion and uncertainty are reported as one value inthe following format:



insertion : RISEmin FALLmin : RISEtyp FALLtyp : RISEmax FALLmax

uncertainty : EARLYrise EARLYfall LATErise LATEfall

The -to uncertainty is denoted by (T) next to the number. If a value is not specified, itis denoted by a dash (- )(see below).

ac_shell[7]>report_port -type insertion uncertainty -pin clk

+-------------------------------------------------------------------------+

| Pin | Dir | Assertion | Value |

| Name | | | |

|-------+-------+-----------------------+---------------------------------|

| clk | IN | insertion | ( 1.50 3.50 : - - : 2.50 4.50 ) |

| clk | IN | uncertainty | 1.00(T) 1.10 - 1.20(T) |

+-------------------------------------------------------------------------+



report_timing

report_timing[-clock_from clock_name_list ] [-clock_to clock_name_list ] [-edge_from{lead | trail}][-edge_to {lead | trail}][-rise] [-fall] [-early | -late] [-max_slack float ] [-min_slack float ][-max_paths integer | -max_points npoint ] [-nworst integer ][{-from | -from_rise | -from_fall} pin_list ][{-through | -through_rise | -through_fall} pin_list ][{-to | -to_rise | -to_fall} pin_list ][-bidi_input_from | -bidi_output_from][-bidi_input_through | -bidi_output_through][-bidi_input_to | -bidi_output_to][-uncons] [-delay_limit] [-check_clocks] [-net][-false_path_analysis {static | robust}] [-justify] [-true][-tclfile tclfile_name ] [-gcffile gcffile_name ][-summary] [-format column_list ] [-tcl_list] [{> | >>} filename ]Valid columns are: addition arc arrival bottle cell clkordata clkordatapindelay delay_ast direction edge eslack fanin fanout fpin from_edge hpininstance load lslack net phase pin pinload required slack slew stolen to_edgetpin wireload wlmodel

The report_timing command generates a timing report that provides information aboutthe various paths in the design. The reports typically contain data on the delay through theentire path. The start node and the end node of each path is identified.

The report contains the following information:

■ The slack times of the arriving signal at the end node

■ The start node

■ The associated transitions

■ The signal required times and the actual signal arrival times

If the filename is specified, then the report is written out to the file. Otherwise, the reportis displayed on the standard output. The detailed timing information is reported by default.

The -format option lets you customize the reports to your needs by requesting the exactfields in which you have an interest. Using a combination of the -format and -tcl_listoptions lets you integrate the timing reports into your Tcl scripts.

The -from option lets you limit the number of paths reported. It can also be used to findspecific paths in the design. Using this option with the max_paths option finds all paths froma specific input. The -max_paths and the -max_points options limit the -from option.



Arguments

-clock_from clock_name_listEnables reports generated based on source clock. Reports onlythose paths whose source clocks are the clocks inclock_name_list .

-clock_to clock_name_listEnables reports generated based on target clock. Reports onlythose paths whose target clocks are the clocks inclock_name_list .

-edge_from {lead | trail}Enables reports generated based on source clock edge.

-edge_to {lead | trail}Enables reports generated based on target clock edge.

-from | -from_rise | -from_fall pin_listReports paths starting from the pin(s) specified by thepin_list . Using -from_rise (or -from_fall ) specifiesthat the rising (or falling) edge of the signals on the pins inpin_list are the start of the paths.

Note: This option combined with the -through and -to options provides a method forspecifying particular paths in the design.

-through | -through_rise | -through_fall pin_listReports paths that pass through the pin(s) specified by thepin_list . Any number of -through pins can be specified.Using -through_rise (or -through_fall ) specifies that thepaths go through the rising (or falling) edge of the signals on thepins in pin_list .

-to | -to_rise | -to_fall pin_listReports paths leading to the pin(s) specified by the pin_list .Pins in the pin_list can be either pins on the designboundary (ports) or pins on an instance. Only one list of -to pinscan be specified per report. Using -to_rise (or -to_fall )specifies that the rising (or falling) edge of the signals on the pinsin pin_list are at the end of the paths.

-bidi_input_from | -bidi_output_fromSpecifies that the bidirectional pins in the -from /-from_rise /



-from_fall pin list refer to the input or output part of thebidirectional pins.

-bidi_input_through | -bidi_output_throughSpecifies that the bidirectional pins in the -through /-through_rise /-through_fall pin list refer to the input oroutput part of the bidirectional pins.

-bidi_input_to | -bidi_output_toSpecifies that the bidirectional pins in the -to /-to_rise /-to_fall pin list refer to the input or output part of thebidirectional pins.

-unconsReports only the unconstrained paths (paths with no slack). If nopaths are found, there may be constrained paths or false pathsor the path may not exist. Each signal arriving at the path endnode which does not have a matching required time, results in anunconstrained path. If there is an asynchronous signal (specifiedwith ’@’ clock) arriving at the path end node, the path is alwaysreported as an unconstrained path.

Note: An asynchronous signal is applied to all the unconstrained primary inputs duringthis mode.

The report_timing command without -uncons optionreports only constrained paths. If no constrained path is found,there may be unconstrained paths or false paths or the path maynot exist. If no constrained or unconstrained path is found, thepath is either false or does not exist structurally.

Note: The -min_slack and -max_slack options cannot be specified with the-uncons option. See -delay_limit option described below.

See for the conditions under which a path is reported asconstrained or unconstrained.

-delay_limit floatSpecifies the path delay limit for unconstrained paths (-unconsoption).

For early paths (-early option), reports only those paths withpath delay less than the delay limit. For late paths (-late option)



reports only those paths with path delay more than the delaylimit.

-early | -lateThe timing report is generated for early paths (hold checks) orlate paths (setup checks). The default is -late .

-max_slack floatReports only those paths with slack equal to or less than thevalue of float are reported. The -max_slack option limits thereport to paths that fall into the specified range. A positive slackvalue indicates that timing was met. A negative value for slackindicates a timing violation.

Typically, you can report all violating endpoints by using:-max_slack 0.0 -max_points 1000

Note: This still limits the report to 1000 endpoints. The endpoint limitation can beadjusted to a reasonable number.

-min_slack floatReports only those paths whose slack is greater than the valueof float .

-max_paths integerEnables enumeration in the path filter, allowing the specifiednumber paths to be shown. The worst paths are enumeratedfirst.

The -max_paths option finds all the violating paths in thedesign, regardless of the endpoint. This is useful, but can be timeconsuming if a large number of paths are requested. The reportsare always sorted based on slack. The default number is oneendpoint. By default, report_timing reports the worst path itfinds to each endpoint up to the number specified by the-max_points option.

The -max_paths option does not work with the -max_pointsoption.

-max_points integerReports only the worst number of endpoints.The default is toshow one endpoint. This is the fastest and the most frequentlyused report.



The -max_points option does not work with the -max_pathsoption.

-nworst integerSpecifies the number of paths to be enumerated for eachendpoint. By default, only the worst path to each endpoint isreported.

The -nworst option does not work with the -max_path soption.

-rise | -fallReports the path with the specified edge on the endpoint.

If an endpoint is specified using -to_rise (or -to_fall )option, the -rise (or -fall ) option is ignored and paths withedge specified by -to_rise (or -to_fall ) are reported.

-check_clockEnables reports generated based on timing paths on the clocknetwork, instead of the standard timing to data endpoints.

Options for Reporting False Paths

In addition to the analysis that is performed by default, you can use options to perform falsepath analysis. The following five options (-false_path_analysis through -gcffile )deal with false path analysis. For more information, see Identifying and Eliminating FalsePaths in the Timing Analysis for Ambit BuildGates Synthesis and Cadence PKSmanual.

-false_path_analysis {static | robust}The -false_path_analysis option determines the status ofa path using static (or robust) analysis. Unless the -true optionis used to disable printing of false paths, a false path is indicatedin the report as shown in this example:

Path 1: FALSE PATH

-justifyThe -justify option gets one test vector for which the reportedpaths become true. This option also displays a test pattern foreach true path.

Note: This option can only be used with the -false_path_analysis option.



-trueThe -true option displays all true paths identified. The falsepaths identified are not printed. The sensitization criterion mustbe specified using the -false_path_analysis option.


-tclfile tclfilenameGenerates a Tcl file, tclfilename , containingset_false_path commands corresponding to the false pathsidentified. An error message is issued if tclfilename is notspecified.

You can source tclfilename before running thereport_timing command again. This filters out the falsepaths from the report and next available true paths are reported.The Tcl file can also be sourced before performing finer timingoptimizations so that the false paths are not optimized.


-gcffile gcffilenameGenerates a General Constraint Format (GCF) file,gcffilename , containing GCF DISABLE constraints whichcorrespond to the false paths identified. An error message isissued if gcffilename is not specified.

You can use gcffilename to pass the DISABLE constraints(false paths) to backend tools for operations like place and route.These backend tools will not consider the timing on the falsepaths while doing placement and routing.


Options for Formatting and Redirecting Reports

-netAdds a row for the net arc. By default, the net arc is not shown,and the net delay is added to the following delay.

-summaryGenerates a summary report for each path consisting of anendpoint, cause, slack, arrival time, required time, and phase.



-format column_listFormats the report according to the column_list . Thecolumn_list specifies which columns to display in the timingreport and the order in which they appear. For example:

-format {hpin cell delay required arrival required edge}

See Table 7-2 on page 633 for a list of valid options.

-tcl_listThe report is produced in a tcl list, not a human-readable report.This is useful for integrating timing with custom Tcl functions andalso for customizing report generation.

{> | >>} filenameStores the generated report in the file specified by filename .If the filename is not specified the report is displayed on standardoutput. The filename must be the last argument in the list.

Related Information

report_net

report_port

set_table_style


Examplesac_shell[33]>report_timing -to out+--------------------------------------------+| Report | report_timing ||---------------------+----------------------|| Options | -to out |+---------------------+----------------------+| Date | 20000820.204141 || Tool | ac_shell || Release | v4.0-eng || Version | Aug 18 2000 07:33:54 |+---------------------+----------------------+| Module | top || Timing | LATE || Slew Propagation | FAST || Operating Condition | CTLF_OP_COND || PVT Mode | worst_case || Tree Type | worst_case || Process | 1.00 |



| Voltage | 3.30 || Temperature | 25.00 || time unit | 1.00 ns || capacitance unit | 1.00 pF || resistance unit | 1.00 kOhm |+--------------------------------------------+Path 1: VIOLATED External Delay AssertionEndpoint: out (^) checked with trailing edge of ’CLK1’Beginpoint: J_block/C_reg/Q (^) triggered by leading edge of ’CLK2’Other End Arrival Time 2.00- External Delay 1.00+ Phase Shift -1.00= Required Time 0.00- Arrival Time 9.25= Slack Time -9.25 +--------------------------------------------------------------------+ | Instance | Arc | Cell | Delay | Arrival | Required | | | | | | Time | Time | |---------------+-------------+---------+-------+---------+----------| | | clkC ^ | | | 0.05 | -9.20 | | J_block | clkc ^ | J_block | | 0.05 | -9.20 | | J_block/C_reg | CP ^ -> Q ^ | FD1QA | 0.21 | 0.26 | -8.99 | | J_block/zbuf0 | A ^ -> Z ^ | BUFA | 0.13 | 0.39 | -8.86 | | J_block/zbuf1 | A ^ -> Z ^ | BUFA | 0.13 | 0.52 | -8.73 | | J_block/u000 | A ^ -> Z ^ | AND2L | 8.73 | 9.25 | 0.00 | | J_block | out ^ | J_block | | 9.25 | 0.00 | | | out ^ | | 0.00 | 9.25 | 0.00 | +--------------------------------------------------------------------+

The following command gives a report similar to the first with the addition of net arcinformation.

report_timing -to {out[4]} -net+------------------------------------------------------------------------------------+| Pin | Edge | Net | Cell | Delay | Arrival | Required || | | | | | Time | Time ||------------------+-------+------------------+---------+-------+---------+----------|| clkC | ^ | clkC | | | 0.05 | -9.20 || J_block/clkc | ^ | J_block/clkc | J_block | | 0.05 | -9.20 || J_block/C_reg/CP | ^ | J_block/clkc | FD1QA | 0.00 | 0.05 | -9.20 || J_block/C_reg/Q | ^ | J_block/w03 | FD1QA | 0.21 | 0.26 | -8.99 || J_block/zbuf0/A | ^ | J_block/w03 | BUFA | 0.00 | 0.26 | -8.99 || J_block/zbuf0/Z | ^ | J_block/w03prime | BUFA | 0.13 | 0.39 | -8.86 || J_block/zbuf1/A | ^ | J_block/w03prime | BUFA | 0.00 | 0.39 | -8.86 || J_block/zbuf1/Z | ^ | J_block/Z | BUFA | 0.13 | 0.52 | -8.73 || J_block/u000/A | ^ | J_block/Z | AND2L | 0.00 | 0.52 | -8.73 || J_block/u000/Z | ^ | J_block/out | AND2L | 8.73 | 9.25 | 0.00 || J_block/out | ^ | out | J_block | | 9.25 | 0.00 || out | ^ | out | top | 0.00 | 9.25 | 0.00 |+------------------------------------------------------------------------------------+

The following command displays the worst late path in the design. The format of the report issimilar to the first example.



report_timing

The following command displays the worst late path to each violating endpoint that has aslack less than -1.0:

report_timing -max_slack -1.0

The following command displays all the late paths that end at port out[2] and that havenegative slack up to a maximum of 1000 worst paths. If there are more than 1000 paths, onlythe 1000 worst paths are reported.

report_timing -to out[2] -max_paths 1000 -max_slack 0.0

This command reports the worst late path that starts at in[0] and ends at out[1] .

report_timing -from in[0] -to out[1]

The following command displays the three latest paths that start at in[1] and end at out[3 ].With reconvergent fanout, more than one path may exist:

report_timing -from in[1] -to out[3] -max_paths 3

The following command displays the ten latest paths. Only the paths between the specifiedpins are enumerated.With reconvergent fanout, more than one path may exist:

report_timing -from i102/Z -to i123/A -max_paths 10

The next command enumerates the worst ten paths through the given two pins, starting atthe beginning points in the design and ending at the endpoints. This is similar to using the-from option.

report_timing -through i102/Z -through i123/A -max_paths 10

The following command reports the ten worst paths through blocks A and C, or blocks B andC. The path only has to satisfy one element in a through list, but all through lists must besatisfied. The example can be thought of as ((A or B) and C).

report_timing -through {A/*B/*} -through {C/*} -max_paths 10



The next command reports the worst endpoint and the ten worst paths to that endpoint.Similar to report_timing -max_paths 10 -to out[1] , if out[1] is the worstendpoint:

report_timing -max_points 1 -nworst 10

The next two examples illustrate the -uncons option.

ac_shell[6]>report_timing -uncons+--------------------------------------------+| Report | report_timing ||---------------------+----------------------|| Options | -uncons |+---------------------+----------------------+| Date | 20010122.181608 || Tool | ac_shell || Release | v4.1-eng || Version | Jan 22 2001 15:25:02 |+---------------------+----------------------+| Module | scid || Timing | LATE || Slew Propagation | WORST || Operating Condition | NOM || PVT Mode | max || Tree Type | balanced || Process | 1.00 || Voltage | 5.00 || Temperature | 25.00 || time unit | 1.00 ns || capacitance unit | 1.00 pF || resistance unit | 1.00 kOhm |+--------------------------------------------+Path 1:Endpoint: O2 (^)Beginpoint: reg2/Q (v) triggered by trailing edge of ’vclk’ +--------------------------------------------------+ | Instance | Arc | Cell | Delay | Arrival | | | | | | Time | |----------+-------------+-------+-------+---------| | | clk1 v | | | 10.00 | | nand1 | B v -> Z ^ | ND2 | 0.17 | 10.17 | | buf1 | A ^ -> Z ^ | BUF8A | 0.18 | 10.35 | | reg2 | CP ^ -> Q v | FD1 | 0.74 | 11.09 | | nand4 | A v -> Z ^ | ND2 | 0.07 | 11.16 | | | O2 ^ | | 0.00 | 11.16 | +--------------------------------------------------+

ac_shell[3]>report_timing -uncons -summary+--------------------------------------------+| Report | report_timing ||---------------------+----------------------|| Options | -uncons -summary |+---------------------+----------------------+| Date | 20010122.181053 || Tool | ac_shell || Release | v4.1-eng |



| Version | Jan 22 2001 15:25:02 |+---------------------+----------------------+| Module | scid || Timing | LATE || Slew Propagation | WORST || Operating Condition | NOM || PVT Mode | max || Tree Type | balanced || Process | 1.00 || Voltage | 5.00 || Temperature | 25.00 || time unit | 1.00 ns || capacitance unit | 1.00 pF || resistance unit | 1.00 kOhm |+--------------------------------------------+ +----------------------------------------------------------+ | Pin | Cause | Arrival | Phase | |-----------+--------------------+---------+---------------| | O2 ^ | Unconstrained Path | 10.82 | vclk N | | O1 v | Unconstrained Path | 0.70 | vclk P | | reg2/D ^ | Unconstrained Path | 0.24 | Unconstrained | | reg3/D ^ | Unconstrained Path | 0.17 | Unconstrained | | reg1/D v | Unconstrained Path | 0.15 | Unconstrained | | reg4/D v | Unconstrained Path | 0.15 | Unconstrained | | nand1/A v | Unconstrained Path | 0.00 | Unconstrained | +----------------------------------------------------------+

Figure 7-3 Conditions for Unconstrained and Constrained Paths

The path from I to O is reported as an unconstrained path under the following conditions(constraints on I and O):

1. No constraints on either I or O

2. set_input_delay -clock ck1 1.0 INo set_external_delay constraint on O

3. set_external_delay -clock ck1 1.0 ONo set_input_delay constraint on I

4. set_input_delay 1.0 Iset_external_delay 1.1 O

5. set_input_delay -clock ck1 1.0 Iset_data_required_time -clock ck2 1.0 O

I O



The path from I to O is reported as a constrained path under the following conditions(constraints on I and O):

1. set_input_delay -clock ck1 1.0 Iset_external_delay -clock ck1 1.0 O


3. set_data_arrival_time -clock ck1 1.0 Iset_data_required_time -clock ck1 1.0 Oset_data_required_time -clock ck2 1.0 O

Two paths from I to O are reported one as a constrained path and the other one as anunconstrained path under the following conditions (constraints on I and O):

1. set_input_delay -clock ck1 1.0 Iset_input_delay -clock ck2 1.0 I


The following command changes the format of the report, Compare the output to that shownin the first example.

report_timing -to out -format {instance arc net load delay arrival}+--------------------------------------------------------------------------+| Instance | Arc | Net | Load | Delay | Arrival || | | | | | Time ||---------------+-------------+------------------+-------+-------+---------|| | clkC ^ | clkC | | | 0.05 || J_block | clkc ^ | J_block/clkc | | | 0.05 || J_block/C_reg | CP ^ -> Q ^ | J_block/w03 | 0.00 | 0.21 | 0.26 || J_block/zbuf0 | A ^ -> Z ^ | J_block/w03prime | 0.00 | 0.13 | 0.39 || J_block/zbuf1 | A ^ -> Z ^ | J_block/Z | 0.00 | 0.13 | 0.52 || J_block/u000 | A ^ -> Z ^ | J_block/out | 3.20 | 8.73 | 9.25 || J_block | out ^ | out | | | 9.25 || | out ^ | | | 0.00 | 9.25 |+--------------------------------------------------------------------------+

Table 7-2 Report Timing — Column List Options

Option Description

addition Delay addition on pin. This delay typically comes from cycleaddition or clock uncertainty. The column is labeled DelayAddition .



arc The arc as described by the from pin, from pin edge, to pin,and to pin edge. For example, the arc from the rising edge ofpin A to the falling edge of pin Z is reported as:

A ^->Z v

arrival The arrival time on the pin.

bottle The number of paths in the report that pass through the pin.

cell The cell name of the given pin’s instance.

clkordata Reports whether the given pin is on a clock path or a datapath. The column is labeled Clock/Data .

clkordatapin Reports whether the given pin expects a clock signal or adata signal. The column is labeled Clock Expected .

delay The arc delay.

delay_ast Reports if a delay has been asserted on the arc.

direction The pin direction (IN, OUT).

edge The edge on the pin (^=rise, v=fall).

eslack The worst early slack at the given pin.

fanin The total fanin on the net.

fanout The total fanout on the net.

fpin The from or source pin of the arc.

from_edge The edge on the from, or source, pin.

hpin The hierarchical pin name.

instance The hierarchical name of the given pin’s instance.

load The total capacitive load on a given pin.

lslack The worst late slack at the given pin.

net The hierarchical name of the net connected to given pin.

phase Phase name on pin.

pin The pin name of the given hierarchical pin.

pinload The total capacitive load from pins on a given pin, includingits own load.

required The required time on the pin.



slack The slack on the pin (this is the same for the entire path).

slew The propagated slew at the given pin

stolen The slack stolen at the given pin. (only visible on the outputof transparent latches.)

to_edge The edge on the to, or sink, pin.

tpin The to, or sink, pin of the arc.

wireload The total capacitive load from the wire on a given pin.

wlmodel Wireload model used to calculate load on the net.



reset_clock_gating_check

reset_clock_gating_check [-setup | -hold] [-rise | -fall][-pin instance_or_pin_list ] [-clock clock_list [-lead | -trail]]

With reset_clock_gating_check , any timing margin specified withset_clock_gating_check can be set back to the default value.

Arguments

-setup | -holdResets the timing margin (setup value or hold value) for theclock-gating setup check back to the default setup or hold value.

-rise | -fallResets the specified timing margin for the rising (or falling) delayonly. If neither option is specified, the default resets both risingand falling.

-lead | -trailResets the specified timing margin for only those clock-gatingchecks for which the reference clock edge is the leading (ortrailing) edge. If neither option is specified, the timing marginsare reset on both leading and trailing edges.

The -lead or -trail options can only be used with the-clock option.

-pin instance_or_pin_listList of pins for which the timing margins (setup/hold values) forclock-gating checks are reset. If the name of a clock-gatinginstance is given in the argument list, the command resets allinputs of the instance. Likewise, if the clock input pin of theinstance is given, the command again resets all the instanceinputs.

-clock clock_listSpecifies the ideal clocks for which the command resets aclock-gating assertion to the default. The timing margins forclock-gating checks for any instance that gates a clock signalhaving such an assertion are reset.



Related Information

set_clock_gating_check

Clock Gating Setup and Hold Checks in the Timing Analysis for Ambit BuildGatesSynthesis and Cadence PKS manual.

Examplesreset_clock_gating_check -setup -clock CLK1



reset_clock_root

reset_clock_root [-clock clk_name ] [-pos] [-neg] pin_list

Removes previously given clock root assertions. Its behavior follows that ofset_clock_root , except both -pos and -neg can be given at the same time. If the-clock option is absent, all clock root assertions are removed.

Tip

Alternatively, you can use the following command to remove all clock assertions ona pin x :

remove_assertions -type clock_root x

Arguments

-clock ideal_clock_nameName of the ideal clock as specified by the previousset_clock_root assertion.

-posRemoves a positive ideal clock. If neither -pos nor -neg isspecified, the default is -pos (rising edge precedes falling edge).

-negRemoves a negative ideal clock. If neither -pos nor -neg isspecified, the default is -pos (rising edge precedes falling edge).

pin_listList of pins to remove from association with an ideal clock. Thepin can be a port or an instance pin. These can either be objectIDs or hierarchical names relative to the current module.

Related Information

set_clock_root

remove_assertions

Examplesreset_clock_root -clock master -neg -pos {negclk posclk}




reset_constant_for_timingpin_list

The reset_constant_for_timing command removes previously asserted constants onthe specified pin(s). Once a constant has been reset, the timing engine returns to analyzingthe system by calculating and propagating the arrival times (and in turn computing therequired times) at the pin.

Arguments

pin_listSpecifies a single pin or multiple pins to reset. To specify multiplepins, enclose the list with curly braces ({) } and separate the pininformation with white-spaces.

Related Information



Examplesreset_constant_for_timing X20/Z



reset_disable_cell_timing

reset_disable_cell_timing [-library library_name ] -cell cell_name -from_pinfrom_pin_name -to_pin to_pin_name

The reset_disable_cell_timing command re-enables timing arcs that were disabledby the set_disable_cell_timing command. The timing arcs from/to internal pins insideIP cells can also be disabled.

Arguments

-cell cell_nameSpecifies the cell in the library for which timing checks arere-enabled.

-from_pin from_pin_nameSpecifies the source pin of the timing arc.

-to_pin to_pin_nameSpecifies the sink pin of the timing arc.

-library library_nameSpecifies the library that contains the cell. If not specified, thedefault is the target technology library.

Related Information

set_disable_cell_timing

set_disable_timing

set_false_path


Examplesreset_disable_cell_timing -cell ram -from_pin write_enable -to_pin Z



reset_disable_timing

reset_disable_timing [-from from_pin ] [-to to_pin ]

The reset_disable_timing command deletes the assertion created byset_disable_timing with the exact same pin(s). For example, you cannot disable all thearcs to a pin individually and then use reset_disable_timing -to pin to reset all thearcs.

Tip

To reset all of the arcs, use the same number of commands with the exact samepin(s), only replacing set_disable_timing with reset_disable_timing .

Check for bidi options

Arguments

-from from_pinsSpecifies the source pin of the timing arc to be re-enabled.If the -from option is used without the -t o option, all pathsoriginating from the from_pins are enabled.Either -from or -to must be used with this command.Specifying both -from and -to identifies a path with specificstart and endpoints.The -from and -to options can be intermediate hierarchicalboundaries.

-to to_pinsSpecifies the sink pin of the timing arc to be re-enabled.If the -to option is used without the -from option, all pathsending in to_pins are enabled.

-bidi_input_from | -bidi_output_fromSpecifies the assertion on the input or output part of the frompin. Default value is shown in “Bidirectional Pin Defaults” onpage 776.

-bidi_input_to | -bidi_output_toSpecifies the assertion on the input or output part of the to pin.Default value is shown in “Bidirectional Pin Defaults” onpage 776.



Related Information

set_disable_timing

set_false_path


Examples

The following command re-enables all timing arcs from the Q pin of instance I1 .

reset_disable_timing -from I1/Q

The following command re-enables the timing arc from the input part of bidirectional pin A tothe output part of bidirectional pin B.

reset_disable_timing -from A -to B -bidi_input_from -bidi_output_to

The following command re-enables the timing arc from the A pin to Z pin of instance NAND2.

reset_disable_timing -from NAND2/A -to NAND2/Z

The following command re-enables all timing arcs which pass through the hierarchical port,port1 , of module mod and end at an input or bidirectional pin.

reset_disable_timing -from mod/port1



reset_external_delay

reset_external_delay [-clock clk_name ] [-lead] [-trail] [-early] [-late][-rise] [-fall] pin_list

Resets previously given external delay assertions. Its behavior follows that ofset_external_delay , except both -lead and -trail can be given at the same time.

Tip

To remove all external delay assertions (without specifying the clocks) for a pin x ,use

remove_assertions -type external_delay x

Arguments

pin_listSpecifies a single pin or multiple pins for which the external delayis reset. To specify multiple pins, enclose the list with curlybraces ({) } and separate the pin information with white-space.

-rise | -fallResets the external delay for the rising edge or falling edge at theinput port. If both -rise and -fall options are omitted, theexternal delay is reset on both the edges.

-early | -lateSpecifies that the constraint refers to the early (hold) or late(setup) times. If both -late and -early options are omitted,then the external delay is reset for both early and late times.

-clock clock_nameSpecifies the name of the clock. Default is the asynchronous (@)clock.

-leadResets the external delay for the leading edge of the clock. Ifneither -lead nor -trail is specified, the default is -lead .

-trailResets the external delay for the trailing edge of the clock. Ifneither option is provided, the default is -lead .



Related Information

set_external_delay

remove_assertions

Examplesreset_external_delay -clock clk1 -lead -trail out




reset_functional_mode -group group_name -mode mode_name instance_list

The reset_functional_mode command lets you reset the DCL or the STAMP functionalmode group and name on hierarchical instances. To determine what modes are available foran instance, use report_functional_mode .

This command has no effect if the mode is already inactive. If you reset a mode which is theonly active mode, then all modes become active. For example, consider a mode group rwwith two modes read and write . If you set read and then reset it, both modes read andwrite become active again, as if no modes had been set. This behavior differs fromPrimeTime which leaves all modes inactive if one is set and then later reset.

Note: Currently there is no command to make all modes inactive.

Arguments

-group group_nameSpecifies the string value of the functional mode group name.

-mode mode_nameSpecifies the string value of the functional mode name.

instance_listSpecifies the list of instances for which the functional modeneeds to be reset.

Related Information


set_functional_mode

Examplesreset_functional_mode -group rw -mode read A1/B3/C2



reset_input_delay

reset_input_delay [-clock clk_name ] [-lead] [-trail] [-early] [-late] [-rise][-fall] pin_list

Resets previously given input delay assertions. Its behavior follows that ofset_input_delay , except both -lead and -trail can be given at the same time.

Tip

To remove all input delay assertions (without specifying the clocks) for a pin x , use

remove_assertions -type input_delay x

Arguments

pin_listSpecifies a single pin or multiple pins for which the input delay isreset. To specify multiple pins, enclose the list with curly braces({) } and separate the pin information with white-space.

-rise | -fallResets the input delay for the rising edge or falling edge at theinput port. If both -rise and -fall options are omitted, theinput delay is reset on both the edges.

-early | -lateSpecifies that the constraint refers to the early (hold) or late(setup) times. If both -late and -early options are omitted,then the input delay is reset for both early and late times.


-leadResets the input delay for the leading edge of the clock. If neither-lead nor -trail is specified, the default is -lead .

-trailResets the input delay for the trailing edge of the clock. If neitheroption is provided, the default is -lead .



Related Information

set_input_delay

remove_assertions

Examplesreset_input_delay -clock clk1 -lead -trail in



reset_tech_info

reset_tech_info({[-library list_of_library_names ][-default_wire_load] [-default_wire_load_selection][-default_operating_conditions][-default_fanout_load] [-default_max_capacitance][-default_max_fanout] [-default_max_transition][-input_threshold_pct_rise] [-input_threshold_pct_fall][-output_threshold_pct_rise] [-output_threshold_pct_fall][-slew_lower_threshold_pct_rise] [-slew_lower_threshold_pct_fall][-slew_upper_threshold_pct_rise] [-slew_upper_threshold_pct_fall][-pvt { min | typ | max}])|([-library list_of_library_names ] -cell list_of_cell_names[-dont_modify] [-dont_utilize][-scaling_factors][-input_threshold_pct_rise] [-input_threshold_pct_fall][-output_threshold_pct_rise] [-output_threshold_pct_fall][-slew_lower_threshold_pct_rise] [-slew_lower_threshold_pct_fall][-slew_upper_threshold_pct_rise] [-slew_upper_threshold_pct_fall][-pvt { min | typ | max}])|([-library list_of_library_names ]-cell list_of_cell_names-pin list_of_pin_names[-fanout_load] [-max_fanout][-max_transition] [-max_capacitance][-pvt { min | typ | max}])}

The reset_tech_info resets the original value of the library data for the specifiedparameters in the named target libraries. This overrides values previously specified with theset_tech_info command with the values from the library itself.


-library list_of_library_namesSpecifies the libraries to which the reset is applied. Default is alllibraries specified with the set_global target_technologycommand.

-pvt {min | typ | max}Resets the value for the environment corner of interest. Sets thevalue for the environment corner of interest. You can set one PVTcorner per command.The default is typ .




-default_wire_loadResets the default wire-load model for the library.

-default_wire_load_selectionResets the default wire-load selection table for the library.

-default_operating_conditionsResets the default operating conditions for the library.

-default_fanout_loadResets the value of the default fanout load for all pins on all cellsin the library.

-default_max_capacitanceResets the value of the default maximum capacitance for all pinson all cells in the library.

-default_max_fanoutResets the value of the default maximum fanout for all pins on allcells in the library.

-default_max_transitionResets the value of the default maximum transition time for allpins on all cells in the library.

-input_threshold_pct_rise floatResets the value of the default input threshold percent for therising edge for all cells in the library.

-input_threshold_pct_fall floatResets the value of the default input threshold percent for thefalling edge for all cells in the library.

-output_threshold_pct_rise floatResets the value of the default output threshold percent for therising edge for all cells in the library.

-output_threshold_pct_fall floatResets the value of the default output threshold percent for thefalling edge for all cells in the library.



-slew_lower_threshold_pct_rise floatResets the value of the default lower threshold percent for theslew time of the rising edge for all cells in the library.

-slew_lower_threshold_pct_fall floatResets the value of the default lower threshold percent for theslew time of the falling edge for all cells in the library.

-slew_upper_threshold_pct_rise floatResets the value of the default upper threshold percent for theslew time of the rising edge for all cells in the library.

-slew_upper_threshold_pct_fall floatResets the value of the default upper threshold percent for theslew time of the falling edge for all cells in the library.


-cell list_of_cell_namesSpecifies the cells to which the reset is applied. Requiredargument for cell and pin level assertions.

-dont_modifyResets to the original value in the library. If true , the cell is notmodified in optimization or time budgeting.

-dont_utilizeResets true or false . If true , the cell is not used inoptimization.

-scaling_factorsResets the name of the derating table used for scaling.

-input_threshold_pct_rise floatResets the value of the default input threshold percent for therising edge for the listed cells.

-input_threshold_pct_fall floatResets the value of the default input threshold percent for thefalling edge for the listed cells.



-output_threshold_pct_rise floatResets the value of the default output threshold percent for therising edge for the listed cells.

-output_threshold_pct_fall floatResets the value of the default output threshold percent for thefalling edge for the listed cells.

-slew_lower_threshold_pct_rise floatResets the value of the default lower threshold percent for theslew time of the rising edge for the listed cells.

-slew_lower_threshold_pct_fall floatResets the value of the default lower threshold percent for theslew time of the falling edge for the listed cells.

-slew_upper_threshold_pct_rise floatResets the value of the default upper threshold percent for theslew time of the rising edge for the listed cells.

-slew_upper_threshold_pct_fall floatResets the value of the default upper threshold percent for theslew time of the falling edge for the listed cells.


-pin list_of_pin_namesSpecifies the pins to which the reset is applied. Requiredargument for pin level assertions.

-fanout_loadResets the value of the fanout load for the named pins.

-max_fanoutResets the value of the maximum fanout for the named pins.

-max_transitionResets the value of the maximum transition time for the namedpins.



-max_capacitanceResets the value of the maximum capacitance for the namedpins.

Related Information

set_tech_info

get_tech_info


Examples

These examples follow those of get_tech_info .

ac_shell>reset_tech_info -library lib1 lib2 -default_fanout_load

ac_shell>reset_tech_info -cell FD2ESSA -dont_utilize

ac_shell>reset_tech_info -library lca300kv -cell B2I -pin Z1 -pvt min -max_fanout




reset_time_borrow_limit -pin pin_list -clock list_of_clocks

The reset_time_borrow_limit command resets the maximum borrow time as set by theset_time_borrow_limit assertion to the default value (Max = pulse width - setup). Theborrow limit can be reset on pins or waveforms.

Arguments

-pin pin_or_instance_listResets the borrow limit on a single pin or multiple pins of latches.To specify multiple pins, enclose the list with curly braces ({} )and separate the pin information with white-space.

You can alternatively give a list of latch instances. In which case,the default limit applies to the clock pins of the instances listed.


Resets the borrow limit for the named ideal clocks.

If neither -pin nor -clock option is specified, the borrow limitis placed on all clocks.

Related Information




Examplesreset_time_borrow_limit -pin l1/en



reset_wire_load

reset_wire_load[-pvt {min | typ | max}] [ list_of_instances ]

The reset_wire_load command resets the wire-load model to the default wire-load modelon the specified instances. The default model is the default specified in the library, unlessoverridden by the set_tech_info -default_wire_load command. If the list ofinstances is omitted, the wire-load model is reset for the current instance.

Arguments

list_of_instancesSpecifies the instances to which the default wire-load model isre-applied. The default is the current instance.

-pvt {min | typ | max}Resets the wire-load model for a particular PVT (process,voltage, temperature) corner. You can choose one, two, or threePVT corners. If you choose more than one corner, enclose thelist in curly braces ({} ) and separate the values by spaces. Bydefault, the specified wire-load model is reset for all three PVTcorners.

Related Information

set_wire_load

write_assertions

set_tech_info -default_wire_load

get_tech_info -default_wire_load

Examplesreset_wire_load -pvt min J_block



reset_wire_load_selection_table

reset_wire_load_selection_table[-library library_name ] [-pvt {min | typ | max}]

The reset_wire_load_selection_table command lets you reset the wire-loadselection table entry previously specified by the set_wire_load_selection_tablecommand. The default wire load selection table specified in the library library_namebecomes the selection table to be used for wire load calculations.

Arguments

-library library_nameThe name of the technology library to search for the wire loadselection table. The default is the target technology library.

-pvt {min | typ | max}Resets the wire-load model selection table for a particular PVT(process, voltage, temperature) corner. You can choose one,two, or three PVT corners. If you choose more than one corner,enclose the list in curly braces ({} ) and separate the values byspaces. By default, the specified wire-load model selection tableapplies to all three PVT corners.

Related Information

set_wire_load_selection_table

set_wire_load

report_library


Examples

The following command resets the wire-load selection table to the one specified in thewireloads2 library for the min PVT corner.

reset_wire_load_selection_table -library wireloads2 -pvt min



set_begin_tag

set_begin_tag-tag tag_name pin_list

Important

Do not use this command, it is generated by the system. The following descriptionis for reference only.

The set_begin_tag command is automatically generated by the timing analysis systemfrom your multicycle path (MCP) and false path assertions. Internally, set_begin_tagindicates that the specified pin is a begin point for the specified tag.

Arguments

-tag tag_nameThe tag_name is a system-generated string

pin_listA Tcl list of pins. This command associates the tag to all pathsgoing through the specified pins in the pin list.

Related Information

set_cycle_addition

set_false_path



set_clock

set_clock clock_name{[-period period ] | [-waveform { lead_time trail_time }]}

The set_clock command defines an ideal clock. An ideal clock must be defined as a globalreference signal for all the data signals in the design. The ideal clock is defined by its name,period, and position of the leading edge and trailing edge.

In a single-clock design, only one set_clock command is used. In a multiphase clocksystem, several set_clock commands are used to define each phase of the clock. Forpurely combinational design, an ideal clock (or any clock) definition is not necessary.

The scope of this command is the entire session of ac_shell . Once an ideal clock isdefined, it remains accessible to all subsequent commands.

The clock generated by this command is not saved in the .adb file.

Arguments

clock_nameName of the ideal clock.

-period periodThe period of the ideal clock is set to period . If the period is notspecified, it is derived from the waveform specification such thata symmetric clock (50% duty cycle) is generated. Units arespecified in the library.

-waveform { lead_time trail_time }The clock waveform is defined by a leading edge and a trailingedge. The braces are used to create a list. A Tcl list can also becreated using a pair of quotes (““), so braces can be replaced byquotes.

The lead_time is the time at which the first transition on theclock occurs. The trail_time is the time at which secondtransition on the clock occurs.

If -waveform is not specified, the leading edge is placed at 0and the trailing edge is placed at the midpoint of the period suchthat a symmetric clock is generated.

Either the period or the waveform option must be specified.



Related Information

set_clock_root



set_input_delay


set_external_delay

Examples

The first command in this example defines an ideal clock called master with a period of 10 ,with leading transition at 0 and trailing transition at 5. The second command defines an idealclock called A with a period of 100 , with leading transition at 30 and trailing transition at 90 .

set_clock master -period 10 -waveform {0 5}

Figure 7-4 Ideal Cock Example 1.

0 5 10

master

negative clock

positive clock

lead trail period



set_clock A -period 100 -waveform {30 90}

Figure 7-5 Ideal Cock Example 2.

0 30 90 100

A

negative clock

positive clock

lead trail period



set_clock_arrival_time

set_clock_arrival_timeOBSOLETE: Use set_clock_root and set_clock_insertion_delay instead.

Important

Do not use set_clock_arrival_time , use set_clock_root andset_clock_insertion_delay instead. See set_clock_root on page 676 andset_clock_insertion_delay on page 668.

Starting in the Ambit 4.0 release set_clock_arrival_time is an internallygenerated command. You should use set_clock_insertion_delay insteadbecause it is easier to understand and is more consistent with constraints from othertools. Cadence timing analysis still writes out set_clock_arrival_time during timebudgeting. The following description is for reference only.

set_clock_arrival_time-clock clock_name [-early | -late] [-rise rise_time ] [-fall fall_time ][-pos | -neg] [-bidi_input | -bidi_output]pin_list

The internally generated set_clock_arrival_time command associates the ideal clockto physical ports of the design in the database. It defines the actual clock signals arriving atthe input port of the design in relation to the ideal clock signal defined by the set_clockcommand.



set_clock_gating_check

set_clock_gating_check [-setup | -hold] [-rise | -fall][-clock clock_list [-lead | -trail]] [-pin instance_or_pin_list ] float

The set_clock_gating_check command gives you the ability to create or override thedefault setup and hold values for clock-gating timing checks.

You cannot use this command to create clock-gating assertions for hierarchical pins or clockports. You must use it on pins where clock-gating occurs and these assertions are notpropagated along the clock tree.

If neither -pin nor -clock option is specified, then the timing margin specified becomes aglobal assertion and will be used for all clock gating checks. However, pin-based timing checkassertions have higher priority and, if they exist, they override the global assertion.

The timing analyzer uses the following priority rules to determine the timing margin to use fora particular clock gating check:

1. Use the timing check assertion on the data pin if it exists

2. Otherwise, use the timing check assertion on the clock pin if it exists

3. Otherwise, use the timing check assertion on the ideal clock (for the clock pin) if it exists

4. Otherwise, use the global timing check assertion if it exists

5. If no timing check assertion is present, use the gate delay. This value is:

■ For setup checks: the delay from the data pin to the output

■ For hold checks: the delay from the clock pin to the output

These rules are demonstrated in the example.

Arguments

-setup | -holdSpecifies the type of clock-gating check, either setup or hold. Ifneither option is present, the timing margin is applied to bothsetup and hold.

-rise | -fallApplies the specified timing margin to the rising (or falling) delayonly. If neither option is specified, the default is both rising andfalling.



-lead | -trailApplies the specified timing margin to only those clock-gatingchecks for which the reference clock edge is the leading (ortrailing) edge. If neither option is specified, the timing marginsapply to both leading and trailing edges.

The -lead or -trail options can only be used with the-clock option.

-pin instance_or_pin_listList of pins for which the timing margins (setup/hold values) forclock-gating checks are overridden with those specified with the-setup and -hold options. If the name of a clock-gatinginstance is given in the argument list, the command applies to allinputs of the instance. Likewise, if the clock input pin of theinstance is given, the command again applies to all the instanceinputs.

-clock clock_listSpecifies the ideal clocks for which the command creates aclock-gating assertion. The timing margins for clock-gatingchecks for any instance that gates a clock signal having such anassertion are overridden.

floatThe timing margin (setup value or hold value) for the clock-gatingsetup check.

The default values when this command is not used depends onthe anaylsis mode. In ideal propagation mode, the clock networkis assumed to have zero delays, so timing analysis uses zerosetup and zero hold time. In propagated mode, for setup time,the analysis uses the maximum arc delay from the data pin to theoutput pin. For hold time, it uses the minimum arc delay from theclock pin to the output pin.

Related Information

reset_clock_gating_check

Clock Gating Setup and Hold Checks in the Timing Analysis for Ambit BuildGatesSynthesis and Cadence PKS manual.



Examples

This example illustrates the priority rules for multiple timing check assertions for the gatedclock shown in Figure 7-6 on page 663.

Figure 7-6 Gated Clock

Tcl script:

# ideal clock

set_clock CLK1 -period 12 -waveform "0 6"

set_clock_root -clock CLK1 clk

...

# clock-gating timing check assertions

# on ideal clock

set_clock_gating_check -setup 0.44 -clock CLK1

set_clock_gating_check -hold 0.11 -rise -clock CLK1

# on clock pin

set_clock_gating_check -setup 0.55 -pin g1/A

#on data pin

set_clock_gating_check -setup 0.66 -rise -pin g1/B

Given the above commands, the following timing margins are used for slack calculation:

SETUP g1/B rise: 0.66 — from g1/B (rule 1.)

SETUP g1/B fall: 0.55 — from g1/A (rule 2.)

HOLD g1/B rise: 0.11 — from CLK1 (rule 3.)

HOLD g1/B fall: 0.20 — from Delay A->C (rule 5.)

clk

inp CAB

Delay A->C: 0.20Delay B->C: 0.30

g1clk_out




set_clock_info_changeTo change to a data signal use: set_clock_info_change[-lead | -trail] [-early | -late] [-rise | -fall]-clock clock_namepin_list||To change to a clock signal use: set_clock_info_change[-pos | -neg] [-early | -late] [-rise | -fall]-clock clock_namepin_list

The set_clock_info_change command changes the clock/data information for pathsgoing through the specified pins for the downstream logic. This command is useful formodeling frequency dividers and clock-shaping circuits. The command can be used tochange:

■ Clock to data

■ Data to clock

■ Clock to clock (derived clock)

■ The associated clock information

Calculations

This section describes how the rising and the falling edges of the final (mapped) clock signalare computed when the output of a gate register is defined as a clock

Here RAold is the arrival time of the rising edge of the original signal before mapping.Similarly, FAold is the arrival time of the falling signal.

For a signal mapped to a positive clock

Rising edge = RAold

Falling edge = FAold + (ClockTrailingEdge - ClockLeadingEdge)

ClockLeadingEdge and ClockTrailingEdge are times at which the leading and the trailingedges of the ideal clock occur. Here the rising edge of the mapped clock corresponds to theleading edge of the ideal clock and falling edge corresponds to the trailing edge.

Similarly, if the signal is mapped to a negative clock:

Rising edge = RAold + (ClockTrailingEdge - ClockLeadingEdge)



Falling edge = FAold

Here the falling edge of the mapped clock corresponds to the leading edge of the ideal clockand rising edge corresponds to the trailing edge.

Derived Clocks

A clock to clock set_clock_info_change command on a pin results in starting a newclock signal from the pin. The new clock signal is derived from the old. Source and networkclock insertion delays from the source clock are transferred to the derived clock. Here, theclock coming into the pin is being called the source clock, and the new clock created on thepin is called the derived clock.

Details of how source and network insertion delays are transferred to the derived clock areas follows:

First the edge correspondence is determined from the source and derived clock polarities.Edge correspondence means which edge of the derived clock is derived from which edge ofthe source clock. The clock polarity (positive or negative) of the source clock refers to thepolarity of the clock signal arriving at the pin. Similarly, clock polarity of the derived clockrefers to the polarity of the clock signal being generated from the pin.

■ Edge correspondence is determined as follows:

If source and derived clocks are both of positive polarity, or both of negative polarity, thenrising (falling) edge of the derived clock is assumed to be derived from the rising (falling)edge of the source clock. Similarly, if source and derived clocks are of opposite polarity,the rising (falling) edge of the derived clock is assumed to be derived from the falling(rising) edge of the source clock.

Then the source and network insertion delays from the source clock edges are transferred tothe corresponding derived clock edges.

■ Source and network insertion delays from the source clock edges are transferred to thecorresponding derived clock edges, if the following two additional constraints aresatisfied:

❑ Derived clock period must be an integral multiple (n) of the source clock period, withn >= 2.

❑ For the corresponding edges of the source and derived clocks (as determinedabove), following relation must be satisfied:

Edge_time_of_derived_clock = Corresponding_edge_time_of_source_clock+ (n * period_of_source_clock)



where n is an integer.

Arguments

pin_listAssociates paths from the pin list with the specified clockclock_name . The pin list can be ports or instance pins. Thesecan be object IDs or hierarchical names relative to the currentmodule.

-clock clock_nameSpecifies the clock waveform to apply or remove from the pin.

-lead | -trailIndicates that the signal at the specified pin must be recognizedas a data signal with the specified association (lead or trail )with respect to the specified clock clock_name . The default is-lead .

-pos | -negIndicates that paths must be recognized as clock paths and thatthe clock has the specified polarity. This option is required to setthe path as a clock path. If neither -pos or -neg is specified, thepath is treated as a data path.

Note: Because the signal cannot be both a clock signal and a data signal, the -pos | -negoptions cannot be used with the -lead | -trail options.

-early | -lateSpecifies early or late arrival of the signal. The default is both.

-rise | -fallMaps the rising or falling edge of the signal. The default is both.

Related Information

set_clock

set_clock_root


report_clocks



Examples

The following command changes the output of an AND gate to a clock signal type.

set_clock_info_change -clock clk -pos U1/A1/O

The following command issued later changes the output back to data signal type.

set_clock_info_change -clock clk U1/A1/O




set_clock_insertion_delay{([-source] [-lead | -trail][-early | -late] [-pvt {min | typ | max}]insertion_delay list_of_clocks ) | ([-source] [-clock clock_name ][-early | -late] [-pvt {min | typ | max}] [-rise | -fall]insertion_delay -pin list_of_pins )}HINT: Use [-early | -late] only with -source.Use -pvt only for network delay (no -source)

Important

This command in conjunction with the set_clock_root command replacesset_clock_arrival_time command.

The set_clock_insertion_delay command is used to specify clock insertion delay inthe ideal and propagated modes. Clock insertion delay has two components:

■ Source latency

Specified by the -source option, source latency is the delay from the external clockgenerator to the clock port of the design. Source insertion delay is considered in bothideal and propagated modes.

■ Network latency (clock tree insertion delay)

The default delay type. Network delay is the delay from the clock port to the register. Thenetwork delay specified by the set_clock_insertion_delay command is onlyconsidered in ideal mode. In propagated mode, this delay is replaced by the actual clocktree delays.

The command can be used in two ways:

■ To specify clock insertion delay for an ideal clock waveform:

❑ Use this form for source delay associated with a clock:

set_clock_insertion_delay -source [-lead | -trail] [-early | -late]insertion_delay list_of_clocks

❑ Use this form for network delay associated with a clock:

set_clock_insertion_delay [-pvt {min | typ | max}] [-lead | -trail]insertion_delay list_of_clocks

Source and network insertion delays specified on the clock waveforms are picked up forboth set_input_delay and set_external_delay assertions. Insertion delayspecification on a port/pin overrides any previous insertion delay on the port/pin/



waveform. The list_of_clocks is the list of the ideal clock waveform names asspecified by set_clock .

■ To specify clock insertion delay on clock pins:

❑ Use this form for source delay on a clock pin:

set_clock_insertion_delay -source [-early | -late] [-rise | -fall]insertion_delay -pin list_of_pins

❑ Use this form for network delay on a clock pin:

set_clock_insertion_delay [-pvt {min | typ | max}] [-rise | -fall]insertion_delay -pin list_of_pins

Note: In case of assertions on both the clock waveform and the clock pin, the specificationon the clock tree pin has priority over that on the clock waveform. The specification on theclock tree pin furthest down the clock tree decides the insertion delay to a register. A balancedclock tree is assumed.

During ideal propagation, the last full specification along a path wins. A full specification is thespecification of both source and network insertion delays. This is useful in intentionallyskewing the clock tree and modeling physical hierarchical clock tree situations.

In rare cases, more than one clock generator is connected to the input port., for exampleCLK1 and CLK2 both connect to clock port clkA . The -clock option makes the assertionfor the named clock. The -clock option can only be used with -source option. Only sourcedelay can be specified from the clock generator to the input port.

set_clock_insertion_delay -source -clock clock_name [-early | -late][-rise | -fall] insertion_delay -pin list_of_pins

Arguments

list_of_clocksList of ideal clock names to associate with the clock insertiondelay.

-pin list_of_pinsList of pins to associate with the clock insertion delay. The pincan be a port or an instance pin. These can either be object IDsor hierarchical names relative to the current module.

For internal pins, both the source and network delay must bespecified.



-sourceSpecifies that the delay is a source delay. Without this option, thedelay is considered a network delay.

-rise | -fallSpecifies insertion delay at the rising or falling edge of the clock.

-lead | -trailSpecifies insertion delay at the leading or trailing edge of theclock waveform. Default is both edges.

-clock clock_nameSpecifies that the source insertion delay is caused by the namedclock waveform. Used when more than one clock generator isconnected to the port.

-early | -lateClock arrival time is specified with respect to the early (hold) orthe late (setup) time. If neither option is specified, the default isboth early and late. These options can only be used with the-source option.

-pvt {min | typ | max}Specifies the clock insertion delay for a particular PVT (process,voltage, temperature) corner. You can choose one, two, or threePVT corners. If you choose more than one corner, enclose thelist in curly braces ({} ) and separate the values by spaces. Bydefault, the specified clock insertion delay applies to all threePVT corners. This option cannot be used with the -sourceoption.

Related Information

set_clock

set_clock_root



set_input_delay



set_external_delay


Examplesac_shell[2]>set_clock CLK1 -period 10 # Define the ideal clock CLK1

ac_shell[3]>set_clock CLK2 -period 20 # Define the ideal clock CLK2

ac_shell[4]>set_clock_root -pos -clock CLK1 clkA

ac_shell[5]>set_clock_root -pos -clock CLK2 {clkA clkB clkD}

ac_shell[6]>set_clock_insertion_delay -source 2 -pin {clkB clkD}

ac_shell[7]>set_clock_insertion_delay -rise 5 -pin {clkB clkD}

ac_shell[8]>set_clock_insertion_delay -fall 7 -pin {clkB clkD}

ac_shell[9]>set_clock_insertion_delay -source -clock CLK2 5 -pin clkA




set_clock_propagation{ideal | propagated}

The set_clock_propagation command tells the timing analyzer to treat all clock signalsassociated with the current timing top module as either ideal or propagated signals for thepurpose of timing analysis. One of the signal types must be specified when using thiscommand. If this command is not used, the default is ideal .

Important

if you backannotate delays to the clock network, you must use propagated modeto enable them in the timing analysis.

Arguments

idealIgnores actual clock tree network latency and uses networklatency asserted by the set_clock_insertion_delaycommand. The total delay is the sum of the clock source latencyand the asserted network latency. This is the default when thecommand is not issued.

propagatedThe actual clock tree delays are used in the timing of the circuit.The total delay is the sum of the clock source latency and thebackannotated clock tree delay. Use propagated mode forpostlayout analysis when you have accurate clock treeinformation in the form of an SDF file, or backannotated netcapacitance and resistance.

Related Information


set_clock

set_clock_root





Examplesset_clock_propagation propagated



set_clock_required_time

set_clock_required_time-clock clock_name[-pos | -neg] [-late | -early] [-rise | -fall]time pin_list

The set_clock_required_time command is analogous to theset_data_required_time command except that the signal arriving at the port is expectedto be a clock signal. This happens if there is a straight clock path through a module.

This is not a frequently used command and should not be used in most situations.

Note: By default, optimization does not work on the clock network. You must use thecommand do_xform_timing_correction -fix_clock_net to work on the clocknetwork.

Arguments

-clock clock_nameSpecifies the ideal clock for which the required time is set.

timeSpecifies the required time for the clock.

pin_listThe list of output ports or instance pins. They can be object IDsor hierarchical names relative to the current module.

-pos | -negSpecifies the polarity of the clock signal.

-late | -earlyThe timing check to which the required time applies, either late(setup) or early (hold). If neither option is specified, the default is-late .

-rise | -fallSpecifies the edge at which the required time applies. If neitheroption is specified, the default is both.



Related Information

set_clock

set_clock_root


Examplesset_clock_required_time -clock CLK1 5 out



set_clock_root

set_clock_root-clock ideal_clock_name [-pos | -neg]list_of_pins

The set_clock_root command assigns a polarity to a previously specified ideal clock andassociates a list of clock pins or ports with the ideal clock signal.

Arguments

-clock ideal_clock_nameName of the ideal clock as specified by the set_clockcommand.

-pos | -negSpecifies a positive or negative ideal clock. The default is -pos(rising edge precedes falling edge).

list_of_pinsList of pins to associate with an ideal clock. The pin can be a portor an instance pin. These can either be object IDs or hierarchicalnames relative to the current module. Pins can be associatedwith more than one ideal clock.

Related Information

set_clock



set_input_delay

set_external_delay

Examples

The following command puts the negative waveform of ideal clock named master on theinput port named negclk . The ideal clock master is shown in Figure 7-4 on page 658.

set_clock_root -clock master -neg negclk



Figure 7-7 Defining a Clock Pin

negclk0 5 10

ExternalClockGenerator




set_clock_uncertainty[-ideal | -propagated] [-early | -late]{([-clock_from clk_from ] [-clock_to clk_to ][-edge_from {leading | trailing}] [-edge_to {leading | trailing}]) |(-pin list_of_clock_tree_pins [-rise] [-fall] [-to])}float

The set_clock_uncertainty command is used to specify the clock uncertainty (skew)between two clock edges for one or more paths. The command has two mutually exclusiveforms, one for uncertainty on the clock waveform and one for uncertainty on clock pins.

■ The uncertainty can be specified for clock waveforms by using this set of options:

set_clock_uncertainty [-ideal | -propagated] [-early | -late][-clock_from clk_from ] [-clock_to clk_to ][-edge_from {leading | trailing}] [-edge_to {leading | trailing}] float

The specified uncertainty applies to paths starting from the clock_from signal and endingat registers clocked by the clock_to signal.

The edge_from parameter is the type of edge for the launching clock of the path. Theedge_to parameter is the capturing clock edge type of the destination register.

This command can also be used to add optimism by using negative values for the clockuncertainty value. This can be convenient when the design has paths starting in one clockdomain and ending in another clock domain, and there is no synchronous relationshipbetween the two clocks.

■ The following set of options specify clock uncertainty on a clock pin:

set_clock_uncertainty [-ideal | -propagated] [-early | -late]-pin list_of_clock_tree_pins [-rise] [-fall] [-to]float

Uncertainty on a clock pin affects paths downstream from that pin. By default, an uncertaintyspecification on a pin X is honored only at those registers or latches where there is a pathfrom pin X to both the data pin and the clock pin of the register/latch. However, the -to optionlifts this restriction and makes it applicable to all registers and latches whose clock pin is inthe transitive fanout of pin X. Pin-based uncertainty has priority over clock-based uncertainty.Among all applicable pin-based uncertainty specifications, the one furthest down the clocktree has the highest priority.

Arguments

-ideal | -propagatedSpecifies whether the uncertainty applies to the ideal clock



propagation mode or the propagated mode of analysis. Ifneither option is given, the uncertainty applies in both ideal andpropagated modes by default.

floatSpecifies the uncertainty value.

-early | -lateSpecifies whether the uncertainty is with respect to the earlytimes or the late times. In other words, whether it applies to hold(-early ) or setup (-late ) checks. The default is both early andlate.

-clock_from clk_fromSpecifies the starting point of the paths for which the uncertaintyis specified. The clk_from argument is the name of clocksignal with respect to which the uncertainty is specified.

If the -clock_from option is omitted then the uncertaintyapplies to all the paths ending at the registers clocked by the-clock_to signal.

-clock_to clk_toSpecifies the endpoint of the paths for which the uncertainty isspecified. The specified uncertainty applies to all paths startingfrom the -clock_from signal and ending at the registersclocked by -clock_to signal.

If the -clock_to option is omitted then the uncertainty appliesto all paths starting at the -clock_from signal.

If both the options -clock_from and -clock_to are omittedthen the specified uncertainty applies to all clocked paths in thedesign, including combinational paths constrained by theset_input_delay and set_external_delay timesassociated with the clock.

-edge_from { leading | trailing}Specifies whether the triggering (launching) edge of the clock isa leading or a trailing edge. It must match the edge used in thetiming check for the destination register. The default is leadingedge.



-edge_to { leading | trailing}Specifies whether the capturing edge at the destination registeris a leading or a trailing edge. The default is leading edge.

-pin list_of_clock_tree_pinsApplies the uncertainty to the given list of clock pins. Each pincan be a port or an instance pin. It can either be given as anobject ID or a hierarchical name relative to the current module.Cannot be used with -clock_from or -clock_to options.

-toSpecifies that the uncertainty applies to all the registers andlatches whose clock pin is in the transitive fanout of a clock pinfrom the list_of_clock_tree_pins .

-rise | fallSpecifies the rising (or falling) edge of the clock pins on which theuncertainty is asserted. For each edge, the assertion is usedonly if that edge fans out to the data and the clock pin of aregister or latch. With the -to option, the assertion is used if thatedge fans out to the clock pin of a register or latch. The default isboth edges.

Related Information

set_clock

Specifying Clock Uncertainty in the Timing Analysis for Ambit BuildGates Synthesis andCadence PKS manual.

Examples

This command gives all paths starting from registers clocked by c1 to registers clocked by c2a hold (early) uncertainty of 2.0 when the triggering edge is the leading edge and thecapturing edge is the trailing edge,

set_clock_uncertainty -clock_from c1 -clock_to c2 \-edge_from leading -edge_to trailing -early 2.0

In case of multiple assertions, the actual uncertainty applied by the timing analysis dependson which constraint matches the specific path in the question. Timing analysis may also applythe worst case uncertainty in some situations like the example below.



The following two commands cause a path starting at a register clocked by c1 and ending ata register clock by c2 to have an uncertainty of 3.0 (which is the worse of the two).

set_clock_uncertainty -clock_from c1 2.0 -late

set_clock_uncertainty -clock_to c2 3.0 -late

The following command sets an uncertainty on a clock pin (clk_in ) only for propagatedmode.

set_clock_uncertainty -propagated -pin clk_in 1.2




set_constant_for_timing{0 | 1} list_of_pins

The set_constant_for_timing command sets the value of the specified pin(s) to eithera 1 or 0 for use by the timing engine. The applied state value propagates through thecorresponding combinational logic cone(s) and the enable or disable sections of logic.Constants do not propagate through sequential logic, however you can set the constant at thesequential output. Constants can also be applied at primary IO and hierarchical ports.

The set_constant_for_timing command can be used to control the transparency of alatch. Constants can also be applied to clear or preset a latch. For more information, seeSpecifying Latch Transparency in the Timing Analysis for Ambit BuildGates Synthesisand Cadence PKS manual.

Arguments

0 | 1

Specifies a logic value of 0 or 1.

list_of_pins

Specifies a single pin or multiple pins on which to applyconstraints. To specify multiple pins, enclose the list with curlybraces ({} ) and separate the pin names with white-space.

Related Information



set_disable_timing

set_false_path

Examplesset_constant_for_timing 1 i4/A



set_cycle_addition

set_cycle_addition[{-from | -from_rise | -from_fall} pin_list ][{-through | -through_rise | -through_fall} pin_list ][{-to | -to_rise | -to_fall} pin_list ][-clock_from list_of_clocks ] [-edge_from {leading | trailing}][-clock_to list_of_clocks ] [-edge_to {leading | trailing}][-early | -late][-bidi_input_from | -bidi_output_from][-bidi_input_through | -bidi_output_through][-bidi_input_to | -bidi_output_to][-target]float

The set_cycle_addition command identifies multicycle paths in the design for timinganalysis. A path is a multicycle path when the signal propagation from the start point to theendpoint of the path takes more than one clock cycle. Normally, timing analysis takes placeover one clock cycle, and by default all paths are considered one cycle paths. This commandlets you add a certain number of cycles to the path under consideration. Timing analysis isthen done for the total number of cycles, thereby eliminating violations caused by inadequateanalysis time. The information about number of cycles for a path is attached to the pins of thepath.

All paths starting in one clock domain and ending in another clock domain are taken asmulticycle paths. You cannot have -clock_from/clock_to options in the same commandwith -from/to options.

A path can have more than one path exception. When the globalpath_style_timing_constraint is set to true , multiple path exceptions that match agiven path are prioritized. The adjustment on the path is from the path exception with thehighest priority. Table 7-4 on page 774 ranks path exception priorities from highest to lowest.Examples are provided in “Examples of Path Exception Priorities” on page 775.

Important

When the global path_style_timing_constraint is set to false , only thepath exceptions supported before version 3.0 are observed, the rest are ignored.Furthermore, there is no prioritization on overlapping path exceptions.The falseoption exists for backward compatibility with releases prior to 3.0. The default in 4.0is true . You can avoid problems by always using the default value.

The cycle addition values are stored at the -to pins if -to is specified, otherwise values arestored at the -from pins. If neither -to nor -from is specified, values are stored at the-through pins.



You can specify a group of pins by enclosing the group with curly braces ({} ) within oneset_cycle_addition command.

Tip

To add cycles for any path beginning at p1 or p2 and terminating at t1 or t2 , therecommended method is to group the pins as follows:

set_cycle_addition -from {p1 p2} -to {t1 t2} 2.2

Note: This method of pin grouping reduces the number of exceptions. Having largenumbers of exceptions adversely impacts the run time of report_timing .

Arguments

floatSpecifies the number of extra cycles that should be added to thepath. The number of cycles to be added for an N cycle path isN-1 , because all paths by default are single cycle paths. Thenumber of cycles can be negative, thus reducing the number ofcycles for the path.

Note: Although a floating point number is allowed, if you pass the constraint todownstream tools with GCF, the value must be an integer.

{-from | -from_rise | -from_fall} pin_listSpecifies the pins that are at the start of the paths. If the -fromoption is used without the -to option, all paths originating fromthe pin_list are considered as multicycle paths.

Either -from , -to, or -through must be used with theset_cycle_addition command to identify the paths.Specifying both -from and -to identifies a path with specificstarting and ending points.

The pin_list can contain either object IDs or hierarchicalnames relative to the current module. The pins can be onintermediate hierarchical boundaries. You can use only one-from (or -from_rise or -from_fall ) option per command.

By default, -from applies the assertion to both the rising and thefalling edges.



Using -from_rise applies the assertion at the rising edge ofthe signal on the through pins.

Using -from_fall applies the assertion at the falling edge ofthe signal on the through pins.

{-through | -through_rise | -through_fall} pin_listSpecifies the pins that the path goes through. When usedwithout -from or -to , all paths that go through the -throughpins are multicycle paths.

When used with both -from and -to , any path starting at anypin on the -from list AND going through any point on the-through pin list AND going to any point on the -to list isaffected by the assertion.

The pin_list can contain either object IDs or hierarchicalnames relative to the current module. The pins can be onintermediate hierarchical boundaries.There can be only one-from and one -to , but many -through options in the samecommand.

By default, -through applies the assertion to both the risingand the falling edges.

Using -through_rise applies the assertion at the rising edgeof the signal on the through pins.

Using -through_fall applies the assertion at the falling edgeof the signal on the through pins.

{-to | -to_rise | -to_fall} pin_listSpecifies the pins that are at the end of the paths. If -to optionis used without the -from option, all paths ending in the -to pinlist are considered as multicycle paths.

The pin_list can contain either object IDs or hierarchicalnames relative to the current module. The pins can be onintermediate hierarchical boundaries.You can use only one -to(or -to_rise or -to_fall ) option per command.

By default, -to applies the assertion to both the rising and thefalling edges.



Using -to_rise applies the assertion at the rising edge of thesignal on the through pins.

Using -to_fall applies the assertion at the falling edge of thesignal on the through pins.

-clock_from list_of_clocksAdjusts the cycle count for all paths originating from the specifiedclocks.

-edge_from {leading | trailing}Specifies an edge for the -clock_from . This option can only beused with the -clock options. Default is both edges.

-clock_to list_of_clocksAdjusts the cycle count for all paths going to the specified clocks.

-edge_to { leading | trailing}Specifies an edge for the -clock_to . Default is both edges.

-bidi_input_from | -bidi_output_fromSpecifies that the assertion applies to the input or output ofbidirectional pins in the -from pin list. Default value is shown in“Bidirectional Pin Defaults” on page 776.

-bidi_input_through | -bidi_output_throughSpecifies that the assertion applies to the input or output ofbidirectional pins in the -through pin list. Default value isshown in “Bidirectional Pin Defaults” on page 776.

-bidi_input_to | -bidi_output_toSpecifies that the assertion applies to the input or output ofbidirectional pins in the -to pin list. Default value is shown in“Bidirectional Pin Defaults” on page 776.

-early | -lateSpecifies whether the cycles added are with respect to the early(hold) or the late (setup) times of the data signal. If neither optionis specified, -late is the default.

-targetThe cycle adjustment is calculated using the cycle time of thecapturing (target) clock.



Related Information

set_false_path

report_timing -format addition

path_style_timing_constraint

Examples

The following command specifies all paths from port Q of instance I1 as 3-cycle paths(additional 2 cycles). The paths can end anywhere in the design.

set_cycle_addition -from I1/Q 2

The following command sets all paths ending at port A of instance I2 as 2-cycle paths. Thepaths can start anywhere in the design.

set_cycle_addition -to I2/A 1

The following command sets all paths from port Qof instance I1 to port B of instance I3 as2-cycle paths. The paths can go through any pins in the design.

set_cycle_addition -from I1/Q -to I3/B 1

The following command sets only the path from port Q of instance I1 through port Q ofinstance I2 to port B of instance I3 as a 3-cycle path.

set_cycle_addition -from I1/Q -through I2/Q -to I3/B 2

To set a different number of cycles on the early and late paths, issue two commands as shownbelow:

[2]>set_cycle_addition -late -from I1/Q 2

[3[>set_cycle_addition -early -from I1/Q 1

Tip

Be careful of multiple cycle additions on the same path. The priority rules say thatthe most constraining value is used. For example:


[12]>report_path_exceptions -from I1/Q

+------------------------------------------------+

| From | Early | Late |

|--------------------------------+-------+-------|

| I1/Q | | add 2 |

+------------------------------------------------+




[14]>report_path_exceptions -from I1/Q

+--------------------------------------------------------+

| From | Early | Late |

|--------------------------------+-------+---------------|

| I1/Q | | add 3 ignored |

| I1/Q | | add 2 |

+--------------------------------------------------------+



set_data_arrival_time

set_data_arrival_timeOBSOLETE: Use set_input_delay instead.

Important

Do not use set_data_arrival_time , use set_input_delay instead. Seeset_input_delay on page 716.

Starting in the Ambit 4.0 release set_data_arrival_time is an internally generatedcommand. You should use set_input_delay instead because it is easier tounderstand and is more consistent with constraints from other tools. Cadence timinganalysis still writes out set_data_arrival_time during time budgeting. The followingdescription is for reference only.

set_data_arrival_time[-clock clock_name ][-lead | -trail] [-early | -late] [-rise | -fall] [-bidi_input | -bidi_output]time pin_list

The internally generated set_data_arrival_time command attaches arrival times toinput ports in the database.

Note: The arrival time is always specified as an absolute time with respect to the ideal clocktime zero, even if the pertinent edge of the ideal clock is not at time zero. When you useset_input_delay the time is relative to the clock.




set_data_required_time[-clock clock_name ][-lead | -trail] [-early | -late] [-rise | -fall] [-bidi_input | -bidi_output]time pin_list

The set_data_required_time command specifies the required time that the output portsmust be stable.

The timing information for an output port is specified in terms of when the valid data signal isrequired to be stable at the output port. The change caused at the output port is associatedwith either the leading or trailing edge of the ideal clock. The required time is attached to theport in the database.

An alternate method of setting output delay constraint is supported by theset_external_delay command, which refers to the required time for a signal to be stableat a port external to the module. The set_external_delay command is the preferredmethod because it uses relative time.

Arguments

timeThe required time at which the output ports must be stable.

pin_listList of pins for which the required time is specified.

-clock clock_nameThe name of the ideal clock associated with the register causingchange in the signal. The clock specification can be omitted if thesignal arriving at the output port is generated by a combinationalblock. If the signal generated by a combinational block has aregister on its path, usually it is necessary to associate the clockwith such a signal for proper timing analysis. If the clock name isunspecified, the default value is * (all clock signals).

-lead | -trailSpecifies the edge of the ideal clock that triggers the pin beingconstrained. Time units are always expressed in absolute time,NOT time relative to the triggering edge. Only one of theseoptions can be specified per command line. If the constraintapplies to both edges, use two commands as shown inExamples .



If neither option is specified, the default is lead .

-rise | -fallSpecifies whether the signal refers to the rising edge or thefalling edge at the output port. If neither option is specified, datarequired time applies to both edges.

-early | -lateStates that the required time specified is the earliest or the latesttime when the output port is allowed to change. The default is-late .

-bidi_input | -bidi_outputSpecifies the constraint on the input or output part of abidirectional port.

Related Information

set_external_delay

set_input_delay

set_current_module


remove_assertions

Examples

These commands require the output port Qof the current module to complete its transitionsno later than 2ns in absolute time. The requirements are associated with the ideal clockmaster which has a period of 10ns.

set_data_required_time -clock master -lead 2 Q

set_data_required_time -clock master -trail 7 Q




set_dcl_calculation_mode-mode {best_case | nominal_case | worst_case}

The set_dcl_calculation_mode command sets the current DCL calculation mode. Ifthis command is not specified, the default is worst_case . The DCM must be loaded first withthe load_dcl_rule command.

The library developer defined the calculation modes in the DCL library to model three processconditions, best_case , nominal_case , and worst_case , within one library. Refer to thevendor documentation for more information.

Note: Process, temperature, and voltage are set independently of the calculation mode usingthe set_operating_parameter command.

Arguments

-mode {best_case | nominal_case | worst_case}Specifies which calculation mode to use for analysis.

Related Information




load_dcl_rule

Examplesset_dcl_calculation_mode -mode nominal_case




set_dcl_functional_mode-group group_name -mode mode_nameinstance_list

The set_dcl_functional_mode command sets the DCL functional mode by group andname on hierarchical instances. To determine what modes are available for an instance, usethe command get_dcl_functional_mode_array on the underlying library cell of thatinstance.

Functional modes defined in a DCL library allow the vendor library developer to model thetiming arcs and timing checks for a technology cell in a variety of ways. For example, a scanflip-flop could have functional modes defined for normal flip-flop behavior and for scanbehavior with different timing arcs and checks for each mode.

Arguments

-group group_nameSpecifies the functional mode group name.

-mode mode_nameSpecifies the functional mode name.

instance_listList of instances for which the functional mode needs to be set.

Related Information



load_dcl_rule

Examplesset_dcl_functional_mode -group rw -mode read {A1/B3/C2 A1/B2/C2}



set_dcl_level

set_dcl_level-perfLevel {0 | 1}

The set_dcl_level command sets the desired performance level for DCL-based delaycalculations. A value 0 indicates lower accuracy in favor of faster run time while a value of 1indicates calculations for maximum accuracy. If this command is not issued, the defaultperformance level is 0.

Arguments

-perfLevel {0 | 1}Specifies the performance level. DCL supports two performancelevels for delay calculation, where one performance level targetsfaster run time with less accurate timing while the other targetsmore accurate timing with slower run time.

The library vendor who provided the DCM also documents thecharacteristics of each performance level in their library andwhether or not both 0 and 1 levels are supported and which isfaster (usually 0). In general, the faster performance in terms ofrun time should be used for initial synthesis and the moreaccurate level should be used in final timing correction.

Related Information

get_dcl_level

load_dcl_rule

Examplesset_dcl_level -perfLevel 1



set_default_slew_time

set_default_slew_time [-early | -late] [-rise | -fall] float

The set_default_slew_time command specifies the default slew time for the ports. Thesystem uses this slew value for any input or bidirectional port for which slew or driveassertions are not specified. If this command is not issued, the system uses a value of 0.0 .

The set_default_slew_time command is ignored for a port if set_slew_time ,set_drive_cell , or set_drive_resistance constraints have been set for that port.

Arguments

floatSpecifies the default slew time for input and bidirectional portsthat do not have slew or drive assertions on them.

-rise | -fallSpecifies that the slew time should be applied to the rising edgeor the falling edge of the signal. If neither edge is specified, thedefault is to use both.

-late | -earlyIndicates whether the slew times are with respect to the late(setup) or the early (hold) checks. If neither option is specifiedthe default is to use both.

Related Information

set_slew_time

set_drive_cell

set_drive_resistance

Examplesac_shell[6]>set_default_slew_time -rise -early 10.0

ac_shell[7]>set_default_slew_time -fall -early 20.0

ac_shell[8]>set_default_slew_time -rise -late 30.0

ac_shell[9]>set_default_slew_time -fall -late 40.0




set_disable_cell_timing[-library library_name ] -cell cell_name-from_pin from_pin_name -to_pin to_pin_name

The set_disable_cell_timing command disables all timing arcs (delay as well ascheck arcs) between the specified from and to pins for the specified cell in the library. Thetiming arcs from/to internal pins inside IP cells can also be disabled.

Arguments

-cell cell_nameSpecifies the cell in the library for which timing checks aredisabled.

-from_pin from_pin_nameSpecifies the source pin of the timing arc.

-to_pin to_pin_nameSpecifies the sink pin of the timing arc.

-library library_nameSpecifies the library that contains the cell. If not specified, thedefault is the target technology library.

Related Information

set_disable_timing

set_false_path


Examplesset_disable_cell_timing -cell ram -from_pin write_enable-to_pin Z



set_disable_timing

set_disable_timing -from from_pins -to to_pins [-bidi_input_from |-bidi_output_from] [-bidi_input_to | -bidi_output_to]

The set_disable_timing command disables (snips) timing arc(s) of an instance orinterconnect and is used for breaking combinational loops.

The set_disable_timing command can also be used to control the transparency of alatch. For more information, see Specifying Latch Transparency in the Timing Analysis forAmbit BuildGates Synthesis and Cadence PKS manual.

This command differs from the set_false_path command as follows:

■ set_disable_timing snips a timing arc such that neither arrival times nor constantvalues propagate through it.

■ set_false_path selectively disables the arrival time information depending upon theprecedence rules given in Table 7-4 on page 774. Constant values are not affected bythe set_false_path command.

Arguments

-from from_pinsSpecifies the source pin of the timing arc to be disabled.If the -from option is used without the -t o option, all pathsoriginating from the from_pins are disabled.Either -from or -to must be used with this command.Specifying both -from and -to identifies a path with specificstart and endpoints.The -from and -to options can be intermediate hierarchicalboundaries.

-to to_pinsSpecifies the sink pin of the timing arc to be disabled.If the -to option is used without the -from option, all pathsending in to_pins are disabled.





Related Information

set_false_path


Examples

The following command disables all timing arcs from the Q pin of instance I1 .

set_disable_timing -from I1/Q

The following command disables the timing arc from the input part of bidirectional pin A to theoutput part of bidirectional pin B.

set_disable_timing -from A -to B -bidi_input_from -bidi_output_to

The following command disables the timing arc from the A pin to Z pin of instance NAND2.

set_disable_timing -from NAND2/A -to NAND2/Z

The following command disables all timing arcs which pass through the hierarchical port,port1 , of module mod and end at an input or bidirectional pin.

set_disable_timing -from mod/port1



set_drive_cell

set_drive_cell[-early | -late][-library library_name ] [-library_rise library_name ][-library_fall library_name ][-cell cell_name ] [-cell_rise cell_name ] [-cell_fall cell_name ][-pin pin_name ] [-pin_rise pin_name ] [-pin_fall pin_name ][-from_pin from_pin_name ] [-from_pin_rise from_pin_name ][-from_pin_fall from_pin_name ][-rise_source_edge {R | F}] [-fall_source_edge {R | F}][-clock clock_name ][-lead | -trail | -pos | -neg][-source_slew slew_value ][-rise_source_slew rise_slew_value ][-fall_source_slew fall_slew_value ]port_list

The set_drive_cell command is used to accurately model the drive capability of anexternal driver connected to the input port. It is only used for timing analysis. It does not affectthe electrical properties of the design. This means that the capacitance of the output pin ofthe driving cell does not add to the total capacitance of the input port.

The timing analyzer computes an offset to the arrival time of an input and also changes theslew time used to compute the delay of the cell on the sink of the net. The offset todata_arrival_time is computed by taking the total delay of the cell for C seen at the input(not including its own Cdriver) and subtracting the total delay of the cell given Cload of zero.The total delay means the propagation and transition delays, if applicable. The transitiondelay itself is used as the slew value for the delay calculation of the next cell. The library cellthat drives the input of the design must be identified. The cell can be designated as the drivingcell for the ports in context by using set_drive_cell command.

This command overrides the set_drive_resistance command, per port or per net, if it isthe last command applied. Also, if set_drive_cell is set for a port, set_slew_time isignored for that port.

Arguments

port_listList of ports driven by the driver cell.

-earlySpecifies that the driver provides an early signal, also known ashold.



-lateSpecifies that the driver provides a late signal, also known assetup.

-cell cell_nameName of the driver cell that provides both a rising edge transitiondriver and a falling edge transition driver.

-cell_rise cell_nameName of the cell that provides a rising transition driver.

-cell_fall cell_nameName of the cell that provides a falling transition driver.

-library library_nameName of the library that contains the driving cell. This option isused if the same cell provides both the rising and the falling edgetransitions, or if different cells provide the rising edge and fallingedge transitions but are in the same library.

-library_rise library_nameName of the library that contains the rising edge transition driver.

-library_fall library_nameName of the library that contains the falling edge transition driver.

-pin pin_nameName of the output port of the driver cell that drives the signal atthe input port of the design. This option is required if there aremultiple output ports on the driver. If there is only one output porton the driver cell, use of this option is not necessary.

-pin_rise pin_nameName of the output port of the driver cell which provides therising edge transition drive to the input port of the design.

-pin_fall pin_nameName of the output port of the driver cell which provides thefalling edge transition drive to the input port of the design.

-from_pin from_pin_nameName of the input port of the driver cell which has an arc to theoutput port of the driver cell which is connected to the input port



of the design. This option is required if there are multiple timingarcs in the driver cell from its input ports to its output ports. Itassumes that the same timing arc between the input port and theoutput port of the driver cell is driving both the rising edgetransition and the falling edge transition on the input port of thedesign.

-from_pin_rise from_pin_nameName of the input port of the driver cell with the controlling timingarc to the output port of the driver cell that provides the risingedge transition drive to the input port of the design.

-from_pin_fall from_pin_nameName of the input port of the driver cell with the controlling timingarc to the output port of the driver cell that provides the fallingedge transition drive to the input port of the design.

-rise_source_edge R | FSpecifies whether the rising (R) edge or the falling edge (F) at thefrom_pin_name is controlling the rising edge transition at theinput port of the design.

-fall_source_edge_ R | FSpecifies whether the rising edge (R) or the falling edge (F) at thefrom_pin_name is controlling the falling edge transition at theinput port of the design.

-clock clock_nameSpecifies the ideal clock that is controlling the signal.

-lead | -trail | -pos | -negSpecifies that the slew time is for a data signal triggered by theleading or the trailing edge of the ideal clock. The default optionis -lead .

For a clock signal, -pos and -neg specify that the slew timeshould be applied to an actual clock that has positive or negativepolarity with respect to the ideal clock.

-source_slew slew_valueThe slew value for the signal at the input of the drive cell.



-rise_source_slew rise_slew_valueThe slew value for the rising signal at the input of the drive cell.

-fall_source_slew fall_slew_valueThe slew value for the falling signal at the input of the drive cell.

Related Information


set_slew_time

Examplesset_drive_cell -cell IV [ find -input -port * ]set_drive_cell -cell AN3 -from_pin I0 input1




set_drive_resistance-clock clk_name [-lead | -trail][-rise | -fall] [-early | -late][-slew_res slew_res_value ][-slew_intrinsic slew_intrinsic_value ]value port_list

The set_drive_resistance command is a simpler version of the set_drive_cellcommand and can be used in many situations where the drive resistance can be specified. Itis used only for timing analysis. It does not affect the electrical properties of the design. It isused to specify the drive resistance of a cell. It computes an offset to the arrival time of aninput and also changes the slew time used to compute the delay of the cell on the sink of thenet.

The arrival time at the input port is modified by adding the RC constant to the specified arrivaltime at the input port. The RC constant is the capacitance (C) seen at the input port multipliedby the drive resistance (R). The RC value is used as the slew value for the delay calculationof the next cell.

Note: This command overrides a set_drive_cell command that was previously appliedto the same port. Also, if set_drive_resistance is set for a port, set_slew_time isignored for that port.

Arguments

valueResistance value.

port_listList of ports for which drive resistance is specified.

-clock clk_nameThe name of the clock.

-lead | -trailIndicates that the signal at the specified port must be recognizedas a data signal with the specified association (lead or trail )with respect to the specified clock clock_name .

-rise | -fallSpecifies that the drive resistance is applicable to only the risingedge or the falling edge transition at the input port. If neither rise



nor fall options are specified then the resistance is applied toboth transitions at the input port.

-early | -lateSpecifies that the drive resistance should be applied to the earlyarrival time (hold time) or late arrival time (setup time) for timinganalysis.

-slew_res slew_res_valueThe value of resistance used in the slew computation at the inputport of the module.

-slew_intrinsic slew_intrinsic_valueThe intrinsic value of slew used in the slew computation at theinput port of the module. The slew value at the input port of themodule is computed as follows, assuming cap is the capacitanceat this port:

slew = slew_intrinsic_value + slew_res_value * cap

Related Information

set_drive_cell

set_slew_time

Examplesset_drive_resistance [expr 3 * [get_cell_drive -cell IV -pin A] ] [-input -port * ]



set_external_delay

set_external_delay[-rise | -fall] [-late | -early] [-sig | -ref] [-lead | -trail][-clock clock_name ] [-arrival float ] [-bidi_input | -bidi_output]external_delay port_list

The set_external_delay command provides an alternate way to specify the requiredtime that the output ports must be stable by using external delay requirements. This constraintconsiders the timing requirement of the configuration of the output port and the connection tothe register input of the external block.

When you know the critical path from the output port of the current block to the register of theexternal block, you can specify required time at the output with this command. The requiredtime is derived from the port and path configuration. If you do not have data for the path tothe register of the external block, use the set_data_required_time command.

If set_data_required_time command is used on an output port then the commandset_external_delay on the same port does not have any effect.

A successive set_external_delay assertions on the same output port with respect to thesame clock overrides a previous assertion. If multiple set_external_delay assertions areused on the same output port, but with respect to different clocks, then the worst caserequired time is used for timing analysis.

Arguments

external_delayExternal delay, including setup time for the external register.

port_listList of ports.

-clock clock_nameThe ideal clock which is controlling the external register. Thedefault is the asynchronous (@) clock.

-lead | -trailSpecifies that the leading or trailing edge of the ideal clockcontrols the external register. If both -lead and -trail optionsare omitted, the default is lead . If the external register is a latch,the controlling edge is the capturing edge.



-rise | -fallSpecifies that the external delay refers to the rising edge orfalling edge at the output port. If both -rise and -fall optionsare omitted, the external delay applies to both the edges at theoutput port.

-early | -lateSpecifies that the constraint refers to the early (hold) or late(setup) times. If both -late and -early options are omitted,then the external delay is considered to apply to late times.

-arrival floatThis option is used to specify the actual arrival time of the edgeof the ideal clock that is being used to determine the externaldelay. This option is similar to specifying the actual clock usingthe set_clock_arrival_time command in relation to theideal clock signal defined by the set_clock command.This is used if the arrival time of the capturing clock is differentthan the arrival time of the corresponding edge of the ideal clock.

-bidi_input | -bidi_outputSpecifies the constraint on the input or output part of abidirectional port.

-sig | -refDetermines whether the external delay assertion is beingapplied on a data path (-sig ) or a clock network (-ref ). Ifneither option is given, the default is -sig .

Related Information

set_clock


remove_assertions

Examples

The following command sets an external delay of 4.1 ns on the output port pout which isdriving the input to a register that is controlled by the leading edge of the ideal clock clk .

set_external_delay -lead -clock clk 4.1 pout



In the following example set_external_delay has no effect becauseset_data_required_time was previously specified for the same port.

set_data_required_time -clock "*" -lead -late -rise 2.000 {out}

set_external_delay -clock "@" -lead -arrival 0.000 -sig -late -rise 4.000 {out}



set_false_path

set_false_path[{-from | -from_rise | -from_fall} pin_list ][{-through | -through_rise | -through_fall} pin_list ][{-to | -to_rise | -to_fall} pin_list ][-clock_from clk_name ] [-edge_from {leading | trailing}][-clock_to clk_name ] [-edge_to {leading | trailing}][-early | -late][-bidi_input_from | bidi_output_from][-bidi_input_through | -bidi_output_through][-bidi_input_to | bidi_output_to]

The set_false_path command is used in timing analysis to identify false paths in a design.Path exceptions between clock domains are accepted. The command is also used to breakor disable specific instance timing arcs in a design.

Important

To break combinational loops, use the set_disable_timing command (seeset_disable_timing on page 697) instead of the set_false_path command.

The set_false_path command differs from the set_disable_timing command asfollows:

■ set_false_path selectively disables the arrival time information depending upon theprecedence rules.

■ set_false_path does not affect constant values.

■ set_disable_timing actually physically snips a timing arc such that neither arrivaltimes nor constant values propagate through it.

The set_false_path -from fpin command disables all timing arcs whose source pinis fpin . Similarly, the set_false_path -to tpin command disables all timing arcswhose sink pin is tpin . Using set_false_path -from fpin -to tpin disables alltiming arcs whose source is fpin and sink is tpin .



You can specify a group of pins by enclosing the group with curly braces ({} ) within oneset_false_path command.

Tip

To set a false path for any path beginning at p1 or p2 and terminating at t1 or t2 ,the recommended method is to group the pins as follows:

set_false_path -from {p1 p2} -to {t1 t2}

Note: This method of pin grouping reduces the number of exceptions. Having largenumbers of exceptions adversely impacts the run time of report_timing .

Arguments

{-from | -from_rise | -from_fall} pin_listSpecifies the pins that are at the start of the false paths. If the-from option is used without the -to option, all paths originatingfrom the pin_list are false paths.

Either -from , -to, or -through must be used with theset_false_path command to identify the paths. Specifyingboth -from and -to identifies a path with specific starting andending points.



Using -from_rise applies the assertion at the rising edge ofthe signal on the from pins.

Using -from_fall applies the assertion at the falling edge ofthe signal on the from pins.

{-through | -through_rise | -through_fall} pin_listSpecifies the pins that the path goes through. When usedwithout -from or -to , all paths that go through the -throughpins are false paths.




The pin_list can contain either object IDs or hierarchicalnames relative to the current module. The pins can be onintermediate hierarchical boundaries.There can be only one-from and one -to , but many -through options in the samecommand.




{-to | -to_rise | -to_fall} pin_listSpecifies the pins that are at the end of the false paths. If -tooption is used without the -from option, all paths ending in the-to pin list are false paths.



Using -to_rise applies the assertion at the rising edge of thesignal on the to pins.

Using -to_fall applies the assertion at the falling edge of thesignal on the to pins.

Note: Only internally generated scripts like write_assertions use -rise and -fall asoptions. You should use [-from_rise | -from_fall] and [-to_rise | -to_fall]options.




-bidi_input_through | -bidi_output_throughSpecifies the assertion on the input or output part of thethrough pin. Default value is shown in “Bidirectional PinDefaults” on page 776.


-clock_from clk_nameSpecifies the starting point of the false paths. The clk_nameargument is the name of clock signal.

If the -clock_from option is omitted then the path exceptionapplies to all the paths ending at the registers clocked by the-clock_to signal.

-clock_to clk_nameSpecifies the endpoint of the false paths. The path exceptionapplies to all paths starting from the -clock_from signal andending at the registers clocked by -clock_to signal.

If the -clock_to option is omitted then the path exceptionapplies to all paths starting at the registers clocked by the-clock_from signal.

-edge_from { leading | trailing}Specifies whether the triggering (launching) edge of the clock isa leading or a trailing edge. It should match the edge used in thetiming check for the destination register. The default is leadingedge.

-edge_to { leading | trailing}Specifies whether the capturing edge at the destination registeris a leading or a trailing edge. The default is leading edge.



-early | -lateIf neither the -early nor the -late options are specified thenit is assumed to be both early and late (hold and setup). This onlyapplies to the -to side if the -to pin_list is present. Itapplies to the -from side in other case.

Related Information

set_disable_timing


set_cycle_addition

set_path_delay_constraint


Examples

The following command sets all paths from port Q of instance I1 to false paths.

set_false_path -from I1/Q

In the next command all paths ending in port A of instance I2 are considered false paths.

set_false_path -to I2/A 1

The following command makes the path from port Q of instance I1 to port A of instance I2into a false path.

set_false_path -from I1/Q -to I2/A 2



set_fanout_load

set_fanout_loadfloat port_list

The set_fanout_load command is used to specify the fanout load on the ports of a cell.Fanout loads are only used to enforce the design rule checks and have no effect on timing.Setting the port capacitance affects timing analysis.

Arguments

floatTotal fanout load external to the cell.


Related Information

set_port_capacitance

set_fanout_load_limit

set_global max_fanout_load_limit

set_current_module

Examplesset_fanout_load 4 [find -port -output data*]




set_fanout_load_limitfloat port_list

The set_fanout_load_limit command is used to specify the fanout load limit (maximumvalue) on the ports of a cell. Fanout load limits are only used to enforce the design rulechecks, they do not affect timing analysis. Setting port capacitance limit affects timinganalysis.

The design rule requirement of a maximum fanout load value is set using the set_globalfanout_load_limit command. For the specified ports, set_fanout_load_limitoverrides the global default fanout load limit.

Arguments

floatFanout load limit on the ports.


Related Information


set_current_module

set_global max_fanout_load_limit

Examplesset_fanout_load_limit 4 [find -port -output data*]

set_fanout_load_limit 3 [find -port -input reset]



set_functional_mode

set_functional_mode [-group group_name ] [-mode mode_name] instance_list

The set_functional_mode command lets you set the DCL or the STAMP functional modeby group and name on hierarchical instances. To determine what modes are available for aninstance, use report_functional_mode .

Once mode_name is set, all other modes in group_name become inactive and stayinactive unless they are explicitly set later.

The following form of the command makes all modes in all mode groups ofinstance_list active.

set_functional_mode instance_list

While this form of the command makes all modes in the group group_mode ofinstance_list active.

set_functional_mode -group group_mode instance_list

Arguments

-group group_nameSpecifies the string value of the functional mode group name.Default is all groups.

-mode mode_nameSpecifies the string value of the functional mode name. Defaultis all modes.

instance_listSpecifies the list of instances for which the functional modeneeds to be set.

Related Information



Examplesset_functional_mode -group rw -mode read {A1/B3/C2 A1/B2/C2}



set_input_delay

set_input_delay[-early | -late] [-rise | -fall] [-clock clock_name ] [-lead | -trail][-worst_case] float port_list

The set_input_delay command sets input path delay values on input ports. This inputpath delay models the delay from an external register to an input port of the module.

The set_input_delay command differs from dc_shell in that -min and -max options arereplaced by -early and -late options. The justification is that there could be multiple pathsbetween the fictitious register and the input port. The -early and -late options properlycapture the difference in delays for these paths.

Note: The set_input_delay command replaces the set_data_arrival_timecommand.

Arguments

floatSpecifies the delay value.

port_listSpecifies a single input port or multiple ports to which the inputdelay applies. To specify multiple ports, enclose the list with curlybraces ({) } and separate the port information with white-space.

-rise | -fallSpecifies that the input delay refers to the rising edge or fallingedge at the input port. If both -rise and -fall options areomitted, the input delay applies to both the edges.

-early | -lateSpecifies that the constraint refers to the early (hold) or late(setup) times. If both -late and -early options are omitted,then the input delay is considered to apply to both early and latetimes.

-worst_caseTakes the worst-case delay when multiple input delays for thesame clock are specified. Without this option, successive inputdelays on the same clock overwrite previously asserted values.




-lead | -trailSpecifies that the input delay is with respect to the leading or thetrailing edge of the clock. If neither option is provided, the defaultis -lead .

Related Information


set_external_delay

reset_input_delay

remove_assertions

Examplesset_input_delay -clock CLK -early -rise -0.05 [ find -inputs ]

set_input_delay -clock CLK -late -rise 0.05 [ find -inputs ]

set_input_delay -clock CLK -early -fall 0.15 [ find -inputs ]

set_input_delay -clock CLK -late -fall 0.25 [ find -inputs ]



set_max_delay

set_max_delayNot an ac_shell command, use set_path_delay_constraint instead.

See set_path_delay_constraint on page 726.



set_min_delay

set_min_delayNot an ac_shell command, use set_path_delay_constraint instead.

See set_path_delay_constraint on page 726.



set_num_external_sinks

set_num_external_sinksnon_neg_integer port_list

The set_num_external_sinks command can be specified on top level input and outputports only. This command sets the constraint for the number of external sinks that areconnected to the ports in the port list. This number is factored into the wire capacitance andthe wire resistance estimation done for the port nets using the wire-load models.

It does not add to the total fanout count for Design Rule Violation (DRV) checks. For moreinformation on design rule violations, see the description for max_fanout_load_limit in“Command Arguments for set_global” on page 203.

If you do not use set_num_external_sinks , the default fanout is 1 for the port (and anyother internal sinks of the wire). If you specify set_num_external_sinks , then you getthat exact number added to the count of internal sinks of the wire.

Arguments

non_neg_integerNumber of external sinks. The default is 1.


Related Information

set_num_external_sources


do_derive_context

do_time_budget

set_port_wire_load

set_fanout_load

Examples

set_num_external_sinks 3 out




set_num_external_sourcesnon_neg_integer port_list

The set_num_external_sources command can be specified on top level input andoutput ports only. This command sets the constraint for the number of external sources thatare connected to the ports in the port list. This number is factored into the wire capacitanceand the wire resistance estimation done for the port nets using the wire-load models.

It does not add to the total fanin count for Design Rule Violation (DRV) checks. If you do notuse set_num_external_sources , then the fanin is 1 for the port (and any other internalsources on the wire). If you specify set_num_external_sources , then you get that exactnumber added to the count of internal sources of the wire.

Arguments

non_neg_integerNumber of external sources. The default is 1.


Related Information



do_derive_context

do_time_budget

set_port_wire_load

set_fanout_load

Examples

set_num_external_sources 2 in




set_operating_condition[-library library_name ] operating_condition_name [-pvt {min | typ | max}]

The set_operating_condition command specifies the operating condition (process,temperature, voltage, and tree-type) for the design from a given library. The named operatingcondition is used by the mapping and optimization commands to appropriately select cells.

Each technology library contains one or more operating conditions. Each condition isidentified by name, which specifies a set of process, temperature, voltage, and tree-typeconditions as the operating condition. This information is used to calculate accurate celldelays from the nominal cell delays and the k-factors (also called derating factors) from eitherlinear or nonlinear models.

You can get a list of all operating conditions in a technology library along with their PVT andOC type values by using the report_library command.

Arguments

operating_condition_nameSpecifies the name of the operating condition in the library.

-library library_nameSpecifies the technology library containing the named operatingcondition.

-pvt {min | typ | max}Sets the operating condition for a particular PVT (process,voltage, temperature) corner. You can choose one, two, or threePVT corners. If you choose more than one corner, enclose thelist in curly braces ({} ) and separate the values by spaces. Bydefault, the specified operating condition applies to all three PVTcorners.

Related Information

read_alf

read_tlf

report_library





Examplesset_operating_condition wccom




set_operating_parameter{-process float | -voltage float | -temperature float }[-pvt {min | typ | max}]

The set_operating_parameter command is used to individually set the operatingparameters (process, temperature, or voltage) for the design.

This information is used in calculating accurate cell delays from the nominal cell delays andthe k-factors (also called derating factors) from either linear or non-linear models.

If a DCM has been loaded, the delay and slew equations in the DCM use the operatingparameters specified here.

The set_operating_parameter command overrides the parameter value from thedefault operating condition of the technology library. It also overrides the parameter valuefrom any operating condition you previously selected with the set_operating_conditioncommand.

Note: Only one of the parameters (process, voltage, or temperature) can be set percommand.

Arguments

-process floatSpecifies the process multiplier.

-voltage floatSpecifies the voltage at which the circuit operates.

-temperature floatSpecifies the temperature at which the circuit operates.

-pvt {min | typ | max}Sets the operating parameter for a particular PVT (process,voltage, temperature) corner. You can choose one, two, or threePVT corners. If you choose more than one corner, enclose thelist in curly braces ({} ) and separate the values by spaces. Bydefault, the specified operating parameter applies to all threePVT corners.



Related Information



load_dcl_rule

Examplesset_operating_parameter -voltage 3.3 -typ

set_operating_parameter -process 1.0

set_operating_parameter -temperature 25 -typ



set_path_delay_constraint

set_path_delay_constraint[{-from | -from_rise | -from_fall} pin_list ][{-through | -through_rise | -through_fall} pin_list ][{-to | -to_rise | -to_fall} pin_list ][-early | -late][-clock_from list_of_clocks ] [-edge_from {leading | trailing}][-clock_to list_of_clocks ] [-edge_to {leading | trailing}][-bidi_input_from | bidi_output_from][-bidi_input_through | -bidi_output_through][-bidi_input_to | bidi_output_to]float

The set_path_delay_constraint path exception specifies a delay that must be met(-late ) or exceeded (-early ).

Note: The set_path_delay_constraint command requires set_globalpath_style_timing_constraint to be set to true , which is the default.

Arguments

floatSpecifies the delay value for the constraint.

{-from | -from_rise | -from_fall} pin_listSpecifies the pins that are at the start of the paths. If the -fromoption is used without the -to option, all paths originating fromthe pin_list are constrained.

Either -from , -to, or -through must be used with theset_path_delay_constraint command to identify thepaths. Specifying both -from and -to identifies a path withspecific starting and ending points.


Specifying set_path_delay_constraint -from ahierarchical pin treats the hierarchical pin as a -through . A-from pin must be an instance pin in order to place a constrainton a combinational path.




Using -from_rise applies the assertion at the rising edge ofthe signal on the through pins.

Using -from_fall applies the assertion at the falling edge ofthe signal on the through pins.

{-through | -through_rise | -through_fall} pin_listSpecifies the pins that the path goes through. When usedwithout -from or -to , all paths that go through the -throughpins have the specified delay.


The pin_list can contain either object IDs or hierarchicalnames relative to the current module. There can be only one-from and one -to , but many -through options in the samecommand.




{-to | -to_rise | -to_fall} pin_listSpecifies the pins that are at the end of the paths. If -to optionis used without the -from option, all paths ending in the -to pinlist have the specified delay.




Specifying set_path_delay_constraint -to ahierarchical pin treats the hierarchical pin as a -through . A -topin must be an instance pin in order to place a constraint on acombinational path.


Using -to_rise applies the assertion at the rising edge of thesignal on the through pins.

Using -to_fall applies the assertion at the falling edge of thesignal on the through pins.

-clock_from list_of_clocksSets the delay for all paths originating from the specified clocks.

-edge_from {leading | trailing}Specifies an edge for the -clock_from . Default is both edges.

-clock_to list_of_clocksSets the delay for all paths going to the specified clocks.

-edge_to { leading | trailing}Specifies an edge for the -clock_to . Default is both edges.

-bidi_input_from | -bidi_output_fromSpecifies that the assertion applies to the input or output ofbidirectional pins in the -from pin list. Default value is shown in“Bidirectional Pin Defaults” on page 776.

-bidi_input_through | -bidi_output_throughSpecifies that the assertion applies to the input or output ofbidirectional pins in the -through pin list. Default value isshown in “Bidirectional Pin Defaults” on page 776.

-bidi_input_to | -bidi_output_toSpecifies that the assertion applies to the input or output ofbidirectional pins in the -to pin list. Default value is shown in“Bidirectional Pin Defaults” on page 776.



-late | -earlySpecifies the maximum delay (-late ) or minimum delay(-early ). If neither option is specified, -late is the default.

Related Information

set_cycle_addition

Examples

The following command constrains the delay on the path from in to out to a maximum of 3.

set_path_delay_constraint -from in -to out 3




set_port_capacitancefloat port_list [-pvt {min | typ | max}]

The set_port_capacitance command specifies the capacitance external to the designbased on input and output loading from other ports and nets connected to the ports of thecurrent module.

The capacitance at any port is the sum of the external port capacitances that are connectedto the port. For an input port, the port capacitance refers to the capacitance of all the portsthat drive the net and the capacitance of the other loads on the net. For output ports, the portcapacitance refers to the capacitance of all the external sinks, (and external drivers, for thecase of a net with multiple drivers) that are connected to the net as well as the capacitanceof the input port of any other external drivers.

Arguments

floatSpecifies the capacitance value. The unit of capacitance must bethe same as the unit of capacitance used in the library.


-pvt {min | typ | max}Sets the port capacitance for a particular PVT (process, voltage,temperature) corner. You can choose one, two, or three PVTcorners. If you choose more than one corner, enclose the list incurly braces ({} ) and separate the values by spaces. By default,the specified port capacitance applies to all three PVT corners.

Related Information

set_current_module

set_port_capacitance_limit

set_global max_capacitance_limit



Examples

This command sets a 3.2 capacitance on all output ports of the current module whose namesstart with the string dbus .

set_port_capacitance 3.2 [find -port -output dbus*]



set_port_capacitance_limit

set_port_capacitance_limit[-min | -max] float port_list

The set_port_capacitance_limit command sets the limit on the capacitance externalto the design based on input and output loading from other ports and nets connected to thespecified ports of the current module.

This design rule constraint can be specified on top level input and output ports. The limit, bydefault, is the maximum value for the total capacitances (wire capacitance and pincapacitance) of nets attached to the ports in the port list. You can specify a minimum valuelimit with the -min option.

If set_global max_capacitance_limit (or set_globalmin_capacitance_limit ) has also been set, the most constraining value is used.

Arguments

-min | -maxSpecifies minimum (or maximum) design rule constraints. Ifneither option is given, the default is -max for backwardcompatibility.

floatSpecifies the capacitance value. Units must match the units usedin the library.


Related Information


set_slew_limit

set_slew_time_limit






do_derive_context

do_time_budget

set_global max_capacitance_limit

set_global min_capacitance_limit

Examplesset_port_capacitance_limit 5.0 [find -port dbus*]



set_port_wire_load

set_port_wire_load[-library library_name ] wire_load_model port_list [-pvt {min | typ | max}]

The set_port_wire_load command specifies the wire load for an input or output top levelport of a design. The net connected to the port is associated with the specified wireloadmodel, which is used for wire capacitance and resistance estimation.

If a net is connected to more than one port with a set_port_wire_load assertion, thenthe worst wireload model on the net is computed and used for timing analysis.

Arguments

-library library_nameIndicates the library containing the specified wire-load model. Ifthis option is not specified, the default is the target technologylibrary.

wire_load_modelSpecifies the name of the wire-load model to use for estimatingwire capacitance and resistance.


-pvt {min | typ | max}Sets the port wire-load model for a particular PVT (process,voltage, temperature) corner. You can choose one, two, or threePVT corners. If you choose more than one corner, enclose thelist in curly braces ({} ) and separate the values by spaces. Bydefault, the specified port wire-load model applies to all threePVT corners.

Related Information

set_wire_load


Examplesset_port_wire_load B0X0 out



set_scale_delays

set_scale_delays[-net_delay | -cell_delay | -cell_check] [-incl_sdf] [-pvt {min | typ | max}]scale_factor

The set_scale_delays command scales min , typ , or max delays from the library andoptionally from SDF assertions by the specified scaling factor. To specify unique scalingfactors and PVT for cell and net, issue the command multiple times. You can use thiscommand to remove or add a certain degree of pessimism.

Arguments

scale_factorFactor used to scale the delay. Scaling is specified by thedecimal notationx. nwhere:x = 0 for negative scaling (reducing) or 1 for positive scaling(increasing).n = 0 to 99For example:0.95 scales delays by -5%1.1 scales delays by 10%1.5 scales delays by 50%

-net_delaySpecifies scaling on net delays.

-cell_delaySpecifies scaling on cell delays.If neither -cell_delay nor -net_delay is specified, thespecified scaling factor applies to both types of delays.

-cell_checkSpecifies scaling on timing checks.

Note: Specifying -cell is equivalent to both -cell_delay and -cell_check .

-incl_sdfSpecifies scaling on SDF assertions.

-pvt {min | typ | max}Associates a min, typ, or max PVT (process, voltage, or



temperature) corner with the scale delay. Three PVT corners areallowed, namely, min, typ and max. By default, the specifieddelay scaling is applied to all PVT corners.

Related Information

get_scale_delays

Examplesset_scale_delays -incl_sdf -pvt min 0.95

set_scale_delays -incl_sdf -pvt max 1.05

For the min PVT corner, the library delays are scaled to 95% of the original value. For the maxPVT corner, the library delays are scaled to 105% of the original value.

These commands set different delay scaling for cells and nets.

set_scale_delays -cell_delay -pvt min 0.90

set_scale_delays -cell_delay -pvt max 1.1

set_scale_delays -net_delay -pvt min 1.1

set_scale_delays -net_delay -pvt max 1.3



set_slew_limit

set_slew_limit float port_list - Renamed to set_slew_time_limit

The set_slew_limit command has been renamed because it limits the slew timeparameter. See set_slew_time_limit on page 740.



set_slew_time

set_slew_time[-clock clkname ] [-early | -late] [-rise | -fall][-lead | -trail] |-pos | -neg]time port_list

The set_slew_time command is used to specify the slew time for a port on the top levelmodule of a design or for a pin on an instance of a technology cell anywhere in the hierarchy.It is useful only in specifying a hard ramp signal as if the pin were driven by a very powerfuldriver. It does not change the arrival time of an input, but changes the slew time used tocompute the delay of the cell on the sink of a net.

Note: The set_slew_time command is ignored for a port if set_drive_cell orset_drive_resistance constraints have been set for that port.

Arguments

-clock clock_nameSpecifies the name of the ideal clock that is associated with theslew time. If this option is not specified, the default is @, a signalwithout an associated clock (asynchronous).

timeSpecifies the slew time.

port_listList of top level nets or technology cell instance pins for which theslew time is specified.

-lead | -trailThe -lead and -trail options specify whether the slew timedata signal is triggered by the leading edge or trailing edge of theideal clock. The default is -lead .

-pos | -negFor a clock signal, the -pos and -neg options specify that theslew time should be applied to an actual clock having a positiveor negative polarity with respect to the ideal clock. Only oneoption either -pos or -neg can be specified per command. Thedefault is -pos .

-rise | -fallSpecifies that the slew time should be applied to the rising edge



or the falling edge of the signal (data or clock). If neither time isspecified, the default is to use both.

-early | -lateIndicates whether the slew times are with respect to the early(hold) or the late (setup) time checks. If neither time is specifiedthe default is to use both.

Related Information

set_slew_time_limit

set_drive_cell



set_global slew_time_limit

Examplesset_slew_time 0.5 input3

set_slew_time -clock B0 -pos 0.1 clk_b



set_slew_time_limit

set_slew_time_limit[-min | -max] float port_list

The set_slew_time_limit command specifies the limit (maximum or minimum) for slewtime at the input and output ports of a module. The slew limit is usually derived from thedesign rule constraints placed on the cells that an output port is driving or an input port isdriven by.

This command is used to override the default slew time limit placed on specific ports by theset_global max_slew_time_limit or set_global min_slew_time_limitcommands.

Arguments

-min | -maxSpecifies minimum (or maximum) design rule constraints. Ifneither option is given, the default is -max for backwardcompatibility.

floatSpecifies the maximum (or minimum) slew allowed.

port_listList of ports to which the limit applies.

Related Information

set_slew_time


set_global max_slew_time_limit

set_global min_slew_time_limit

Examples

The following command sets the maximum slew time limits for bus1 and bus2 to 2.3 :

set_slew_time_limit 2.3 {bus1 bus2}



set_tech_info

set_tech_info{([-library list_of_library_names ][-default_wire_load wlm_name][-default_wire_load_selection wireload_selection_table ][-default_operating_conditions op_cond_name ][-default_fanout_load float ] [-default_max_capacitance float ][-default_max_fanout value ] [-default_max_transition value ][-input_threshold_pct_rise float ] [-input_threshold_pct_fall float ][-output_threshold_pct_rise float ] [-output_threshold_pct_fall float ][-slew_lower_threshold_pct_rise float ][-slew_lower_threshold_pct_fall float ][-slew_upper_threshold_pct_rise float ][-slew_upper_threshold_pct_fall float ][-pvt {min | typ | max}])|([-library list_of_library_names ]-cell list_of_cell_names{[-dont_modify true | false] [-dont_utilize true | false][-scaling_factors value ][-input_threshold_pct_rise float ] [-input_threshold_pct_fall float ][-output_threshold_pct_rise float ] [-output_threshold_pct_fall float ][-slew_lower_threshold_pct_rise float ][-slew_lower_threshold_pct_fall float ][-slew_upper_threshold_pct_rise float ][-slew_upper_threshold_pct_fall float ][-pvt {min | typ | max}])|([-library list_of_library_names ]-cell list_of_cell_names-pin list_of_pin_names[-fanout_load value ] [-max_fanout value ] |[-max_transition value ] [-max_capacitance float ][-pvt {min | typ | max}])}

The set_tech_info command makes assertions (overrides values) for the specifiedparameters in the named target technology libraries. Assertions apply to the library, cell, orpin level and can be specified for one PVT value at a time.

You can use this command to loosen overly pessimistic values in the library. Be careful whenapplying overrides to vendor determined values.


-library list_of_library_namesOverrides data for the named libraries. Default is all libraries



specified with the set_global target_technologycommand.

-pvt {min | typ | max}Sets the value for the environment corner of interest. You can setone PVT corner per command.The default is typ .


-default_wire_load wlm_nameSpecifies the default wireload for the library.

-default_wire_load_selecti on wireload_selection_tableSpecifies the default wire-load selection table for the library.

-default_operating_conditions op_cond_nameSpecifies op_cond_name as the default operating conditionsfor the library.

-default_fanout_load floatSpecifies the value of the default fanout load for all pins on allcells in the library.

-default_max_capacitance floatSpecifies the value of the default maximum capacitance for allpins on all cells in the library.

-default_max_fanout floatSpecifies the value of the default maximum fanout for all pins onall cells in the library.

-default_max_transition floatSpecifies the value of the default maximum transition time for allpins on all cells in the library.

-input_threshold_pct_rise floatSpecifies the value of the default input threshold percent for therising edge for all cells in the library.

-input_threshold_pct_fall floatSpecifies the value of the default input threshold percent for thefalling edge for all cells in the library.



-output_threshold_pct_rise floatSpecifies the value of the default output threshold percent for therising edge for all cells in the library.

-output_threshold_pct_fall floatSpecifies the value of the default output threshold percent for thefalling edge for all cells in the library.

-slew_lower_threshold_pct_rise floatSpecifies the value of the default lower threshold percent for theslew time of the rising edge for all cells in the library.

-slew_lower_threshold_pct_fall floatSpecifies the value of the default lower threshold percent for theslew time of the falling edge for all cells in the library.

-slew_upper_threshold_pct_rise floatSpecifies the value of the default upper threshold percent for theslew time of the rising edge for all cells in the library.

-slew_upper_threshold_pct_fall floatSpecifies the value of the default upper threshold percent for theslew time of the falling edge for all cells in the library.


-cell list_of_cell_namesSpecifies the cells to which the assertions are applied. Requiredargument for cell and pin level assertions.

-dont_modify {true | false}When set to true this option puts the dont_modify propertyon the named cells. These cells are not modified by optimizationor time budgeting. The default is false .

-dont_utilize {true | false}When set to true this option puts the dont_utilize propertyon the named cells. These cells are not used in optimization. Thedefault is false.



-scaling_factors derate_table_nameSpecifies a derating table containing scaling factors for the celldelay of the named cells.

Note: The read_library_update command has been enhanced to update scaling factorgroups to the target library similar to a wire-load models update. The -scaling_factorsoption can be used in conjunction with read_library_update to set a new scaling factorsgroup for a cell or to change the scaling factors group of a cell within a library.

-input_threshold_pct_rise floatSpecifies the value of the default input threshold percent for therising edge for the listed cells.

-input_threshold_pct_fall floatSpecifies the value of the default input threshold percent for thefalling edge for the listed cells.

-output_threshold_pct_rise floatSpecifies the value of the default output threshold percent for therising edge for the listed cells.

-output_threshold_pct_fall floatSpecifies the value of the default output threshold percent for thefalling edge for the listed cells.

-slew_lower_threshold_pct_rise floatSpecifies the value of the default lower threshold percent for theslew time of the rising edge for the listed cells.

-slew_lower_threshold_pct_fall floatSpecifies the value of the default lower threshold percent for theslew time of the falling edge for the listed cells.

-slew_upper_threshold_pct_rise floatSpecifies the value of the default upper threshold percent for theslew time of the rising edge for the listed cells.

-slew_upper_threshold_pct_fall floatSpecifies the value of the default upper threshold percent for theslew time of the falling edge for the listed cells.




-pin list_of_pin_namesSpecifies the pins to which the assertions are applied. Requiredargument for pin level assertions.

Note: The pin assertions apply to a specific pin type. If the correct pin type is not specified,an error is flagged.

-fanout_load floatSpecifies the value of the fanout load for the named pins.Overrides the library default value. This option can be specifiedonly for an input pin.

-max_fanout floatSpecifies the value of the maximum fanout for the named pins.Overrides the library default value. This option can be specifiedonly for an output pin.

-max_transition floatSpecifies the value of the maximum transition time for the namedpins. Overrides the library default value. This option can bespecified for both input and output pins.

-max_capacitance floatSpecifies the value of the maximum capacitance for the namedpins. Overrides the library default value. This option can bespecified only for an output pin.

Related Information

get_tech_info

reset_tech_info


Examplesset_tech_info -library lib1 lib2 -default_fanout_load 1.4111

set_tech_info -cell FD2ESSA -dont_utilize true

set_tech_info -library lca300kv -cell B2I -pin Z1 Z2 -pvt min -max_fanout 3



The following commands set the values shown in Figure 7-8 on page 746 for all cells in thetarget technology library.

set_tech_info -input_threshold_pct_rise 50 -input_threshold_pct_fall 50

set_tech_info -output_threshold_pct_rise 50 -output_threshold_pct_fall 50

set_tech_info -slew_lower_threshold_pct_rise 10 -slew_upper_threshold_pct_rise 90

set_tech_info -slew_lower_threshold_pct_fall 10 -slew_upper_threshold_pct_fall 90

Figure 7-8 Thresholds Example

rise time

cycle time

fall time

fall slew timerise slew time

threshold

10

90

50




set_time_borrow_limit -pin pin_list -clock list_of_clocks borrow_limit

Used with level-sensitive latches, the set_time_borrow_limit command specifies themaximum time that can be borrowed by one cycle from the next cycle in order to meet timingconstraints. Time borrowing is sometimes called cycle stealing. Time borrowing is performedautomatically when performing a timing analysis.

The set_time_borrow_limit assertion can be made on pins or waveforms. If theassertion is placed on an ideal clock, all latches triggered by this clock get the specifiedmaximum time borrow limit. If both the clock waveform arriving at the clock pin of a latch andthe clock pin itself have time borrow limit assertions, the maximum borrow limit on the latchis decided by the assertion on the latch clock pin.

Arguments

-pin pin_or_instance_listSpecifies a single pin or multiple pins to which the borrow limitapplies. To specify multiple pins, enclose the list with curlybraces ({) } and separate the pin information with white-space.

You can alternatively give a list of latch instances. In which case,the assertion applies to the clock pins of the instances listed.


Specifies the ideal clock names to which the borrow limit applies.

If neither -pin nor -clock option is specified, the borrow limitis placed on all clocks.

borrow_limitA nonnegative real number that specifies the maximum amountof time that can be borrowed. The minimum value allowed is 0which disables time borrowing. The maximum allowed is equal tothe pulse width minus the setup time:Max = pulse width - setup

Related Information






Examplesset_time_borrow_limit -pin l1/q 1.5




set_top_timing_modulemodule_name

The set_top_timing_module command identifies the module to be used by subsequentcommands as a context for setting timing constraints.

All the constraints are set with reference to the module specified as the top timing module.The optimization commands operate on the module (and its hierarchy) set by the top timingmodule. If you set a new top timing module, you change the context for the subsequent timingconstraints and the optimization steps. The constraints applied to the previous top timingmodule are preserved but do not affect the steps carried out in the new top timing module.

Note: If a different module needs constraints set on its ports as part of thetop_timing_module context, then it should be set using set_current_modulecommand.

Arguments

module_nameName of the module being set as the timing context.

Related Information

set_current_module

do_optimize


Examples

This command sets the control_block module as the context for all timing constraints.Timing constraints can be specified for control_block or any instances in the downwardhierarchical path.

set_top_timing_module control_block



set_wire_capacitance

set_wire_capacitancefloat net_names [-subtract_pin_caps] [-pvt {min | typ | max}]

The set_wire_capacitance command is used after the physical design has been done,to backannotate the capacitance on each net for the purpose of reanalyzing the netlist fortiming. The command set_wire_capacitance is used to backannotate the data.

You can remove pin and port capacitance from the wire capacitance to be backannotated byusing the -subtract_pin_caps option.

Arguments

floatThe wire capacitance to be backannotated. Units are determinedby the library.

net_namesThe list of nets having this capacitance.

-subtract_pin_capsCalculates wire capacitance by subtracting the capacitance onpins and ports of the net from the specified wire capacitancevalue. The wire capacitance that is backannotated does notinclude pin capacitance.

-pvt {min | typ | max}Sets the capacitance for a particular PVT (process, voltage,temperature) corner. You can choose one, two, or three PVTcorners. If you choose more than one corner, enclose the list incurly braces ({} ) and separate the values by spaces. By default,the specified capacitance applies to all three PVT corners.

Related Information

set_wire_resistance

report_net



Examples

The following commands backannotate a wire capacitance of 2 on the net named foo for minand typ environment corners and a wire capacitance of 2.2 for max PVT.

set_wire_capacitance 2 foo -pvt {min typ}

set_wire_capacitance 2.2 foo -pvt max

Suppose the total pin capacitance on net foo is 0.5, this command backannotates a wirecapacitance of 1.5.

set_wire_capacitance 2 foo -pvt {min max} -subtract_pin_caps



set_wire_load

set_wire_load[-library library_name ] [-pvt {min | typ | max}] [-hier]wireload_model list_of_instances

The set_wire_load command is used to specify the wire-load model to be used from thetechnology library. It sets the wire-load model on the current instance, if the list of instancesis omitted. Otherwise, the wire-load model is set on all instances specified.

Wire-load models are used for estimating delays before the actual wire loads arebackannotated. A technology library contains different wire-load models, that were previouslycomputed based on the analysis of several designs differing in area. Use thereport_library command to list all the wire-load models in a library.

Arguments

wireload_modelThe name of the wire-load model in the library.

port_listThe list of ports.

library_nameThe name of the technology library.

list_of_instancesThe list of instances.

-library library_nameThe technology library to use when searching for the wire loadmodel.

-pvt {min | typ | max}Sets the wire-load model for a particular PVT (process, voltage,temperature) corner. You can choose one, two, or three PVTcorners. If you choose more than one corner, enclose the list incurly braces ({} ) and separate the values by spaces. By default,the specified wire-load model applies to all three PVT corners.

-hierAffects wire-load assertions in the enclosed wire-load mode.(See set_wire_load_mode on page 755). By default (without-hier switch), in the enclosed wire load mode, the asserted



wire-load model applies to only those nets for which the specifiedhierarchical instance is the lowest enclosing module.

If -hier is set, then for all nets fully contained within thehierarchical instance (or any of its lower level hierarchicalinstances), the asserted wire-load model is used, unless anothersuch assertion is present on one of the lower level hierarchicalinstances.

In the top wire-load mode, a wire-load assertion on ahierarchical instance applies to all the nets fully enclosed withinthe hierarchical instance (unless there is another such wire loadassertion present on one of the lower level hierarchicalinstances) meaning the -hier switch is always on.

Here is how wire load for a net is looked up. The search processstarts with the lowest hierarchical instance completely enclosingthe net and recursively traverses up the hierarchy chain, until itreaches (and includes) the top module.

Enclosed wire load modeIf a wire-load model is asserted on the lowest enclosinghierarchical instance (with or without -hier switch), thatwire-load model is used. Otherwise, travel up the hierarchylooking for an asserted wire-load with -hier switch. If one isfound, that wire load is used. Otherwise, area-based lookup isused.

Note: As search traverses up the hierarchy chain, if a wire load without a -hier switchis found, that assertion is ignored. Thus, the assertion for wire-load model without -hierswitch applies only to the nets fully enclosed within that specific hierarchical instance(and not in any of its lower level hierarchical instances).

Top modeIn this mode, -hier switch on the wireload assertion iscompletely ignored. Again, start from the lowest enclosinghierarchical instance and travel up the hierarchy chain. As soonas a wire-load assertion is found on an instance (with or without-hier switch), that wire-load model is used. If no wire-loadassertion is found, then the area-based lookup is used.



Related Information

do_derive_context

report_library

set_wire_load_mode

set_port_wire_load

set_current_module


Examplesset_wire_load B5X5 {I_block J_block}



set_wire_load_mode

set_wire_load_mode{top | enclosed}

The set_wire_load_mode command controls the determination of the wire-load model.

Arguments

topSelects the wire-load model using the area lookup table of thetop level module (as set by the set_top_timing_modulecommand). The default wire-load mode is top .

enclosedSelects the wire-load model using an area lookup table for themodule that is at the lowest level in the design hierarchy thatcontains the entire net.

Related Information

report_library

set_wire_load


set_current_module


Examplesset_wire_load_mode enclosed



set_wire_load_selection_table

set_wire_load_selection_table[-library library_name ] [-pvt {min | typ | max}] [-min_area float ]wireload_selection_table

The set_wire_load_selection_table command can be used to override the wire-loadselection table in the library, library_name . When library_name is the targettechnology library, the specified wire_load_selection_table is used in analysis.

Arguments

wireload_selection_tableThe name of the wire-load selection table.

-library library_nameThe name of the technology library to search for the wire-loadselection table. The default is the target_technology file.

-pvt {min | typ | max}Controls the choice of wire-load selection table for different PVTvalues. The default is to select the table for all PVTs.

-min_area floatSelects the area wire-load model for all area values smaller thanfloat .

Related Information

reset_wire_load_selection_table

set_wire_load

report_library


Examplesset_wire_load_selection_table TLM



set_wire_resistance

set_wire_resistance[-pvt {min | typ | max}] float net_names

The set_wire_resistance command is used to backannotate the resistance on each netafter the physical design has been done.The netlist can then be reanalyzed for timing.

Arguments

floatSpecifies the resistance value

net_namesList of nets with the resistance

-pvt {min | typ | max}Sets the resistance for a particular PVT (process, voltage,temperature) corner. You can choose one, two, or three PVTcorners. If you choose more than one corner, enclose the list incurly braces ({} ) and separate the values by spaces. By default,the specified resistance applies to all three PVT corners.

Related Information

set_wire_capacitance

report_net

Examples

This command sets the resistance for the nets bus1 and bus2 at 4.6

set_wire_resistance 4.6 {bus1 bus2}



unload_dcl_rule

unload_dcl_rule

The unload_dcl_rule command removes a previously loaded binary Delay and PowerCalculation Module (DPCM) from memory. The DPCM is an executable shared library that islinked to an application (like Ambit BuildGates synthesis) at runtime. DPCM is oftenabbreviated as DCM. After unloading the DCM, all timing calculations are performed withoutinformation from the DCM.

Related Information

load_dcl_rule

Examplesunload_dcl_rule



write_assertions

write_assertions[-no_internal_arr_req] [-no_timing] [-no_tag] [ file_name ]

The write_assertions command writes out the assertions made on the design during theoptimization process for future reference and use. The assertions are created bydo_derive_context and do_time_budget commands.

The assertions for wire capacitance and wire resistance are not written out by thewrite_assertions command. Wire capacitance and wire resistance are stored in the ADBfile.

Arguments

-no_internal_arr_reqInternal arrival times are not written to the file.

-no_timingTiming assertions, such as clock assertions, arrival and requiredtime assertions are not written to the file. Only those assertionsthat are not related to timing checks, such as load, drive,wire-load model, operating conditions, and so on, are written out.

-no_tagRemoves all proprietary information (set_begin_tag , -tag ,-from_tag , and -info ) from the output file. The resultingassertions file is in a form that is easier for a script to translate toa third-party language.

Note: The -no_tag option works only for chip-level constraints. If you have done timebudgeting, then write_assertions -no_tag for block level constraints does notwork. Removing tags from constraints is not the solution either. This is similar to droppingconstraints from the design. Therefore, you are stuck with using budgeted blockconstraints in BG/PKS only.

file_nameName of the file in which to write the assertions. If file_nameis not specified, assertions are written to stdout .

Related Information

do_derive_context



do_time_budget

remove_assertions

Examples

The following command saves all the assertions, except timing assertions, inmy_assert_file .

write_assertions -no_timing my_assert_file



write_constraints

write_constraints[-max_slack slack_value ] [-max_paths num_paths ][-coverage_ratio float ] [-min_constraint float ]file_name ]

The write_constraints command writes the constraints of the currenttop_timing_module context to the named file. The file is written in Standard Delay Format(SDF} for timing-driven place and route using path constraint constructs to cover all nets inthe design.

The write_constraints command outputs constraints for use by place and route tools.Therefore this command must provide a set of paths that cover the design. The default valueof max_paths is 1000, unless a higher number is specified. The paths included are onlythose whose slack is less than the value specified by the -max_slack option.

Arguments

file_nameThe name of the resulting SDF file.

-max_slack slack_valueLimits the number of paths by specifying the maximum slack ofthe net for which to write a path. The default value formax_slack is +infinity.

-max_paths num_pathsAn optional limit to the number of paths produced.

-coverage_ratio floatSpecifies a coverage ratio that is the number of arcs covered inthe constraints divided by the total number of arcs in the design.By specifying a coverage_ratio the number of paths can belimited.

-min_constraint floatIf the paths in the design are overconstrained, the resultantconstraint file is similarly overconstrained. By using the-min_constraint option, the path constraints written arerelaxed by the specified amount.



Related Information

write_sdf

Examplesset_top_timing_module top

set_current_module top

write_constraints constraints.sdf



write_gcf_assertions

write_gcf_assertions[-version {1.3 | 1.4}] [ file_name ]

The write_gcf_assertions command automatically translates the Ambit BuildGatessynthesis Tcl constraints into Cadence General Constraint Format (GCF). When using theBuildGates/Deep-Submicron System Level Constraints flow (BG/DSM-SLC flow) for ASICdesign, there are two timing analysis engines that interact between the synthesis and theplace-and-route phase. The front-end of the flow uses Cadence timing analysis from AmbitBuildGates synthesis and the back-end uses Pearl from the place-and-route tool suite. Pearlalso reads the TLF libraries to calculate the delays in the ASIC during floorplanning and place& route. Pearl utilizes the GCF constraints file in conjunction with the TLF libraries and theVerilog gate-level netlist to create the Stage-Based Constraints (SBC) file. Pearl uses theSBC file to drive all the floorplanning and place-and-route phases of Cadence Design Plannerand Silicon Ensemble. This combination yields a very tight correlation between the timingreports generated by Pearl and those generated by Cadence timing analysis. Thiscombination also speeds up the conversion process to final silicon. Other flows like theSE-PKS flow also use this combination.

Arguments

-version {1.3 | 1.4}Specifies the version of GCF to write out. The version shows inthe header of the GCF file and is used by the tools that read GCF.Version 1.4 has more constructs for greater intertoolcompatibility. The default is 1.4 .

file_nameSpecifies the file name. If it is not specified, the default is thestandard output.

Related Information

read_verilog

read_vhdl

read_tlf

write_verilog

report_timing



Examples

This writes out the file cpu.gcf :

write_gcf_assertions cpu.gcf




write_library_assertions[-library list_of_library_names ] file_name

The write_library_assertions command writes out any assertions you have made tothe named libraries using the set_tech_info command.

Arguments

-library list_of_library_namesReports data for the named libraries. Default is all librariesspecified with the set_global target_technologycommand.

file_nameThe name of the output file. Required argument.

Related Information

set_tech_info

get_tech_info

reset_tech_info

Examples

The following command writes out all assertions previously defined by the set_tech_infocommand:

write_library_assertions assert.txt

Here are the contents of assert.txt showing that two default values in the cb library havebeen overwritten:

set_tech_info -library cb -default_max_transition 5.000000 -pvt typset_tech_info -library cb -default_max_capacitance 2.500000 -pvt min



write_rspf

write_rspfOBSOLETE: Use write_spf instead.

Important

The write_rspf command is no longer supported, use write_spf instead.

Related Information

write_spf



write_sdf

write_sdf[-version { 2.1 | 3.0 }] [-precision non_neg_integer ] [-scale float ][-delimiter char ] [ {-early | -late} ][-celltiming {all | none | nochecks}][-interconn {all | none | noport | noinport | nooutport}][-edges {edged | library | noedge}] [-remashold] [-splitrecrem][-splitsetuphold] [-condelse] [-nonegchecks] [-force_calculation][ file_name ]

The write_sdf command writes assertions to a Standard Delay Format (SDF) file. Fordelay calculation, write_sdf uses fast slew propagation mode with depth of 2.

Arguments

file_nameThe name of the SDF output file. If omitted, this argumentdefaults to stdout .

-version {2.1 | 3.0}Specifies whether to generate the SDF V2.1 or V3.0. The defaultSDF version is 3.0. Used in combination with the remasholdoption.

-precision non_neg_integerControls the number of digits appearing after the decimal pointin the output SDF file. The default precision is 3 unless thereport_precision global is set.

-scale floatSpecifies a multiplier to the delay values used in the SDF file.The default multiplier is 1. This option does not change thetimescale setting of the SDF file. The delay values are scaled,but the units are the same.

-delimiter charSpecifies the hierarchy divider character to use in the SDF outputfile. This option sets the hierarchy divider of only the write_sdfcommand. If omitted, the default ac_shell hierarchy dividercharacter (/ ) is used as the write_sdf default.



-early | -lateSpecifies early mode or late mode analysis for computing SDFdelays. The default mode is -late .

-edges {edged | library | noedge}The default is edged . Refer to Table 7-3 on page 770 for fullqualifications of the three possible values for the edges option.

edgedWrites the SDF IOPATH and timing checks with appropriateedges.

libraryCadence timing analysis assumes that the sdf_edgesattributes are specified in the .lib file or the library. The defaultsdf_edges value of a timing arc is noedge .

noedgeDefined in Table 7-3 on page 770.

-interconn {all | none | noport | noinport | nooutport}Specifies which interconnect delays to write out.

allWrites all INTERCONNdelays into the SDF file. This is thedefault if -interconn is not specified.

noneNo INTERCONN delays are written into the SDF file.

noportNo top level port INTERCONNdelays are written into the SDFfile.

noinportDisables only the input port INTERCONNdelays.

nooutportDisables only the output port INTERCONNdelays.

-celltiming {all | none | nochecks}Specifies which cell delays and timing checks to write out.



allWrites all cell delays and timing checks to the SDF file. This isthe default.

nonePrevents cell delays and timing checks from being written intothe SDF file.

nochecksDisables the writing of timing checks only.

-remasholdWhen combined with the -version 2.1 option, this optionconverts the SDF v2.1 unsupported REMOVAL(and the REMOVALportion of the RECREMconstructs) to HOLDchecks. The default isnot to write out the unsupported checks.

When combined with the -version 3.0 option, this optionconverts the REMOVAL checks to HOLD checks. The RECREMchecks are split into a RECOVERYcheck and a HOLDcheck. Thisoption automatically splits the RECREMchecks. The default is tomaintain the V3.0 checks.

-splitrecremThis option splits the RECREM checks into a RECOVERY checkand a REMOVAL check. The default is to write the combinedRECREM check.

Note: This option can only be used with the version 3.0 option (see page 767).

-splitsetupholdSplits the SETUPHOLD timing checks into separate SETUP andHOLD checks. The default is to write the combined SETUPHOLDchecks.

-condelseWhen a COND construct is written, it also writes CONDELSEconstructs with the default value.

Note: This option can only be used with the -version 3.0 option (see page 767).

-nonegchecksConverts all negative timing check values to 0.0 .



-force_calculationForces the recomputation of delays during write_sdf andwrites triplets (min:typ:max ). This was the default behaviorprior to 4.0.8. You should use this option for backwardcompatibility with 4.0.

Without this option write_sdf uses delays already cached inthe system and writes only values of the triplets specified by thepvt_early_path and pvt_late_path globals.

Related Information

write_pdef

write_verilog

Examples

The following command writes out SDF 2.1 compliant output file named my.sdf with 4 digitsafter the decimal point:

write_sdf -version 2.1 -precision 4 my.sdf

Table 7-3 Definition of -edges Option Values

edged Value library Value noedge Value

IOPATH from aunate input pin tooutput pin

No edge specifier. No edge specifier. No edge specifier.

IOPATH from anon-unate inputpin to output pin

Edge specifier at theinput pin.

Edge specifier at theinput pin whensdf_edges is either“both_edges” or“start_edge”

No edge specifier.

When mergingedged paths, themaximum values areused for MAX andTYP fields; minimumvalues are used forMIN fields.



IOPATH of aclock/enable pinto data out pin

Edge specifier at theinput pin.

Edge specifier at theinput pin whensdf_edges is either“both_edges” or“start_edge”

No edge specifier.

Table 7-3 Definition of -edges Option Values, continued




Timing Checks Edge specifiersmatch the check arcsspecified in thetiming library.

Overridden by valueof the “sdf_edges”attribute.

For “both_edges”,the timing checks willcontain edgespecifier on bothstarting and endingpins.

For “start_edge,” thestarting pin (forHOLD type check) orending pin (forSETUP type check)will beedge-specified.

For “end_edge,” theending pin (for HOLDstyle check) or thestarting pin (forSETUP type check)will beedge-specified.

The timing checkswill be duplicated orcombinedappropriately. The“start_edge” and“end_edge” areinterpreted as firstand second events,respectively, of theVerilog-XL’s $hold()and $setup systemtasks.

Edge specifiersmatch the check arcsspecified in thetiming library.

Table 7-3 Definition of -edges Option Values, continued




write_spf

write_spf [-pvt {min | typ | max}] [-no_instance_section] file_name

The write_spf command writes out the reduced format SPF file in the database to thenamed file. You must have read in an SPF file before issuing this command.

Note: This command replaces the obsolete write_rspf command.

Arguments

-pvt {min | typ | max}Specifies which PVT value to write. SPF format supports onlyone value (no pairs or triplets). Choose either min or typ or max.

-no_instance_sectionTells the system not to write the instance section of the SPF file.Some tools require the instance section, you should checkbefore using this option.

file_nameSpecifies the name of the file to which the reduced SPF iswritten.

Related Information

read_spf

read_spef

Exampleswrite_spf -pvt min min.rspf



Path Exception Priorities

Table 7-4 shows the priority for path exceptions applied to the same path. See “Examples ofPath Exception Priorities” on page 775.

The path exception command descriptions are available at:

■ set_false_path on page 708

■ set_path_delay_constraint on page 726

■ set_cycle_addition on page 683

Table 7-4 Path Exception Priorities

Priority Path Exception

1. (Highest) set_false_path

2. set_path_delay_constraint -from pin_list

3. set_path_delay_constraint -to pin_list

4. set_path_delay_constraint -through pin_list(greatest number of throughs has highest priority)

5. set_path_delay_constraint -clock_from ideal_clk

6. set_path_delay_constraint -clock_to ideal_clk

7. set_path_delay_constraint(most constraining adjustment has higher priority over lessconstraining adjustments)

8. set_cycle_addition -from pin_list

9. set_cycle_addition -to pin_list

10. set_cycle_addition -through pin_list(greatest number of throughs has highest priority)

11. set_cycle_addition -clock_from ideal_clk

12. set_cycle_addition -clock_to ideal_clk

13. (Lowest) set_cycle_addition(most constraining adjustment has higher priority over lessconstraining adjustments)



Examples of Path Exception Priorities

Examples of the path exception priorities for path starting at A, going through B, and endingwith C appear below. The priorities indicated assume that the globalpath_style_timing_constraint is set to the default value, true .

The pairs of examples are ordered such that the highest priority constraint in the first pair hasprecedence over the highest priority constraint in the second pair.

In the following pair of constraints, the false path overrides the cycle addition.

set_false_path -from A -through B -to C

set_cycle_addition -from A 1

In the following pair, the first constraint is applied (2 cycles added) because -from haspriority over -to .


set_cycle_addition -to C 1

In the following pair, the first constraint is applied (2 cycles added) because it specifies morepins on the path.

set_cycle_addition -through {A B} 2

set_cycle_addition -through B 1

In the following pair, the first constraint is applied (2 cycles added) because it specifies-through pin as well as -to pin.

set_cycle_addition -through A -to B 2

set_cycle_addition -to B 1

In the following pair, the first constraint is applied (2 cycles added) because -clock_fromhas precedence over -clock_to .

set_cycle_addition -clock_from CLKA 2

set_cycle_addition -clock_to CLKB 1

In this pair of path exceptions, 1 cycle is added because it is the most constraining value.





Bidirectional Pin Defaults

The following tables show the default pin type that the system uses for bidirectional pins. Inthe case of path exceptions, you can override the default with these options:

[-bidi_input_from | bidi_output_from][-bidi_input_through | -bidi_output_through][-bidi_input_to | bidi_output_to]

Table 7-5 defines the pin and port types that are used in Table 7-6. Table 7-7 and Table 7-8on page 777 show default types for ports.Table 7-5 Bidirectional Pin Type Definitions

Pin Type Type 1 Type 2

Blackbox pins out in

Instance pins out in

Netlist ports in out

Hierarchical ports in out

Table 7-6 Bidirectional Pin Type Defaults

Pin or Port Constraint Type Hierarchical Port

set_input_delay 1 ignored

set_external_delay 2 ignored

set_clock_insertion_delay 1 ignored

set_clock_required_time 2 ignored

set_clock_info_change 1 used

set_slew_time 1 ignored

set_drive_cell 1 ignored

set_drive_resistance 1 ignored

path exception (from) 1 used

path exception (through) 1 used

path exception (to) 2 used



Table 7-7 defines the pin and port types that are used in Table 7-8.Table 7-7 Bidirectional Port Type Definitions

Pin Type Type 1 Type 2

Netlist ports in out

Hierarchical ports in out

Table 7-8 Bidirectional Pin Type Defaults

Port Constraint Type Hierarchical Port

set_fanout_load 2 ignored

set_fanout_load_limit 2 ignored

set_num_external_sources 2 ignored

set_num_external_sinks 2 ignored

set_port_capacitance 2 ignored

set_port_capacitance_limit 2 ignored

set_port_wire_load 2 ignored

set_slew_time_limit 2 ignored



Command Index

Aac_shell 25alias 28all_children 29all_parents 31

Ccheck_batch 310check_design 344check_dft_rules 480check_dist 312check_host 313check_libraries_and_design_compatibility

345check_library 346check_netlist 32check_option 33check_option on page 30 20check_timing 532create_blockage 348create_module_reference 36create_placement_area 350

Ddebug 37delete_aware_component 39delete_blockage 352delete_object 40display_scan_chains 482do_blast_busses 42do_build_clock_tree 294do_build_generic 44do_build_physical_tree 297do_change_name 48do_copy_module 52do_cppr_analysis 535do_create_hierarchy 54do_derive_context 537do_dissolve_hierarchy 56do_extract_critical 58do_extract_fanin 61

do_extract_fanout 63do_extract_non_critical 65do_extract_route_parasitics 353do_generate_estcap 354do_initialize_floorplan 355do_optimize 66do_place 356do_placement_spread 361do_pop_module 69do_push_module 70do_rebind 71do_remove_design 73do_remove_scan_order_data 486do_rename 74do_reset_floorplan 362do_route 363do_snap_instance_to_row 369do_time_budget 539do_uniquely_instantiate 76do_xform_buffer 87do_xform_buffer_tree 88do_xform_clone 90do_xform_connect_scan 483do_xform_fast_optimize 91do_xform_fix_design_rule_violations 92do_xform_fix_hold 93do_xform_fix_multiport_nets 94do_xform_footprint 95do_xform_map 98do_xform_optimize_generic 99do_xform_optimize_power 449do_xform_optimize_slack 100do_xform_pre_placement_optimize_slack

101do_xform_propagate_constants 102do_xform_reclaim_area 103do_xform_remove_redundancy 104do_xform_resize 105do_xform_restructure 106do_xform_structure 107do_xform_tcorr_eco 370do_xform_timing_correction 108do_xform_unmap 109dump_adb 110



Eeval_bottom_up 111

Ffind 113

Ggenerate_supply_rails_on_rows 372get_area 120get_attribute 122get_buswidth 123get_cell_area 124get_cell_drive 543get_cell_pin_load 545get_clock 546get_clock_propagation 548get_clock_source 549get_clock_tree_constraints 286get_clock_tree_objects 287get_cluster_names 373get_constant_for_timing 551get_current_congestion 374get_current_instance 125, 552get_current_module 126get_current_utilization 375get_dcl_calculation_mode 552get_dcl_functional_mode 553get_dcl_functional_mode_array 554get_dcl_level 555get_derived_clock 556get_drive_pin 557get_equivalent_cells 127get_fanin 559get_fanout 561get_global 128get_hdl_file 129get_hdl_hierarchy 130get_hdl_top_level 132get_hdl_type 133get_host_info 314get_info 134get_job_info 317get_library_layer_capacitance 376get_library_layer_offset 377get_library_layer_resistance 378

get_library_layer_usage 379get_load_pin 563get_logic_0_net 380get_logic_1_net 381get_message_count 136get_message_verbosity 137get_min_porosity_for_over_block_routing

382get_min_wire_length 383get_module_worst_slack 564get_names 138get_net 139get_operating_parameter 565get_parent_instances 141get_physical_info 384get_pin_location 385get_power 454get_route_availability 386get_scale_delays 567get_scan_chain_info 487get_slack 568get_sleep_mode_options 456get_special_netpins 387get_steiner_capacitance 388get_steiner_channel_width 389get_steiner_length 390get_steiner_resistance 391get_tech_info 569get_time_borrow_limit 574get_timing 575get_top_timing_module 578get_weight_batch_option 323

Hhelp 143highlight 144

Iissue_message 145

Kkill_job 324



Llibcompile 579limit 146load_dcl_rule 580Low Power Options for Existing BuildGates

Commands 477

Qquit 148

Rread_adb 149read_alf 581read_ctlf 583read_dc_script 151read_def 392read_edif 153read_layer_usages 394read_lef 395read_lef_update 396read_library_update 584read_ola 586read_pdef 397read_scan_order_file 489read_sdf 587read_spef 593read_spf 591read_stamp 594read_symbol 154read_symbol_update 155read_tcf 458read_tlf 596read_verilog 156read_vhdl 158record_macro 161remove_assertions 598remove_host 325remove_job 326remove_placement_area 399remove_supply_rails_on_rows 400report_annotations 600report_area 162report_aware_library 164report_block_halo 401report_cell_instance_timing 602

report_clock_tree 299report_clock_tree_violations 305report_clocks 604report_design_rule_violations 165report_dft_assertions 490report_dft_registers 491report_fanin 167report_fanout 169report_floorplan_parameters 402report_fsm 171report_functional_mode 174, 608report_globals 174report_hierarchy 176report_job 327report_library 609report_net 611report_path_exceptions 615report_placement_area 404report_port 617report_power 461report_preroute_parameters 405report_resources 178report_supply_rails_on_rows 406report_tc_stats 464report_timing 622reset_clock_gating_check 636reset_clock_root 638reset_clock_tree_constraints 307reset_constant_for_timing 639reset_dft_compatible_clock_domain 493reset_dft_internal_clock_domain 494reset_dft_transparent 495reset_disable_cell_timing 640reset_disable_timing 641reset_dist_bits 328reset_dist_point 329reset_dist_weight 330reset_dont_modify 180reset_dont_move 407reset_dont_scan 496reset_dont_touch_scan 497reset_external_delay 643reset_failsafe 181reset_functional_mode 645reset_global 182reset_input_delay 646reset_must_scan 498reset_scan_data 499reset_tech_info 648reset_test_mode_setup 500reset_time_borrow_limit 653



reset_wire_load 654reset_wire_load_selection_table 655

Sset_attribute 185set_aware_component_property 189set_aware_library 190set_begin_tag 656set_block_halo 408set_cell_property 191set_clock 657set_clock_arrival_time 660set_clock_gating_check 661set_clock_gating_options 467set_clock_info_change 664set_clock_insertion_delay 668set_clock_propagation 672set_clock_required_time 674set_clock_root 676set_clock_tree_constraints 284set_clock_uncertainty 678set_constant_for_timing 682set_current_instance 192set_current_module 193set_cycle_addition 683set_data_arrival_time 689set_data_required_time 690set_dcl_calculation_mode 692set_dcl_functional_mode 693set_dcl_level 694set_default_slew_time 695set_dft_compatible_clock_domain 501set_dft_internal_clock_domain 503set_dft_transparent 505set_disable_cell_timing 696set_disable_timing 697set_dist_bits 331set_dist_point 332set_dist_weight 338set_dont_modify 194set_dont_move 409set_dont_scan 506set_dont_touch_scan 507set_drive_cell 699set_drive_resistance 703set_external_delay 705set_failsafe 197set_false_path 708set_fanout_load 713

set_fanout_load_limit 714set_floorplan_parameters 410set_functional_mode 715set_global 198set_host_config 334set_host_list 337set_input_delay 716set_layer_usages_table 413set_lef_multiplier 415set_library_layer_offset 417set_library_layer_usage 420set_library_layers_cap_multiplier 418set_library_layers_res_multiplier 419set_logic_0_net 422set_logic_1_net 423set_logic0 262set_logic1 263set_lssd_aux_clock 508set_lssd_scan_clock_a 509set_lssd_scan_clock_b 510set_max_delay 718set_max_scan_chain_length 511set_message_count 264set_message_verbosity 265set_min_delay 719set_min_porosity_for_over_block_routing

424set_min_wire_length 425set_must_scan 512set_net_physical_attribute 426set_num_external_sinks 720set_num_external_sources 721set_number_of_scan_chains 514set_operating_condition 722set_operating_parameter 724set_path_delay_constraint 726set_physical_instance 429set_pin_location 430set_port_capacitance 730set_port_capacitance_limit 732set_port_property 266set_port_wire_load 734set_power_stripe_spec 432set_preroute_parameters 434set_route_availability 436set_scale_delays 735set_scan_data 515set_scan_mode 518set_scan_style 520set_sleep_mode_options 475set_slew_limit 737



set_slew_time 738set_slew_time_limit 740set_special_netpin 437set_steiner_channel_width 438set_steiner_mode 439set_supply_rails_on_rows 441set_table_style 269set_tech_info 741set_test_mode_setup 522set_time_borrow_limit 747set_top_timing_module 749set_unconnected 272set_vhdl_library 273set_weight_batch_option 339set_wire_capacitance 750set_wire_load 752set_wire_load_mode 755set_wire_load_selection_table 756set_wire_resistance 757

Uunalias 275unload_dcl_rule 758

Wwrite_adb 276write_assertions 759write_atpg_info 524write_constraints 761write_def 443write_edif 278write_gcf_assertions 763write_layer_usages 445write_library_assertions 765write_pdef 446write_rspf 766write_scan_order_file 525write_sdf 767write_spf 773write_verilog 279write_vhdl 281




Documents

Product Version 4.0.8 May 2001 - ece.virginia.edumrs8n/soc/SynthesisTutorials/syncomref.pdfCommand Reference for Ambit® BuildGates® Synthesis and Cadence® PKS Product Version 4.0.8