Prof.Manoj Kavedia ( 9860174297 ) ([email protected]) 4 ...kavediasir.yolasite.com/resources/UNIT-4-FYBSCIT.pdf · 4.7 Study of IC 7474 and 7475. 4.8 Applications of flip flops

Prof.Manoj Kavedia ( 9860174297 ) ([email protected])

` Sequential Logic CircuitChapter-4(Hours : Marks: )(12069 – Principle of Digital Electronics)SEQUENTIAL LOGIC CIRCUIT4.1 Introduction to Sequential Logic Circuit – Difference between combinational and sequential circuit.4.2 Triggering methods (edge & level Trigger).4.3 One bit memory cell - RS latch – using NAND & NOR.4.4 Flip Flops - S R Flip flop, Clocked SR flip flop with preset and clear, Drawbacks of SR Flip flop, Clocked JK Flip flop with preset & clear, Race around condition in JK flip flop, Master slave JK flip flop.4.5 D and T flip flop.4.6 Excitation table of flip flops.4.7 Study of IC 7474 and 7475.4.8 Applications of flip flops - Asynchronous counter: up/down, decade, 3 bit synchronous counter design, ring counter, twisted ring counter with wave forms, 4 bit shift register (SISO, SIPO, PISO, PIPO) with waveforms, Study of IC 7490 (mod – 6, mod – 20).

Q1. What is Sequential Circuit ?Explain with the help of block diagram

Ans.There are many applications in which digital output are required to be generated in accordance with which the input signal are received. These requirements are not fulfilled by combination logic system. These applications require output to be generated that are not only dependent on the present output to be generated, but they are also dependent on the on the history of these inputs. The past history is provided by feedback from the output back to the input.

Figure shows block diagram of sequential logic circuit

4

Combinational Circuit

Memory Element

External Input

Output from Combinational

Circuit

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A sequential circuit consists of combinational circuit, which accepts digital signal from external input and from output of memory elements and generates signals from external outputs and for inputs to memory elements.

A memory is a same medium in which one bit of information can be or retained until necessary and thereafter it contents can be replaced by new value. The contents of the memory elements can be changed by the output of combinational circuit, which are connected to its input.

Hence output of sequential circuit is dependent on external input and present content of memory element. The new content of memory element is referred to as NEXT STATE. Hence the output of a sequential circuit is function of the time sequence of input and the internal states.

Q2. List different types of Sequential CircuitsAns.Sequential circuits are classified in two main categories known as

1) Asynchronous sequential circuit2) Synchronous sequential circuit

Asynchronous Sequential CircuitA sequential circuit whose behavior depends upon the sequence of

which input signal change is referred to as Asynchronous Sequential Circuits. Such circuits are generally used to provide time delays in memory elements. They operate without a common clock.

Synchronous Sequential CircuitA sequential circuit whose behavior can be defined from knowledge

of its signal at discrete instant of time is referred to as Synchronous Circuits. In these systems the memory elements are affected only at discrete instant of time. The synchronization is achieved is affected by timing device known a SYSTEM CLOCK. They require the common clock.

The memory elements used are flip-flop, which are capable of storing binary information.

Q3. Define FlipFlop?Ans.A basic digital memory is known as flip-flop (FF). It has two stables, which are known as logic 1 state and logic 0 state. These devices remain in one of these states until triggered into the other state. The flip-flop is a basic element of a sequential logic system. Using flip-flop and combinational logic circuit any sequential circuit can be designed.

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Any device or circuit that has two stable states is said to be bistable for instance, a toggle switch has two states i.e. open or closed.

A flip-flop is basically a bistable multi-vibrator type circuit other name of this circuits are trigger circuit, two toggle circuit, one bit storage cell or latch. The different names of flip-flop are RS, clocked RS , J-K , J-K (master-slave), D-type flip-flop & T-type flip-flop.

Q4. Describe RS Flip Flop using NOR gate , List is truth tableAns.RS flip flop

Figures : RS FlipFLop with NOR Gate.

In figure output of one NOR gates drives one of the input of the other NOR gate. The S and R inputs are used to set and reset the flip flop respectively.Note : For the NOR gate , if any input of the NOR gate is ‘1’ its output will be 0 irrespective of other inputs.

Operation of RS FlipFLopCase 1: When R = 0 and S = 0 and Q = 0 , Q=1

When S = 0, R = 0 and Q=0 , Q=1 a ‘0’ comes out from the upper NOR gate corresponding to Q = 0.

Now the lower NOR gate has both input ‘0’ and hence a ‘1’ comes out from the lower NOR gate corresponding to Q = 1.Hence when R= 0 , S =0 Flip Flop remain in last state or No change State

Case 2: When R = 0 and S = 1 and Q = 0 , Q=1

R

S

Q

Q

Inputs Outputs R S Q Status 0 0 Last State No Change 1 0 0 Reset0 1 1 Set1 1 Forbidden Race

3


When S = 1, R = 0 and Q=0 , Q=1 a ‘0’ comes out from the upper NOR gate corresponding to Q = 0.

Now the lower NOR gate has one input ‘0’ and other input as 1(Q=0 , S=1) ,hence a ‘0’ comes out from the lower NOR gate corresponding to Q = 0.

This Q = 0 is fed as input to upper NOR gate making R =0 and Q = 0 , this time a “1” come upper NOR gate.

Now the lower NOR gate has both input as 1(Q=1 , S=1) ,hence a ‘0’ comes out from the lower NOR gate corresponding to Q = 0.

This process repeats till the output is fixed or settled .Hence at the end when R= 0 , S =0 Flip Flop out Q =1 and Q=0.

Hence when R= 0 , S =1 Flip Flop goes in Set state

Case 3: When R = 1 and S = 0 and Q = 1 , Q=0When S = 0, R = 1 and Q=1, Q=0

a ‘0’ comes out from the upper NOR gate corresponding to Q = 0.

Now the lower NOR gate has both input as ‘0’ (Q=0 , S=0) ,hence a ‘1’ comes out from the lower NOR gate corresponding to Q = 1.

This Q = 1 is fed as input to upper NOR gate making R =1 and Q = 1 , this time a “0” come upper NOR gate.

Now the lower NOR gate has both input as 0(Q=0 , S=0) ,hence a ‘1’ comes out from the lower NOR gate corresponding to Q = 1.

This process repeats till the output is fixed or settled .Hence at the end when R=1 , S =0 Flip Flop out Q =0 and Q=1.

Hence when R=1 , S =0 Flip Flop goes in Reset state

Case 4: When R = 1 and S = 0 and Q = 1 , Q=0If S = 1 and R = 1 a ‘0’ comes

out of both NOR gates giving Q = Q = 1. This is condition is forbidden.

Figure shows the timing diagram. The Q output goes high

4


when S goes low Q returns to low when R goes high and stays low after R return to low.

5


Timing diagram for RS Flip-Flop.

Q5. Describe RS Flip Flop using NAND Gate , Draw its symbol and TruthTable

Reset

Set

Q

6


Ans.RS Flip Flop using NAND gate

Truth Table SR Flip-Flop using NAND GateIn figure output of one NAND gates drives one of the input of the

other NAND gate. The S and R inputs are used to set and reset the flip flop respectively.Note : For the NAND gate , if any input of the NAND gate is ‘0’ its output will be 1 irrespective of other inputs.

Case 1 : S=0 , R =0 Q =0 , Q=1 ( Race Condition )When S = 1, R = 1 and Q=0 , Q=1

a ‘1’ comes out from the upper NAND gate corresponding to Q = 1.

Now the lower NAND gate has one input ‘0’ and Other input as 1 and hence a ‘1’ comes out from the lower NAND gate corresponding to Q = 1.Hence when R=0 , S =0 Flip Flop both outputs try to become one , this undefined or illegal or Forbidden

state. This condition is called as RACE condition.

Case 1 : S=0 , R =1 Q =0 , Q=1 ( SET Condition )When S = 0, R = 1 and Q=0 , Q=1

a ‘1’ comes out from the upper NAND gate corresponding to Q = 1.

Now the lower NAND gate has both input ‘1’ ,hence a ‘0’ comes out from the lower NAND gate corresponding to Q = 0.This state remains as its , Hence when R=1 , S = 0 Flip Flop , output Q = 1 and Q = 0 , and the state is called as Set State

Case 2 : S=1 , R =0 Q =1 , Q=0 ( RESET Condition )

Q

Q

S

R

Inputs Outputs R S Q Status 1 1 Last State No Change 0 1 0 Reset1 0 1 Set0 0 Forbidden Race

R

S

S

R

7


When S = 1, R = 0 and Q=1 , Q=0 a ‘1’ comes out from the upper NAND gate corresponding to Q = 1.

Now the lower NAND gate has both input ‘1’ ,hence a ‘0’ comes out from the lower NAND gate corresponding to Q = 1.This 1 is fed as input to upper gate , now this time upper NAND gate both input as 1 , due to which output is 0.

Now this output is fed as input to lower NAND gate, whose both input are 0 , making output 1.This state remains as its , Hence when R=0 , S=1 Flip Flop , output Q = 0 and Q = 1, and the state is called as Reset State

Case 4: When R = 1 and S = 1 and Q = 1 , Q = 0When S = 1, R = 1 and Q=1 ,

Q=0 a ‘1’ comes out from the upper NAND gate corresponding to Q = 1.

Now the lower NAND gate has both input ‘1’ and hence a ‘0’ comes out from the lower NAND gate corresponding to Q = 0.Hence when R= 0 , S =0 Flip Flop remain in last state or No change State

Note : The Basic NAND gate circuit operation is opposite to that of the NOR gate circuit i.e it needs the input active low for the operation. Hence to have the operation with active high input the R and S input are passed through the NOT gate. The truth table and Circuit is as shown in the figure.

Q6. What is triggering and Describe its different typeAns. In the latches and flip-flops, we use the additional signal called clock signal.

Depending on which portion of the clock signal the latch or flip-flop responds to, we can classier them into two types

1. Level triggered circuits

S

R

S

R

1

8


2. Edge triggered circuits

Concept of Level TriggeringThe latch or flip-flop circuits which respond to their inputs, only if

their enable input (E or ClK) held at an active HIGH or LOW level are called as level triggered latches or flip-flops.

Fig. shows the symbol of a level triggered SR flip flop and Fig. shows the clock signal applied at its inputTypes of Level Triggered Flip-flops

There are two types of level triggered flip-flops:Positive level triggered.Negative level triggered.

Positive Level Triggered FF if the outputs of SR flip-flop respond to the input changes, for its

clock input at HIGH (1), level then it is called as the positive level triggered S- R flip-flop. The circuit shown in Fig. is a positive level triggered S-RFF.

Negative level triggered FFif the outputs of an SR flip-flop respond to the input changes, for its

clock input at LOW (0) level, then it is called as the negative level triggered S - R flip-flop.

Concept of Edge TriggeringThe flipflops which change their outputs only corresponding to the positive or negative edge of the clock input are called as edge triggered flipflops.

These flip-flops are therefore said to be edge sensitive or edge triggered rather than being level triggered.

The rectangular signal applied to the clock input of a flip-flop is shown in Fig. If the same signal is applied as the clock signal to the flip flop, then its outputs will change only at either rising (positive) edge or at the falling (negative) edge of the clock.

There are two types of edge triggered flip flops

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Positive edge triggered flip flops.Negative edge triggered flip flops.Positive edge triggered flip flops will allow its outputs to change only

at the instant corresponding to the rising edges of clock (or positive spikes). Its outputs will not respond to change in inputs at any other instant of time.

Negative edge triggered flip flops will respond only to the negative going edges (or spikes) of the clock.

Q7. Describe the operation of Clocked RS flip-flop with NAND gate, Draw its circuit diagram and List its truth table

Figure Clocked RS Flip-FlopIt is often required to set or reset the memory cell in synchronism

with a train of the pulse known as Clock. Such circuit is referred to as clocked SR (set-reset flip-flop)

The clock is a square wave signal because the clock drives both NAND and prevents S and R from controlling the latch.

Operation is as Follows Case 1 : S =1 , R=0 (Set Condition) If S = 1 and R = 0 the output of gate A = 0 and B = 1. Now with clock

= 1, S = 0, R = 1 and flip-flop set Q = 1 and Q= 0. I.e Set Condition

Case 2 : S =0 , R=1 (Reset Condition) If S = 0 and R = 1 the output of gate A = 1 and B = 0. Thus with clock

= 1, S = 1, R = 0 and flip-flop set Q = 0 and Q = 1. I.e Reset Condition

Q

QR

S Inputs Outputs R S Q Status 0 0 Last State No Change 1 0 0 Reset0 1 1 Set1 1 Forbidden RaceX X Last State No Change

Clock

11110

Clock

10


Case 3 : S =1 , R=1 (Illegal/Forbidden Condition) With S = 1 and R = 1 the output of both gates will be 0 it is a

forbidden condition state or a race condition. I.e Illegal Condition or Forbidden State

Case 4 : S =0 , R=0 (Last State Condition) When both S = 0, R = 0 and clock = 1 the output A & B gate = 1 which

keep the flip-flop in last state. I.e Last State

The above circuits are activated by high level of square wave i.e. why they are called as level triggered flip-flop.

Timing diagram

Timing Diagram of Clocked RS Flip Flop

Q8. Draw the Logical Symbol for RS FlipFlop and Write its truth table

Ans.

Clock

S

R

Q

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Logical Symbol

Truth Table

Q9. Describe the operation of RS flip-flop With Preset and Clear , with its symbol and truth table

Ans.When power is switched ON the state of flip-flop is uncertain i.e. it may be in either set or reset state. In many applications it is necessary to set or reset the flip-flop initially i.e. initial state is to be assigned. This is accomplished by using direct or Asynchronous inputs referred to as preset (Pr) and clear (Cr) input. These inputs may be activated at any instant of time and are not used in Synchronism with clock.

Q

Q

S

R

PR

CR

Clock

PR

CR

S Q

Clk

R Q

Forbidden / Illegal Race Condition

12


PR and CR are Active low inputs. To make preset or clear Inactive they are connected to Logic 1.

Preset & Clear When PR = 0, CR = 1 then the NAND output of C (Q) will be 1 i.e. set

the flip-flop ∴Pr = 1 Preset the flip-flop. When PR = 1, CR = 0 then the output of NAND gate C (Q) will be 0 i.e.

Y = 0 i.e. reset the flip-flop. Therefore Cr = 1 Reset the flip-flop. When Pr = 0, Cr = 0 not to be used since it lead to uncertain state. During normal operation Pr = Cr = 1 i.e. should be connected to logic

1.In logic symbol bubbles are used for Pr and Cr input which means

these are active low i.e. the intended function is performed when the signal for Pr and Cr is low.

The operation of above circuit is summarized in form of truth table as shown

Input Inputs OutputClock S R PR CR Q Status

0 X X X X Last State No Change0 X X 0 0 For Bidden Race0 X X 0 1 1 Preset0 X X 1 0 0 Clear0 X X 1 1 Last State No Change1 0 0 1 1 Last State No Change1 0 1 1 1 0 Reset1 1 0 1 1 1 Set1 1 1 1 1 For Bidden Race

Figure : Truth Table

Q10. State disadvantages of SR Flip Flop , how it is avoidedAns.Disadvantages of SR – flip-flop1. Main disadvantage of SR flip-flop is that when R = 1, S = 1 this state

is called as forbidden or illegal state which must be avoided. This is done by modifying SR flip-flop into JK flip-flop.

2. In JK flip-flop the outputs Q & Q are cross-coupled back at the input through a And gate. Cross-coupled means Q is connected to S input and Q is connected to R input with a clock such that

S = Q.J.clk R = Q.R.clk.

13


Q11. Describe the operation of JK flip-flop With Preset and Clear , with its symbol and truth table

Ans. JK – Flip-Flop: (Edge triggered)

Diagram JK FLIP FLOP Truth Table

JK flip-flop is improvement over RS flip-flop in which forbidden condition is defined, figure shows JK flip flop using RS flip flop. J & K are called control inputs.♦ When J = 0, K = 0 irrespective of the clock pulse both the AND gate

are disabled resulting S = 0, R = 0. Therefore output Q-remains in the last state.

♦ If J = 1, K = 0 the lower AND gate is disabled, i.e. S =1, R = 0 which sets the flip-flop as soon as clock edge comes since upper AND gate is enabled.

♦ If J = 0, K = 1 the upper AND gate is disable, hence it is impossible to set the flip-flop , but the flip-flop can be Reset provided if it is not already in Reset condition i.e. if Q = 1, the lower AND gate produce a reset trigger as soon as clock edge comes therefore output will reset to '0'

♦ If J = 1, K = 1 it is possible to set or reset the flip-flop if Q = 0 in last state Q will be 1 and the upper AND gate produce a set trigger to force Q = 1. On the other hand if Q = 1 in the last state the lower AND gate produce a reset trigger to force Q = 0. In either way Q always changes in opposite state. This is known as toggling meaning switching to opposite state.

J

K

PR

CR

S Q

R Q

Inputs Outputs J K Q Status 0 0 Last State No Change 1 0 0 Reset0 1 1 Set1 1 Last State ToggleX X Last State No Change

Clock

11110

14


Q12. Describe the operation of JK flip-flop With Preset and Clear using NAND gate, with its symbol and truth table

Ans.JK – flip-flop using NAND gate

Figure one way to build JK flip-flop. In this flip-flop the output of flip-flop Q & Q are cross-coupled to input by means of AND gate.

The flip-flop is triggered with +ve level clock i.e. clock should go high & remain high for some time.

Fig shows JK Flip-Flop Timing DiagramOperation :1. Reset condition: (J = 0, K = 1): When J = 0, K = 1, Q = 1 & Ǭ = 0,

the lower NAND gate passes a reset trigger as soon as clock becomes +ve. This forces Q to become ‘O’ and Ǭ = ‘1’. Hence J = 0 & K = 1 means reset the flip-flop on +ve edge clock

2. Set condition: (J = 1, K = 0)When J = 1 and K = 0 and Q = 0 and Ǭ = 1 the upper Nand gate

passes a set trigger as soon as the +ve clock arrives. This forces Q to high and Ǭ to low. Hence J =1, K = 0 means that on +ve clock it will flip-flop.

J Q

Clk

K Q

PR

CR

J Q

Clk

K Q

PR

CR-ve edge triggered JK FlipFlopwith inverted PR and CR

+ve edge triggeredJK flipflop with PR and CR

CR

J

K

PR

Q

Q

CLock

K

Q

J

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3. Inactive (J = 0, K = 0)The J = K = low the circuit is inactive in state including +ve clock

and the flip-flop remains in last or previous state.

4. Toggle (J =1, K = 1)When J = 1, K = 1 it is possible to set or reset the flip-flop depending on the current state of the output Q & Q.If Q = 1 and Q = 0, the lower NAND gate passes a reset trigger on

the next +ve clock.If Q = 0 and Q = 1, the upper NAND gate passes a reset trigger on

the next +ve clock.In either way Q changes to the complement of last state. Therefore

J = 1and K = 1 means that flip-flop will toggle on next +ve pulse.

Operational truth table

Data Input Outputs Inputs OutputsJ K Last Qn State Ǭn S R Ǭn + 1 Final

0 0 0 1 0 0 0 = Ǭn Last state0 0 1 0 0 0 11 0 0 1 1 0 1 = 1 Set1 0 1 0 0 0 10 1 0 1 0 0 0 = 0 Reset0 1 1 0 0 1 01 1 0 1 1 1 0 = Ǭn toggle1 1 1 0 0 0 1

The difficulty of both Input R = S = 1 which was not allowed in SR flip-flop 1’s eliminated in JK flip flop by using feedback connections.Truth table of JK FlipFlop

Input OutputClock J K Q Status

0 X X Last State No Change1 0 0 Last State No Change1 0 1 0 Reset1 1 0 1 Set1 1 1 Toggle Toggle

Q13. What is Racing and Race Around Condition in Flip Flop

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Ans.In RS flip flop the input condition R=S=1 is not allowed as it leads to a state Q=Q=1 i.e. the output oscillates between these two states. In real the circuit ,one of the two gates will operate slightly faster than the other and the circuit will not oscillate but will go in of the two state i.e 0 or 1 , but exact state cannot be predicted. In this case the circuit action is intermediate and a race condition is said to be exist.

Figure shows clock is applied to JK Flip-Flop When input J=K=1 and when after a time interval of ∆t (the delay through two NAND gates in series) the output will change to Q = 1, after time interval of ∆t the output will again change back to zero (0). And hence at the end of clock pulse the value of Q is uncertain. This situation is called as Race around Condition.

Race arround conditions means toggling more than once on the same clock edge.

This condition can be avoided if tp < ∆t < T. This can be done:

1. Use RC differentiator circuit. In which output changes when +ve edge has struck. By the time the new Q & Q signal return to the Input gate the +ve delays to 0 and hence we get once toggling in one clock pulse.

2. Other method is to increase the propagation delay time of the flip-flop; this will take some time for the outputs to change after the clock edge has arrived and therefore returning Q and Q arrive too late to cause false triggering but this technique decrease the speed of operation.

3. Yet another way to avoid is to make use of Master Slave JK-flip-flop.

Q14. Describe the operation of JK-MS flip-flop, with its symbol and truth table

Ans.Master-Slave JK Flip-Flop The more convenient way to avoid Racing (Race around condition) to

make use of Master Slave JK flip-flop, one is called Master and other is called as Slave. Here the Master is +ve edge triggered and slave is –ve edge triggered JK flip-flop. The output Q and Q of master flip flop drivers the J & K Input of the slave flip flop.

T

∆t Leading Edge

Trailing Edge

17


Since Master is +ve edge triggered it responds to J & K inputs before slave.

Operation

Case 1 : If J = 1 & K = 0 Master set on +ve edge of clock while slave sets on –ve edge of the clock.

Case 2 : If J = 0 & K = 1 Master reset on +ve edge of clock while slave reset on –ve edge of the clock.Case 3 : If J = 1 & K = 1 Master toggles on +ve edge of clock while slave toggles on –ve edge of the clock.

Thus whatever the action of master is on the +ve clock edge will be copied by the slave on the –ve clock edge. Hence the name master slave (MS) JK flip flop.

Since J & K Inputs are taken from slave flip flop there will be no question of toggling more than once on the same clock edge. Hence Racing is avoided.

Clk J K Q Operation

J

K

Clock

Q

Q

J Q

Clk

K Q

PR

CR

J Q

Clk

K Q

PR

CR

J Q

Clk

K Q

Inputs Outputs J K Q 0 0 Last State 1 0 1 0 1 0 1 1 Last State X X Last State

Clock

11110

Toggle

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X 0 0 Last State Last State0 1 0 Reset1 0 1 Set1 1 Toggle Toggle.

Q15. Draw the waveform JK MS FlipFlopAns.

Q16. Describe the operation of Toggle(T) flip-flop , with its symbol and truth table

Ans. Toggle flip-flop (T-flip flop)Toggle flip flop is similar to JK flip flop but with J & K inputs

connected together and a common input T. whenever T = 1 (J = 1, K = 1). The flip-flop will toggle hence the name toggle flip-flop.

If T = 0 (J = 0, K = 0). The output will remain in the last state.If T = 1 then the output will toggle.

Truth Table :

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Clock Input(T) Output(Qn + 1) Status1 Ǭn Toggle0 Qn Last State

0 X Qn Last State

Q17. List

Application of Flip-FlopAns.Some of the common uses of flip-flop are

1) Bounce elimination switch2) Latch3) Registers4) Counters5) Memory etc.

Q18. Describe operation of Delay (D) flipflop with its circuit diagram and Truth table

Ans. D or Delay flip-flop

T Q

Clk

Q

CR

J Q

Clk

K Q

CR

T

K

PR

CR

S Q

R Q

JT

PR

T FlipFlop Using SR F/F

T F/F Using JK FlipFlop Symbol

Clk

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The RS flip flop has two data inputs S & R generating two signals to drive a flip-flop is disadvantageous. Again there is possibility of R & S being 1 resulting in forbidden condition of the flip-flop.

This results in design of D-flip flop, which requires a single data Input D to drive the flip-flop. Figure shows D-flip flop using RS flip flop. This is design by connecting S to R Input through Inverter. And Input is labeled as D.

This kind of flip flop prevents the value of D from reaching the Q-output until a clock pulse occurs hence it is called as Delay flip-flop.

OperationWhen clock = 0 irrespective of value of D-both AND gate are

disabled resulting S=0, R = 0 under this condition Y will remain in the Last State.

When clock is 1, D = 1, the upper AND gate is enabled whereas the lower AND gate is disabled due to Inverter. This results in S = 1, R = 0, therefore Y =1 i.e. the value of Y follows the value of D in presence of clock.

When clock = 1 D = 0, the upper AND gate is disabled whereas the lower AND gate is enabled due to Inverter. This results in S = 0, R = 1,

D Q

Clk

Q

CR

PR

Symbol

Clock input Output D Y 1 0 0 1 1 1 0 X Last State

Truth Table

PR

CR

S Q

R Q

D

D FlipFlop Using SR F/F

J Q

Clk

K Q

PR

CR

D

D FlipFlop Using JK F/F

Clk

Clk

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therefore Y =0 i.e. the value of Y follows the value of D in presence of clock.

D-flip flop if also known as D-latch this is because whenever clock pulse is removed the output Y will Latch ON to its Last State. The D-Latch is used to store the binary number.

Timing diagram: (for –value edge trigger)

D-flip-flop using JK flip flop : figure is shown above along with D type using SR Flipflop

Q19. List and Describe Important Flip-Flop Timing related to flipflop

Ans.The circuit components are not ideal components. Components like diode, transistor etc require some finite amount of time for switching from one state to another i.e. ON to OFF and OFF to ON. This is because of different types of capacitance associated with component for e.g. function capacitance.

Generally the switching time is very small in terms of micro and nano second but input has more effect on operation of device at high frequency applications. The different delays associated with flip-flop are:

1. Propagation delay time (tp)2. Setup time (ts)3. Hold time (th)

Propagation Delay Time (tp)

Clock

D

Q

22


Propagation delay time (tp) is the amount of time it takes for output of gate or flip-flop to change its state after input has changed.For Example: if tp = 50 nsec then i.e. it will take 50 nsec to change output to new state after input has changed.

Setup Time (ts)The time (ts) required for the input data to settle before the clock

arrives. For Example : If ts = 10 msec than input data must because present at least 10 msec ahead of clock pulse otherwise there is possibility of getting wrong output.

Hold Time (th)It is the time for which the data must because present stable after

clock pulse arrives.

For Example: If th = 5 msec then data must because present upto 5 msec after clock pulse has arrived.

Q20.What is excitation table? Write the excitation table for SR flipflop?Ans. The truth table of a FLIP—FLOP is also referred to as the characteristic table and specifies the operational characteristic of the FLIP—FLOP.

In the design of sequential circuits, we usually come across situations in which the present state and the next state of the circuit are specified, and we have to find the input conditions that must prevail to cause the desired transition of the state. By the present state and the next state we mean the state of the circuit prior to and after the clock pulse respectively.

The excitation table tells the designer the minimum inputs that are necessary to generate a particular next state when the current state is known.

Excitation Table SR FlipFlop

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For example the outputs of an S-R FF before clock pulse are Qn = 0 and Qn+1 and it is expected that these outputs should remain unchanged after application of clock. Then what must be the values of inputs S and R to achieve this?Refer to the truth table of SR FF to answer this questionThe answer is, for the following two conditions the outputs remain unchanged at Q= 0 and Q=1Condition 1:Sn and Rn= 0 Refer first row of Table.Condition 2: Sn =0 Rn = 1 Refer third row of Table

From the two conditions mentioned above we conclude that Sn input should be equal to 0 and Rn input can be 0 or 1 (don’t care) in order to achieve our objective of maintaining Q=0 and Q =1 before and after clock.Similarly we can find the input conditions for aft the possible situations that may exist on the output side.

The table containing all these output situations arid the corresponding input conditions is called as the “excitation table” of a flip flop.The excitation table of SR flip flop is s in Table.

Description of excitation table of SR FF:Case 1 : already discussed case 1. Case II: Q should change from 0 to 1

This is set condition.Therefore Sn=l and Rn=0 should be he input

Case III: Q should change from 1 to 0This is reset condition.Therefore Sn should be 0 and Rn should be 1

24


Case IV :Q should be 1. No changeFor this requirement there are two possible input condition

Condition 1 : Sn = Rn = 0 ie No change in outputCondition 2 : Sn = 1 and Rn = 0

From these condition we conclude that Sn can be either 0 or 1 ie don’t care and Rn = 0. Hence the input corresponding to this

Sn = X Rn = 0

Q21.Write Excitation table for JK FF , SR FF , D FF, T FFAnsExcitation Table for SR FlipFlop

Excitation Table for JK FlipFlop

Excitation Table for T FlipFlop Excitation Table for D FlipFlop

25


Q22.Describe the IC 7474 Dual D type positive edge triggered flipflop with preset and clearAns.

Pin

Diagram

Truth TableFunctional Diagram

Logical Diagram

Counter

26


Q23. What is counter ? List different types of Counter ? Describe each of them?Ans.A sequential circuit that goes through a prescribed sequence of state upon the application of input clock pulses is called as counter. It is circuit used for counting the pulses is known as counter. Number of state through which counter progresses is called as Modulus of Counter ie MOD of counter.

For any digital system especially for computer, counter are most useful and versatile subsystem. A counter is driven by a clock can be used to count the number of clock cycles. Since the clock pulses occurs at known intervals the counter can be used as an instrument for measuring time and therefore period or frequency.

In a counter the sequence of state may be binary or BCD or any other count. Counters are found in almost all equipment containing digital logic. The counters are classified as

1) Asynchronous or serial or ripple counter2) Synchronous or parallel counter.3) Combination counter.

Basic components used in counter is flip-flop.

1) Asynchronous or ripple or serial counterThese counter are very simple in hardware as well as in operation. It is

an series combination of flip-flop, where the output of 1st flip-flop is connected as clock input of 2nd flipflop, the output of 2nd is connected as the clock input of 3rd and so on, it is called a binary counter , or series counter or ripple counter. Since in the counter in which the output of one flip-flop drives the clock input of another counter are called ripple counter or asynchronous counter.

But these counters have disadvantage of speed limitation because here each flip-flop is triggered by previous flip-flop and the total propagation delay time becomes equal to the sum of the individual propagation delay thereby decreasing the speed of operation.

2) Synchronous or parallel counterIn these counter the transition are simultaneous i.e. all the flip-flop

change their output simultaneously. This is achieved by connecting all the flip-flop to same clock pulse simultaneously i.e. all the flip-flop are directly clocked by same clock. The increase in speed is usually obtained at the price of increased hardware i.e. hardware is increased.

3) Combinational Counter

27


Serial and parallel counters are used in combination to compromise between speed of operation and hardware count. Such counters are called as combinational counter.

Counters can be designed such that each clock pulses advances the content of the counter by one i.e. it is operating in a count up mode i.e. up counter. The opposite is also possible i.e. the counter operate in the count-down mode called as down counter. Many times counter may be cleared or preset so that every flip-flop contains zero’s or one’s or can be preset to required binary numbers.

Q.24.Describe the operation of 4 bit Asynchronous counter with help of circuit diagramQ.25.Describe the operation of 4 bit Serial counter with help of circuit diagramQ.26.Describe the operation of 4 bit Ripple counter with help of circuit diagram

28


Ans. 4-bit binary asynchronous or serial or ripple counter

Fig. Shows a 4bit binary asynchronous counter.

It uses four negative edge triggered JK flip-flop. All the flip-flop will operate in the toggle mode because there J and K input are tied to Vcc. The clock pulse are applied to the flip-flop A. The output of flip-flop A drives clock input of flip-flop B, the output of flip-flop B drives clock input of flip-flop C and the output of flip-flop C drives clock input of flip-flop D. Since all flip-flop are negative edge triggered flip-flop they require a transition of 1 to 0 at their clock input to toggle or change the state.

Clock D C B A Count0(Intially) 0 0 0 0 1

1 0 0 0 1 22 0 0 1 0 33 0 0 1 1 44 0 1 0 0 55 0 1 0 1 66 0 1 1 0 77 0 1 1 1 88 1 0 0 0 99 1 0 0 1 1010 1 0 1 0 1111 1 0 1 1 1212 1 1 0 0 1313 1 1 0 1 1414 1 1 1 0 1515 1 1 1 1 16

J A

K A

J B

K B

J C

K C

J D

K D

Logic 1

Logic 1

Clock

29


16 0 0 0 0 17(0)

Truth Table for 4 bit Aysnchronous Counter

Timing diagramOperation of Counter

Initially all the flip-flop are cleared by using a common low clear signal. Therefore

DCBA = 0000On the first clock pulse A flip-flop will toggle from 0 to 1 this will

not trigger B flip-flop because it requires a change in 1 to 0 in A. Therefore B remain in last state and since B does change its state also C and D remain in last state. Hence on the first clock pulse we get output as,

DCBA = 0001On the second clock pulse A flip-flop again toggles from 1 to 0. This now triggers B flip-flop, Now B FlipFlop toggles from 0 to 1. This will not affect C flip-flop because C flip-flop requires a change of 1 to 0 in B flip-flop. Therefore C remains 0 and so is D flip-flop. Hence on 2nd clock pulse we get

DCBA = 0010.On the 3rd clock pulse A flip-flop changes from 0 to 1, B flip-flop remains at 1 and C and D flip-flop remain at 0 therefore,

DCBA = 0011.On 4th clock pulse A flip-flop changes from 1 to 0 therefore B flip-flop now changes from 1 to 0. Now C flip-flop is triggered which will change from 0 to 1 but this will not effect D because it requires a change from 1 to 0 in C flip-flop. Hence D remains 0. Therefore or 4th clock pulse we get,

DCBA = 0100.

30


Thus it is observed that A flip-flop toggles with every clock pulse it receives. B flip-flop toggles whenever A flip-flop changes from 1 to 0.

C flip-flop toggles whenever B flip-flop changes from 1 to 0 and D flip-flop toggles whenever C changes from 1 to 0.

Hence on 15th clock pulse we get DCBA = 1111. On the next clock pulse A flip-flop changes from 1 to 0, B flip-flop change from 1 to 0. Therefore C flip-flop changes from 1 to 0. Hence D changes from 1 to 0, therefore all flip-flop are cleared again & we get,

DCBA = 0000Thus this counter can count from 0 to 15 i.e. totally 16 count (or

states). The number of discrete states through which the counter can progress on the application of pulse is given by 2n where n= number of flip-flop used into the counter. If we connect 5 flip-flop the counter will progress through 00000 to 11111 i.e. 32 counts (0 to 31).

Q.27what is MOD N counter?Ans.In a binary ripple counter the number of counts or discrete state through which the counter can progress after application of clock pulses is called as modulus of counter. The number of discrete state is given by 2n where n is number of flip-flop used in counter.

Therefore we can easily design a counter which counts through 2,4,8,16,32 by using required number of flip-flop. But often counters other than module, 2,4,8,16,32 etc are required.

For example : Mod7, mod6, mod5 etc. These counters can be designed by nearest highest modulus counter by skipping some of the counts.

For example : Mod7 counter can be designed from mod8 counter by skipping one of the state. Similarly a mod6 counter can be designed from mod 8 counter by skipping two of the states.

Q.28.Describe operation of Mod 7 or divide by 7 counterAns.

J A

K A

J B

K B

J C

K CCBA

Logic 1

Clock

31


Fig : Mod-7 Counter

32


WaveForms :

Count 000 001 010 011 100 101 110 000

State 0 1 2 3 4 5 6 7(0)

Mod 7 counter can be constructed from nearest highest modulus counter i.e. mod8 but skipping 1 of state. Fig. Shows mod7 counter with some feedback to skip one of the state.

It is convenient to skip last state i.e. CBA=111 in natural count sequence of the counter. The arrangement is shown in fig.

Truth table

Clock C B A0 0 0 01 0 0 12 0 1 03 0 1 14 1 0 05 1 0 16 1 1 07 1(0) (0) 1(0)

Working During count 7 CBA= 111, if CBA are connected to NAND gate,

whenever 111 occurs at the input of NAND gate the output of NAND gate is low(0). If the output of NAND gate is connected to all clear inputs of all the flip-flop, as soon as CBA=111 occurs immediately all the flip-flop will

0 1 2 3 4 5 6 7CLK

A

B

C

Cr

33


clear. Therefore the counter progress from 110 to 000 and count 111 is skipped. Since remaining states are only 7 it is called as mod7 counter. fig. Shows the waveform for mod7 counter.

Q.29.How to design Different MOD counters.Ans.MOD 6 Counter

To design mod6 counter we require 3 flip-flop or mod8 counter which is nearest highest modulus. Hence a mod6 counter can be formed by tieing(connecting) input CBA to the NAND gate. When CBA=110 then output of NAND gate becomes how which clears all the flip-flops. Therefore counter progress from 101 directly 000 and here count 110 and 111 are skipped.

Mod 5

counter As mod7 and mod6 counter is designed mod5 can also be designed

using mod8 counter. In this design the inputs CBA are tied to NAND gate. In this counter progress from 100 to 000 because when CBA=100 the output of NAND gate is low thus clearing all flip-flop. In this counter states 101,110 and 111 are skipped.

Mod3

counter Mod3 counter is design by mod4 counter which utilizes 2 flip-flop.

In mod3 state 11 is skipped. This done by following gating circuitry.

CBA

TO All Clear input of the Flip Flop

CBA

TO All Clear input of the Flip Flop

J A

K A

J B

K B

AB

Logic 1

Clock

34


Truth tableCLK B A

0 0 01 0 12 1 0

3(0) 0 0

when BA=11 the NAND gate produce low output which clears flip-flop and counter from state 10 moves to state 00.

Q.30.Describe operation of MOD 8 Counter or Parallel CounterQ.31.Describe operation of 3Bit Synchronous Counter or Parallel Counter

Ans.3 bit binary synchronous or parallel counter:

TruthTable

J A

K A

J B

K B

YX

J C

K C

Logic 1

Logic 1

Clock

35


CLK C B A0 0 0 01 0 0 12 0 1 03 0 1 14 1 0 05 1 0 16 1 1 07 1 1 18 0 0 0

Timing Diagram

Count 000 001 010 011 100 101 110 111 000

State 0 1 2 3 4 5 6 7 8(0)

The speed limitation in the asynchronous counter is over come by using parallel counter. The difference here is that every flip-flop is triggered by clock. Fig. Shows mod8 counter.

As mod8 has natural count of 8 it requires 3 flip-flop. Again all JK flip-flop input are tied to Vcc and the A flip-flop will toggle with each negative transition of clock. The output AND gate X is high whenever clock is high and A is high. Therefore B does not change its state. B changes state with every other clock i.e. when output of X AND gate changes from 1 to 0.

Similarly output AND gate Y goes high when clock is high and A and B are high, therefore flip-flop C changes its state with every 4th clock change from 1 to 0. The truth table and waveform is as shown in fig.

Q.32.Describe operation of Mod7 synchronous counter

0 1 2 3 4 5 6 7CLK

A

B

C

36


Ans.Mod8 counter is taken as basis for building up other modulus counter. The mod8 counter has got 8 discrete states 000 to 111. If we skip one of the states we get mod7 counter.

37


Circuit Diagram for MOD-7 CounterTruth table

CLK C B A1 0 0 12 0 1 03 0 1 14 1 0 05 1 0 16 1 1 07 1 1 11 0 0 1

Fig. Shows a mod7 counter which skip the state 000. When CBA= 111 during count7 the output of the NAND gate Z is ‘0’. The output of NAND gate is connected to k-input of A flip-flop. Therefore the input condition for A flip-flop after the state 111 is J=1 and K=0. Therefore when next clock pulse comes A is prevented from resetting and continue to remain as 1 whereas B and C toggles from 1 to 0 as usual. Therefore counter proceeds from 111 to 001 and we get mod7 counter.

J A

K A

J B

K B

J C

K C

Logic 1

Logic 1

Clock

38


Q.33.Describe operation of Mod6 synchronous counter Ans.

Circuit Diagram for MOD-6 Synchronous Counter

Truth Table

CLK C B A2 0 1 03 0 1 14 1 0 05 1 0 16 1 1 07 1 1 1

A mod7 counter can be easily modified to form mod6 counter by skipping two states 000 & 001. If the output of NAND gate Z is removed from flip-flop A and connected to the K input of flip-flop B and mod6 counter is formed. The arrangement is shown in fig. On the 7th count the output of NAND gate is low corresponding to a low K input i.e. for B flip-flop J=1 & K=0. Hence B flip-flop is prevented from resetting during the transition from 7 to count 0. The counter progress from count7 to count2 and state 0 & 1 are omitted.

Q.34.Describe operation of Mod5 synchronous counter Ans. The mod5 counter can be implemented by combining the method used to form the mod7 and mod6 counter. If the output of the NAND gate Z is connected to the K input of both flip-flop A and B a mod5 counter is

J A

K A

J B

K B

J C

K C

Clock

Logic 1

Logic 1

ABC

39


formed. This is true since the NAND gate output is low during count1 which means that neither flip-flop A nor B flip-flop is allowed to reset during the natural transition from count7 to count0 only flip-flop C is allowed to reset and thus counter advances from state7 to state3. Fig. Shows mod5 counter.

Circuit Diagram for MOD-5 Synchronous CounterTruth Table

CLK C B A3 0 1 14 1 0 05 1 0 16 1 1 07 1 1 13 0 1 1

Q.35.Describe operation of Mod3 synchronous counter Ans.

A mod3 counter can be formed by using two flip-flop. If we connect the output B of B flip-flop to the K-input of A flip-flop. Count ‘0’ can be skipped. The arrangement is as follows.

J A

K A

J B

K B

J C

K C

Logic 1

Logic 1

Logic 1

ABC

J A

K A

J B

K B

Logic 1

Logic 1

Clock

40


Circuit Diagram for MOD-3 Synchronous Counter

Truth tableCLK B A

1 1 12 0 03 0 1

4(1) 0 1

When the first clock pulse occurs the flip-flop A will toggle from 0 to 1. On the next clock pulse A changes from 1 to 0 whereas B changes from 0 to 1 on the 3rd clock pulse flip-flop. A remain high because B=K is low [J=1,K=0] on the 4th clock pulse A remain high B toggles from 1 to 0. Thus the count sequence are 01,10,11,01 etc. and count 00 is skipped. Hence it is a mod3 counter.

Q.36.Describe operation of Mod16 synchronous counter Q.37.Describe operation of 4 bit synchronous counter Q.38.Describe operation of Divide by 16 parallel counter

Ans. 4 bit binary synchronous or parallel counter:

Circuit Diagram of 4-bit synchronous Counter

Truth table

J A

K A

J B

K B

J C

K C

J D

K D

Logic 1

Logic 1

Clock

41


CLK D C B A0 0 0 0 01 0 0 0 12 0 0 1 03 0 0 1 14 0 1 0 05 0 1 0 16 0 1 1 07 0 1 1 18 1 0 0 09 1 0 0 110 1 0 1 011 1 0 1 112 1 1 0 013 1 1 0 114 1 1 1 015 1 1 1 1

16(0) 0 0 0 0

Q.39.Describe Operation of 3 bit /Mod 8 / Divide by 8 Down CounterAns .

Circuit Diagram of Mod8 Down CounterTruth table

J B

K B

J C

K C

J A

K A

Logic 1

Logic 1

Clock

42


Count C B A C B A7 1 0 1 0 0 06 1 0 0 0 0 15 1 0 1 0 1 04 1 0 0 0 1 13 0 0 1 1 0 02 0 0 0 1 0 11 0 0 1 1 1 00 0 0 0 1 1 17 1 1 1 0 0 0

Another Figure For Down Counter

A three flip-flop can be used for up as well as down counter. The truth table is as shown in fig.

Thus if the output are taken from the true side i.e. CBA it works as up counter and if the output is taken from the false side i.e. CBA it works as down counter. Truth table is shown operation is similar to up counter.

A true down counter can be formed by triggering the input of each flip-flop with false side of the previous flip-flop instead of true side as shown in fig. Here A changes state each time the clock goes low however B changes state when A goes high. Since this is the time when A goes low. Similarly C changes state when B goes high or B goes low.

J B

K B

J C

K C

J A

K A

Logic 1

Logic 1

Clock

43


Q.40.Describe operation of 3 bit serial Up-Down Counter Ans.

Circuit diagram of 3bit Serial Up Down Counter

If the flip-flop are triggered from true side of previous flip-flop we get up counting. If flip-flop are triggered from false side of previous flip-flop we get down counting.

Fig. Shows a 4bit binary serial up down counter line is 0. The upper AND gates are enabled and lower AND gates. are disabled therefore flip-flop are triggered from true side of previous flip-flop. Hence we get up counting to start up count initially all flip-flop are cleared to Zero

If the countdown count line is 1 and count up line 1, Lower And gates are enabled and upper AND gates are disabled now the flip-flop are triggered from the false side of previous flip-flop and we get down counting to start down count initially all the flip-flop are preset to 1.

Q.41.Describe 3bit Up-down serial counter using NAND Ans. When the count down line is low and count up line is high the gate X is disabled and gate Y is enabled. Therefore A will not pass through X but A will pass through Y. In passing through gate X, A gets inverted and thus appears at the inputs of next flip-flop as A which gives a count up fashion. Fig. Shows on next page shows the diagram of counter.

J A

K A

J B

K B

J C

K C

Logic 1

Clock

Down

Up

Logic 1

Logic 1

44


Circuit of 3-bit ASynchronous UP-Down CounterWith the count down line is high the count up line is low. Y is

disabled and X is enabled. Thus A is inverted as it passes through the gate X and appears at the input of the next flip-flop as A and this work as up-down counter.

Q.42.Describe operation of 4bit Synchronous /parallel up/down counter Ans.Fig. Shows a 4bit parallel up-down counter. It is former by using some technique as in parallel counter. For up counting count up line is made 1 and for down count down count line is made 1.

J A

K A

J B

K B

J C

K C

Logic 1

Logic 1

Down

Up

Clock

Logic 1

J A

K A

J B

K B

J C

K C

J D

K D

Logic 1

Logic 1

UP

Clock

Down

Logic 1

45


Circuit diagram of 4bit Synchronous Up Down CounterCount up operation If count up line is 1, A is 1 the output of NAND gate Z1 is 1 which makes J & K of B flip-flop 1. Therefore B will toggle on next clock pulse where A also changes from 1 to 0. Similarly if count up line is 1, A & B are 1, output of NAND gate Z2 is 1, which makes J & K input C flip-flop 1. Therefore C will toggle on next clock pulse where A and B change from 0. Similarly D flip-flop will change whenever A,B and C are all changing from 1 to 0.

Down Count operation If count down line is 1 A is 1 the output of NAND gate Z1 is 1 which makes J & K of B flip-flop = 1. Therefore B will toggle on next clock pulse whereas A changes from 1 to 0 or A changes from 0 to 1. Similarly C will toggle whenever A & B are changing from 0 to 1 and D will toggle whenever A,B and C change from 0 to 1.

Application of counterCounters are used to count numbers but in addition they are used

in digital system for various purposes As they can be used to count the occurrence of any event, frequency division or generating timing sequence to control operation in digital system. A few important applications are

1) Precision timer interval meter.2) Digital clock3) Digital voltmeter.4) TV horizontal and vertical timing pulses generator.5) Measurement of frequency.6) Counting of objects like in bottling plants.

RegisterQ.43.What is register?List Different types if register?Ans.Basically all most all digital signal processing requires the storage of information, however momentary that storage may be. The fundamental storage unit is flip-flop which can store only a bit of information for storing more information group of flip-flops may be used together.

Hence flip-flops can store 1 bit of information. It is called as 1 bit register. An array of flip-flop is required to store binary information, the number of flip-flops required are equal to the number of bits in the binary word (1-FLIP FLOP for bit) and is referred to as a register. Register find application in variety of digital system including microprocessor. E.g. Intel 8085 has 7-8bit register and one-five-bit register called as flag.

46


Registers are to classified depending upon the way in which data is entered and retrieved. They are as follows:

1) Serial in Serial out(SISO) register2) Serial in Parallel out (SIPO) register3) Parallel in Parallel out (PIPO) register4) Parallel in Serial out(PISO) register.

Register can be designed using discrete RS, JK ,JKMS or D-type flip-flop.

Q44.Describe Operation of 4 Bit serial shift register (SISO/SIPO)

Circuit Diagram of 4bit Serial Shift Register

Fig Shows a 4bit binary serial-In / serial-out shift register. The serial data is applied at serial input at QA and output can be taken serially at QD and parallel output can be taken serially at QA,QB, QC and QD.

Let a number 1011 to be entered into the register. Initially all flip-flop are cleared and then LSB is applied at serial input on the first clock pulse LSB is loaded into the first flip-flop then second LSB is applied at serial input and on the second clock pulse second LSB is loaded in the first flip-flop and LSB is shifted into second flip-flop.

Similarly the 3rd LSB and MSB are applied at serial input and after 4 clock pulses number 1011 can be loaded into that register. After entering the number of clock pulses are stopped. The output can be taken at once at QA ,QB ,QC ,QD in parallel and shifted out serially at QD

one by one by applying clock pulses. Since LSB is entered first this operation is called right shift operation.

Serial Output

J A

K A

J B

K B

J C

K C

J D

K D

Serial Input

47


Q.45.Describe 4-bit Parallel in Parallel out (Parallel in serial out (PIPO/PISO)) shift register:

Fig. Shows 4bit parallel in parallel out or serial out shift register. It takes the help of preset Input to load the number into register. Hence it is also called as presetable shift register.

Initially all flip-flop are cleared by applying a low clear signal at all clear input. The number to be entered is applied at 23 22 21 20 then load line is made high and the number is shifted into the register. Let the number to be entered is 1011 with load line 1(high), the output of NAND gate are 0100 respectively.

A '0' output from NAND gate preset the flip-flop where as '1' output from NAND gate retain '0' on the flip-flop. Hence we get Q3Q2Q1Q0 = 1011. After shifting the number the output can be taken parallel or serially by applying clock pulses.

Q.46.Describe the operation of Ring or circulating counter Ans

J Q3

K Q3

J Q2

K Q2

J Q1

K Q1

J Q0

K Q0

Serial Output

Serial In

Parallel Output

Parallel InputQ3 Q2 Q1 Q0

Q3 Q2 Q1 Q0Logic 1

48


Fig. Shows circuit of ring counter. It is a serial shift register with direct feed back i.e. D output of D flip-flop is connected to J input of A flip-flop and D is connected to K input A flip-flop.

Suppose initially all flip-flop are reset and clock pulse is allowed to run. Nothing will happen since J=0(D=0) and K=1(D=1) and it continue to remain 0. Therefore to start the counter A is made 1 by presetting of A flip-flop.

Hence on next cycle of clock, 1 in A will be shifted to B and A again resets 0, since D=0; on the 3rd cycle of clock a in B shifted to C and on 4th

cycle 1 in C is shifted to D when D become 1, J=1 and K=0 for A flip-flop therefore on 5th cycle A again set to 1 and with every other clock pulse this 1 goes on shifting from 1 flip-flop to other. Since 1 circulates around the counter it is called as Ring counter or circulating counter.

Waveforms of Ring Counter

A

B

C

D

Clock

J A

K A

J B

K B

J C

K C

J D

K D

Logic 1

Logic 0

Clock

49


Shift counter or Johnson’s counter (Twisted Ring Counter)Consider a 3-stage shift register if connected to J input of A flip-

flop and C is connected to K input of A flip-flop result in a counter known as shift counter or Johnson’s counter. This type of connection is called as Inverse feedback. Fig. is as shown.

Assume that all flip-flop are in reset condition and the clock is allowed to run. Since C is 0, C is 1 therefore J=1,K=0 for A flip-flop. Hence A will set to 1 on 1st clock cycle of clock whereas B and C remains 0 due to shifting operation.

During 2nd clock cycle A remain 1, since C=1, 1 in A is shifted to B and C remain 0.

On 3rd cycle of clock A remain 1, 1 in A is shifted to B and one in B is shifted to C. Thus on 3rd cycle of clock all the flip-flop set to 1. As soon as C=1,C=0 therefore , J=0,K=1 for A flip-flop.

Hence on 4th cycle of clock, A will reset where as B and C remain 1 due to shifting operation.

On 5th clock cycle A remain ‘0’. ‘0’ in A is shifted to B and 1 in B shifted to C. on 6th cycle of clock A remain 0, 0 in A is shifted to B, and 0 in B is shifted to C. Thus all flip-flop reset again. All the states as Mod 6 counter.Truth table

C B A Equivalent decimal count0 0 1 10 1 1 31 1 1 71 1 0 61 0 0 40 0 0 0

J A

K A

J B

K B

J C

K C

Logic 1

Logic 1

Clock

50


0 0 1 1

Illegal states In the truth table counts 2 & 5 are missing these are called as illegal states of counter. Suppose the counter starts from 010(2), when the power is 1st applied following changes occur when clock pulse are applied.

C B A0 1 01st clock pulse1 0 12nd clock pulse0 1 0

Thus the counter oscillates between illegal states 010 & 101. On order to avoid this one method is to use NAND gate as shown.

CBA are all one corresponding to illegal state 010 therefore output of NAND gate is low. The output of NAND gate is connected to preset of A flip-flop. Therefore any time 010 occurs A will set to 1. Counter changes from 010 to 011. Since 011 is one of natural count sequence and therefore counter will operate as desired.

Waveforms of Twisted Ring Counter

Clock

A

B

C

Preset of A flip flop

ABC

51


4 Bit shift or Johnson counters

Truth - TableD C B A Binary equivalent0 0 0 0 00 0 0 1 10 0 1 1 30 1 1 1 71 1 1 1 151 1 1 0 141 1 0 0 121 0 0 0 80 0 0 0 00 0 0 1 1

But in this counter the illegal states are 2,4,5,6,9,10,11,13.

Binary count State New state New binary2 0010 0101 54 0100 1001 95 0101 1011 116 0110 1101 139 1001 0010 210 1010 0100 411 1011 0110 613 1101 1010 10

Hence from above table it is seen that when counter is started in any illegal state counter will progress through count 2,5,11,6,13,10,4,9,2 which are undefined. Thus to care this problem again the inputs ABC are considered. These inputs are true during count 2 and count 10.

J A

K A

J B

K B

J C

K C

J D

K D

Logic 1

Clock

Logic 1

52


Therefore 0010 will start counter with 1110.

Q47.Compare Register and CounterAns.

Q.48. Compare1.Ripple Counter2. Asynchronus and Synchronous counter3.Cobinational and Sequential circuits

Ripple Counter Ring CounterThis counter are designed using T –FlipFlop i.e. each FlipFlop toggle on every clock pulse .

1 This counter is designed using D- FlipFlop i.e. each FlipFlop latch the data on every clock pulse.

Here output of first FlipFlop’s given as clock to Next FlipFlop. Diagram

2 Here each FlipFlop is simultaneously driven by Same clock.. Diagram

Connect to Preset of C and D flip flop

ABCD

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Here counter output is in sequence .i.e. 1,2,3,_,_,_

3 Here counter output is not in sequence.

Ripple counter can be up counter orDown counter.

4 This counter can be multiply by 2 or divide by 2 counter.

The output of last FlipFlop is not connected back

5 Output of last FlipFlop is connected back to input To make Ring or John counter.

Ripple counter are used as Divide by N counter.

6 Ring counter are useful as sequence generator.

Synchronous counter Asynchronous counterIn synchronous counter all flip flop areTriggered by clock simultaneously.

1 In asynchronous counter every flip flop is triggered by previous flip flop output.

Since all FlipFlop are triggered simultaneously No propagation delay and speed is more Compared to asynchronous counter.

2 Asynchronous counter propagation delay Is more since output of one FlipFlop trigger next Flip flop hence operating speed is slow.

Hardware requirement is more. 3 Hardware requirement is less.Difficult to construct. 4 Easy to construct.Glitches are not present in o/p. 5 Glitches are present in output.It is also called as parallel counter. 6 It is also called as serial or ripple

counter.Diagram. 7 Diagram.

Generally while designing synchronous Mod N counter the initial counter are Skipped .i.e. for Mod 3 counts will be 001,10,11 count 00 is skipped.

8 Generally while designing asynchronous Mod N counter last count from truth table skipped. i.e. for Mod 3 count will be 00,01,10,count 11 is skipped.

Combinational Sequential

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In combinational logic circuit the output at any Instant of time depend upon the input present at that instant of time.

1 In sequential logic circuit output is depended on present input and the past input’s output.

No memory element is needed ,since it does not need past information. Diagram.

2 There are memory element to store past Information. Diagram.

No feedback is needed. 3 In sequential circuit feedback is used to Connect output of combinational logic to Memory and output of memory element to Combinational circuit.

In combinational there is no such differentiation.

4 In sequential circuit may be synchronous or Asynchronous .i.e. depending on how clock is connected.

Encoder, Decoder, Mux, Demux, Comparator, Code converter are example of combinational logic design.

5 Flip flop , Counter, Register, etc are example of sequential logic circuit.

Combinational circuit design is done with Truth table and K-Map reduction.

6 Sequential circuit are design using Excitation table and K-Map reduction.

Q.49.Describe IC 74754bit bistable latchesAns.

Pin diagram

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Truth tableQ.50.Describe the IC 7490 decade CounterAns.

Pin diagram

Functional Diagram

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Truth Table Truth Table with Reset

Logical Diagram

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Documents

Prof.Manoj Kavedia ( 9860174297 ) ([email protected]) 4 ...kavediasir.yolasite.com/resources/UNIT-4-FYBSCIT.pdf · 4.7 Study of IC 7474 and 7475. 4.8 Applications of flip flops