Programming of Microcontrollers in Assembly Language

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    Brno University of Technology

    Programming of Microcontrollers in Assembly Language

    Microprocessor Techniques and Embedded SystemsLecture 2

    Dr. Tomas Fryza

    Oct-2012

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    Contents

    Basic Architectures in Microprocessor TechniquesVon Neumann, Harvard, CISC, RISC

    Development of Microcontrollers Applications

    Assembler Directives

    Programming Model

    Types of InstructionsAVR Source Code Example

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    Contents

    Basic Architectures in Microprocessor TechniquesVon Neumann, Harvard, CISC, RISC

    Development of Microcontrollers Applications

    Assembler Directives

    Programming Model

    Types of InstructionsAVR Source Code Example

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    Useful terms

    Central processing unit (CPU)the control section of the computer; the partthat controls its operations, fetches and executes instructions, and performarithmetic and logical functions.

    Microprocessora complete central processing unit for a computer constructed onone chip of silicon.

    Microcomputera computer that has a microprocessor as its central processingunit.

    Nonvolatile memorya memory that retains its contents when power is removed.

    Volatile memorya memory that loses its contents when power is removed.

    Registera storage location inside the CPU.

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    Princeton versus Harvard

    In 1970s U.S. government asked Princeton and Harvard universities to come upwith a computer architecture (used in computing tables of Naval Artillery shelldistances for varying elevations and environmental conditions).

    Two basic conceptions: Von Neumann (chief scientists name in Princeton univ.), Harvard.

    Von Neumann architecture: computer with common memory for storing the control program as well as variables and

    other data structures, three fundamental parts of every computers: CPU, memory, I/O, internal structure is independent to the computer task (i.e. computer is controlled by

    software), program is executed in sequential way (current instruction is defined by Program

    Counter), memory is divided to constant blocks; indexes of these blocks are used as addresses.

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    Harvard Architecture

    Harvard conception used separate memory banks for program storage, theprocessor stack, and variable RAM.

    The Harvard architecture was largely ignored until the late 1970s.

    The Harvard architecture executes instructions in fewer instruction cycles thanthe Von Neumann architecture, because of a much greater amount of instructionparallelism is possible in Harvard architecture.

    Instruction fetches can take place during previous instruction execution and notwait for either a finish of instruction execution or have to stop the processorsoperation while the next instruction is being fetched.

    I.e. the current instruction was fetched during the previous instructionsexecution. This allows the instruction to execute in only one instruction cycle.

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    Separate Memory Conception of Harvard Architecture (ATmega16)

    Figure: Memory space for 8-bit MCU ATmega16.

    Program memory is Flash type.

    Data memory is SRAM (StaticRandom Access Memory):32 general purpose registers,64 I/O registers, internal/externalmemory RAM.

    Date memory is also EEPROMtype (Electrically ErasableProgrammable Read-OnlyMemory).

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    CISC versus RISC

    There are two basic types of processor designed philosophies: CISC (Complex Instruction Set Computer), RISC (Reduced Instruction Set Computer).

    In the 1970s and early 1980s, processors predominantly followed the CISCdesigned. The current trend is to use the RISC philosophy.

    One factor of the popularity of CISC in the 1970s was the high price (mid-1970s:16KB$

    500) and small capacity of memory. So there was a need to minimize theamount of memory required to store a program.

    CISC systems use complex instructions (e.g. instruction that copies an elementfrom one array to another and automatically updates both array subscripts).

    RISC systems use only simple instructions (e.g. adding of two integers). Required

    operands are in the processors internal registers, not in the main memory.

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    CISC Processors

    Table: Percent occurrence of operation types in common source codes.

    Operation Percent occurrence

    Memory loading 27.3 %

    Conditional jump 13.7 %Memory storing 9.8 %P

    50.8 %Values comparison 6.2 %Address loading 6.1 %Subtraction 4.5 %Character insert 4.1 %Addition 3.7 %

    P75.4 %

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    CISC/RISC Comparison

    Table: Comparison of test applications for Intel 8085 (CISC) a ATmega16 (RISC).

    Routine/application Intel 8085 ATmega16

    Delay routine size 6 B 8 BDelay routine velocity* 10.5 ms 2 msStopwatch size 60 B 92 B (assembly)

    3.5 kB (C code)

    * Number of routine repetitions: 1,000, fCPU =2MHz.

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    Intel 8085 Instruction Set

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    RISC Processor Instruction Set

    Op code (instruction structure) of instruction ADD Rd, Rr (Rd=Rd+Rr): 0000 11rd dddd rrrr d {0;31} 1st operand, result r {0;31} 2nd operand

    Op code of instruction INC Rd (Rd=Rd+1): 1001 010d dddd 0011 d {0;31} 1st operand, result

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    Contents

    Basic Architectures in Microprocessor TechniquesVon Neumann, Harvard, CISC, RISC

    Development of Microcontrollers Applications

    Assembler Directives

    Programming Model

    Types of InstructionsAVR Source Code Example

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    Useful terms

    Assemblera computer program that converts aasembly language programs into

    a form (machine language) that the computer can actually execute. Theassembler translates mnemonic operation codes and names into their numericalequivalents and assigns locations in memory to data and instructions.

    Assembly languagea programming language in which the programmer can usemnemonic operation codes, labels, and names to refer to their numericalequivalents.

    Mnemonicsymbolic name for an instruction, register, or memory location thatsuggests its actual purpose or function.

    Low-level languagea language in which each instruction or statement istranslated into a single machine language instruction.

    Operation code (op code)the part of an instruction that specifies the operationto be performed.

    Commenta section of a program that has no function other than to explain themeaning of part of the program. Comments are neighter translated nor executed;they are simply copied into the program listing.

    D l f Mi ll A li i

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    Development of Microcontrollers Applications

    There are three basic methods how to program the target applications for

    a MCU: First approach is to write an entire code in C language. The using of high-levellanguage brings to user the fast development possibilities and high code portability.With taking advantage of effective optimizing tools of development environment, thecompiled application could be optimized by speed and/or size criteria.

    The opposite approach uses the programming in low-level assembly language byparticular MCU instructions. By assembly programming approach, the absolute controlof program flow and the functional units loading is guaranteed.

    Combination of both assembly and C code approaches. The microprocessor is controlled by program, i.e. by succession of instructions

    stored in binary form.

    Instructions are stored in program memory (Flash type in AVRs); allinstructions are read and executed in sequential (successive) order.

    In microprocessor technique, instructions contains double information:

    (1) What kind of operation should be executed (op code),(2) Operands address.

    Each type of microcontrollers use different instruction set, i.e. there is no singleinstruction set for all manufactured microcontrollers.

    S C d T l i

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    Source Code Translation

    Figure: Process of source codetranslation.

    Control unit of microcontroller works withinstructions in binary form machine language(16-bit words for AVRs).

    Compose applications in machine code is

    extremely ineffective, complicated, illegible the assembly code is used.

    Process of translation into machine language issupported by assembler replace eachinstruction with binary succession accordingthe defined rules.

    S C d E l R i t

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    Source Code Example Registers

    1 . include ; d e s c ri p t i on f i le f o r A T m eg a 1 62

    3 L D I R 16 , 0 x0 A ; R1 6 = 0 A ( he x )4 L D I R 17 , 12 ; R1 7 = 12 ( de c )5

    6 M O V R 18 , R1 6 ; R1 8