PS2 Keyboard and VGA Output

8/20/2019 PS2 Keyboard and VGA Output

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Department of Microelectronics and Nanoelectronics

Interfacing a PS-2 Keyboard and VGA Monitor to

Xilinx XC3S200 FPGA

Hardware Description Languages - MNE 2102

Project


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VGA Port


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VGA Port


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640 x 480 Mode VGA Timing

25 MHz


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PS-2 Keyboard Port


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PS/2 Timing


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Keyboard to FPGA Communication

• The Data and Clock lines are both opencollector. A resistor is connected between eachline and +5V, so the idle state of the bus is high.

• When the keyboard wants to send information, itfirst checks the Clock line to make sure it's at a

high logic level. If it's not, the FPGA is inhibitingcommunication and the device must buffer anyto-be-sent data until the host releases Clock.

• The Clock line must be continuously high for atleast 50 µs before the device can begin totransmit its data.


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• The keyboard use a serial protocol with

11-bit frames.

• These bits are:

– 1 start bit. This is always 0. – 8 data bits, least significant bit first.

– 1 parity bit (odd parity).

– 1 stop bit. This is always 1.


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• The keyboard writes a bit on the Data line

when Clock is high, and it is read by the

host when Clock is low.


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PS/2 Keyboard Scan Codes


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Example: 1D => W

s t a

r t

1 1 11 0 0 0 0 1 s t o p

parity bitscan code


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Proposed Architecture

CLK_in red_outscan_code green_out

blue_ouths_outvs_out

CLK_in scan_errreset scan_arvPS2_CLK scan_codePS2_DATAread

50 MHzcrystal

CLK_in red_outscan_code green_out

blue_ouths_outvs_out

CLK_in scan_errreset scan_arvPS2_CLK scan_codePS2_DATAread

50 MHzcrystal


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PS-Keyboard Controller

• reset Asynchronous reset

• CLK_in Main synchronization clock signal

• PS2_CLK Clock signal generated by the keyboard

• PS2_DATA Signal on which serial data from the keyboardis transmitted to the FPGA

• read This is an input which must be pulsed whenthe scan_code is read.

• scan_arv This flag goes to 1 when a word has been

received. Remains there until read is assertedand then goes low at the next clock cycle.

• scan_err This flag is set when the data received isincorrect (parity, stop…) or when there is anoverflow. This flag is automatically cleared

when the reception of a new character begins.• scan_code (8 bits) is the data word received from the

keyboard


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VGA Display Controller

• CLK_in Main synchronization clock signal

• scan_code (8 bits) is the data word received from

the keyboard

• red_out Red Colour Enable

• green_out Green Colour Enable

• blue_out Blue Colour Enable

• hs_out Horizontal sync signal

• vs_out Vertical sync signal

Documents

PS2 Keyboard and VGA Output