QCA4010 Low-Energy Wi-Fi Single-Band 802.11b/g/n SoCimg.cecport.com/product/product/files/201511/ff... · 2015-11-04 · QCA4010 Low-Energy Wi-Fi Single-Band 802.11b/g/n SoC Device

QCA4010 Low-Energy Wi-Fi Single-Band 802.11b/g/n SoC Device Specification (Preliminary Information)

80-Y9047-3 Rev. A

February, 2015
��At�Ux�hZ�Ї?b�[�

3

Revision history

Revision Date Description

A February 2015 Initial release

80-Y9047-3 Rev. A 4

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.2 QCA4010 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.3 Product features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.4 Special marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.5 Integrated network processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.6 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.7 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.8 Reset and startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.8.1 Wakeup manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.8.2 Detailed SPI slave startup sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131.8.3 Power management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.9 Power transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141.9.1 Sleep state management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141.9.2 Hardware power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.10 System clocking (RTC block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151.10.1 High speed clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161.10.2 Low-speed clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161.10.3 Interface clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161.10.4 Wakeup manager clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.11 Front end control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161.12 MAC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171.13 Baseband block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171.14 Active power save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.14.1 Low Power Listen (LPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171.14.2 Green Tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.15 IPv4/IPv6 networking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181.16 Internal voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.16.1 Switching 1.2 V regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191.16.2 Linear 1.2 V regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.17 Bootstrap modes and pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.17.1 Internal bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.17.2 Host mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.17.3 Crystal value configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

80-Y9047-3 Rev. A 5

QCA4010 Low-Energy Wi-Fi Single-Band 802.11b/g/n SoC Device Specification (Preliminary Information) Contents

1.17.4 1.2 V regulator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211.17.5 1.8 V regulator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221.17.6 Test mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221.17.7 JTAG pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.1 I/O parameter definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324.1 Device physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324.2 Part marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.2.1 Specification-compliant devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.3 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384.4 Device moisture-sensitivity level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5 Carrier, Storage, and Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6 PCB Mounting Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7 Part Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

80-Y9047-3 Rev. A 6


Figures

Figure 1-1 QCA4010 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 1-2 Wakeup manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 1-3 QCA4010 power state: USB and UART host modes or hostless systems . . . . . . . . 15Figure 1-4 1.2 V switching power supply regulated by the QCA4010 . . . . . . . . . . . . . . . . . . . . 19Figure 1-5 1.2 V linear power supply regulated by the QCA4010 . . . . . . . . . . . . . . . . . . . . . . . 20Figure 2-1 QCA4010 pin assignments (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 4-1 QCA4010 mechanical dimensions, top and bottom views . . . . . . . . . . . . . . . . . . . . 33Figure 4-2 QCA4010 Package B dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 4-3 QCA4010 device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Figure 4-4 Device identification code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

80-Y9047-3 Rev. A 7


Tables

Table 1-1 Primary QCA4010 documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Table 1-2 Special marks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Table 1-3 Power management states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Table 1-4 QCA4010 IPv4 supported RFCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Table 1-5 QCA4010 IPv6 supported RFCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Table 1-6 Internal bias during power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Table 1-7 Host mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Table 1-8 Crystal value configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Table 1-9 1.2 V regulator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Table 1-10 1.8 V regulator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table 1-11 Test mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table 1-12 JTAG mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table 2-1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Table 2-2 Interface Selection by GPIO Bootstrap Pins (GPIO0-GPIO5) . . . . . . . . . . . . . . . . . . 28Table 2-3 Interface Selection by Firmware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Table 4-1 Package A dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Table 4-2 Package B dimensions10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Table 4-3 Package marking line description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Table 4-4 Device identification details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Table 4-5 Source configuration code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Table 4-6 Ordering numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Table 4-7 Device thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

80-Y9047-3 Rev. A 8

1 Introduction

NOTE This document is preliminary and subject to change without notice.

1.1 Document overviewTechnical information for the QCA4010 is primarily covered by the documents listed in Table 1-1. Each is a self-contained document, but a thorough understanding of the device and its applications requires familiarization with all of them. The device description in is a good place to start.

The QCA4010 Low-Energy Wi-Fi Single-Band 802.11b/g/n SoC Device Specification (Preliminary Information) is organized as follows:

Table 1-1 Primary QCA4010 documentation

Document No. Title/Description

80-Y9047-3(this document)

QCA4010 Low-Energy Wi-Fi Single-Band 802.11b/g/n SoC Device SpecificationConveys all QCA4010 IC electrical and mechanical specifications. Additional material includes pin assignments; shipping, storage, and handling instructions; PCB mounting guidelines; and part reliability. This document can be used by company purchasing departments to facilitate procurement.

Chapter 1 Gives a high-level functional description of the device, lists the device features, and defines marking conventions, terms, and acronyms used throughout this document.

Chapter 2 Defines the device pin assignments.

Chapter 3 Defines the device electrical characteristics, including absolute maximum ratings and recommended operating conditions.

Chapter 4 Provides IC mechanical information, including dimensions, markings, ordering information, moisture sensitivity, and thermal characteristics.

Chapter 5 Describes carrier, storage and handing information of the QCA4010 device.

Chapter 6 Presents procedures and specifications for mounting the QCA4010 device onto printed circuit boards (PCBs).

Chapter 7 Presents the QCA4010 device reliability data, including a definition of the qualification samples and a summary of qualification test results.

80-Y9047-3 Rev. A 9

QCA4010 Low-Energy Wi-Fi Single-Band 802.11b/g/n SoC Device Specification (Preliminary Information) Introduction

1.2 QCA4010 device descriptionThe QCA4010 is a low power MCU with integrated Wi-Fi platform for the Internet of Everything that contains a low-power Wi-Fi connectivity solution on a single chip. It includes a number of TCP/IP-based connectivity protocols along with SSL, enabling a low-cost, low-complexity system to obtain full-featured Internet connectivity and reliable information exchange.

The QCA4010 provides two interfaces for connecting to local system controllers. Primary host interface is SPI. The QCA4010 also supports SDIO, USB and UART interfaces.

The QCA4010 Wi-Fi link is a full-featured, single-band, single stream 802.11n solution. The Wi-Fi link is highly integrated, and includes an energy efficient on-board power amplifier and LNA. RF switches are also integrated. The QCA4010 Wi-Fi link is optimized for low system cost, and minimizes the number and cost of any components required to achieve a reliable Wi-Fi link.

1.3 Product features

Wi-Fi link Support for IEEE 802.11b/g/n

Single stream 1 × 1

Single-band 2.4 GHz

Integrated PA, LNA, with support for external PA and external LNA

Single or dual Rx front end for antenna diversity

Green Tx power saving mode

Low power listen mode

Data rates up to 150 Mbps

Full security support: WPS, WPA, WPA2, WAPI, WEP, TKIP

8 channels 12-bit accuracy ADC, maximum sampling rate is 400 Ksps for multiple channels and 1 Msps for single channel.

8 18-bit resolution PWM with 8-bit clock prescaler

Crypto accelerator supports AES 128/256, DES/3DES, SHA1, SHA224

System cost optimization Highly-Integrated Wi-Fi solution that requires only a single crystal, antenna, and antenna

matching components to complete the RF link

Integrated IPv4/IPv6 TCP/IP stack

Integrated Network services such as HTTP, DNS, FTP

9 mm x 9 mm, 116-pin dual-row QFN package

QCA4010 patch firmware is stored and automatically loaded from a low cost serial flash memory

80-Y9047-3 Rev. A 10


Manufacturing interface USB 2.0 device interface, providing a simplified, high-speed, and scalable manufacturing test

and configuration interface for QCA4010-based systems, using an integrated controller and PHY

Host interfaces SDIO/SPI slave interface

Allows for simplified connection to local host microcontrollers.Host driver source code and programming APIs are available.

UART/SPI host interface allows simple interfacing to microcontrollers.

UART with an AT style command set

Wakeup manager Non-volatile 8 KB RAM

Suspend/resume timer

Crypto accelerator Support AES 128/256, DES/3 DES, SHA1, SHA224

The Crypto accelerator has DMA controller connects to internal AHB bus for data transfer

The clock rate for Crypto accelerator is half of CPU clock rate

Application ADC Can be configured as 8 channels single-ended inputs or 4 channels differential inputs

Support periodic power save, the analog is turned off and digital clock is gated after conversion finished

The analog input level can be either 1.8 V or 3.3 V

Support HW external pin trigger and timer based trigger

DMA control to move conversion data to memory

Sample rate is up to 1 Mbps

12-bit accuracy

PWM Support 8 channels and each has an 18-bit resolution control

Each channel has a prescaler to divide clock from 1 to 256. The clock phase and duty cycle can be adjusted independently for each channel

The source clock can be CPU clock, WLAN clock (88 MHz), crystal clock or internal LPO clock (2MHz). If the PMU would work in sleep mode, the LPO clock should be selected

80-Y9047-3 Rev. A 11


Figure 1-1 QCA4010 functional block diagram

1.4 Special marksTable 1-2 defines special marks used in this document.

1.5 Integrated network processorThe QCA4010 includes a network processor that provides IP services and manages Wi-Fi link operations. The network processor code is loaded automatically from ROM off-chip serial flash memory. The flash memory is also used to store system configuration and persistent data sets. The network processor is optimized for energy efficient communications and includes multiple power states (see Section 1.9). Customers can use the integrated network processor to implement application-specific solutions. This customized code is stored on an off-chip serial flash.

CPU

On-Chip ROM

On-Chip RAM

OTP

2.4 GHz

802.11n WLAN

MAC/BB/Radio

Tx Front End

SPI Flash Memory

GPIOs2 x I2S, I2C

GPIO/Peripherals

Host/Manufacturing Interface Block

JTAG

Wakeup Manager

SPIUSB 2.0UART

OR

Rx Front End

Application ADC

Crypto Accelerator

PWM

Table 1-2 Special marks

Mark Definition

[ ] Brackets ([ ]) sometimes follow a pin, register, or bit name. These brackets enclose a range of numbers. For example, SDC1_DATA[7:4] may indicate a range that is 4 bits in length, or DATA[7:0] may refer to all eight DATA pins.

_N A suffix of _N indicates an active low signal. For example, RESIN_N.

0x000 Hexadecimal numbers are identified with an x in the number (for example, 0x0000). All numbers are decimal (base 10) unless otherwise specified. Non-obvious binary numbers have the term binary enclosed in parentheses at the end of the number; for example, 0011 (binary).

| A blue vertical bar in the outside margin of a page indicates that a change was made since the previous revision of this document.

80-Y9047-3 Rev. A 12


1.6 GPIOThe QCA4010 GPIO pins are fully configurable. They are shared with other interfaces, such as I2C, SPI, and serial flash. Table 2-2 and Table 2-3 provides the set of pin configurations options. Each of the GPIO pins supports these configuration options:

Internal pull-up/down options

API to read the current pin state

API signals host CPU when a GPIO pin transaction is detected

Trigger an exit from the Sleep state when a pin event is detected

Open-drain or push-pull output driver

Output source from a software register or the hardware pulse-width modulation (PWM)

1.7 Serial interfaceThe QCA4010 includes two high-speed Universal Asynchronous Receiver/Transmitter (UART) interfaces, which may be configured to serve as either a host interface link or a debug message console.

1.8 Reset and startup sequenceThe QCA4010 CHIP_PWD_L pin can be used to completely reset the entire chip. After this signal has been de-asserted, if configured for SPI slave operation, the QCA4010 waits in a low-power state until communication from the host, indicating that the Wi-Fi and the network services should be started. When configured for UART host mode, the QCA4010 begins its boot up process and starts network services as soon as CHIP_PWD_L is de-asserted.

1.8.1 Wakeup managerThe wakeup manager enables use of the QCA4010 in low power environments with no external host CPU. To achieve the lowest average power profile, the QCA4010 must be placed in suspend mode for the majority of the time. While in suspend state, the QCA4010 shuts down all circuits except a few critical blocks needed to resume operation after suspend; these include I/O pads to detect a wakeup request, a sleep timer to detect a synchronous wakeup event, and a small RAM that stores state information spanning a suspend-resume cycle.

To enter SUSPEND state, QCA4010 firmware saves state in the on-chip RAM and configures wakeup timers. Firmware then triggers the suspend operation, which turns on isolation circuits and turns off voltage regulators to the QCA4010 main core block.

Only the wakeup manager block and PMU circuits remain powered in suspend mode. When a wakeup event is detected, the device exits suspend back to active state. Wakeup events include synchronous wakeup, which occurs when the sleep timer in the wakeup manager expires, and asynchronous wakeup, which occurs when a pin event is detected on the wakeup pin.

80-Y9047-3 Rev. A 13


Figure 1-2 Wakeup manager

1.8.2 Detailed SPI slave startup sequenceAfter a COLD_RESET event (e.g., the host toggles CHIP_PWD_L), the QCA4010 enters the HOST_OFF state and awaits communication from the host indicating that Wi-Fi and network services should be started. When configured for UART host mode, the QCA4010 begins its boot up process and starts network services as soon as CHIP_PWD_L pin is de-asserted.

When the host is ready to use the QCA4010, it initiates communication viaSPI slave and enables network services by writing to a specific register via the SPI slave interface.

When the QCA4010 enters the WAKEUP state for some duration and transits to the ON state, the on-chip network processor configures the QCA4010 functions and interfaces, as per the configuration and customization data set provided by the serial flash memory. When the QCA4010 is ready to receive commands from the host, it sets a specific flag that is accessible from the Host CPU via the SPI slave interface.

The host reads the ready bit and can now send function commands to the QCA4010.

1.8.3 Power management unit The QCA4010 has an integrated power management unit (PMU) that generates all the power supplies required by its internal circuitry either from an external battery or a 3.3 V supply. The main components of the PMU include:

A switching regulator (SWREG) that produces a 1.2 V supply from the 3.3 V supply.

ResetPower on Reset = 0

Bootstrap Latch Delay

Suspend

Delay Core Ready

Power on Reset = 1

Cold Boot = 1Timer Wakeup Event = 1WAKEUP_L = 1 (pin 27)

Core Power Ready = 1

* Isolation Buffers Open

Susp

end

Req

uest

= 1

Wait for Power Down Request *

Suspend Request = 1

PWRDWN_OUT_L = 1 (pin 26)

LPO CLK Enable is Controlled by CHIP_PWD_L

Wait for Power Up

Wait for Power Down

CHIP_PWD_L = 1 (pin 14)LPO Clock Ready = 1

Host FN Disable

Active *

Host Off

WakeupClocks Gated

On

Host FN EnableSleep

XTAL Off

Sle

epC

riter

ia

XTAL_SETTLE

80-Y9047-3 Rev. A 14


A linear regulator (SREG) which converts the host I/O supply to a 1.2 V supply for some small control blocks which are turned on when CHIP_PWD_L is de-asserted.

A linear regulator which produces a 1.2 V supply from a 3.3 V supply (can be used instead of the SWREG to reduce the BOM cost).

1.9 Power transitionThe QCA4010 provides integrated power management and control functions and extremely low power operation for maximum battery life across all operational states by:

Gating clocks for logic when not needed

Shutting down unneeded high speed clock sources

Reducing voltage levels to specific blocks in some states

1.9.1 Sleep state managementSLEEP state minimizes power consumption while network services are not required, yet the system must remain ready for use within a short time. In SLEEP state, all high speed clocks are gated off and the external reference clock source is powered off. The network processor and Wi-Fi link are also suspended and not operational. All state information in the network processor (and its memory) and the Wi-Fi link are preserved to allow a fast resume to full network services.

The system remains in sleep state until a wakeup event causes the system to enter the WAKEUP state. Once WAKEUP state is entered, the QCA4010 restores all voltage levels and clocks, then automatically moves to the ON state. This wakeup event can be either a pin event or internal timer based event. The pin event may be triggered by the host CPU, or some system level event.

1.9.2 Hardware power statesTable 1-3 describes the top level hardware power states in the QCA4010. Table 1-3 Power management states

State Description

POWER_DOWN

CHIP_PWD_L pin assertion immediately brings the chip to this state.

Sleep clock is disabled.

No state is preserved.

SUSPEND While in suspend state, the chip shuts down all circuits except a few critical blocks needed to resume operation after suspend.

HOST_OFF Network services and WLAN are off. Only the SPI host interface is powered on, the rest of the chip is power gated (off).

The host can transition QCA4010 to WAKEUP (followed by ON) at any time by writing a register in the host interface domain.

WLAN and CPU states are not retained.

For UART hosted, or USB manufacturing configurations, this state is bypassed by pulling GPIO0 low at the de-assertion of CHIP_PWD_L. This state applies only to SPI designs.

80-Y9047-3 Rev. A 15


Figure 1-3 depicts the USB and UART power state transition diagrams.

Figure 1-3 QCA4010 power state: USB and UART host modes or hostless systems

1.10 System clocking (RTC block)The QCA4010 has an RTC block which controls the clocks and power going to other internal modules. Its inputs consist of sleep requests from these modules and its outputs consist of clock enable and power signals which are used to gate the clocks going to these modules. The RTC block also manages resets going to other modules with the device. The QCA4010’s clocking is grouped into two types:

High-speed

Low-speed

SLEEP Only the sleep clock is operating.

The crystal or oscillator is disabled.

Any wakeup events (MAC, host, LF timer, GPIO interrupt force a transition to WAKEUP.

All internal states are maintained.

Host interface is idle (USB is in SUSPEND).

WAKEUP The system transition from sleep OFF states to ON.

The high frequency clock is gated off as the oscillator is brought up and the PLL is enabled.

WAKEUP duration is less than 2 ms.

ON The high speed clock is operational.

Lower-level clock gating is implemented at the block level, including the CPU, which can be gated off using WAITI instructions while the system is on.

Table 1-3 Power management states

State Description

POWER_DOWN

SleepXTAL Off

WakeupClocks Gated

On

WAKEUP Events

~CHIP_PWD_L

SleepCriteria

CHIP_PWD_L

XTAL_SETTLE

80-Y9047-3 Rev. A 16


1.10.1 High speed clockingThe reference clock source drives the PLL and RF synthesizer within the QCA4010. It can be either an external crystal or oscillator. To minimize power consumption, the reference clock source is powered off in SLEEP, HOST_OFF, POWER_DOWN and after HOST_OFF states. For an external crystal, the QCA4010 disables the on-chip oscillator driver. For an external oscillator, the QCA4010 de-asserts its CLK_REQ signal to indicate that a reference clock is not needed.

When exiting SLEEP state, the QCA4010 waits in WAKEUP state for a programmable duration. During this time, the CLK_REQ signal is asserted to allow for the reference clock source to settle. The CLK_REQ signal remains asserted in ON state.

The QCA4010 supports reference clock sharing in all power states. For an external crystal, the on-chip oscillator driver drives a reference clock output whenever an external clock request signal is asserted. For an external oscillator, the external clock request signal is forwarded on the CLK_REQ signal, and the input clock is passed along to the reference clock output.

1.10.2 Low-speed clockingThe QCA4010 has eliminated the need for an external sleep clock source thereby reducing system cost. Instead, an internal ring oscillator is used to generate a low frequency sleep clock. It is also used to run the state machines and counters related to low power states.

The QCA4010 has an internal calibration module which produces a 32.768 KHz output with minimal variation. For this, it uses the reference clock source as the golden clock. As a result, the calibration module adjusts for process and temperature variations in the ring oscillator when the system is in ON state.

1.10.3 Interface clockThe host interface clock represents another clock domain for the QCA4010. This clock comes from the host and is completely independent from the other internal clocks. It drives the host interface logic as well as certain registers which can be accessed by the host in HOST_OFF and SLEEP states.

1.10.4 Wakeup manager clockThe QCA4010 includes a dedicated always-on clock oscillator. In the SUSPEND state, this clock oscillator is the only clock that continues to run. This clock is used to calculate the resume from SUSPEND time interval. The QCA4010 has an option for using an external 32-KHz oscillator instead of the onboard low-power oscillator.

1.11 Front end controlFor applications that use external front-end components, the QCA4010 provides the ability to control them with four antenna switch control outputs named:

ANTA

80-Y9047-3 Rev. A 17


ANTB

ANTC

ANTD

A programmable switch table indexed by transceiver state offers flexibility for various front-end configurations. The QCA4010 supports antenna sharing with another wireless chip in all power states by using ANTD to control the shared antenna switch.

1.12 MAC blockThe QCA4010 Wireless MAC consists of these major blocks:

Host interface unit (HIU) for bridging to the AHB for bulk data accesses and APB for register accesses

10 queue control units (QCU) for transferring Tx data

10 DCF control units (DCU) for managing channel access

Protocol control unit (PCU) for interfacing to baseband

DMA receive unit (DRU) for transferring Rx data

Supports Rx diversity

1.13 Baseband blockThe QCA4010 baseband (BB) module is the physical layer controller for the 1x1 802.11b/g/n air interface. It is responsible for modulating data packets in the transmit direction, and detecting and demodulating data packets in the receive direction. It has a direct control interface to the radio to enable hardware to adjust analog gains and modes dynamically.

1.14 Active power save

1.14.1 Low Power Listen (LPL)To minimize active current consumption, the QCA4010 firmware will set the receiver in a low power listen mode, thus saving active power in between frames, when the transceiver is awaiting frames, as well as during active reception. It can be enabled in most conditions with minimal performance impact, between 1 and 2 dB. If harsh channel conditions require it, firmware will automatically revert to full power mode.

1.14.2 Green TxTo minimize active current consumption during transmission, the QCA4010 will utilize Green Tx. This feature allows the device to save power when communicating with a nearby station or access point when high output power is not required to sustain reliable communications. In such cases,

80-Y9047-3 Rev. A 18


the transmitter will reduce the transmit power to obtain current saving, while maintaining its high uplink throughput.

1.15 IPv4/IPv6 networkingThe QCA4010 includes a TCP/IP and UDP offload capability. This capability can reduce Flash requirements on a host MCU by up to 100 KBytes and also free up CPU cycles. The IP stack is a simultaneous IPv4/IPv6 stack with a BSD-like interface to simplify porting and integration with common embedded operating systems. The supported features of the QCA4010 (support for DHCP, multicast, and ARP) include:

ARP

Forwarding

Fragmentation/reassembly (supported with limitation)

IPv4/v6 header processing

UDP/TCP socket support

DHCP v4

Neighbor discovery

Broadcast/multicast

Address auto-configuration

Multicast

TCP zero-copy feature

HTTP/SSL client/server feature

DNS proxy server and client

SNTP client

Bridging/Routing

Raw sockets

The QCA4010 supports many key IPv4 and IPv6 RFCs as shown in Table 1-4 and Table 1-5.Table 1-4 QCA4010 IPv4 supported RFCs

IPv4 RFC Number

RFC1122: TCP Timeout/retransmission

RFC1122: TCP Keep-alive

RFC1122: TCP Zero-Window-Probe

RFC1122: TCP Sliding window protocol

80-Y9047-3 Rev. A 19


1.16 Internal voltage regulatorThe QCA4010 supports two regulator modes for its on-chip 1.2 V regulator; see Section 1.17.4 for more information.

1.16.1 Switching 1.2 V regulatorFigure 1-4 depicts the switching 1.2 V switching power supply regulated by the QCA4010. Refer to the reference design schematics for details.

Figure 1-4 1.2 V switching power supply regulated by the QCA4010

1.16.2 Linear 1.2 V regulatorFigure 1-5 depicts the switching 1.2 V linear power supply regulated by the QCA4010. Refer to the reference design schematics for details.

Table 1-5 QCA4010 IPv6 supported RFCs

IPv6 RFC Number

RFC2464:Transmission of IPv6 packets over Ethernet networks

RFC2460: Internet Protocol version 6

RFC2462: Duplicate Address Detection (DAD)

RFC2463: ICMPv6

RFC3513: IP version 6 addressing architecture

RFC3484: Default Address Selection

RFC2461: Neighbor discovery for IPv6 host

RFC4862: Stateless Address Auto-configuration

SREG_OUT

VD33_xxx C2 = 470 pF

Switching Regulator

(1.2 V)

VDD33

A18

SWREG_IN A15

C1

B10

SWREG_OUTA14

C3L1SWREG_FB_VDD12B12

DVDD12B1, B11, B15, B26, B31, B49

VDD12_xxxB36, B37, B41

Typical values for L1 = 1-4.7 nH,For C3 = 10 µ F

Decoupling capacitors should be connected to each power rail

80-Y9047-3 Rev. A 20


Figure 1-5 1.2 V linear power supply regulated by the QCA4010

1.17 Bootstrap modes and pinsCertain pins in the QCA4010 are sampled at startup, and these sampled values are used to select among various bootstrap modes and chip configurations.

1.17.1 Internal biasTable 1-6 shows the pins biased by chip hardware during power down. After startup, chip firmware may change the bias.

1.17.2 Host mode configurationTable 1-7 lists the QCA4010 bootstrap pins that select the interface used to communicate with the external host CPU. Host mode selection affects pin behavior of host interface pins as well as bootup processes in the PCM state machine. It informs the QCA4010 about the presence of an external CPU (referred to as the host controller) and the interface used to exchange messages.

SREG_OUT

VD33_xxx C2 = 470 pF

Linear Regulator

(1.2 V)

VDD33

A18

SWREG_IN A15

C1

B10

SWREG_OUTA14

C3SWREG_FB_VDD12B12

DVDD12B1, B11, B15, B26, B31, B49

VDD12_xxxB36, B37, B41

Typical values C3 = 10 µ F

Decoupling capacitors should be connected to each power rail

Table 1-6 Internal bias during power down

GPIO Internal bias

GPIO[6] Pull-Down

GPIO[11]

GPIO[20] Pull-Up

GPIO[30]

GPIO[31]

80-Y9047-3 Rev. A 21


1.17.3 Crystal value configurationTable 1-8 shows the bootstrap pin to configure the crystal value.

1.17.4 1.2 V regulator configurationThe QCA4010 supports two regulator modes for its on-chip 1.2 V regulator: switching and linear. Linear mode requires fewer board-level components, but at a slightly higher power consumption than switching mode. Table 1-9 shows the bootstrap pin to configure the 1.2 V regulator.

Table 1-7 Host mode configuration

Pin name

Bootstrap function name

On chip biasing

GPIO[0,4] Description

GPIO[0], GPIO[4]

hostmode — 00 QCA4010 CPU bootup is under control of the host CPU via the USB interface. The external CPU is required and the host interface is USB.

01 No host required at startup time. The QCA4010 CPU self boots and firmware may configure any of the available interfaces. No external CPU is required.

10 The QCA4010 CPU bootup is under control of host CPU via SPI Slave interface. The external CPU is required and the SPI interface is the host interface.

11 The QCA4010 CPU bootup is under control of the host CPU via the SDIO interface. The external CPU is required and the SDIO interface is the host interface.

Table 1-8 Crystal value configuration

Pin name Bootstrap function name On chip biasing Description

GPIO[36] xtal_freq[0] – 0 26 MHz

1 40 MHz

Table 1-9 1.2 V regulator configuration


GPIO[9] en_linear – 0 Switching regulator

1 Linear regulator

80-Y9047-3 Rev. A 22


1.17.5 1.8 V regulator configurationThe QCA4010 supports a regulator mode for its on-chip 1.8 V regulator.

1.17.6 Test mode configurationTable 1-11 shows the bootstrap pin to configure the test mode. GPIO[8] has an on-chip pull down.

GPIO_IOE[2] is enabled for on-chip 1.8 V regulator whose output is on VDD_1P8_OUT (pin A21).

1.17.7 JTAG pinsWhen the bootstrap power up is configured for JTAG mode, the QCA4010 will connect its TAP controller to the pins shown in Table 1-12.

Table 1-10 1.8 V regulator Configuration


GPIO_IOE[2] 1p8_reg_enable Pull Up Enable for on chip 1.8 V regulator

0 1.8 V regulator is disabled

1 1.8 V regulator is enabled

Table 1-11 Test mode configuration

Bootstrap function name Description

Normal Function Mode GPIO[8] 0

GPIO_IOE[1] 1

JTAG Function Mode GPIO[8] 1

GPIO[7] 1

Table 1-12 JTAG mode

Pin name Bootstrap function name

GPIO[6] TDI

GPIO[10] TMS

GPIO[12] TCK

GPIO[13] TDO

GPIO[25] TRST

80-Y9047-3 Rev. A 23

2 Pin Descriptions

The QCA4010 device is available in the 116-pin DRQFN that includes several ground pins for electrical grounding, mechanical strength, and thermal continuity. See Chapter 4 for package details. A high-level view of the pin assignments is shown in Figure 2-1.

Figure 2-1 QCA4010 pin assignments (top view)

QCA4010(Top View)

GPIO[18]GPIO[19]DVDD12GPIO[14]GPIO[13]GPIO[12]GPIO[11]GPIO[10]GPIO[9]

VDDIO_SDIO_1GPIO[8]GPIO[7]GPIO[6]GPIO[5]GPIO[4]GPIO[3]GPIO[2]

VDDIO_SDIO_0GPIO[1]GPIO[0]

SREG_OUTVDDIO_SDIO_PMU

DVDD12CHIP_PWD_L

SWREG_FB_DVDD12SWREG_OUT

NCSWREG_IN

IOT_MODE_EN

A1A2

B1A3

B2A4

B3A5

B4A6

B5A7

B6A8

B7A9

B8A10

B9A11

B10A12

B11A13

B12A14

B13A15A16

NCRFIN2P1_ANT2NCRFIN2N1_ANT2XPABIAS2NCVDD12_SYNTHVDD33_SYNTHVDD12_BB_PLLXTALIVDD33_PLL_XTALXTALOEXT_CLK_OUTANTAANTBANTCANTDVDD33_ANTDVDD12ADC[0]ADC[1]ADC[2]ADC[3]VDD33_ADCADC[4]ADC[5]ADC[7]ADC[6]GPIO[27]

A48A47

B39A46

B38A45

B37A44

B36A43

B35A42

B34A41

B33A40

B32A39

B31A38

B30A37

B29A36

B28A35

B27A34A33

GP

IO[1

6]VD

DIO

_GP

IO_0

NC

GP

IO[1

7]G

PIO

[20]

GP

IO[2

1]G

PIO

[22]

GP

IO[2

3]D

VD

D12

VDD

IO_G

PIO

_1G

PIO

[24]

GP

IO[2

5]G

PIO

[26]

NC

NC

NC

VDD

33_R

FR

FOU

T2N

1N

CR

FOU

T2P

1N

CN

CN

CN

CVD

D12

_RF

RFI

N2N

1N

CR

FIN

2P1

NC

A64

A63

B52

A62

B51

A61

B50

A60

B49

A59

B48

A58

B47

A57

B46

A56

B45

A55

B44

A54

B43

A53

B42

A52

B41

A51

B40

A50

A49

NC

VDD

33_P

MU

US

BN

CU

SB

_DP

OS

DV

DD

12U

SB_

DN

EGVD

D33

_IO

TVD

D_1

P8_O

UT

32K

_OS

C_I

N32

K_O

SC

_OU

TG

PIO

_IO

E[2

]G

PIO

_IO

E[1

]G

PIO

_IO

E[0

]G

PIO

[40]

GPI

O[3

9]G

PIO

[38]

GPI

O[3

7]V

DD

IO_G

PIO

_3G

PIO

[36]

GPI

O[3

5]G

PIO

[34]

GPI

O[3

3]G

PIO

[32]

GPI

O[3

1]G

PIO

[30]

VD

DIO

_GPI

O_2

DV

DD

12 NC

NC

A17

A18

B14

A19

B15

A20

B16

A21

B17

A22

B18

A23

B19

A24

B20

A25

B21

A26

B22

A27

B23

A28

B24

A29

B25

A30

B26

A31

A32

80-Y9047-3 Rev. A 24

QCA4010 Low-Energy Wi-Fi Single-Band 802.11b/g/n SoC Device Specification (Preliminary Information) Pin Descriptions

2.1 I/O parameter definitionsThe following nomenclature is used for signal names:

The following nomenclature is used for signal types:

NC/Reserved No connection should be made to this pin

_L At the end of the signal name, indicates active low signals

P At the end of the signal name, indicates the positive side of a differential signal

N At the end of the signal name indicates the negative side of a differential signal

IA Analog input signal

I Digital input signal

IH Input signals with weak internal pull-up, to prevent signals from floating when left open

IL Input signals with weak internal pull-down, to prevent signals from floating when left open

I/O A digital bidirectional signal

OA An analog output signal

O A digital output signal

P A power or ground signal

Table 2-1 Pin description

Signal Name Pin Type Description

General

EXT_CLK_OUT B34 O External clock out: 40 or 26 MHz; its corresponding half rate is available when configured.

XTALI A43 I/O Supports 40 MHz or 26 MHz crystal. When an external reference clock is used, connect the clock signal to the XTALO pin and ground the XTALI pin.XTALO A42 I

Radio

CHIP_PWD_L A13 I Chip power-down control

RFIN2N1 A51 IA The first differential RF inputs

RFIN2P1 A50 IA

RFOUT2N1 A55 OA The first differential RF outputs

RFOUT2P1 A54 OA

RFIN2P1_ANT2 A47 IA The second differential RF inputs for 2.4 GHz Rx/LNA diversity using two antennas; can be left open if not in use

RFIN2N1_ANT2 A46 IA

Analog Interface

80-Y9047-3 Rev. A 25


XPABIAS2 B38 OA Bias for optional external power amplifier in 2.4 GHz

External Switch Control

ANTA A41 O External RF switch control

ANTB B33 O

ANTC A40 O

ANTD B32 O

USB

USB_DPOS A19 IA/OA USB D+ signal; carries USB data to and from the USB 2.0 PHY

USB_DNEG A20 IA/OA USB D- signal; carries USB data to and from the USB 2.0 PHY

Internal Switching Regulator

SREG_OUT B10 P 1.2 V regulator output, connect to a 470 pF bypass capacitor on the board

SWREG_OUT A14 P Output of the switching regulator to an LC filter or the LDO

SWREG_IN A15 P 3.3 V input to the internal switching regulator or LDO

Wakeup Manager

IOT_MODE_EN A16 I Power island isolation setting.This pin should be tied to the VDD33_IOT signal. When this pin is low, the internal signal connections between pins A21 through B19 are isolated from rest of the chip. When this pin is high, internal connections are enabled, and pins A21 through B19 can be used.

32K_OSC_IN B17 IA 32 KHz crystal oscillator input

32K_OSC_OUT A22 OA 32 KHz crystal oscillator output

Table 2-1 Pin description (cont.)


80-Y9047-3 Rev. A 26


GPIO

GPIO[0] A11 I/O General purpose input/output. The QCA4010 supports a USB interface as well as an RGMII interface. The QCA4010 can be configured to support any of these interfaces by tying certain inputs externally.See Interface Selection by GPIO Bootstrap Pins (GPIO0-GPIO5) for more information on GPIOs and interface options.

GPIO[1] B9 I/O

GPIO[2] B8 I/O

GPIO[3] A9 I/O

GPIO[4] B7 I/O

GPIO[5] A8 I/O

GPIO[6] B6 I/O

GPIO[7] A7 I/O

GPIO[8] B5 I/O

GPIO[9] B4 I/O

GPIO[10] A5 I/O

GPIO[11] B3 I/O

GPIO[12] A4 I/O

GPIO[13] B2 I/O

GPIO[14] A3 I/O

GPIO[16] A64 I/O

GPIO[17] A62 I/O

GPIO[18] A1 I/O

GPIO[19] A2 I/O

GPIO[20] B51 I/O

GPIO[21] A61 I/O

GPIO[22] B50 I/O

GPIO[23] A60 I/O

GPIO[24] B48 I/O

GPIO[25] A58 I/O

GPIO[26] B47 I/O

GPIO[27] A33 I/O

GPIO[30] B25 I/O

GPIO[31] A29 I/O

GPIO[32] B24 I/O

GPIO[33] A28 I/O

GPIO[34] B23 I/O

GPIO[35] A27 I/O

GPIO[36] B22 I/O

GPIO[37] B21 I/O



80-Y9047-3 Rev. A 27


GPIO[38] A25 I/O

GPIO[39] B20 I/O

GPIO[40] A24 I/O

DVDD12 B1, B11, B15, B26, B31, B49

P Digital 1.2 V power supply, should be connected to the SWREG_FB pin.

SWREG_FB_DVDD12

B12 P Reference feedback voltage to the internal switching regulator or LDO

VDD_1P8_OUT A21 P 1.8 V LDO output, connect to a > 1 µF bypass capacitor on the board

VDD12_BB_PLL B36 P Analog 1.2 V power supply, should be connected to the SWREG_FB pin.

VDD12_RF B41 P

VDD12_SYNTH B37 P

VDD33_ANT A39 P Analog 3.3 V power supply

VDD33_RF B45 P

VDD33_PLL_XTAL B35 P

VDD33_SYNTH A44 P

VDD33_PMUUSB A18 P 3.3 V power input for PMU and USB PHY

VDD33_ADC A36 P 3.3 V power for application ADC

VDDIO_SDIO_1 A6 P I/O power of GPIO[0] ~GPIO[13], provided by host in hosted design, connect to other IO power in hostless design

VDDIO_SDIO_0 A10 P

VDDIO_SDIO_PMU A12 P 3.3 V power input for SDIO power domain regulator

VDD33_IOT B16 P 3.3 V power input for wakeup manager

GPIO_IOE[2] B18 I/O GPIO in wakeup manager power domain

GPIO_IOE[1] A23 I/O

GPIO_IOE[0] B19 I/O

VDDIO_GPIO_3 A26 P I/O power for GPIO[34] ~ GPIO[40]; it can be 1.8 V or 3.3 V. These GPIOs are mainly for SPI flash

VDDIO_GPIO_2 A30 P I/O power for GPIO[27] ~ GPIO[33], it connects to 3.3 V power supply

VDDIO_GPIO_1 A59 P I/O power for GPIO[14] ~ GPIO[26], it connects to 3.3 V power supply

VDDIO_GPIO_0 A63 P



80-Y9047-3 Rev. A 28


Interface Selection

The QCA4010 supports multiple interfaces including SPI, I2S, I2C, UART, debug UART, and JTAG. It is possible to configure the QCA4010 to support these interfaces by connecting certain inputs externally. See Section 1.17 for information on bootstrap modes and pins.

Table 2-2 and Table 2-3 illustrate examples interface selection by GPIO bootstrap pins.

ADC[0] A38 I Application ADC inputs

ADC[1] B30 I

ADC[2] A37 I

ADC[3] B29 I

ADC[4] B28 I

ADC[5] A35 I

ADC[6] A34 I

ADC[7] B27 I

Ground

GND – P Exposed ground pad (Mechanical Information)

NC

NC B13, A17, B14, A31, A32, A45, A48, A49, A52, A53, A56, A57, B39, B40, B42, B43, B44, B46,

B52

Not connected pins

Table 2-2 Interface Selection by GPIO Bootstrap Pins (GPIO0-GPIO5)

GPIO Bootstrap [GPIO4, GPIO0]=01SPI Function Enabled

GPIO[0] SPI_CS

GPIO[1] SPI_MOSI

GPIO[2] GPIO/LED

GPIO[3] SPI_INT

GPIO[4] SPI_MISO

GPIO[5] SPI_CLK



80-Y9047-3 Rev. A 29


Table 2-3 Interface Selection by Firmware Configuration

GPIO Alternate FunctionAlternate Function

Alternate Function

Alternate Function

Alternate Function

Alternate Function

GPIO[0] SPIM_CS SPIM_CS SDIO_CMD SPI_CS – –

GPIO[1] SPIM_MOSI SPIM_MOSI SDIO_D3 SPI_MOSI – ST_RF_ACTIVE

GPIO[2] UART2_RXD UART2_RXD SDIO_D2 GPIO/LED UART2_TXD ST_RF_STATUS

GPIO[3] UART2_TXD UART2_TXD SDIO_D1 SPI_INT UART2_RXD ST_RF_FREQ

GPIO[4] SPIM_MISO SPIM_MISO SDIO_D0 SPI_MISO UART2_RTS ST_RF_REQACK

GPIO[5] SPIM_CLK SPIM_CLK SDIO_CLK SPI_CLK UART2_CTS –

GPIO[6] PWM[0] PWM[0] PWM[0] PWM[0] SPIM_MISO –

GPIO[7] PWM[1] PWM[1] PWM[1] PWM[1] SPIM_MOSI –

GPIO[8] PWM[2] PWM[2] PWM[2] PWM[2] SPIM_CS –

GPIO[9] PWM[3] PWM[3] PWM[3] PWM[3] SPIM_CLK I2S_BCLK0

GPIO[10] PWM[4] I2CS_SCK0 I2CS_SCK0 PWM[4] PWM[4] I2S_SDI0

GPIO[11] PWM[5] I2CS_SDA0 I2CS_SDA0 PWM[5] PWM[5] I2S_SDO0

GPIO[12] PWM[6] BT_FREQUENCY

BT_FREQUENCY

PWM[6] PWM[6] I2S_WS0

GPIO[13] PWM[7] BT_ACTIVE BT_ACTIVE PWM[7] PWM[7] I2S_MCLK0

GPIO[14 ] I2CM_SDA1 BT_PRIORITY

BT_PRIORITY

I2CM_SDA1 I2CM_SDA1 I2S_BCLK1

GPIO[16] I2S_BCLK0 I2S_BCLK0 I2S_BCLK0 I2S_BCLK0 I2S_BCLK0 I2S_SDI1

GPIO[17] I2S_SDI0 I2S_SDI0 I2S_SDI0 I2S_SDI0 I2S_SDI0 I2S_SDO1

GPIO[18] I2S_SDO0 I2S_SDO0 I2S_SDO0 I2S_SDO0 I2S_SDO0 I2S_WS1

GPIO[19] I2S_WS0 I2S_WS0 I2S_WS0 I2S_WS0 I2S_WS0 I2S_MCLK1

GPIO[20] I2S_MCLK0 I2S_MCLK0 I2S_MCLK0 I2S_MCLK0 I2S_MCLK0 BT_FREQUENCY

GPIO[21] HSUART_RTS/CTS

HSUART_RTS/CTS

HSUART_RTS/CTS

HSUART_RTS/CTS

HSUART_RTS/CTS

BT_ACTIVE

GPIO[22] HSUART_CTS/RTS

HSUART_CTS/RTS

HSUART_CTS/RTS

HSUART_CTS/RTS

HSUART_CTS/RTS

BT_PRIORITY

GPIO[23] HSUART_RXD/TXD

HSUART_RXD/TXD

HSUART_RXD/TXD

HSUART_RXD/TXD

HSUART_RXD/TXD

WLAN_ACTIVE

GPIO[24] HSUART_RXD/TXD

HSUART_RXD/TXD

HSUART_RXD/TXD

HSUART_RXD/TXD

HSUART_RXD/TXD

–

GPIO[25] I2CM_SDA0 I2CM_SDA0 I2CM_SDA0 I2CM_SDA0 I2CS_SDA0 –

GPIO[26] I2CM_SCK0 I2CM_SCK0 I2CM_SCK0 I2CM_SCK0 I2CS_SCK0 –

GPIO[27] I2S_BCLK1 I2S_BCLK1 I2S_BCLK1 I2S_BCLK1 I2S_BCLK1 –

80-Y9047-3 Rev. A 30


GPIO[30] I2S_SDI1 I2S_SDI1 I2S_SDI1 I2S_SDI1 I2S_SDI1 ST_RF_ACTIVE

GPIO[31] I2S_SDO1 I2S_SDO1 I2S_SDO1 I2S_SDO1 I2S_SDO1 ST_RF_STATUS

GPIO[32] I2S_WS1 I2S_WS1 I2S_WS1 I2S_WS1 I2S_WS1 ST_RF_FREQ

GPIO[33] I2S_MCLK1 I2S_MCLK1 I2S_MCLK1 I2S_MCLK1 I2S_MCLK1 ST_RF_REQACK

GPIO[34] SPIM_CLK SPIM_CLK SPIM_CLK SPIM_CLK – –

GPIO[35] SPIM_CS0 SPIM_CS0 SPIM_CS0 SPIM_CS0 – –

GPIO[36] SPIM_DIO0 SPIM_DIO0 SPIM_DIO0 SPIM_DIO0 – –




GPIO[40] SPIM_CS1 SPIM_CS1/ SPIM_CS1 SPIM_CS1 CLKOBS ADC_HW_TRIG

Table 2-3 Interface Selection by Firmware Configuration (cont.)

GPIO Alternate FunctionAlternate Function

Alternate Function

Alternate Function

Alternate Function

Alternate Function

80-Y9047-3 Rev. A 31

3 Electrical Characteristics

This information will be included in future revisions of this document.

80-Y9047-3 Rev. A 32

4 Mechanical Information

4.1 Device physical dimensionsThe QCA4010 device is available in the 9 mm × 9 mm × 0.9 mm Dual-Row Quad Flat pack No-lead (DRQFN) package that includes a ground pad for improved grounding, mechanical strength, and thermal continuity. Pin 1 is located by an indicator mark on the top of the package.

Figure 4-1 shows the QCA4010 device mechanical dimensions, top and bottom views.

80-Y9047-3 Rev. A 33

QCA4010 Low-Energy Wi-Fi Single-Band 802.11b/g/n SoC Device Specification (Preliminary Information) Mechanical Information

Figure 4-1 QCA4010 mechanical dimensions, top and bottom views

Table 4-1 Package A dimensions 1

Dimension label Min Nom Max Unit

A 0.80 0.85 0.90 mm

A1 0.00 0.0 0.05 mm

A2 0.65 0.70 0.75 mm

80-Y9047-3 Rev. A 34


A3 0.15 REF mm

b 0.18 0.22 0.30 mm

D/E 8.90 9.00 9.10 mm

D1/E1 8.75 BSC mm

D2 5.10 5.20 5.30 mm

E2 4.74 4.84 4.94 mm

D3/E3 3.775 BSC mm

eT 0.50 BSC mm

eR 0.55 BSC mm

L 0.25 0.35 0.45 mm

θ 5 – 15 °

R 0.09 – 0.14 mm

K 0.20 – – mm

aaa 0.10 mm

bbb 0.10 mm

ccc 0.10 mm

ddd 0.05 mm

eee 0.08 mm

fff 0.10 mm

ggg 0.20 mm

1. Reference document: NT90-Y8665-D1

Table 4-1 Package A dimensions 1

Dimension label Min Nom Max Unit

80-Y9047-3 Rev. A 35


Figure 4-2 QCA4010 Package B dimension

Table 4-2 Package B dimensions10

Dimension label Min Nom Max Unit Note

A 0.80 0.85 0.90 mm

A1 0.00 0.01 0.05 mm 8

A2 0.55 0.60 0.65 mm

80-Y9047-3 Rev. A 36


A3 0.25 REF mm

eT 0.50 BSC mm

eR 0.55 BSC mm

N 116 mm 3

La 0.25 0.35 0.45 mm

Lb 0.25 0.35 0.45 mm

b 0.18 0.22 0.30 mm 4

θ – – 12 °

P 0.24 0.42 0.60 mm

1. Die thickness allowable is 0.305mm maximum.2. Dimension & tolerances conform to ASME Y14.5M – 1994.3. N is the number of terminal.

NDa, NDb are the number of terminals in X-direction &NEa, NEb are the number of terminals in Y-direction.

4. Dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip.5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or

other feature of package body.6. Exact shape and size of this feature is optional.7. All dimensions are in millimeters.8. Bilateral coplanarity zone applies to the exposed pad as well as the terminals.9. Applied only for terminals.10. Reference document: NT90-Y8665-C1.

Table 4-2 Package B dimensions10

Dimension label Min Nom Max Unit Note

80-Y9047-3 Rev. A 37


4.2 Part marking

4.2.1 Specification-compliant devices

Figure 4-3 QCA4010 device marking

Table 4-3 Package marking line description

Line Marking Description

Logo 1 and Logo 2 Q Qualcomm Atheros logo

Line P1 QCA4010 Qualcomm Atheros product name

Line P2 PBB P = product configuration code See Table 4-4 for assigned values.BB = feature code See Table 4-4 for assigned values.

Line E Blank space between Line P2 and Line T1

Line T1 FXXXXXXX F = source of supply code F = F (TSMC)XXXXXXX = traceability number

Line T2 ASYWWRR A = assembly site code A = K (SPIL, Taiwan) A = U (Amkor, ATC, China)S = traceability numberY = single/last digit of yearWW = 2 digit work week of current yearRR = product versionSee Table 4-4 for assigned values.

Logo 1

Logo 2

Line P1

Line P2

Line E

Line T1

Line T2

Q C A 4 0 1 0

P B B

F X X X X X X X

A S Y W W R R

Pin 1 identifier

80-Y9047-3 Rev. A 38


4.3 Device ordering informationFigure 4-4 shows the form of ordering numbers.

Figure 4-4 Device identification code

Device identification details for all sample available to date are summarized in Table 4-4.

Table 4-4 Device identification details

DeviceProduct

configuration code (P)

Product revision (RR)

Sample type

Hardware version

Shipping package S value

1

1. S is the source configuration code that identifies all the qualified die fabrication-source combinations available at the time a particular sample type was shipped. S values are defined in Table 4-5.

BB value2

2. BB is the feature code that identifies an IC’s specific feature set, which distinguish it from other versions or variants.

QCA4010 0 00 Pre-ES 1.0 TR = tape and reel

0 VV

0 00 Pre-ES 1.0 MT = matrix tray

0 VV

1 00 Pre-ES 1.0 TR = tape and reel

0 VV


0 VV


0 VV


0 VV


0 VV


0 VV

Table 4-5 Source configuration code

S value Die F value = F

0 Digital TSMC

Device ID code

Symbol definition

Example

- PAAA-AAAA - CCC DDDDDD - RR- EE - S - BB

Config codeProduct name

Number of pins

Package type

Product revision

Shipping package

Source code

Feature code

- 0QCA-4010 - 116 BDRQFN - 00- TR - 0 - VV

Feature code (BB) may not be included when identifying older devices.

80-Y9047-3 Rev. A 39


Table 4-6 shows the available ordering numbers.

4.4 Device moisture-sensitivity levelPlastic-encapsulated surface mount packages are susceptible to damage induced by absorbed moisture and high temperature. A package’s moisture-sensitivity level (MSL) indicates its ability to withstand exposure after it is removed from its shipment bag, while it is on the factory floor awaiting PCB installation. A low MSL rating is better than a high rating; a low MSL device can be exposed on the factory floor longer than a high MSL device.

Qualcomm Atheros follows the latest IPC/JEDEC J-STD-020 standard revision for moisture-sensitivity qualification. The QCA4010 is classified as MSL3; the qualification temperature was 255ºC.

4.5 Thermal characteristics

Table 4-6 Ordering numbers

Chip variant Ordering number Hardware version DescriptionWorking

temperature

QCA4010-0 QCA-4010-0-116BDRQFN-MT-00-0 v1.0 2.4G; 1x1; Single-band concurrent; 802.11n; USB, SDIO; 1MB RAM; C-Temp

0 to 70°C

QCA-4010-0-116BDRQFN-TR-00-0

QCA4010-1 QCA-4010-1-116BDRQFN-MT-00-0 v1.0 2.4G; 1x1; Single-band concurrent; 802.11n; USB, SDIO; 1MB RAM; E-Temp

-40 to 115°C

QCA-4010-1-116BDRQFN-TR-00-0

QCA4010-2 QCA-4010-2-116BDRQFN-MT-00-0 v1.0 2.4G; 1x1; Single-band concurrent; 802.11n; USB, SDIO; 1.5MB RAM; C-Temp

0 to 70°C

QCA-4010-2-116BDRQFN-TR-00-0

QCA4010-3 QCA-4010-3-116BDRQFN-MT-00-0 v1.0 2.4G; 1x1; Single-band concurrent; 802.11n; USB, SDIO; 1.5MB RAM; E-Temp

-40 to 115°C

QCA-4010-3-116BDRQFN-TR-00-0

Table 4-7 Device thermal resistance

Parameter Comment Typ Unit

θJA Junction-to-Ambient With thermal vias JESD51-2A, JESD51-7

25.7 °C/W

Psi_jt Junction-to-top-center of the package thermal resistance

With thermal vias JESD51-2A, JESD51-7

0.245 °C/W

θJB Junction-to-Board No thermal vias JESD51-7, JESD51-8

17.4 °C/W

θJC Junction-to-Case No thermal vias JESD51-7, JESD51-8

5.8 °C/W

80-Y9047-3 Rev. A 40

5 Carrier, Storage, and Handling Information


80-Y9047-3 Rev. A 41

6 PCB Mounting Guidelines


80-Y9047-3 Rev. A 42

7 Part Reliability


¤ﬂD@¡�IÿU½�'A¹tÚ°ŁIÅ‹·€é �,¿dT�HÆ-Åâ‰ RÜ�JÁÆP€�¥ ��àÉ−ô� 6ÄO%�¥˛I‚95Y£

Documents

QCA4010 Low-Energy Wi-Fi Single-Band 802.11b/g/n SoCimg.cecport.com/product/product/files/201511/ff... · 2015-11-04 · QCA4010 Low-Energy Wi-Fi Single-Band 802.11b/g/n SoC Device