RDHCS12E128UPSPPT

8/17/2019 RDHCS12E128UPSPPT

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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product

or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2!.

TM

Single Phase On-Line UPS Demo

Using MC9S12E128


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"# Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product

or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2!.Slide2

$ %ased on the topology the &'Ses are classified to the three (asic

categories )I*+ 2-/01 'assive Stand(y )ffline0

3ineinteractive

4ou(le +onversion )n3ine0

UPS Classification


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D C

A C

5 6

7

D C

A C

56

L I E ! I L T E "

# A T T E " $

C % A " & E "

# A T T E " $

I ' E " T E "

S ( I T C %

8 o r m a l o p e r a t i o n% a c k u p o p e r a t i o n

A)*antages+

9ery low cost

:igh efficiency

+ompact si;e

A)*antages+

9ery low cost :igh efficiency

+ompact si;e

Disa)*antages+

3imited protection

8ot sinusoidal output &ses (attery during

(rownouts Short dropout during

transition on (attery

Disa)*antages+

3imited protection

8ot sinusoidal output

&ses (attery during(rownouts

Short dropout during


MCU+ #+


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DC

AC

5 6

7

DC

AC56

#ATTE"$C%A"&E"

#ATTE"$

I'E"TE"

S(ITC%

#$PASS

8ormal operation%ackup operation

LIE !ILTE" A'"

A)*antages+ #edium cost

:igh efficiency

%etter voltage

conditioning

A)*antages+

#edium cost :igh efficiency

%etter voltage

conditioning

Disa)*antages+

Still limited protection Short dropout during


Disa)*antages+

Still limited protection Short dropout during

transition on (atteryMCU+ #+


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7

" E C T I ! I E "

# A T T E " $

C % A " & E "

# A T T E " $

D C - D C

C O ' E " T E "

# $ P A S S

D C

6D C

6D C

6D C

6

D C

A C

56

I ' E " T E "

8 o r m a l o p e r a t i o n% a c k u p o p e r a t i o n

A)*antages+

*>cellent voltageconditioning

Full protection

A)*antages+

*>cellent voltageconditioning

Full protection

Disa)*antages+

:igh cost 3ow efficiency

Disa)*antages+

:igh cost

3ow efficiency Possi/le MCU+ :+S@2*@2< 4S'!F 4S'!F>4S'!F>

Possi/le MCU+ :+S@2*@2< 4S'!F 4S'!F>4S'!F>

#asic UPS To,olog - On-Line UPS


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Single Phase On-Line UPS Demo Using MC9S12E128

Single Phase On-Line UPS DemoUsing MC9S12E128


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$ 4emo Features

Single 'hase nline "opology

! 9A utput 'ower

@@!B2/ 9 Input 3ine

+ontrolled (y #+=S@2*@2<

Single 3*4 &ser Interface

C0 Stats LEDsC LEDs #a. &.a,hC2 #ttons

Draphical &ser Interface on '+

?eady for D&I 4isplay

4emo suitcase


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$ 4emo +oncept

Four '+%sCUPS Po3e. StageCIn,t !ilte. CUse. Inte.faceCMC9S12E128

Cont.ol #oa.)

4emo case


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$ +oncept Schematic

D84

3@4@

4!

- +

42E%&. utput 'ower1

$/ J State +harging Algorithm )%ulk charge,

A(sorption, Float0 controlled (y #+&

P!C$ Average +urrent #ode 'F+$4irectly controlled (y #+&

P!C$ Average +urrent #ode 'F+$4irectly controlled (y #+&

In,t "ectifie. $9oltage 4ou(ler

In,t "ectifie. $9oltage 4ou(ler

Ot,t In*e.te. $"rue Sinusoidal utput$4irectly controlled (y #+&

Ot,t In*e.te. $"rue Sinusoidal utput$4irectly controlled (y #+&

DC-DC Ste, U, Con*e.te.

$'ush 'ull +onverter

$4irectly +ontrolled (y #+&

$#a>. utput 'ower1 !

DC-DC Ste, U, Con*e.te.

$'ush 'ull +onverter

$4irectly +ontrolled (y #+&

$#a>. utput 'ower1 !

(hole UPS cont.olle) / one MC9S12E128 onl(hole UPS cont.olle) / one MC9S12E128 onl



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$ #+=S@2*@2< Features

@(it :+S@2 +'&, ! #:; core clock

@2 II+

/ > -channel @(it timer modules )"I#0

channel @!(it 'ulse #odulator with Fault protection module

)'#F0 channel @channel additional e>ternal asynchronous interrupts

&p to - IB port pins and @< input only pins for @@2 pin package

&p to -2 IB port pins and @< input only pins for


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$ %attery +harger

Fly%ack "opology +onverter

4edicated circuit used )"'2-=0

utput parameters

COt,t *oltage+ 2940 o. 2540 ' 6set / MCU7COt,t c..ent+ ma4 148 A

CC..ent limitation+ : 148 A 6set / MCU7+harge algorithm

C; state 6/l< cha.ge= a/so.,tion= float7#+& Interface

C2 analog in,ts 6/atte. *oltage an) /atte. c..ent7C1 analog ot,t 6P(M > filte.= c..ent limitation7C1 )igital ot,t 6ot,t *oltage 2940 o. 2540 '7

Single Phase On-Line UPS Demo Using MC9S12E128- %( Im,lementation


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$ %attery +harger Schematic

8

I%A"K+8"?3

9%A"

4

D

SG/@##%F2@83"@

D84A

:9K%A"K3*9*3

I%A"

9%A"

+/@-

@n

?//@@

D84

D84K+:

D84K+:

D84K+:

D84

3/@

-u:

G/

%+


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$ %attery +harging Algorithm

/ Step +harging1 %ulk, A(sorption, Float


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$ 4+B4+ Step &p +onverter

+onverts the (attery voltage )2- 90 to 4+ (us voltage

)7B /=90

'ush'ull "opology

! k:; switching freMuency

Fully controlled (y #+&utput parameters

COt,t 'oltage+ >?- ;9 'COt,t C..ent+ 48 A

#+& interfaceC2 analog in,ts 6>?- DC /s *oltage7C2 P(M ot,ts 6P(M fo. t.ansisto.s7


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$ 4+B4+ Step &p +onverter Schematic

ut%In%

D84

InA

8+ 8+

utA

9++&! #+//@!24

2

/

!

,


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$ Input ?ectifier 7 'ower Factor +orrection )'F+0

9oltage dou(ler rectifier 'F+ using (idirectional switch )one transistor only0 +ontrol techniMue

CA*e.age C..ent Mo)e Cont.ol / MCUC0


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$ Input ?ectifier 7 'F+ +ontroller Schematic

+ +,<//uFB-!9

G,<

:D"D@8@2%84

G,!

:D"D@8@2%84+,/

#E'@B22nFB,/94+

+,

#E'@B22nFB,/94+

3!!

2.!m:

- +

4,,E%'+,,

G,,

I?D-I%+2

DA"*K'F+

D84

4,-

?:?'


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$ utput Inverter

:alf (ridge topology

2 k:; switching freMuency

+ontrol techniMue

C!ll cont.olle) / MCUCPID cont.olle. > *oltage fee) fo.3a.) > c..ent

fee)/ac<

CB s cont.ol loo, utput parameters

COt,t 'oltage+ 11 - 20 'COt,t c..ent+ ;4; A

#+& Interface

C0 analog in,t 62 DC /s *oltage= 1 ot,t c..ent=1 ot,t *oltage7

C2 P(M ot,ts 6in*e.te. t.ansisto.s7


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$ utput Inverter Schematic

+ +,<//uFB-!9

G,<

:D"D@8@2%84

G,!

:D"D@8@2%84+,/

#E'@B22nFB,/94+

+,

#E'@B22nFB,/94+

+,!

/./uFB-9

3!,

,m:

IK&"@IK&"2

< !

@ 2 / -

+"2

+S2@,

4,-

?:?'


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$ #+=S@2*@2< +ontrol %oard

#+=S@2*@2< @(it 7!9 #icrocontroller operating at 2!#:;

ptically isolated ?S2/2 interface

+ommunication :eader )S'I, S+I@, II+0

'# and "imer :eader CPlse (i)th Mo)lation= P(M= o. Time.2= TIM2 Time.1= TIM1

A4+ and 4A+ :eader

CAnalog-to-Digital Con*e.te.= ADCCDigital-to-Analog Con*e.te.= DAC E,ansion %ea)e. fo. 1-/it

Mlti,lee) (i)e #s

n(oard power regulation from an e>ternal @29 4+ supplied

power input


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$ #+=S@2*@2< +ontrol %oard continue

3ight *mitting 4iode )3*40 power indicator

ne on(oard realtime user de(ugging 3*4s

Si> on(oard '# monitoring 3*4s

Si> on(oard '#F monitoring 3*4s

Four on(oard '#F Fault monitoring 3*4s

&8I/ #otor interface

ver9oltage sensing

ver+urrent sensing

+omparators for automatic current profiling

*ncoderB:all*ffect interface

#anual ?*S*" push(utton

Deneral purpose and interrupt toggle switch

2> Deneral purpose and interrupt push(utton


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$ #+=S@2*@2< +ontrol %oard J %lock 4iagram

MC9S12E128

&8I/ *>pansion

+onnector

4igital

*>pansion:eaders

%4#

+onnector

*ncoder

+onnector

2 > ?S2/2Interface

/./9 Analog

?eference

!9 Analog

'ower Supply

!9 4igital'ower Supply


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Single Phase On-Line UPS Demo Using MC9S12E128- S( Im,lementation

$ Software Structure

!> periodical interrupts )2> ! µs, @> @ ms, @> @ ms, @> !ms0/> event interrupts )'#F faults, 39I, S+I0

%ackground loop

ritten in + language

Some critical algorithms written in assem(ler )sine wavegeneration, 'I4 controllers, arithmetic functions0

S O S C S


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$ Software Structure continue

Si l Ph O Li UPS D U i MC9S12E128


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$ Software Structure continue



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$ %attery +harger

Execution period: 50 ms



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$ 4+B4+ Step &p +onverter




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$ 'ower Factor +orrection


Execution period: 50 s



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$ utput Inverter


Execution period: 50 s



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$ Application State #achine

Single Phase On Line UPS Demo Using MC9S12E128


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Single Phase On-Line UPS Demo Using MC9S12E128- Soft3a.e Meas.ements

$ &'S Software #easurements

+ode 3engthCF3AS: memory1 @


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Single Phase On-Line UPS Demo Using MC9S12E128- Soft3a.e Meas.ements

$ &'S Software #easurements continues

PM! "eloa)

ATD Com,lete

TIM chB OC

TIM ch OC



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Single Phase On-Line UPS Demo Using MC9S12E128- Pe.fo.mance Meas.ements

$ 3oad defined (y I*+ 2-@

3inear load )!2! 0C? 6 @ Ω

8onlinear load )! 9A0

C? 6 @ Ω

C?s 6 2.< ΩC+ 6


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$ verall efficiency J linear load



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$ verall efficiency J nonlinear load



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"# Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other productor service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2!.

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$ utput freMuency synchroni;ed



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$ utput freMuency J free running



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$ utput 9oltage ":4 J without load



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$ utput 9oltage ":4 J with linear load



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$ utput 9oltage ":4 J with nonlinear load



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Single Phase On Line UPS Demo Using MC9S12E128- Pe.fo.mance Meas.ements




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$ Input 'ower Factor



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$ utput 'ower Factor )linear load0



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$ 3oad Step 2 P C @ P



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$ 3oad Step 2 P C @ P



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$ 3oad Step @ P C 2 P



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g g- Pe.fo.mance Meas.ements

$ 3oad Step @ P C 2 P



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g g- Pe.fo.mance Smma.

"opology nline )dou(le conversion0

Input 9oltage @29, .2 Ah

D&I 2 > (uttons, @> 3*4s

?emote control From '+ (y '+ #aster

+ommunication 2> ?S2/2



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g g- De*elo,ments tools

$ Free#aster

?eal time monitor ?ead and write any varia(le in application

4isplay the varia(les in physical Muantities

Scope

?ecorder

+ontrol page in :"#3 code



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Sco,e o. .eco.)e.

'a.ia/les 3in)o3



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Cont.ol ,age



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$ ?eference 4esign 4elivera(les

4esign documentation )source and '4F0 "argeting documentation )source and '4F0

Application note

'resentation #aterial

All source code and related material for written software

'+% layout ger(er files )source and '4F0

Schematic files )source and '4F0

%# )source and '4F0

g g- Deli*e.a/les


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"#

Slide !-

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other productor service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2!.

estions an)estions an)Ans3e.sAns3e.s

Than


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Slide

Than

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RDHCS12E128UPSPPT