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Reduced Instruction Set Computing Ammi Blankrot April 26, 2011 (RISC)

Reduced Instruction Set Computing

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Ammi Blankrot April 26, 2011. Reduced Instruction Set Computing. (RISC). Before Compilers. Programming was done mainly in machine code or assembly code. Programming was very tedious. - PowerPoint PPT Presentation

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Page 1: Reduced Instruction Set Computing

Reduced Instruction Set Computing

Ammi BlankrotApril 26, 2011

(RISC)

Page 2: Reduced Instruction Set Computing

Before Compilers

Programming was done mainly in machine code or assembly code.

Programming was very tedious.

To make programming easier, more and more complex instructions were created (The more tasks one instruction could perform, the less number of instructions was needed which sped up the program)

Page 3: Reduced Instruction Set Computing

Computers had very little memory

A lot of information was packed into the programs Instructions of variable size, instructions which

perform multiple operations, instructions that both moved data and performed data computations, and therefore instructions that varied in cycle times

The ability to pack instructions densely was considered more important than instruction decodability

Page 4: Reduced Instruction Set Computing

Register count was small

Bits in registers are more expensive than external memory, and would have been difficult to include in large numbers due to technology limitations

More registers require more instruction bits which requires more memory which was expensive at the time

Page 5: Reduced Instruction Set Computing

Result:

Each instruction was designed to do as much work as possible:

Different versions for the same instruction were created: One instruction could load up two numbers, add them, and store the

result back to memory

Another version of that instruction would do the same, but store the result in a register

Yet another version would read one number from memory, the second from register, and write the result back to memory

This design philosophy became known as CISC (Complex Instruction Set Computer).

Page 6: Reduced Instruction Set Computing

Orthogonality

The goal was to provide every possible variation of every instruction. This principle is known as ”Orthogonality” and leads to complexity on the CPU (On the Hardware)

Page 7: Reduced Instruction Set Computing

Compilers Arrive

A compiler is a computer program (or set of programs) that transforms source code written in a programming language (High Level) into another computer language (Low level, often having a binary form known as object code). The most common reason for wanting to transform source code is to create an executable program.

The greatest benefit to the use of compilers is the ability to re-use code.

The majority of programming began to shift more towards software and less in hardware

Page 8: Reduced Instruction Set Computing

Limited use of CISC by Compilers

In the late 1970s researchers at IBM demonstrated that the majority of the orthogonal instructions were being ignored.

Compilers were gaining steam, and they only had a limited ability to make full use of CISCs orthogonal capabilities

Extremely specific instructions were found to be slower than the more general instructions doing the same thing

Page 9: Reduced Instruction Set Computing

Compiler use It is hard for a compiler to exploit a CISC

instruction because it must find the exact specific variation of the instruction that fits the current situation. On the other hand it is quite easy for the compiler to optimize a RISC instruction which is smaller and more general and can fit many different situations

Even with the use of CISC the compiler tends to only go for the more general instructions of the CISC and not bother with the more specific, complex ones which become a “waste” when compilers are utilized

Page 10: Reduced Instruction Set Computing

CPU speedup

CPUs started to run faster than the memory they used To support the higher CPU speeds, more registers

were needed Additional registers would require more space on the

chip This space could be created by reducing the

complexity of the CPU

Page 11: Reduced Instruction Set Computing

Simple Operations

Research has shown that real world programs spend most of their time executing simple operations

The focus shifted to making these common operations as simple and fast as possible

The goal was to make instructions so simple, each could be fully completed in a single clock cycle.

Page 12: Reduced Instruction Set Computing

RISC vs. CISC

The focus on ”reduced instructions” led to the result being called ”reduced instruction set computer”(RISC)

Over time, the old design technique became known as Complex Instruction Set Computer(CISC)

Page 13: Reduced Instruction Set Computing

RISC

Instead of a single complex instruction, code was implemented as a series of smaller instructions

This left more room in the instruction for data

Unfortunately, this also meant that the total number of instructions that needed to be read from memory for any single program is larger, and takes longer.

Page 14: Reduced Instruction Set Computing

More Speed

In an attempt to speed up processors, the ideas of having pipelined and superscalar processors were conceived

Because of the streamlining of the RISC architecture, RISC chips easily took advantage of these new techniques

The complexity of CISC architecture kept CISC chips from immediately taking advantage of the new technology.

Page 15: Reduced Instruction Set Computing

Side by Side

CISC

Complexity found in hardware

Memory-to-memory : load and store functionality found in a single instruction

Less lines of code needed to provide same functionality

RISC

Complexity on software side

Register-to-Register : load and store are separate instructions

More instructions necessary to provide same functionality

Page 16: Reduced Instruction Set Computing

Side by Side (Continued)

CISC

Instructions not always the same size

Instructions are difficult to decode because instructions are not uniform

To make use of pipelining, instructions need to be broken down to smaller components at processor level

RISC

All instructions of a uniform size with more or less uniform timing cycle

Instructions are easier to decode because of how they are set up-ex: opcode will always be in the same place

Capable of using pipelining by design

Page 17: Reduced Instruction Set Computing

Pipelining

Some people call pipeline a well-coordinated assembly-line

It allows the next instruction to be loaded and processed before the previous instruction completed. In other words, several instructions can be processed at the

same time speeding up the process.

The time uniformity of RISC allows it to take advantage of pipelining, which is one of the reasons for it gaining popularity over CISC.

Page 18: Reduced Instruction Set Computing

Analogy:

Imagine Michael Jordan playing against a team all by himself.

Who will win ?

Possibilities:

1)The team is not very well trained or coordinated and the timing of their actions are inconsistent. Michael Jordan is so talented and could probably win the game

2)The team is very well trained and coordinated. They work well together and have been coached very well. None of them is quite as talented as Michael Jordan but since they know how work together as a team, more than likely they will win the game

Page 19: Reduced Instruction Set Computing

Analogy (continued)

Without pipelining CISC would win over RISC just like Michael Jordan would win over an uncoordinated team. A CISC instruction, like Michael Jordan, is very “talented”: One large robust instruction that can achieve many things

With pipelining RISC would win over CISC just like a well trained team would overcome the Michael Jordan of CISC being able to more efficiently carry out the instructions with each one carrying out a simple task

Page 20: Reduced Instruction Set Computing

RISC (A general definition from the Book)

o A large number of general purpose registers and /or the use of compiler technology to optimize register usage (A greater number of simpler instructions requires a greater number of registers to hold temporary data and instructions)

o A limited and simple instruction set

o An emphasis on optimizing the instruction pipeline

Page 21: Reduced Instruction Set Computing

Characteristics of RISC

o One Instruction per cycle

o Register to Register operations

o Simple addressing modes

o Simple instruction formats

Page 22: Reduced Instruction Set Computing

What is driving the popularity of RISC over CISC ?

o Over time: Hardware costs go down while Software costs go up

o This has inspired researchers to use an approach that makes the architecture that supports the high level languages simpler (RISC)

o A larger number of simpler instructions requires more hardware (registers and memory) but provides more simplicity and uniformity that eases software development and compiler optimizations

o A larger number of registers also enables localization of data in the CPU and the reduction of memory references which are slower.

Page 23: Reduced Instruction Set Computing

RISC vs. CISC RevisitedAfter the initial enthusiasm for RISC machines,

there has been a growing realization that

1) RISC designs may benefit from the inclusion of some CISC features

2) CISC designs may benefit from the inclusion of some RISC features.

The result is that more recent designs have combined some RISC and CISC features together.

Some people call these systems: CRISC

Page 24: Reduced Instruction Set Computing

Analogy (Revisited)

The Chicago Bulls became very successful in the 1990s because they had a combination of a good team (RISC), a good coach (CPU), and they had Michael Jordan (CISC), with the result (CRISC) that they won 6 NBA championships

Page 25: Reduced Instruction Set Computing

References

•http://www.cs.drexel.edu/~wmm24/cs281/lectures/pdf/RISCvsCISC.pdf

•http://en.wikipedia.org/wiki/Reduced_instruction_set_computing

•http://en.wikipedia.org/wiki/Compiler

•Course Textbook: Computer Organization and Architecture, eighth edition, by William Stallings