References DSP vs. FPGA

CHAPTER 2

Introduction to SoC Architecture

1

System design

Requirements for 3G (WCDMA) / 4G (LTE)1. Software

– 3GPP standards: 25.xxx / 36.xxx series

2. Hardware:S d f t i t t– Speed, memory, power, footprint, cost

3. Market demand - Scalability, flexibility:y y– macro, metro, micro, pico, femto – cells

– Multimode (3G/4G in the same chip)Multimode (3G/4G in the same chip)

– Market window (development time)

2

References

• Article on Freescale Small Cell Portfolio http://cache.freescale.com/files/rf_if/doc/white_paper/SMCELLRFWP.pdf

• White paper on Power Architecture technologyhttp://www.freescale.com/files/64bit/doc/white_paper/64BTTCHNLGYWP.pdf

• Beyond DSPs StarCore MSC8xxx and DSP56K Familieshttp://cache.freescale.com/files/dsp/doc/brochure/BYNDDSPBRO.pdf

• QorIQ Qonverge Portfolio Next Generation Wireless• QorIQ Qonverge Portfolio - Next-Generation Wireless Network Bandwidth and Capacity Enabled by Heterogeneous and Distributed Networksg

http://cache.freescale.com/files/32bit/doc/white_paper/QORIQQONVERGEWP.pdf

3

DSP vs. FPGA

DSP FPGA

Elementary digital logic

ALU AGU PCU ALU 1ALU 1ALU 1ALU 2ALU 1

Program

Cfg file

-Flexible architecture-Configure your architecture for the app

-Fixed architecture-Program the usage in time-Imperative programming (how app

-Data flow programming (how thingsconnect)

things happen)

4

DSP vs. FPGA

DSP• Fixed architecture

FPGA• Dedicated HW digitalFixed architecture

• Lower prices and power consumption

Dedicated HW digital solutions (ASICs) are expensive to produceconsumption

• Bad at bit processing • FPGAs offer flexibility at a lower cost than ASIC,

Modern DSP• Multiple processing units

higher than DSP• Large power consumption

Multiple processing units• Multiple cores• HW accelerators for bit-

• Parallel processing• Bit processing

HW accelerators for bit-processing

5

Complex architectures

• Large arrays of small DSPsDistributed processing• Distributed processing

• Example: Picochip™ architecture

Elementary DSP

Hundreds of DSPs running in parallel!

6

Freescale StarCore DSP

Single core Multicoregfully programmable DSP

Aerospace &

fully programmable DSP

Defense

Medical

Test & Measurement

7

StarCore DSP Devices Roadmap

Pi f PiSC

- Basestation- Medical

Production

Next Gen

Pin-for-Pin Compatible

Devices

MSC8156 MSC8154

• 6/4 SC3850 1 GHz+Cores

• MAPLE-B Coprocessor• SRIO PCIe

Sample

• SRIO, PCIe

MSC8256 MSC8254

- Aerospace & Defense- Test & Measurement

Next Gen

• 6/4 SC38501 GHz+ Cores

• SRIO, PCIeMSC8144

• 4 SC3400 1GHz Cores

MSC812x• 4 SC140 300-

500MHz Cores Next GenMSC8152

MSC8252

- Medical- General Purpose

MSC8113/2• 3/2 SC140 300-

400MHz Cores

Next Gen

MSC711x

MSC8151• 2/1 SC3850 1 GHz+ Cores• SRIO, PCIe• MAPLE-B Coprocessor

2010

MSC8251• 2/1 SC3850 1 GHz+ Cores• SRIO, PCIe

Available Now 2011 2012

MSC711x• 1 SC1400 266-

300MHz Core

Planning Execution ProductionProposal Pin for pin compatible Families:

8

Hardware EnablementMSC8156AMC MSC8156 EVM

MSC8156ADS/ MSC8156EADS

MSC8144ADS/ MSC8144AMC-SA ATCA-9100MSC8144ADS/ MSC8144EADS

MSC8122ADSE MSC8126ADSE

MSC711xEVMMSC711xADS

9

StarCore140 DSP

Level-1 Memory Expansion Area S tLevel 1 Memory Expansion AreaUnified Data and Program Memory

ROM, RAM

Star*Core 140 DSP Core

System

External Memory

Expansion Area

Interface

DSP Engine

True 16-bit instruction set DMA

CACHE

Interface

Variable Length Execution Set (VLESTM) ModelCACHE

4 Arithmetic Interrupt Ctrl.

g ( )

Level 2 Memory2 Address

Arithmetic Units& Logic Units

Peripheral and Accelerators Expansion AreaStandard Input/Output Peripherals

Level-2 Memory Expansion

Arithmetic Units& Logic Units

p p pApplication Specific AcceleratorsGeneral Purpose Programmable Accelerator

10

StarCore140 DSP

Quad Access UnifiedData/Program Memory

6464323232128 PAB

PDB

XABA

XDBB

XDBA

XABB

Program Address Generator Data ALU InstructionOnCE™

128

ProgramSequencer

Address GeneratorRegister File

Data ALURegister File

Instruction-setAccelerator

OnCE

PowerManagement

Instruction Bus

2 AAUs 4 ALUs140

BMU 24

ClockGenerator

PLLInstruction Bus 128

11

MSC8113 – Multicore DSP

Boot ROM

MSC8113 Block Diagram

H/W S h

476 KBM2 shared

►Cores• Three SC140 cores @ 300 MHz/400 MHz• 16 KB ICache• 224 KB M1 memory

PLL

St C

ROM

32 Timers

128 Bit MQ Bus

Semaphoresmemory►Shared Memory• 476 KB internal M2 shared memory

►Ethernet• 10/100 FEC w/SMII/RMII

JTAGStarCore

SC140

Memory 32B

itIP

Bus

I2CUARTTDMGPIOGIC

RS232

4 x TDM

Interrupts

StarCore SC140

16KBI Cache

224KBM1 Memory

StarCoreSC140

►Memory Interface• 100/133 MHz, 64/32 bit SRAM interface w/ ECC,

Boot FLASH, SRAM►Host Port

64/32 bit Di t Sl I t f

128 Bit SQ Bus

Memory Controller

3

Direct SlaveInterface

GICEthernet

DSI Port

MII/RMII/SMII

60x compatible

64 Bit Local Bus

64 Bit Internal Local Bus

• 64/32 bit Direct Slave Interface►TDM Highway

• 4 physical ports supporting 256 channels each►16 Channel DMA

P i h l I t f IPMaster

System Interface

Internal System Bus

DMA BridgeSIURegisters

Memory Controller

Sys Bus►Peripheral Interfaces• UART• I2C• Timers• GPIOGPIO• 4 kB Boot ROM• JTAG

►Hardware Semaphores►Technologygy

• 90nmG• 1.1V Core, 3.3 V I/O• 431 FCPBGA (20x20) 0.8 mm pitch RoHS 12


Boot


H/W476 KB

M2 shared

► Cores• Four SC140 cores @ 300MHz/400MHz/500MHz• 16 KB ICache• 224 KB M1 memory Boot

ROM

128 Bit MQ Bus

H/W Semaphores

M2 shared memory► Shared Memory

• 476 KB internal M2 shared memory► Ethernet

• 10/100 FEC w/SMII/RMII

StarCore SC140

PLL

JTAGStarCore

SC140StarCore SC140

32 Timers

Bit

IPB

us I2CUARTTDM

RS232

4 x TDM

16KB 224KB

StarCoreSC140

► Memory Interface• 100/133/167 MHz, 64/32 bit SRAM interface w/

ECC, Boot FLASH, SRAM► Host Port

64/32 bit Di t Sl I t f

128 Bit SQ Bus

Memory Controller 64 Bit Local Bus


32B


GPIOGIC

Ethernet

DSI Port

Interrupts

MII/RMII/SMI

I

16KBI Cache

224KBM1 Memory• 64/32 bit Direct Slave Interface

► TDM Highway• 4 physical ports supporting 256 channels each

► 16 Channel DMAP i h l I t f

IPMaster

System Interface

Internal System Bus


Interface

Memory Controller

60x compatible

Sys Bus

►Peripheral Interfaces• UART• I2C• Timers• GPIO Internal System BusGPIO• 4kB Boot ROM• JTAG

► Hardware Semaphores►Technologygy

• 90 nmG• 1.1V/1.2V Core, 3.3 V I/O• 431 FCPBGA (20x20) 0.8 mm pitch RoHS 13


Boot


H/W 476 KB

M2 shared

►Cores• Four SC140 cores @ 400 MHz/500 MHz• 16 KB ICache• 224 KB M1 memory

Sh d M

PLL

ROM

128 Bit MQ Bus

SemaphoresM2 shared

memory►Shared Memory• 476 KB internal M2 shared memory

►Coprocessors• Turbo & Viterbi

►Ethernet

Turbo

Viterbi

StarCore SC140

PLL

JTAGStarCore

SC140StarCore SC140

32 Timers

Bit

IPB

us I2CUARTTDMGPIO

RS232

4 x TDM

16KB 224KB

StarCoreSC140

►Ethernet• 10/100 FEC w/SMII/RMII

►Memory Interface• 100/133/167 MHz, 64/32 bit SRAM interface

w/ ECC, Boot FLASH, SRAM

128 Bit SQ Bus

Memory Controller 64 Bit Local Bus


32


GPIOGIC

Ethernet

DSI Port

Interrupts

MII/RMII/SMII

16KBI Cache

224KBM1 Memory►Host Port

• 64/32 bit Direct Slave Interface►TDM Highway

• 4 physical ports supporting 256 channels each►16 Ch l DM

IPMaster

System Interface

Internal System Bus


Interface

Memory Controller

60x compatible

Sys Bus

►16 Channel DM►Peripheral Interfaces

• UART• I2C• Timers y• GPIO• 4 kB Boot ROM• JTAG

►Hardware Semaphores►Technology►Technology

• 90nmG• 1.1V/1.2V Core, 3.3 V I/O• 431 FCPBGA (20x20) 0.8 mm pitch RoHS 14

MSC8144 – Multicore DSP32b 400MH

DDR 2Shared

M3M

►4GHz DSP = 4x SC3400 core subsystems (up to 16 GMACs), each with• SC3400 DSP core at 1GHz (4 GMACs 16b or 8 GMACs 8b)• 16 Kbyte I-cache, 32 Kbyte D-cache, MMU, PIC

► Internal Memories/Caches• 10 Mbyte shared M3 unified memory

CLAS

CLAS

32b 400MHz

Shared M2

MemoryController

4

SC3400 core

16KB 32KBI-Cache D-

Cache

Memory

10 Mbyte

10 Mbyte shared M3 unified memory• 512 shared M2 unified memory• 128 KB shared L2 I-cache

►CLASS – Chip-Level Arbitration and Switching Fabric• Non-blocking, fully pipelined at low latency accesses• Operates at 400 MHzHi h S d I t t

SS–

Non-Blockin

SS–

Non-Blockin

SC3400 core

16KB 32KBI-Cache D-

CacheShared

L2M2Memory 512 KB

4 cores

I²C, UART, GPIOs

►High Speed Interconnects• x4/x1 Serial RapidIO – 1.25/2.5/3.125 Gbaud

►Ethernet & ATM• Dual SGMII/RGMII Gigabit Ethernet ports or Dual RMII/SMII

Fast Ethernet ports• Utopia 16b/50Mhz supporting AAL-0/2/5 and POS in

ngSw

itchFabric

ngSw

itchFabric

DMA Engine

SC3400 core

16KB 32KBI-Cache D-

Cache

SC3400 core

16KB 32KBI-Cache D-

Cache

L2I-Cache 128 KB

CLASS – Non-Blocking Switch Fabric

Security Processing Engine

TDM Highway

H/W Semaphores

SRIO x4/x1

I C, UART, GPIOsp pp gfirmware

• Eth, ATM protocols and sRIO offload►DDR Memory Controller

• DDR2 SDRAM 400MHz, 32/16 bit w/ECC►TDM Highway

• 2048 DS 0 divided into 8 ports 256 each

cc

2x 10/100/1000Ethernet, TDM Highway

8 ports

SERDES

SRIO x4/x1• 2048 DS-0, divided into 8 ports 256 each►PCI 32b/66MH►DMA Engine 32 ch.► Integrated Security Engine

• AES, Kasumi, 3/DES, SHA, RC-4, RNG (data and code protection)

PCI

,UTOPIA /POS-

PHY,SPI

►Other Peripheral Interfaces• SPI, UART, I2C, 32 GPIO, 16 Timers, 96 KB boot ROM,

JTAG►Boot options – Ethernet, I2C, SPI, Serial RapidIO, PCI Technology

• Process: 90nm SOIIn Production

4 lanes 3.125Gbaud Dual SGMII Utopia 16b 50MHz PCI bus 32b 66MHzTDM

Process: 90nm SOI• Voltage: 1V core, 3.3/2.5/1.8 V I/O• Package: 783 pins, FCBPGA (29x29), 1mm pitch, RoHS

15

MSC8144 ADS (Application Development System)► DSP – MSC8144

• Memory – DDR2 - 256 MByte• Dual GE Ethernet – to switch and to PHY• 4x/1x Serial RapidIO over AMC connector• TDMTDM• Dual E1/T1 framers• DS-3 framer (optional)• Stereo codec (16-bit)• Utopia – to MPU and to PTMC expander• PCI (32bit) – to MPU and to PTMC expander

I2C 64 Kbyte• I2C – 64 Kbyte• RS-232

► MPU – MPC8560• Memory – DDR1, 256 MByte• Ethernet – to Switch and to PHY• Utopia – to DSP and to PTMC expander• Flash – 16 MByte• RS-232

►Ethernet Switches• SGMII (6 ports) and RGMII (8 ports) switchesSGMII (6 ports) and RGMII (8 ports) switches• Quad GE PHY – 2 to switches and 2 DSP and MP

►AMC Connector• GE, Serial RapidIO, TDM

JTAG

U

►JTAG• Chained DSP+MPU• Using USBTAP

►RoHS Compliant►Includes Device Drivers

16

MSC8144AMC-SA►Board Level Device Features

4 x MSC8144:• 4 x SC3400 extended cores at 800 MHz / 1

GHz• 16 x ALUs deliver up to 12800 / 16000 MMACS• 512 Kbyte shared M2 memory• 10 Mbytes of 128-bit wide shared M3 memory10 Mbytes of 128 bit wide shared M3 memory• DDR memory controller: 200 MHz• QUICC Engine• 8 x TDM interfaces• Security Engine Core optimized for IPSec,

IKE, WTLS/WAP, SSL/TLS, and 3GPPprotocolsprotocols

• 2 x Gigabit Ethernet interface• 1 x ATM controller supporting a UTOPIA interface• 1 x Serial RapidIO interface supporting x1/x4• Serial Peripheral Interface (SPI)

Gigabit Ethernet Switch:• Routes and switches Ethernet ports from each

MSC8144E over SGMII to external connectors

►Board Memory256 Mbytes DDR II (Discrete) per MSC8144256 Mbytes DDR II (Discrete) per MSC8144

►Board I/OAMC Connector:

• 2 x Gigabit Ethernet interfaces (Port 0,1)• x1/x4 sRIO (Port 4:7)

► Front Panel• Via Expansion Headerx1/x4 sRIO (Port 4:7)

• x1/x4 sRIO (Port 8:11)• TDM (16Tx, 16Rx, SYNC, CLK) (Port 12:20)

Headers and Debug:• DSP JTAG/EONCE

CPLD JTAG

Via Expansion Header•1 x Gigabit Ethernet (RJ45)•1 x JTAG (MMC)•1 x UART•SPI/I2C Programming Headers

• CPLD JTAG

17

New Product Rack and StackPin for Pin compatible

Device 8156 8154 8256 8254 8252 8251SC3850 DSP Cores 6 4 6 4 2 1

MHz 1GHz 1GHz 1GHz 1GHz 1GHz 1GHz

MMACs Up to 48000 Up to 32000 Up to 48000 Up to 32000 Up to 16000 Up to 8000Int. Memory 1MB 1MB 1MB 1MB 1MB 1MB

L1I 4 x 32KB 4 x 32KB 4 x 32KB 4 x 32KB 4 x 32KB 4 x 32KB

L1D 4 x 32KB 4 x 32KB 4 x 32KB 4 x 32KB 4 x 32KB 4 x 32KB

L2 512KB 512KB 512KB 512KB 512KB 512KB

M3 1MB 1MB 1MB 1MB 1MB 1MB

DDR2/3 1 (800MHz) 2 (800MHz) 1 (800MHz) 2 (800MHz) 2 (800MHz) 2 (800MHz)

PCIe 1 1 1 1 1 1

GEMAC (RGMII SGMII) 2 2 2 2 2 2GEMAC (RGMII, SGMII) 2 2 2 2 2 2

SRIO 2 1 2 1 1 1

TDM 4 4 4 4 4 4

SPI 1 1 1 1 1 1

UART 1 1 1 1 1 1UART 1 1 1 1 1 1

I2C 1 1 1 1 1 1

FFT/DFT Accelerators 1 1

Security AES, SHA, RC-4,Kasumi, SNOW

AES, SHA, RC-4,Kasumi, SNOW





P T h 45 SOI 45 SOI 45 SOI 45 SOI 45 SOI 45 SOIProc. Tech. 45nm SOI 45nm SOI 45nm SOI 45nm SOI 45nm SOI 45nm SOI

Package 783 Ball FC-PBGA

783 Ball FC-PBGA

783 Ball FC-PBGA

783 Ball FC-PBGA

783 Ball FC-PBGA

783 Ball FC-PBGA

18

SC3850 DSP Core and Subsystem

►SC3850 SUBSYSTEM advantages►SC3850 SU S S ad a tages• Memory management unit (MMU)

• Flexible memory protection - Easier debug, faster time to market• Address translationAddress translation• Better MTBF (mean time between errors)

• L1 data and instr. caches – 2*32 KB, 8 way, hardware and software pre-fetch• Private L2 cache 512 KB unified data/Instr dynamically defined as M2• Private L2 cache – 512 KB, unified data/Instr., dynamically defined as M2• Debug and profiling - smart breakpoints, non intrusive profiling capabilities

19

SC3850 DSP Core and Subsystem

►SC3850 CORE advantages►SC3850 CO ad a tages• 8MACs/cycle, 1GHz => 8GMACS per core at 45nm• High performance for deep pipeline architecture – advanced branch prediction

Control code efficiency hardware support for stack many control oriented instr• Control code efficiency - hardware support for stack, many control-oriented instr.• Easy programming - interlocked pipeline, backward compatible with all SC

devicesI t i i MAC f ti lit (V MPY + ADD) 8 GMAC• Intrinsic MAC functionality (Vs. MPY + ADD) – 8 GMAC per core

• Multicore support - semaphore support (read-modify-write)20

MSC815x DSP Family►Target applications

StarCoreSC3850 DSP Core512 KB

►Target applications• Baseband• Medical imaging• General purpose

1024 KBShared

M3 memory

64-bit DDR-2/3

Memory Controller

I2C

SPI

SC3850 DSP Core

32 KB 32 KBD-Cache I-Cache

512 KBBackside L2 Cache►Key advantages

• Industry’s highest performance DSP outperforms competitors’

CLASS FabricClocks/Reset

I C

GPIO

DUARTDSP, outperforms competitors highest performing multicore DSP by more than 2x

• Featuring up to six fully-bl 1 GH DSPprogrammable 1 GHz DSP

cores, delivering up to 6 GHz of DSP processing power with high speed peripheral interfaces

QEEthernet

DMA

sRIO

sRIO

PCIe

MAPLE-BAccelerator

HSSI Security Engine

DMA TDM

• MAPLE hardware accelerators

8-Lanes 3.125G SerDes

s sPCIe

x4 x4 x4

1GE 1GE

21

MSC825x DSP Family

StarCoreSC3850 DSP Core512 KB

►Target applications• Aerospace & defense• Test and measurement• Medical

1024 KBShared

M3 memory

64-bit DDR-2/3

Memory Controller

I2C

SPI

SC3850 DSP Core


512 KBBackside L2 Cache

• Medical

►Key advantages• Industry’s highest performance


I C

GPIO

DUART

y g pDSP, outperforms competitors’ highest performing multicore DSP by more than 2x

• Featuring up to six fully-Featuring up to six fullyprogrammable 1 GHz DSPcores delivering up to 6 GHz of DSP processing power with high-speed peripheral

QEEthernet

DMA

sRIO

sRIO

PCIe

HSSIDMA TDM

high speed peripheral interfaces


s sPCIe

x4 x4 x4

1GE 1GE

22

Easy-to-use Development Tools and TrainingMSC825x/815x ADS Board►$3900 (includes 1 year free CodeWarrior tools subscription)►On board emulation►On-board emulation

CodeWarrior Software Development Tools►New Eclipse IDE►New Eclipse IDE►Trace and profile, SmartDSP OS, debugger, C/C++ compiler

Software Migration Tools►Texas Instruments C64x+ to FSL SC3850 migration tools

DSP lib i►DSP libraries

Documentation and Available Supportwww.freescale.com/dsp►Device and tool fact sheets►Product data sheets

F l DSP f►Freescale DSP forums►System block diagrams on all target end equipment

23

MSC8154/E – Broadband Wireless DSP

Starcore™SC3850 DSP Core512 KB

► Target applications• PHY layer processing for FDD-

LTE, TDD-LTE, HSPA+, TD-

1024 KBShared

M3 memory

64-bit DDR-2/3

Memory Controller

I2C

SPI

SC3850 DSP Core

32 KBD-Cache

32 KBI-Cache


SCDMA, CDMA2K and WiMAXchannel cards in NodeB BTS

► Key advantages


I2C

GPIO

DUART• Featuring four fully-programmable 1 GHz DSP cores delivering 4 GHz ofDSP processing power plus i ti lti t d d

QEEthernet

DMA

sRIO

sRIO

PCIe

MAPLE-BBaseband Accelerator

HSSIDMA Security Engine

innovative, multi-standardbaseband specific accelerators

• Enables pico/micro base stations


s sPCIe

x4 x4 x4

1GE 1GE

► The MSC8154 DSP has been qualified on advanced 45 nm process technology

24

MSC8156/E – Broadband Wireless DSP

Starcore™SC3850 DSP Core512 KB

► Target applications• PHY layer processing for FDD-LTE,

TDD-LTE, HSPA+, TD-SCDMA,

1024 KBShared

M3 memory

64-bit DDR-2/3

Memory Controller

I2C

SPI

SC3850 DSP Core



CDMA2K and WiMAX channel cards in NodeB BTS

► Key advantages


I2C

GPIO

DUART• Industry’s highest performance

DSP, outperforms competitors’ highest performing multicore DSP by more than double

QEEthernet

DMA

sRIO

sRIO

PCIe

MAPLE-BBaseband Accelerator

HSSIDMA Security Engine

• Featuring six fully-programmable1GHz DSP cores delivering 6 GHz of DSP processing power plus innovative, multi-standard baseband

ifi l t


s sPCIe

x4 x4 x4

1GE 1GEspecific accelerators• Supports at least 3G-LTE 10 MHz

sector, UL+DL including MIMO in a single device

► The MSC8156 DSP has been qualified on advanced 4 5nm process technology

25

MSC8156 Highlights► Target wireless base station systems

• 3G-LTE, TDD-LTE, WiMAX, HSPA+ and TD-SCDMA

► MSC8156 device performance• Optimized programmable

performanceand TD SCDMA• Meets all leading future wireless

technologies

► Multi standard technology Single

performance• Based on next generation SC3850

DSP core, delivers up to 48 GMACS– 6 GHz effective performance

► Multi-standard technology, Single device performance:

• Single-sector 3G-LTEMulti sector WIMAX

• Embedded with innovative baseband accelerators

• High-speed standard interfaces• Multi-sector WIMAX• Multi-carrier TD-SCDMA• Multi-sector HSPA along with external

chip rate acceleration

• 2x Serial RapidIO®, 2xSGMII, 2xDDR-3, PCI Express®

• Highly optimized multilevel memoryHigh speed DDR interfacechip rate acceleration

► Highly efficient internal memory• Large on die low latency memory:

• High-speed DDR interface

• 6x 512 KB of L2/M2 + 1 MB M3 = 4 MB

► MAPLE-B accelerator• High throughput, multi-standard

compliant, re-programmable

26

MSC8156/E Architecture64 bit @

MAPLE-B

TV

800MHz-1GHzStarCore SC3850

Subsystem


Subsystem


Subsystem


Subsystem

64-bit @ DDR800

Baseband Accelerators800MHz-1GHz

StarCore SC3850 Subsystem

64-bit @ DDR800


Subsystem

DDR 2/3Controller

TV PE

RISC RISC

FFT PE

DFT PE

M3Memory 1056 KB

SC3850DSP Core

32 KB 32 KBI-Cache D-Cache

MMU

512 KB

SC3850DSP Core


MMU

512 KB

SC3850DSP Core


MMU

512 KB

SC3850DSP Core


MMU

512 KB

DDR 2/3Controller

SC3850DSP Core


MMU

512 KB

SC3850DSP Core


MMU

512 KBRISC RISC 512 KB L2/M2

512 KB L2/M2

512 KB L2/M2

512 KB L2/M2

Non-blocking Switching Matrix

512 KB L2/M2

<8 <8 8 4 8 8 4 8 4 8 4 8 4 8 4 8

GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s GB/s

512 KB L2/M2

Boot QUICCEngineTM

8 GB/s8 GB/s

g g12 masters x 8 slaves each with 128 bit i/f

High Speed Serial Interfaces (HSSI)

8 GB/s

Virtual Interrupts & Hardware

Semaphores

Boot ROM

JTAG/ SAP

I2C

UART

TDM 1024Ch.

Security Engine

1Gbps Ethernet

1Gbps Ethernet

RISC RISC

SPI

32 ch. DMASRIO

1x/4xSRIO1x/4x

OCN8

LYNX LYNX

(HSSI)

PCI-EX

200Mbps

1 Gbps1 Gbps

Two 1x/4x 3.125Gbaud

RGMIIRGMII

PCIe 1x/4x, two SGMII

27

MSC8156 Other Building Blocks

►Security engine acceleration – enabling data protection for MAC/L2processing

►Dual Serial RapidIO® – x4 at 3.125G => 20 Gbps, high throughput interfaces connecting to antenna, L2/MAC processor and other DSPson channel cardon channel card

►Dual Gigabit Ethernet – control path

►PCI Express® x4 at 2 5G high throughput interface connecting to►PCI Express® – x4 at 2.5G, high throughput interface connecting toL2/MAC processor or ASIC/FPGA

►Dual DDR 2/3 64b 800 MHz – high throughout memory interfaces►Dual DDR 2/3 64b 800 MHz high throughout memory interfaces

28

MAPLE-B Block Diagram

PSIF

Interrupts2x 64b 450MHz

64b 450MHz

PSIF config

CESlave

Arbitration and switching

System DMA EngineMAG2DRAM IRAM

16kBRISC 1

CoreIRAM 16kB

RISC 0Core PICLocal DMA/

CRC PE x2

SIF FFTPE SIF DFTPETVPE SIFSIFDRAM

gan

d C

onfig

I/O Data Buffer

Radix 8 Cells

Radix 4

Radix 2 Cells

I/O Data Buffer

gan

d C

onfig

Radix 4 Cells

Radix 5Radix 3

Radix 2 Cells

DATA SRAM 16kB

CD , NII, HO MEM

CDLEXTL

EXT MEM

NIIL HOL

Rou

ting

Twiddles Memory SBIF

Radix 4 Cells

Twiddles Memory

Rou

tingRadix 5

CellsRadix 3

Cells

SBIF

DATA SRAM 16kB

CTL

DRE0 DRE1 DRE2 DRE3VRE

PSIF : Programmable System Interface TVPE : Turbo/Viterbi Processing Engine FFTPE : FFT Processing EngineDFTPE : DFT Processing Engine CRCPE: CRC processing EngineCRCPE: CRC processing Engine

29

MAPLE-B Baseband Acceleration – Benefits

Cost Flexibility:• Technologies/standards modifications

Al ith i difi ti

FPGA

MAPLE

• Algorithmic modifications• Architecture options• Solution scalability

Hardware/ASIC

Flexibility

Cost:• Power dissipation• Silicon area

Programmable System Interface (PSIF)• 1-4 RISC controllers

• Multistandard support1 4 RISC controllers

• 1-12 Processing Elements• 1-4 System DMA’s & internal DMA’s

• High throughputs• From Macro to Femto• Adaptable to multiple standardsPE PE PEPEPE • Adaptable to multiple standards• Mix and match different PE’s for various

solution scalability and derivativesProcessing Engines

30

MAPLE-B Accelerator - Performance and Standards Compliance

3GPP TS 36.212 FEC and CRC3GLTE FDD/TDD Systems MAPLE-B (MSC8156)Turbo DecodingOptional support for sub-block de-interleaving

> 200 Mbps (6 iterations)

Viterbi Decoding > 100 Mbps (Tail-biting multi-iteration)Optional support for periodic de-puncturing

FFT/IFFT/DFT/IDFTOptional support for guard bands insertion

> 280 Msps FFT using FFTPE> 175 Msps DFT using DFTPE

CRC, Insertion for downlink and check for uplink > 10 Gbps , CRC24A, CRC24B

IEEE® 802.16 Rev2UMTS – WCDMA, HSPA+ MAPLE-B (MSC8156)Turbo Decoding > 165 Mbps (6 iterations)

Viterbi Decoding > 115 Mbps (Zero tail, K=9)gOptional support for periodic de-puncturing

p ( , )

FFT/IFFT > 350 Msps FFT using FFTPE and DFTPE

CRC, Insertion for DL and check for UL > 10 Gbps , CRC24

3GPP TS 25.212 (FDD) FEC & CRC3GPP TS 25.222 (TDD) FEC & CRC

WiMAX Systems MAPLE-B (MSC8156)Turbo DecodingOptional support for sub-block de-interleaving

> 195 Mbps (6 iterations)

Viterbi Decoding > 100 Mbps (Tail-biting multi-iteration)Viterbi DecodingOptional support for periodic de-puncturing

> 100 Mbps (Tail-biting multi-iteration)

FFT/IFFTOptional support for guard bands insertion

> 350 Msps using 2 units (FFTPE, DFTPE)

CRC, Insertion for DL and check for UL > 10 Gbps , CRC16 (PDU)

31

Power Architecture® Technology Overview

32

MSC8156 ADS (Application Development System)

►MSC8156 or MSC8154 Multicore DSP►Memories – DDR2 and DDR3, 1 Gbyte each►Ethernet Switches – SGMII and RGMII►SGMII/RGMII PHY►TDM – 2x E1/T1 framers and PTMC

• AdvancedMC™ connector• Dual 1000BaseX• Dual Serial RapidIO® x4 / PCI Express® x4• TDM

►Board form factor – Dual Width AMC►Availability – Now►P i $3900►Price: $3900

33

MSC8156AMC – Reference Development System► High-density DSP platform

• 3x MSC8156 multicore DSP – each with:• 6x SC3850 StarCore DSP cores at 1 GHz +

MAPLE-B baseband accelerator• 2x 512 MB of 64-bit DDR3 memory

► Connectivity• Four 3.125 GB Serial RapidIO® (x4)

interfaces from backplane to DSP farm via Serial RapidIO switch

Ethernet

Serial RapidIO switch• Two 1000 Base-X Gigabit Ethernet

interfaces from backplane to DSP farm via Ethernet switch

► Module Management Controller

Port 8:11

Port 4:7

Port 1

Port 0

PCIe

SRIO SWITCH [IDT 80KSW0005]

DD

RIII

DD

RIII

The image cannot be display ed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart y our computer, and then open the file again. If the red x still appears, y ou may have to delete the image and then insert it again.

4x 4x

Ethernet RGMII Switch

[VSC7384]RJ45

SPI JTAG

2:1 2:1SRIO/PCIe

EEPROM

Ethernet Trans

[VSC8224]JTAG64– bit

64– bit

MSC8154 MDIOGigE GigEsRIO sRIO

I2C JTAG

Mezzanine

MDIO

RJ45

SPI

Ethernet Ethernet

SRIO/PCIe

g(MMC)

• Hot swapping• Board control

► Target applications

I2C

Port 8:11

Port 12:15

Port 17:20

FPGA

4x 4x

4x4x4x4xD

DR

IIID

DR

III64–bit

The image cannot be display ed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart y our computer, and then open the file again. If the red x still appears, y ou may hav e to delete the image and then insert it again.

GigE GigE

I2C

sRIO sRIOJTAG

4x 4x4xI2C

4x 4x4x4x

JTAG

SRIO

64–bit MSC8154 MDIOMezzanine

SPI

SRIO SRIO SRIO

{USB]

► Target applications• 3G-LTE, WCDMA, WiMAX base stations

and media gateway systems• Design reference and enablement platform

for customers and third parties

MMC

FPGA

EEPROM

DD

RIII

64– bit

DD

RIII

64– bit

The image cannot be display ed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart y our computer, and then open the file again. If the red x still appears, y ou may have to delete the image and then insert it again.MSC8154

GigE

I2C

GigE sRIOsRIOJTAG

Mezzanine MDIO

SPIFlash

SPI

4x 4x

EEPROM

Mini- USB

Mini- USB

USB

► Form factor• Single-width AMC

► Availability – Now► Price - $6000

JTAGConn.

UART FT2232► Price $6000

34

Freescale QorIQ Converge SoC

StarCore DSP + Power Architecture® +Power ArchitectureBaseband Accelerators

= Scalable solution

35

3G-LTE eNodeB – Capacity and Software Processes Mappingpp g

► 3G-LTE FDD/TDD:• Single sector 20

MHz 2x4 MIMOMHz, 2x4 MIMO UL, 4x4 MIMO DL

• Up to 300 Mbps DL, Up to 150 Mbps ULUp to 150 Mbps UL

► WiMAX TDD:• 3 sectors 10 MHz• Up to 50

Mbps/Sector DLMbps/Sector DL• Up to13

Mbps/Sector UL

36

MSC8154 Picocell System

►3G-LTE FDD/TDD -• Single sector 10 MHz• 100 Mbps DL, Up to 50 Mbps UL• 2x2 MiMO

L2/L3 - MAC/RLC/Transport

GbE

P2020GbE

ckPl

ane

4xDDD

L1 - PHYMSC8154

sRIO sRIO

DDR LBsRIO

Bac

DD

R

DR2/3

sRIO

GbE

DDR2/DDR3

37

P2020-MSC8156/4 AdvancedMC™ Reference DesignFor 3G-LTE Picocell

P2020+MSC8156 Combined Channel Card

LTE R fLTE Reference Software

Frequency P i

User P i

IP Security

IP

SchedulerPDCP (En-Processing Processing IPMAC RLC(En

crypt)

SmartDSP OS Linux OS Linux OS

Layer 2/3Layer 1

MSC8156 AMC P2020 AMC38

Documents

References DSP vs. FPGA