Regarding the change of names mentioned in the document

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.

The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi

Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names

have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.

Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been

made to the contents of the document, and these changes do not constitute any alteration to the

contents of the document itself.

Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices

and power devices.

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

https://www.datasheetcrawler.com/

https://www.stockedmro.com/

M35054-XXXFP/M35055-XXXFP

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS

MITSUBISHI MICROCOMPUTERS

DESCRIPTIONThe M35054-XXXFP and M35055-XXXFP are TV screen display con-trol IC which can be used to display information such as number ofchannels, the date and messages and program schedules on the TVscreen.In particular, owing to the built-in SYNC-SEP (synchronous separa-tion) circuit, the synchronous correction circuit, external circuits canbe decrease and character turbulence that occurs when superim-posing can be reduced. The processor is suitable for AV systemssuch as VTRs, LDs, and so on.It is a silicon gate CMOS process and M35054-XXXFP and M35055-XXXFP are housed in a 20-pin shrink SOP package.For M35054-001FP/M35055-001FP that are a standard ROM ver-sions of M35054-XXXFP/M35055-XXXFP respectively, the charac-ter pattern is also mentioned.

FEATURES• Screen composition .............................. 24 characters 10 lines,

32 characters 7 lines

• Number of characters displayed .................................. 240 (Max.)

• Character composition ..................................... 12 18 dot matrix

• Characters available ............................. 128 characters (M35054)............................. 256 characters (M35055)

• Character sizes available .................... 4 (horizontal) 4 (vertical)

• Display locations availableHorizontal direction ............................................... 240 locationsVertical direction ................................................... 256 locations

• Blinking ................................................................. Character unitsCycle : approximately 1 second, or approximately 0.5 secondsDuty : 25%, 50%, or 75%

• Data input .............................. By the serial input function (16 bits)

• ColoringBackground coloring (composite video signal)

• BlankingTotal blanking (14 18 dots)Border size blankingCharacter size blanking

• Synchronizing signalComposite synchronizing signal generation(PAL, NTSC, M-PAL)

• 2 output ports (1 digital line)

• Oscillation stop functionIt is possible to stop the oscillation for synchronizing signalgeneration

• Built-in half-tone display function

• Built-in reversed character display function

• Built-in synchronous correction circuit

• Built-in synchronous separation circuit

APPLICATIONTV, VCR, Movie

PIN CONFIGURATION (TOP VIEW)

M35054-X

XX

FP

M35055-X

XX

FP

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

10

CP1

TESTA

CS

SCK

SIN

AC

VDD2

CVIDEO

LECHA

CVIN

VDD1

HOR

CP2

OSCIN

VSS

P1

P0

TESTB

TESTC

VSS

Outline 20P2Q-A

→→

→←

←

→→

→→

→→

←

←

REV.1.2






2

PIN DESCRIPTION

Function

This is the filter output pin 1.

This is the pin for test. Connect this pin to GND during normal operation.

This is the chip select pin, and when serial data transmission is being carried out, it goesto “L”. Hysteresis input. Built-in pull-up resistor.

__

When CS pin is “L”, SIN serial data is taken in when SCK rises. Hysteresis input. Built-inpull-up resistor.

This is the pin for serial input of data and addresses for the display control register andthe display data memory. Hysteresis input. Built-in pull-up resistor.

When “L”, this pin resets the internal IC circuit. Hysteresis input. Built-in pull-up resistor.

Please connect to +5V with the analog circuit power pin.

This is the output pin for composite video signals. It outputs 2VP-P composite videosignals. In superimpose mode, character output etc. is superimposed on the externalcomposite video signals from CVIN.

This is the input pin which determines the “white” character color level in the compositevideo signal.

This is the input pin for external composite video signals. In superimpose mode, characteroutput etc. is superimposed on these external composite video signals.

Please connect to GND using circuit earthing pin.

This is the pin for test. Open this pin during normal operation.

This is the pin for test. Connect this pin to GND during normal operation.

This pin outputs the port output or BLNK1 (character background) signal.

This pin outputs the port output or CO1(character) signal.

Please connect to GND using circuit earthing pin (Analog side).

This is the input pin for the sub-carrier frequency (fSC) for generating a synchronoussignal.A frequency of 3.580MHz is needed for NTSC, and a frequency of 4.434MHz in neededfor PAL and 3.576MHz is needed for M-PAL.

Filter output pin 2.

This is the input pin for external composite video signals. This pin inputs the externalvideo signal clamped sync-chip to 1.5V, and internally carries out synchronous separa-tion.

Please connect to +5V with the digital circuit power pin.

Symbol

OSC1

TESTA__

CS

SCK

SIN

__

AC

VDD2

CVIDEO

LECHA

CVIN

VSS

TESTC

TESTB

P0

P1

VSS

OSCIN

CP2

HOR

VDD1

Pin name

Clock input

Test pin input

Chip select input

Serial clock input

Serial data input

Auto-clear input

Power pin

Composite videosignal output

Character level input

Composite videosignal input

Earthing pin

Test pin output

Test pin input

Port P0 output

Port P1 output

Earthing pin

fSC input pin forsynchronous signalgeneration

Filter output

Horizontal synchro-nizing signal input

Power pin

Input/Output

Input

—

Input

Input

Input

Input

—

Output

Input

Input

—

—

—

Output

Output

—

Input

Output

Input

—






3

BLO

CK

DIA

GR

AM

Dat

aco

ntro

l ci

rcui

t

Add

ress

co

ntro

l ci

rcui

t

Dis

play

con

trol

re

gist

er

Dis

play

RA

M

Dis

play

cha

ract

er R

OM

Tim

ing

gene

rato

r

Blin

king

circ

uit

Shi

ft re

gist

er

Dis

play

con

trol

ci

rcui

t

Rea

ding

add

ress

cont

rol c

ircui

t

H c

ount

er

NT

SC

PAL

M-P

AL

vide

o ou

tput

ci

rcui

t

Tim

ing

gene

rato

r

SY

NC

-SE

Pci

rcui

t3.

580M

Hz(

NT

SC

)4.

434M

Hz(

PAL)

3.57

6MH

z(M

-PA

L)

TE

STA

TE

ST

B

Por

t out

put

circ

uit

Clo

ck o

scill

atio

n ci

rcui

tS

CK

SINCS

CV

IDE

O

CV

IN

LEC

HA

VD

D1

AC

VS

S

VD

D2

HO

R

P0

P1

CP

1

VS

S

TE

ST

C

OS

CIN

CP

2

I/O control circuit

Osc

illat

ion

circ

uit

for

sync

hron

izin

g si

gnal

gen

erat

ion

Dis

play

loca

tion

dete

ctio

n ci

rcui

t

7161120 6132543

119

17 18 8 10 9 12 14 15






4

MEMORY CONSTITUTIONAddress 0016 to EF16 are assigned to the display RAM, address F016

to F816 are assigned to the display control registers.The internal circuit is reset and all display control registers (addressF016 to F816) are set to “0” and display RAM (address 0016 to EF16)

__

are RAM erased when the AC pin level is “L”.When using M35054-XXXFP, set “0” in any of DA7, DAD throughDAF of addresses 0016 through EF16, and of DAE and DAF of ad-

dresses F016 through F816.Setting the blank code “FF16” as a character code is an exception.When using M35055-XXXFP, set “0” in any of DAD through DAF ofaddresses 0016 through EF16, and of DAE and DAF of addressesF016 through F816.TESTn (n : a number) is MITSUBISHI test memory, so be sure toobserve the setting conditions.

Fig. 1 Memory constitution (M35054-XXXFP)

Fig. 2 Memory constitution (M35055-XXXFP)

Reverse

Address

0016

EF16

F016

F116

F216

F316

F416

F516

F616

F716

F816

DADA DAF E D0 0 0

0 0 0

0 0 TEST15

0 0 TEST21

0 0 TEST27

0 0 TEST33

0 0 TEST36

0 0 TEST42

0 0 TEST43

0 0 TEST46

0 0 LEVEL1

DA DA DA DA DA DA DA DA DA DA DA DA DAC B A 9 8 7 6 5 4 3 2 1 0

REV BLINK B G R C6 C5 C4 C3 C2 C1 C0

REV BLINK C6 C5 C4 C3 C2 C1 C0

TEST13 TEST12 SYSEP1 SYSEP0 SEPV1 SEPV0 PTD1 PTD0 PTC1 PTC0

HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0

VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0

VSZ21 VSZ20 VSZ11 VSZ10 HSZ21 HSZ20 HSZ11 HSZ10

TEST35 TEST34 SPACE DSP9 DSP8 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 DSP0

TEST41 TEST39 TEST38 TEST37 EQP PALH MPAL INT/NON N/P BLINK2 BLINK1 BLINK0

TEST2 TEST1 TEST0 LBLACK LIN24/32 BLKHF BB BG BR LEVEL0 PHASE2 PHASE1 PHASE0

TEST45 RGBON TEST44 CL17/18 CBLINK CURS7 CURS6 CURS5 CURS4 CURS3 CURS2 CURS1 CURS0

RAMERS DSPON STOP1 STOPIN SCOR EX BLK1 BLK0

TEST23TEST24TEST25TEST26 TEST22

TEST30TEST31TEST32

TEST47TEST48TEST49TEST50TEST51

0

0B G R

TEST16

TEST10TEST11TEST14

TEST17TEST18TEST19TEST20

TEST28TEST29

TEST40

Dis

play

RA

MD

ispl

ay c

ontr

ol r

egis

ter

Blinking Character color Character code

Address DADA DAF E D0 0 0

0 0 0

0 0 TEST15

0 0 TEST21

0 0 TEST27

0 0 TEST33

0 0 TEST36

0 0 TEST42

0 0 TEST43

0 0 TEST46

0 0 LEVEL1

DA DA DA DA DA DA DA DA DA DA DA DA DAC B A 9 8 7 6 5 4 3 2 1 0

REV BLINK B G R C6 C5 C4 C3 C2 C1 C0

REV BLINK C6 C5 C4 C3 C2 C1 C0

TEST13 TEST12 SYSEP1 SYSEP0 SEPV1 SEPV0 PTD1 PTD0 PTC1 PTC0

HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0

VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0

VSZ21 VSZ20 VSZ11 VSZ10 HSZ21 HSZ20 HSZ11 HSZ10

TEST35 TEST34 SPACE DSP9 DSP8 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 DSP0

TEST41 TEST39 TEST38 TEST37 EQP PALH MPAL INT/NON N/P BLINK2 BLINK1 BLINK0

TEST2 TEST1 TEST0 LBLACK LIN24/32 BLKHF BB BG BR LEVEL0 PHASE2 PHASE1 PHASE0

TEST45 RGBON TEST44 CL17/18 CBLINK CURS7 CURS6 CURS5 CURS4 CURS3 CURS2 CURS1 CURS0

RAMERS DSPON STOP1 STOPIN SCOR EX BLK1 BLK0

TEST23TEST24TEST25TEST26 TEST22

TEST30TEST31TEST32

TEST47TEST48TEST49TEST50TEST51

B G R

TEST16

TEST10TEST11TEST14

TEST17TEST18TEST19TEST20

TEST28TEST29

TEST40

C7

C7

Reverse

0016

EF16

F016

F116

F216

F316

F416

F516

F616

F716

F816

Dis

play

RA

MD

ispl

ay c

ontr

ol r

egis

ter

Blinking Character color Character code






5

SCREEN CONSTITUTIONThe screen lines and rows are determined from each address of thedisplay RAM. The screen consitution (24 characters 10 lines) isshown in Figure 3 the screen constitution (32 characters 7 lines) isshown in 4.

Not

e :

The

hex

adec

imal

num

bers

in th

e bo

xes

show

the

disp

lay

RA

M a

ddre

ss.

1 2 3 4 5 6 7 8 9 10

1

0016

1816

3016

4816

6016

7816

9016

A81

6

C01

6

D81

6

2

0116

1916

3116

4916

6116

7916

9116

A91

6

C11

6

D91

6

3

0216

1A16

3216

4A16

6216

7A16

9216

AA

16

C21

6

DA

16

4

0316

1B16

3316

4B16

6316

7B16

9316

AB

16

C31

6

DB

16

5

0416

1C16

3416

4C16

6416

7C16

9416

AC

16

C41

6

DC

16

6

0516

1D16

3516

4D16

6516

7D16

9516

AD

16

C51

6

DD

16

7

0616

1E16

3616

4E16

6616

7E16

9616

AE

16

C61

6

DE

16

8

0716

1F16

3716

4F16

6716

7F16

9716

AF

16

C71

6

DF

16

9

0816

2016

3816

5016

6816

8016

9816

B01

6

C81

6

E01

6

10 0916

2116

3916

5116

6916

8116

9916

B11

6

C91

6

E11

6

11 0A16

2216

3A16

5216

6A16

8216

9A16

B21

6

CA

16

E21

6

12 0B16

2316

3B16

5316

6B16

8316

9B16

B31

6

CB

16

E31

6

13 0C16

2416

3C16

5416

6C16

8416

9C16

B41

6

CC

16

E41

6

14 0D16

2516

3D16

5516

6D16

8516

9D16

B51

6

CD

16

E51

6

15 0E16

2616

3E16

5616

6E16

8616

9E16

B61

6

CE

16

E61

6

16 0F16

2716

3F16

5716

6F16

8716

9F16

B71

6

CF1

6

E71

6

17 1016

2816

4016

5816

7016

8816

A01

6

B81

6

D01

6

E81

6

18 1116

2916

4116

5916

7116

8916

A11

6

B91

6

D11

6

E91

6

19 1216

2A16

4216

5A16

7216

8A16

A21

6

BA

16

D21

6

EA

16

20 1316

2B16

4316

5B16

7316

8B16

A31

6

BB

16

D31

6

EB

16

21 1416

2C16

4416

5C16

7416

8C16

A41

6

BC

16

D41

6

EC

16

22 1516

2D16

4516

5D16

7516

8D16

A51

6

BD

16

D51

6

ED

16

23 1616

2E16

4616

5E16

7616

8E16

A61

6

BE

16

D61

6

EE

16

24 1716

2F16

4716

5F16

7716

8F16

A71

6

BF1

6

D71

6

EF1

6

1 2 3 4 5 6 7

1

0016

2016

4016

6016

8016

A01

6

C01

6

2

0116

2116

4116

6116

8116

A11

6

C11

6

3

0216

2216

4216

6216

8216

A21

6

C21

6

4

0316

2316

4316

6316

8316

A31

6

C31

6

5

0416

2416

4416

6416

8416

A41

6

C41

6

6

0516

2516

4516

6516

8516

A51

6

C51

6

7

0616

2616

4616

6616

8616

A61

6

C61

6

8

0716

2716

4716

6716

8716

A71

6

C71

6

9

0816

2816

4816

6816

8816

A81

6

C81

6

10 0916

2916

4916

6916

8916

A91

6

C91

6

11 0A16

2A16

4A16

6A16

8A16

AA

16

CA

16

12 0B16

2B16

4B16

6B16

8B16

AB

16

CB

16

13 0C16

2C16

4C16

6C16

8C16

AC

16

CC

16

14 0D16

2D16

4D16

6D16

8D16

AD

16

CD

16

15 0E16

2E16

4E16

6E16

8E16

AE

16

CE

16

16 0F16

2F16

4F16

6F16

8F16

AF1

6

CF1

6

17 1016

3016

5016

7016

9016

B01

6

D01

6

18 1116

3116

5116

7116

9116

B11

6

D11

6

19 1216

3216

5216

7216

9216

B21

6

D21

6

20 1316

3316

5316

7316

9316

B31

6

D31

6

21 1416

3416

5416

7416

9416

B41

6

D41

6

22 1516

3516

5516

7516

9516

B51

6

D51

6

23 1616

3616

5616

7616

9616

B61

6

D61

6

24 1716

3716

5716

7716

9716

B71

6

D71

6

25 1816

3816

5816

7816

9816

B81

6

D81

6

26 1916

3916

5916

7916

9916

B91

6

D91

6

27 1A16

3A16

5A16

7A16

9A16

BA

16

DA

16

28 1B16

3B16

5B16

7B16

9B16

BB

16

DB

16

29 1C16

3C16

5C16

7C16

9C16

BC

16

DC

16

30 1D16

3D16

5D16

7D16

9D16

BD

16

DD

16

31 1E16

3E16

5E16

7E16

9E16

BE

16

DE

16

32 1F16

3F16

5F16

7F16

9F16

BF1

6

DF1

6

Not

es 1

. T

he h

exad

ecim

al n

umbe

rs in

the

boxe

s sh

ow th

e di

spla

y R

AM

add

ress

.N

otes

2. W

hen

32 c

hara

cter

s ×

7 lin

es a

re d

ispl

ayed

, set

bla

nk c

ode

“FF

16”

to c

hara

cter

cod

e of

add

ress

es E

0 16

to E

F16

.

Fig

. 4 S

cree

n co

nstit

utio

n (3

2 ch

arac

ters

7 li

nes)

Fig

. 3 S

cree

n co

nstit

utio

n (2

4 ch

arac

ters

10

lines

)

Rows

Rows

Lines

Lines






6

Status

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DA

0~C

0

1

2

3

4

5

6

7

8

9

A

B

C

Name

C0

(LSB)

C1

C2

C3

C4

C5

C6

(MSB)

—

R

G

B

BLINK

REV

Contents

Function

Set ROM-held character code of a character neededto display.

Set to “0” during normal operation

Can not be used

When RGBON=1, set background color by characterunit.

Remarks

(Note 2)

Refer to supplementalexplanation (3).

Notes__

1. Resetting at the AC pin RAM-erases the display RAM, and the status turns as indicated by the mark around in the status column.2. Set to “1” only when setting a blank code. When using M35055-XXXFP, DA7 is C7 (MSB).

Display RAM DESCRIPTIONDisplay RAM Address 00 16 to EF16

Refer to BLINK2 to 0(address F516)

No blinking

Blinking

Normal character

Reversed character






7

Status

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DA

0~D

0

1

2

3

4

5

6

7

8

9

A

B

C

D

Register

PTC0

PTC1

PTD0

PTD1

SEPV0

SEPV1

SYSEP0

SYSEP1

TEST10

TEST11

TEST12

TEST13

TEST14

TEST15

ContentsRemarks

Function

P0 output (port 0)

BLNK1 output

P1 output (port 1)

CO1 output

It is negative polarity at P0 output “L”, BLINK1 output.

It is positive polarity at P0 output “H”, BLINK1 output.

It is negative polarity at P01 output “L”, CO1 output.

It is positive polarity at P01 output “H”, CO1 output.

It should be fixed to “0”.

Can not be used.


Can not be used.

SYSEP10011

SYSEP00101

Bias potentialCan not be used.Can not be used.

1.75VCan not be used.

Can not be used.



Can not be used.


Can not be used.


Can not be used.__

Note: The mark around the status value means the reset status by the “L” level is input to AC pin.Notes

Display control register(1) Address F0 16

Port output control

Refer to supplemental explanation (4).

Control the port data


Specifies the vertical synchronousseparation criterion


Specifies the sync-bias potential


Can not be used.


Can not be used.






8

Status

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Register

HP0

(LSB)

HP1

HP2

HP3

HP4

HP5

HP6

HP7

(MSB)

TEST16

TEST17

TEST18

TEST19

TEST20

TEST21

ContentsRemarks

Set the horizontal display startposition by use of HP7 throughHP0. HP7 to HP0 = (00000000)to (00001111) setting isforbidden.

It can be set this up to 240 stepsin increments of one T.

DA

0~D

0

1

2

3

4

5

6

7

8

9

A

B

C

D

Function

Let horizontal display start position be HS,

HS = T (Σ 2nHPn+6)

T : The oscillation cycle of display clock

Can not be used.


Can not be used.


Can not be used.


Can not be used.


Can not be used.



Can not be used.

(2) Address F1 16

7

n=0

VS

HS

HOR

VE

RT

Characterdisplaying

area






9

Status

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Register

VP0

(LSB)

VP1

VP2

VP3

VP4

VP5

VP6

VP7

(MSB)

TEST22

TEST23

TEST24

TEST25

TEST26

TEST27

ContentsDA

0~D

0

1

2

3

4

5

6

7

8

9

A

B

C

D

Function

Let vertical display start position be VS,

VS = H Σ 2nVPnVS

Can not be used.


Can not be used.


Can not be used.


Can not be used.


Can not be used.



Can not be used.

(3) Address F2 16

Remarks

Set the vertical display startposition by use of VP7 throughVP0. VP7 to VP0 = (00000000)to (00000110) setting isforbidden.

It can be set this up to 249 stepsin increments of one H.

VP7 to VP0 = (00000000) to(00100011) setting is forbidden.

H : The oscillation cycle of horizontalsynchronous signal

7

n=0

VS

HS

HOR

VE

RT

Characterdisplaying

area






10

Register

HSZ10

HSZ11

HSZ20

HSZ21

VSZ10

VSZ11

VSZ20

VSZ21

TEST28

TEST29

TEST30

TEST31

TEST32

TEST33

ContentsDA

0~D

0

1

2

3

4

5

6

7

8

9

A

B

C

D

Function

HSZ11

0

0

1

1

HSZ10

0

1

0

1

Horizontal direction size

1T/dot

2T/dot

3T/dot

4T/dot

HSZ21

0

0

1

1

HSZ20

0

1

0

1

Horizontal direction size

1T/dot

2T/dot

3T/dot

4T/dot

VSZ11

0

0

1

1

VSZ10

0

1

0

1

Vertical direction size

1H/dot

2H/dot

3H/dot

4H/dot

VSZ21

0

0

1

1

VSZ20

0

1

0

1

Vertical direction size

1H/dot

2H/dot

3H/dot

4H/dot


Can not be used.


Can not be used.

Status

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(4) Address F3 16

Remarks

Character size setting in thehorizontal direction for the firstline.

Character size setting in thehorizontal direction for the 2ndline to 10th line.

Character size setting in thevertical direction for the first line.

Character size setting in thevertical direction for the 2nd lineto 10th line.


Can not be used.


Can not be used.


Can not be used.


Can not be used.






11

Register

DSP0

DSP1

DSP2

DSP3

DSP4

DSP5

DSP6

DSP7

DSP8

DSP9

SPACE

TEST34

TEST35

TEST36

ContentsDA

0~D

0

1

2

3

4

5

6

7

8

9

A

B

C

D

Function

Normal display

Put a space line between line 2 and line 3, andbetween line 8 and line 9.


Can not be used.


Can not be used.


Can not be used.

DSPn= “0”

Matrix-outline size

Character size

Border size

Matrix-outline size

BLK1

0

0

1

1

BLK0

0

1

0

1

DSPn= “1”Matrix-outline bordersize

Border size

Matrix-outline size

Character size

Status

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(5) Address F4 16

Depends on BLK0 and BLK1 (address F816)DSPn in the generic name for DSP0 to DSP9.DSP0 to DSP9 are each controlled independently.

Remarks

Set the display mode of line 1.










Put a space line between line 2and line 3 in displaying 32characters.






12

Status

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Register

BLINK0

BLINK1

BLINK2

_____

N/P

______________________

INT/NON

MPAL

PALH

EQP

TEST37

TEST38

TEST39

TEST40

TEST41

TEST42

ContentsDA

0~D

0

1

2

3

4

5

6

7

8

9

A

B

C

D

Function

BLINK0

0

0

1

1

BLINK1

0

1

0

1

Duty

Blinking off

25%

50%

75%

(6) Address F5 16

Remarks

Blinking duty ratio can bealtered. (Note)

Blinking cycle can be altered.

Refer to register MPAL

Scanning lines control (only ininternal synchronization)

Synchronizing signal is selected_

with this register and N/Pregister.

It should be fixed to “0” at NTSC

Effective only at non-interlace

Division of vertical synchronizing signal into 1/64.Cycle approximately 1 second.

Division of vertical synchronizing signal into 1/32.Cycle approximately 0.5 second.

NTSC, M-PAL mode

PAL mode

Interlace

Non interlace

Not include the equivalent pulse.

Include the equivalent pulse.


Can not be used.


Can not be used.


Can not be used.


Can not be used.


Can not be used.


Can not be used.

_N/P

0

0

1

1

MPAL

0

1

0

1

Synchronous mode

NTSC

M-PAL

PAL

Not available

PALH

0

1

__INT/NON

0

1

0

1

Number of scanning lines

625H lines

626H lines

627H lines

628H lines

Note. To blink a character, set 1 to DAB (the blinking bit) of the display RAM.






13

Register

PHASE0

PHASE1

PHASE2

LEVEL0

BR

BG

BB

BLKHF

__________

LIN24/32

LBLACK

TEST0

TEST1

TEST2

TEST43

ContentsDA

0~D

0

1

2

3

4

5

6

7

8

9

A

B

C

D

Function

Internal bias off

Internal bias on

The halftone displaying “OFF” in superimpose

The halftone displaying “ON” in superimpose

24 characters 10 lines display

32 characters 7 lines display

Blanking level I 2.3V

Blanking level II 2.1V


Can not be used.


Can not be used.


Can not be used.

Can not be used.

It should to be fixed to “1”.

PHASE2

0

0

0

0

1

1

1

1

PHASE1

0

0

1

1

0

0

1

1

PHASE0

0

1

0

1

0

1

0

1

Raster

Black

Red

Green

Yellow

Blue

Magenta

Cyan

White

BB

0

0

0

0

1

1

1

1

BG

0

0

1

1

0

0

1

1

BR

0

1

0

1

0

1

0

1

Black

Red

Green

Yellow

Blue

Magenta

Cyan

White

Status

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Character back-ground color

Remarks

Raster color setting

Refer to supplementalexplanation (2) about videosignal level

Generates bias potential forcomposite video signals

Character background colorsetting.

Refer to supplementalexplanation (2) about videosignal level

This register is available in thesuperimpose displaying only. (Note)

Set a blackness level

(7) Address F6 16

Note. It is neccessary to input the external composite video signal to the CVIN pin, and externally connect a 100 to 200Ω register in series.






14

Register

CUR0

CUR1

CUR2

CUR3

CUR4

CUR5

CUR6

CUR7

CBLINK

__________

CL17/18

TEST44

RGBON

TEST45

TEST46

ContentsDA

0~D

0

1

2

3

4

5

6

7

8

9

A

B

C

D

Function

Let cursor displaying address be CURS,

CURS = Σ 2nCURn

No blinking

Blinking

Cursor displaying at the 17th dot by vertical direction.

Cursor displaying at the 18th dot by vertical direction.


Can not be used.

Normal

Character background coloring


Can not be used.


Can not be used.

Status

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(8) Address F7 16

Remarks

Set the cursor displayingaddress by use of CUR7 throughCUR0.

CUR7 to CUR0 (11110000)setting is forbidden under 24characters display.

CUR7 to CUR0 (11100000)setting is forbidden under 32characters display.

Set CUR7 to CUR0 = (11111111)under cursor is not be displayed.

The cursor displaying address(CURS) is correspond to displayconstruction.

The cursor blinking setting

Refer to character construction.

Refer to supplementalexplanation (3).

7

n=0






15

Status

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Register

BLK0

BLK1

EX

SCOR

STOPIN

STOP1

DSPON

RAMERS

TEST47

TEST48

TEST49

TEST50

TEST51

LEVEL1

ContentsDA

0~D

0

1

2

3

4

5

6

7

8

9

A

B

C

D

Function

External synchronization

Internal synchronization

Superimpose monotone display

Superimpose coloring display (only NTSC)

fSC input mode

Can not be used.

Oscillation VCO for display

Stop oscillation VCO for display

Display OFF

Display ON

RAM not erased

RAM erased

Can not be used.


Can not be used.


Can not be used.


Can not be used.


Can not be used.


Internal bias OFF

Internal bias ON

DSPn= “0”

Matrix-outline size

Character size

Border size

Matrix-outline size

BLK1

0

0

1

1

BLK0

0

1

0

1

DSPn= “1”Matrix-outlineborder size

(9) Address F8 16

Remarks

Display mode(BLNK output) variable

Synchronizing signal switching(Note1)

“1” setting is forbidden at internalsynchronous or PAL, M-PALmode displaying.

OSCIN oscillation control

Control oscillation VCO fordisplay

This register does not exist(Note 3).

Notes 1. In dealing with the internal synchronization, cut off external video signals outside the IC. The leakage of external input video signalscan be avoided.

Notes 2. In displaying color superimposition, enter into the OSCIN pin the fSC signal that phase-synchronizes with the color burst of thecomposite video signals (input to the CVIN pin).

Notes 3. Erases all the display RAM. The character code turns to blank-FF16, the encode data bit and the blinking bit turn to “1” respectively,and reversed character bit turns to “0”.

Border size

Matrix-outline size

Character size

Generates bias potential for syn-chronous separation.






16

Supplemental explanation about display control register

(1) How to effect synchronous separation from composite video signalsSynchronous separation is effected as follows depending on the width of L-level of the vertical synchronous period.

1. Less than 8.4µs ······ Not to be determined to be a vertical synchronous signal.2. Equal to or higher than 8.4µs but less than 15.6µs ······ When two clocks continue, if take place, it is “L” period is determined to be a

vertical synchronization signal.3. Equal to or higher than 15.6µs ······ It is “L” period is determined to be a vertical synchronous signal with no condition.

The determination is made at the timing indicated by V in Fig.4 either in case 2 or in case 3.

Fig. 5 The method of synchronous separation from composite video signal.

8.4µs

15.6µs

Vertical synchronous signal

Composite video signal

V8.4µsEqualizing pulse

Sequence of synchronizing pulse






17

Fig. 6 Bector phases

B

0

0

0

0

1

1

1

1

G

0

0

1

1

0

0

1

1

R

0

1

0

1

0

1

0

1

Color

Black

Red

Green

Yellow

Blue

Magenta

Cyan

White

Color Setting

VDD : 5.0V, Ta : 25°C(2) Video signal level

(3) Setting RGBON (address F7 16)RGBON = “0” ..... Sets background colors depending on BB, BG,

and BR (address F616), screen by screen.RGBON = “1” ..... Sets background colors depending on R, G, B

(address 0016 to EF16), character by character.The color setting is shown below.

Phase angle (rad) Brightness level (V) Amplitude ratio (to color burst)

PAL, M-PAL method

—

—

± 4 /16

—

± 7 /16 ± 2 /16

5 /16 ± 2 /16

± /16 ± 2 /16

15 /16 ± 2 /16

± 11 /16 ± 2 /16

9 /16 ± 2 /16

—

Color

Sync-chip

Pedestal

Color burst

Black

Red

Green

Yellow

Blue

Magenta

Cyan

White

NTSC method

—

—

0

—

7 /16 ± 2 /16

27 16 ± 2 /16

/16 ± 2 /16

17 /16 ± 2 /16

11 /16 ± 2 /16

23 /16 ± 2 /16

—

Min.

1.3

1.9

1.9

2.1

2.3

2.7

3.1

2.0

2.5

2.9

3.1

Typ.

1.5

2.1

2.1

2.3

2.5

2.9

3.3

2.2

2.7

3.1

3.3

Max.

1.7

2.3

2.3

2.5

2.7

3.1

3.5

2.4

2.9

3.3

3.5

Min.

—

—

—

—

1.5

1.4

1.0

1.0

1.4

1.5

—

Typ.

—

—

1.0

—

3.0

2.8

2.0

2.0

2.8

3.0

—

Max.

—

—

—

—

4.5

4.2

3.0

3.0

4.2

4.5

—

±

±

±

CB

CB1

CB2

RS1

RS2

/ 4

R-Y

B-Y

- / 4CB Color burst under NTSCCB1,CB2 Color burst under PAL or M-PALRS1,RS2 Color subcarrier under PAL or M-PAL






18

(4) Port output and BLNK1, CO1 output

Fig. 7 Example of port control

STOP1

DSPON

CS pin

at display clock operating

0

1

L

at display clock stop

1

0

H

STOP1, CDSPON (Address F816)

(5) Setting conditions for oscillating or stopping the display clock

LEVEL0

LEVEL1

0

0

External synchronous

1

1

Operation state (Character display)

Internal synchronous

1

0

LEVEL0 (address F616), LEVEL1 (address F816)

Now-working condition(no characters are

displayed)

(6) Setting condition at LEVEL0,1

1

0

Polarity switching

1

0

Select

Output

PTD0, 1, PTC0, 1 (Address F016)

PTC0 (PTC1)

PTD0 (PTD1)BLNK1 (CO1)

PTD0 (PTD1)






19

This display format allows each line to be controlled independently,so that two kinds of display formats can be combined on the samescreen.

DISPLAY FORMSM35054-XXXFP/M35055-XXXFP have the following four displayforms as the blanking function, when CO1 and BLNK1 are output.(1) Character size : Blanking same as the character size.(2) Border size : Blanking the background as a size from cha-

racter.(3) Matrix-outline size: Blanking the background as a size from all

character font size.(4) Matrix-outline : Blanking the background as a size from all

border size character font size.Border display.

Fig. 8 Display forms at each display mode

Scanningline

CVIDEO

12 dots 14 dots

a: Background carriercolor signal

(1) Character size (2) Border size (3) Matrix-outline size

CO1

BLNK1

a aa a

Note: In this case, the output polarity that CO1 and BLNK1 is positive.

14 dots

(4) Matrix-outline border size

12 dots

18 dots






20

DATA INPUT EXAMPLEData of display RAM and display control registers can be set by thenserial input function.Owing to automatic address increment, not necessary to enter ad-dresses for the second and subsequent data.In automatically, the next of address F816 is assigned to address0016.Fig. 9 shows an example of data setting by the serial input function(M35054-XXXFP), Fig. 10 shows an example of data setting by theserial input function (M35055-XXXFP).

Fig. 9 Example of data setting by the serial input function (M35054-XXXFP)

Address/Data

Data(F116)

Data(F216)

Data(F316)

Data(F416)

Data(F516)

Data(F616)

Data(F716)

Data(F816)

Data(F016)

Spplemental explanation

Data contewtsNO.

1 Address(F816) Address setting

Data(F816)

Data(0016)

2

3

4

241

Data(0116)

Data(EF16)

Display OFF

Display RAM address 0016 to EF16 setting

Display ON

Data(EE16)

242

243

244

245

246

247

248

249

250

251

Register address F016 to F716 setting

DA DA DAF E D

0 0

0 0 0

0 0 0

0 0 0

0 0 0

0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 1

0 0 0

0 0

DA DA DA DA DA DA DA DA DA DA DA DA DA C B A 9 8 7 6 5 4 3 2 1 0

0 0 0

0 0 0

0 0 1 1 1 1 1 0 0 0

0 0 0 0 0 0 0 0 0 0

C6 C5 C4 C3 C2 C0C1BBLINK G RREV

C6 C5 C4 C3 C2 C0C1BLINKREV



HP HP HP HP HP

VSZ VSZ VSZ VSZ HSZ

SPACEDSP DSP DSP DSP DSP DSP DSP

EQP PALH MPAL/NON N/P

TEST TESTTESTLBLACK

LINBLKHF BB BG BR

LEVEL PHASE

LEVEL RAMDSPON

STOP STOPSCOR

0 0

HP

HSZ

DSP

BLINK

EX

HP

HSZ

DSP

BLINK

BLK

PTC

HP

HSZ

DSP

BLINK

BLK

CURS

0PTC

1PTD

0PTD

1

01234567VP VP VP VP VP VP VP VP

01234567

101120211011202100

01234567890

012

012 0PHASE PHASE

012

01IN1ERS

24/32

11

CURS CURS CURS CURS CURS CURSCURS01234567

INT

0 1

0

0 00 0

CBLINKCL17/18

RGBON

000100

0

0

0

0

B G R

B G R

B G R

0 0

11111

1111

0

11111

0

0






21

Fig. 10 Example of data setting by the serial input function (M35055-XXXFP)

Address/Data

Data(F116)

Data(F216)

Data(F316)

Data(F416)

Data(F516)

Data(F616)

Data(F716)

Data(F016)

Supplemental explauation

Data couteutsNO.

1 Address(F816) Address setting

Data(F816)

Data(0016)

2

3

4

241

Data(0116)

Data(EF16)

Display OFF

Display RAM address 0016 to EF16 setting

Display ON

Data(EE16)

242

243

244

245

246

247

248

249

250

251

Register address F016 to F716 setting

DA DA DAF E D

0 0

0 0 0

0 0 0

0 0 0

0 0

0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 0

0 0 1

0 0 0

0 0

DA DA DA DA DA DA DA DA DA DA DA DA DA C B A 9 8 7 6 5 4 3 2 1 0

0 0 0

0 0 0

0 0 1 1 1 1 1 0 0 0

0 0 0 0 0 0 0 0 0 0

C6 C5 C4 C3 C2 C0C1BBLINK G RREV




HP HP HP HP HP

VSZ VSZ VSZ VSZ HSZ

DSP DSP DSP DSP DSP DSP DSP

EQP PALH MPAL/NON N/P

TEST TEST TESTLBLACK

LINBLKHF BB BG BR

LEVEL PHASE

LEVEL RAMDSPON

STOP STOPSCOR

0 0

HP

HSZ

DSP

BLINK

EX

HP

HSZ

DSP

BLINK

BLK

PTC

HP

HSZ

DSP

BLINK

BLK

CURS

0PTC

1PTD

0PTD

1

01234567VP VP VP VP VP VP VP VP

01234567

101120211011202100

01234567890

012

012 0PHASE PHASE

012

01IN1ERS

24/32

11

CURS CURS CURS CURS CURS CURSCURS01234567

INT

0 1

0

0 00 0

CBLINKCL17/18

RGBON

000100

B G R

B G R

B G R

0 0

11111

1111

0

11111

0

0

C7

C7

C7

C7

Data(F816)

SPACE






22

SERIAL DATA INPUT TIMING(1) The address consists of 16 bits.(2) The data consists of 16 bits.(3)

__

The 16 bits in the SCK after the CS signal has fallen are the ad-dress, and for succeeding input data, the address is incrementedevery 16 bits.

Fig. 11 Serial input timing

Address (16 bit)

N =1, 2, 3

CS

SCK

LSB MSB

SIN

Data N (16 bit) Data N+1 (16 bit)

LSB MSB LSB MSB






23

Fig. 12 Character font and border

(1) Border display (set by register BLK0, 1 (address F816))

(2) Cursor display (Border display)

CHARACTER FONTImages are composed on a 12 18 dot matrix, and characters canbe linked vertically and horizontally with other characters to allow thedisplay the continuous symbols.

Character code “FF16” is so fixed as to be blank and to have nobackground, thus cannot assign a character font to this code.

18 d

ots

Note: Hatching represents border.

12 dots

Positioning the cursor at the 17th dot.

Positioning the cursor at the 18th dot.

CharacterNote: When the cursor positioning

at the bottom (18th) dot, no border is left at the bottom.

When the character extends to the top dot of the matrix, no border is left at the top.

When the character extends to the bottom (18th) dot of the matrix, no border is left at the bottom.

Register CL17/18 =“0”Register CL17/18 (address F716) = “0”






24

M35054-XXXFP/M35055-XXXFP PERIPHERAL CIRCUIT

Fig. 13 M35054-XXXFP/M35055-XXXFP example of peripheral circuit

No

te 7

: In

deal

ing

with

the

inte

rnal

syn

chro

niza

tion,

cut o

ff ex

tern

al v

ideo

sig

nals

out

side

the

IC.

The

leak

age

of e

xter

nal i

nput

vid

eo s

igna

lsca

n be

avo

ided

.

No

te 1

:C

lam

p sy

nc c

hip

to 1

.50V

.N

ote

2:

Set

bas

ic e

lect

ric p

oten

tial i

n co

nsid

erat

ion

of d

ynam

ic r

ange

of t

he tr

an-

sist

or.

No

te 3

:E

xter

nal l

oop

filte

r 1

cons

tant

is p

ro-

visi

onal

val

ve.

No

te 4

:Con

stru

ct in

tegr

al c

ircui

t by

bui

lt-in

30k

Ωof

AC

pin

and

an

exte

rnal

con

dens

er.

Atte

ntio

n to

sup

ply

volta

ge r

ise

time

abou

tth

is C

R c

onst

ant.

No

te 5

:E

xte

rna

l lo

op

filt

er

2 c

on

sta

nt

is p

rovi

-si

onal

val

ve.

No

te 6

: C

onne

ct fS

C fr

eque

ncy.

0.3V

p-p

4.0V

p-p

NT

SC

= 3

.580

MH

zP

AL=

4.4

34M

Hz

M-P

AL=

3.5

76M

Hz

220

2.2k

120

150+7.

0V

Com

posi

te v

ideo

sign

al in

put

10k

47µ

Fro

m m

icro

com

pute

r

+

Not

e 1

+5.

0V

470+7.

0V

Ext

erna

l com

posi

te v

ideo

sig

nal i

nput

47 µ

Not

e 2

1.50

V

75

220µ

+

Not

e 5

47P

Not

e 6

+

1 2 3 4 5 6 7 8 9 1011121314151620 19 18 17

CP

1

TE

ST

A

SIN

CV

IDE

O

LEC

HA

CV

IN

SC

K

VD

D2

CS

AC

VD

D1

VS

S

HO

R P1

P0

OS

CIN

TE

ST

B

CP

2

TE

ST

C

1µ+

1µ10

0µ

0.01

µ

+5.

0V

++

Not

e 4

1k

0.01

µ

0.22

µ

470P

1.5k

fsc

Not

e 3

+5.

0V

0.1µ

1µ10

0µ++

VS

S

Not

e 7

Del

ayci

rcui

t

In d

ispl

ayin

g co

lor

supe

rim

posi

tion,

ent

erin

to t

he

OS

CIN

pin

th

e f

SC

sig

na

l th

at

phas

e-sy

nchr

oniz

es w

ith t

he c

olor

bur

st o

fth

e co

mpo

site

vid

eo s

igna

ls (

inpu

t to

the

CV

IN p

in).

VO

SC

IN






25

Fig. 14 Example of display

Fig. 15 Example of display

Precautions(1) Points to note in setting the display RAMs

a) Be careful to the edges may sway depending on the combina-tion of character’s background color and raster color.

b) If what display exceeds the display area in dealing with exter-nal synchronization, (if use double - size characters), set thecharacter code of the addresses lying outside that display areablank code – “FF16”.

Edge sway

0C16

2416

Outside of display areaInside of display

part.

Out

side

of

disp

lay

area

Insi

de o

f dis

play

0016

1816

0B16

2F16

1716

Numbers are adresses

2316

3016

4816

4716

5F16

C016

D816 EF16

D716

Set blank code “FF16” to character code of






26

(2) Before setting registers at the starting of system, be sure to reset__

the M35052-XXXSP/FP by applying “L” level to the AC pin.

(3) Power supply noiseWhen power supply noise is generated, the internal oscillator cir-cuit does not stabilize, whereby causing horizontal jitters acrossthe picture display. Therefore, connect a bypass capacitor be-tween the power supply and GND.

(4) Synchronous correction actionWhen switching channel or in the special playback mode (quickplayback, rewinding, and so on) of VTR, effect of synchronouscorrection becomes strong, and distortion of a character is apt tooccur because the continuity of video signal is suddenly switched.When the continuity of video signal is out of order, erasure ofdisplayed characters is recommended in a extreme short time toraise the quality of displayed characters.

(5) Notes on f SC signal inputThis IC amplifies the subcarrier frequency (fSC) signal (NTSC, M-PAL system: 3.58MHz, PAL system: 4.43MHz) input to the OSCINpin (17-pin) and generates the composite video signal internally.The amplified fSC signal can be destabilized in the following cases.a) When the fSC signal is outside of recommended operating con-

ditions.b) When the waveform of the fSC signal is distorted.c) When DC level in the fSC waveform fluctuates.

When the amplified signal is unstable, the composite videosignal generated inside the IC is also unstable in terms of syn-chronization with the subcarrier and phase.Consequently, this results in color flicker and lost synchroniza-tion when the composite video signal is generated. Make noteof the fact that this may prevent a stable blue background frombeing formed.

(6) Forbidding to stop entering the f SC signalThis IC doesn’t properly work if the fSC signal is not entered intothe OSCIN pin (pin 17), so don’t stop the fSC signal so as to workthe IC. To stop the IC, turn the display off (set 0 in the registerDSPON (address F816).)

(7) Forbidding to set data during the period in which the internaloscillation circuit stabilizesa) To start entering the fSC signal when its input is stopped.b) To start oscillating the oscillation circuit for display when its

oscillation is stopped. (to assign “1” to the register STOP1 (ad-dress F816) when it is assigned “0”, or the like.)

c) To turn on the internal bias when it is turned off. (to assign “1”to the register LEVEL1 (address F816) when it is assigned “0”.)

There can be instances in which data are not properly set in theregisters until the internal oscillation circuit stabilizes, so followthe steps in sequence as given below.

1) Set “0” in the register DSPON (address F816). (the display is turnedoff)

2) Effect the settings a), b), and c) given above.

3) Wait 20 ms (the period necessary for the internal oscillation cir-cuit to stabilize) before entering data.

4) Set necessary data in other registers, and make the display RAMready.






27

Parameter

SCK width__

CS setup time__

CS hold time

SIN setup time

SIN hold time

1 word writing time

Symbol

tw(SCK)__

tsu(CS)__

th(CS)

tsu(SIN)

th(SIN)

tword

Min.

400

200

2

200

200

12.8

Unit

ns

ns

µs

ns

ns

µs__ __

Note. When oscillation stop at register STOR1 (address F816), 1V (field term) or more of tSU(CS) and th(CS) are needed.

Max.

—

—

—

—

—

—

Typ.

—

—

—

—

—

—

Limits

TIMING REQUIREMENTS (Ta = –20°C to 70°C, VDD = 5±0.25V, unless otherwise noted)

Fig. 16 Serial input timing requirements

SCK

CS

CS2µs(min.)

tw(CS)

tw(SCK)

tsu(SIN) th(SIN)

tsu(CS) th(CS)tw(SCK)

SIN

SCK

tword

1 2 1614 153 1 2 1614 153






28

24 characters10 lines

32 characters7 lines

Symbol

VDD

VI

VO

Pd

Topr

Tstg

Parameter

Supply voltage

Input voltage

Output voltage

Power dissipation

Operating temperature

Storage temperature

Conditions

With respect to VSS

Ta=25°C

Ratings

–0.3~6.0

VSS–0.3≤VI≤VDD+0.3

VSS≤VO≤VDD

300

–20~70

–40~125

Unit

V

V

V

mW

°C

°C

Limits

Min.

4.75

0.8VDD

0

–

0.3VP-P

–

–

–

Typ.

5.00

VDD

0

2.0VP-P

–

3.580

4.434

3.576

480fH

640fH

Max.

5.25

VDD

0.2VDD

–

4.0VP-P

–

–

–

Unit

V

V

V

V

V

MHz

MHz

MHz

Notes 1. Noise component is within 30mV.Notes 2. fH: Horizontal synchronous frequency (MHz).

Symbol

VDD

IDD

VOH

VOL

RI

Limits

Min.

4.75

–

3.75

–

10

Typ.

5.00

30

–

–

30

Max.

5.25

50

–

0.4

100

Unit

V

mA

V

V

kΩ

Parameter

Supply voltage

Supply current

“H”level output voltage P0, P1

“L” level output voltage P0, P1

Pull-up resistance__ __

AC, CS, SCK, SIN, TESTB

Symbol

VDD

VIH

VIL

VCVIN

VOSCIN

fOSCIN

fOSC1

fOSC2

Test conditions

Ta=–20~70°C

VDD=5.00V

VDD=4.75V, IOH=–0.4mA

VDD=4.75V, IOL=0.4mA

VDD=5.00V

ABSOLUTE MAXIMUM RATINGS (VDD = 5V, Ta = –20 to 70°C, unless otherwise noted)

RECOMMENDED OPERATING CONDITIONS (VDD = 5V, Ta = –20 to 70°C, unless otherwise noted)

ELECTRICAL CHARACTERISTICS (VDD = 5V, Ta = 25°C, unless otherwise noted)

Symbol

VIN-SC

Limits

Min.

–

Typ.

1.5

Max.

–

Unit

V

Parameter

Composite video signal input clamp voltage

Test conditions

Sync-chip voltage

VIDEO SIGNAL INPUT CONDITIONS (VDD = 5V, Ta = –20 to 70°C, unless otherwise noted)

Parameter

Supply voltage________ _______

“H”level input voltage AC, CS, SIN, SCK, TESTA, TESTB_________ __________

“L” level input voltage AC, CS, SIN, SCK, TESTA, TESTB

CVIN, HOR

Input voltage OSCIN (Note)

Synchronous signal oscillation frequency

(Duty 40~60%)

Display oscillation frequency






29

Note for Supplying Power(1)

__

Timing of power supplying to AC pinThe internal circuit of M35054-XXXFP/ M35055-XXXFP is reset

__

when the level of the auto clear input pin AC is “L”. This pin ishysteresis input with the pull-up resistor. The timing about power

__

supplying of AC pin is shown in Figure 16. tW is the interval afterthe supply voltage becomes 0.8 VDD or more and before the

__ __

supply voltage to the AC pin (VAC) becomes 0.2 VDD or more.After supplying the power (VDD and VSS) to M35054-XXXFP/M35055-XXXFP, the tW time must be reserved for 1ms or more.

Before starting input from the microcomputer, the waiting time(ts) must be reserved for 500ms after the supply voltage to the__

AC pin becomes 0.8 VDD or more.(2) Timing of power supplying to VDD1 pin and VDD2 pin

The power need to supply to VDD1 and VDD2 at a time, though itis separated perfectly between the VDD1 as the digital line andthe VDD2 as the analog line.

ROM ORDERING METHODPlease submit the information described below when ordering MaskROM.(1) ROM Order Confirmation Form ................................................. 1(2) Data to be written into mask ROM ................................ EPROM

(three sets containing the identical data)(3) Mark Specification Form............................................................ 1(4) Program for character font generating + froppy disk in which char-

acter data is input

PRECAUTION FOR USENotes on noise and latch-up

Connect a capacitor (approx. 0.1 F) between pins VDD and VSS atthe shortest distance using relatively thick wire to prevent noise andlatch up.

__

Fig. 17 Timing of power supplying to AC pin

Supply voltageVDD

VAC

ts

Voltage [V]

Time t [s]

(AC pin input voltage)0.8VDD

0.2VDD

tw






30

STANDARD ROM TYPE : M35054-001FPM35054-001FP is a standard ROM type of M35054-XXXFPcharacter patterns are fixed to the contents of Figure 18 to 19.






31

Fig. 18 M35054-001FP character pattern (1)

0016 0116 0216 0316 0416 0516 0616 0716

0816 0916 0A16 0B16 0C16 0D16 0E16 0F16

15161016 13161116 1216 1416 1616 1716

1816 1916 1A16 1B16 1C16 1D16 1E16 1F16

2016 2116 2216 2316 2416 2516 2616 2716

2816 2916 2A16 2B16 2C16 2D16 2E16 2F16

3016 3116 3216 3316 3416 3516 3616 3716

3816 3916 3A16 3B16 3C16 3D16 3E16 3F16






32

4016 4116 4216 4316 4416 4516 4616 4716

4816 4916 4A16 4B16 4C16 4D16 4E16 4F16

5016 5116 5216 5316 5416 5516 5616 5716

7816 7916 7A16 7B16 7C16 7D16 7E16 7F16


5816 5916 5A16 5B16 5C16 5D16 5E16 5F16

6016 6116 6216 6316 6416 6516 6616 6716

6816 6916 6A16 6B16 6C16 6D16 6E16 6F16

7016 7116 7216 7316 7416 7516 7616 7716






33

STANDARD ROM TYPE : M35055-001FPM35055-001FP is a standard ROM type of M35055-XXXFPCharacter patterns are fixed to the contents of Figure 20 to 23.






34


0016 0116 0216 0316 0416 0516 0616 0716

0816 0916 0A16 0B16 0C16 0D16 0E16 0F16

1016 13161116 1216 1416 1516 1616 1716

1816 1916 1A16 1B16 1C16 1D16 1E16 1F16

2016 2116 2216 2316 2416 2516 2616 2716

2816 2916 2A16 2B16 2C16 2D16 2E16 2F16

3016 3116 3216 3316 3416 3516 3616 3716

3816 3916 3A16 3B16 3C16 3D16 3E16 3F16






35


4016 4116 4216 4316 4416 4516 4616 4716

7816 7916 7A16 7B16 7C16 7D16 7E16 7F16

7016 7116 7216 7316 7416 7516 7616 7716

6816 6916 6A16 6B16 6C16 6D16 6E16 6F16

6016 6116 6216 6316 6416 6516 6616 6716

5816 5916 5A16 5B16 5C16 5D16 5E16 5F16

5016 5116 5216 5316 5416 5516 5616 5716

4816 4916 4A16 4B16 4C16 4D16 4E16 4F16






36


8016 8116 8216 8316 8416 8516 8616 8716

8816 8916 8A16 8B16 8C16 8D16 8E16 8F16

9016 9116 9216 9316 9416 9516 9616 9716

9816 9916 9A16 9B16 9C16 9D16 9E16 9F16

A016 A116 A216 A316 A416 A516 A616 A716

A816 A916 AA16 AB16 AC16 AD16 AE16 AF16

B016 B116 B216 B316 B416 B516 B616 B716

B816 B916 BA16 BB16 BC16 BD16 BE16 BF16






37


C016 C116 C216 C316 C416 C516 C616 C716

C816 C916 CA16 CB16 CC16 CD16 CE16 CF16

D016 D116 D216 D316 D416 D516 D616 D716

D816 D916 DA16 DB16 DC16 DD16 DE16 DF16

E016 E116 E216 E316 E416 E516 E616 E716

E816 E916 EA16 EB16 EC16 ED16 EE16 EF16

F016 F116 F216 F316 F416 F516 F616 F716

F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 blank






38

PACKAGE OUTLINE



© 2000 MITSUBISHI ELECTRIC CORP.New publication, effective August. 2000.Specifications subject to change without notice.

Notes regarding these materials• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property

rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples

contained in these materials.• All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by

Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor productdistributor for the latest product information before purchasing a product listed herein.The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).

• When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decisionon the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.

• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi ElectricCorporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,aerospace, nuclear, or undersea repeater use.

• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved

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• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

Keep safety first in your circuit designs!• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to

personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammablematerial or (iii) prevention against any malfunction or mishap.






Rev. Rev.

No. date

1.0 First Edition 980402

1.1 P48 20P2Q-A (20-PIN SSOP) MARK SPECIFICATION FORM 000707

B: Note 4 added

1.2 Delete Mask ROM ORDER CONFIRMATION FORM and MASK SPECIFICATION FORM 000829

REVISION DESCRIPTION LIST M35054-XXXFP/M35055-XXXFP DATA SHEET

(1/1)

Revision Description



Documents

Regarding the change of names mentioned in the document