Regarding the change of names mentioned in the document ... · PDF filecircuit application examples contained in these materials. ... FS4 FS3 FS2 FS1 FS0 CPU SDCLK ZCLK AGP ... MULTISEL

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Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

Keep safety first in your circuit designs!

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HD151TS407SSMother Board Clock Generator

for SiS 645/645DX/648/648FX/650/651/655/660 P4 Chipset

ADE-205-703A (Z)

PreliminaryRev.1

Nov. 2002

DescriptionThe HD151TS407 is a high-performance, low-skew, low-jitter, PC motherboard Clock generator. It isspecifically designed for SiS 645/645DX/648/648FX/650/651/655/660 Pentium®4 chip set.

Features• 1 memory clock up to 200 MHz (DDR200/266/333/400 Support).• 2 differential pairs of current mode control CPU clock.• 6 PCI clocks and 2 PCI_F clocks @3.3 V, 33.3 MHz typ.• 2 copies of AGP clock @3.3V, 66.6 MHz typ.• 2 Zclock @3.3 V, up to 133.3 MHz.• 1 copy of 48 MHz for USB @3.3 V• 12 MHz / 48 MHz, 24 MHz / 48 MHz selectable clock @3.3 V• 3 copies of 14.318 MHz reference clock @3.3 V• Power save and clock stop function.• Programmable clock output skew control function.• I2CTM serial port programming.• Spread Spectrum modulation (–0.5/–1.0/–1.5/–2.0% or ±0.25/±0.50/±0.75/±1.0%).• Watchdog timer and reset output.• VCO Direct Frequency Setting function.• 48pin SSOP (300 mils).• Supports 3 × DDR DIMM application with clock buffer HD74CDCV851 (SSOP48pin)• Supports 2 × DDR DIMM Micro-ATX application with clock buffer HD74CDCV852 (SSOP28pin)• Ordering Information

Part Name Package Type Package Code PackageAbbreviation

TapingAbbreviation (Quantity)

HD151TS407SSEL SSOP-48 pin SS EL (1,000 pcs / Reel)Note: Please consult the sales office for the above package availability.

Note: I2C is a trademark of Philips Corporation.Pentium is registered trademark of Intel Corporation

HD151TS407SS

Rev.1, Nov. 2002, page 2 of 35

Key Specifications

• Supply Voltages: VDD = 3.3 V ±5%• Clock cycle to cycle jitter = |100| ps typ• CPU clock group Skew = 150 ps max• AGP clock group Skew = 175 ps max• ZCLK clock group Skew = 175 ps max• PCI clock group Skew = 500 ps max• CPU(early) to PCI, AGP & ZCLK offset = 1 to 4 ns (typ. 2ns)

HD151TS407SS


Pin Arrangement

1

2

3

4

5

6

7

8

9

10

VDDREF

*FS0/REF0

*FS1/REF1

*FS2/REF2

GNDREF

X1

X2

GNDZ

ZCLK1

VDDZ

PCI_STP#/WDRESET#

VDDPCI

FS3*/PCI_F0

FS4*/PCI_F1

PCI0

PCI1

GNDPCI

VDDPCI

PCI2

PCI3

PCI4

PCI5

GNDPCI

ZCLK0

11

12

13

14

15

16

17

18

19

20

21

22

23

24 25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

GND48

24MHz/48MHz/MULTISEL*

48MHz/12MHz

VDDAGP

AGPCLK1

VDDA

GNDAGP

PD#/VTT_PWRGD

GNDA

CPU0C

CPU0T

GNDCPU

AGPCLK0

VDDCPU

CPU1C

CPU1T

GNDSD

VDDSD

SDCLK

VDD48

SDATA

SCLK

IREF

CPU_STP#

(Top view)

* Latch input / multi function pin.

Note: FS0, 1, 2, 3, 4 = 120 kΩ Internal Pull-down.PCI_STP#, MULTISEL, PD#, CPU_STP# = 120 kΩ Internal Pull-up.27 Pin = 48 MHz when power on.26 Pin = 24 MHz when power on.

HD151TS407SS


Block Diagram

Synthesizer

(CPU PLL)

Mode Control

Logic

1/n1OSC

XTAL

14.318 MHz

SSC Modulator

3.3 V VDD48

3× REF 3.3 (14.318 MHz)

2× CPUCLK (HCSL)

1× SDCLK 3.3

Note: Latched Input / Multi Function pin.

3.3 V VDDAGND48 GNDA 7× 3.3V VDD 7×GND IREF

6× PCICLK 3.3

2× ZCLK 3.3

2× AGP 3.3

48/12 MHz 3.3

*FS0, 1, 2, 3, 4

SCLKSDATA

CPU_STP#

*MULTISELPD#

PCI_STP#

Synthesizer

(48 MHz PLL)

1/n2

1/m2

1/m1Clock

Divider

Clock

Divider

2× PCICLK_F 3.3

24/48 MHz 3.3

WDRESET#

ClockDivider

WatchdogTimer

HD151TS407SS


Table1 Clock Frequency Function Table & I2C

Byte4 (bit2, 4, 5, 6 & 7)

Bit2 Bit7 Bit6 Bit5 Bit4

FS4 FS3 FS2 FS1 FS0 CPU SDCLK ZCLK AGP PCICLK FSB DDR VCO

0 0 0 0 0 100 100 133.33 66.67 33.33 0 400 200 400

0 0 0 0 1 100 133.33 133.33 66.67 33.33 1 400 266 400

0 0 0 1 0 100 166.67 125 62.5 33.33 2 400 333 500

0 0 0 1 1 100 200 133.33 66.67 33.33 3 400 400 400

0 0 1 0 0 133.33 100 133.33 66.67 33.33 4 533 200 400

0 0 1 0 1 133.33 133.33 133.33 66.67 33.33 5 533 266 400

0 0 1 1 0 133.33 166.67 133.33 66.67 33.33 6 533 333 667

0 0 1 1 1 133.33 200 133.33 66.67 33.33 7 533 400 400

0 1 0 0 0 133.33 166.67 133.33 50 33.33 8 533 333 667

0 1 0 0 1 200 133.33 133.33 66.67 33.33 9 800 266 400

0 1 0 1 0 222.22 166.67 133.33 66.67 33.33 10 667

0 1 0 1 1 200 200 133.33 66.67 33.33 11 800 400 400

0 1 1 0 0 166.67 166.67 133.33 50 33.33 12 667 333 667

0 1 1 0 1 166.67 133.33 133.33 66.67 33.33 13 667 266 667

0 1 1 1 0 166.67 166.67 133.33 66.67 33.33 14 667 333 667

0 1 1 1 1 166.67 222.22 133.33 66.67 33.33 15 667 444 667

1 0 0 0 0 100 100 66.67 66.67 33.33 16 400 200 400

1 0 0 0 1 100 133.33 66.67 66.67 33.33 17 400 266 400

1 0 0 1 0 100 166.67 62.5 62.5 33.33 18 400 333 500

1 0 0 1 1 100 200 66.67 66.67 33.33 19 400 400 400

1 0 1 0 0 133.33 100 66.67 66.67 33.33 20 533 200 400

1 0 1 0 1 133.33 133.33 66.67 66.67 33.33 21 533 266 400

1 0 1 1 0 133.33 166.67 66.67 66.67 33.33 22 533 333 667

1 0 1 1 1 133.33 200 66.67 66.67 33.33 23 533 400 400

1 1 0 0 0 140 175 116.67 63.6 33.3 24 700

1 1 0 0 1 145 193.3 116 64.4 32.2 25 580

1 1 0 1 0 150 150 120 66.67 33.33 26 600

1 1 0 1 1 155 155 124 62 32.6 27 620

1 1 1 0 0 160 160 128 64 32 28 640

1 1 1 0 1 133.33 133.33 100 66.67 33.33 29 533 266 400

1 1 1 1 0 133.33 166.67 95.24 66.67 33.33 30 533 333 667

1 1 1 1 1 133.33 200 100 66.67 33.33 31 533 400 400

HD151TS407SS


Table2 Outputs State at Power Down

INPUT OUTPUTS

PD# CPUT CPUC SDCLK PCICLK ZCLK AGP 24/48 MHz 48 MHz0 2 × IREF Hi-Z L L L L L L

1 Run Run Run Run Run Run Run Run

Table3 CPUCLK Outputs Specification

MULTISEL (pin26) Board TargetTrace / Term Z

Reference R,Iref = VDD / (3Rr)

Output Current Ioh Voh @Z

1 60 Ω Rr = 475 1%I_REF = 2.32 mA

6 × Iref 0.85 V @60 Ω

1 50 Ω Rr = 475 1%I_REF = 2.32 mA

6 × Iref 0.71 V @50 Ω

0 60 Ω Rr = 475 1%I_REF = 2.32 mA

4 × Iref 0.56 V @60 Ω

0 50 Ω Rr = 475 1%I_REF = 2.32 mA

4 × Iref 0.47 V @50 Ω

HD151TS407SS


I2C Controlled Register Bit Map

Byte0, 1, 2, 3 are reserved. All bits are default “1” at POWER ON.

Byte4 CLK Frequency & SSC Control Register

Bit Description Contents Default

7 Clock frequency control bit (See Table1) 0




3 Clock frequency select mode bit 0 = Freq. is selected by latched input FS0:41 = Freq. is selected by I2C Byte4 bit2, 4–7

0


1 SSC enable bit 0 = SSC ON, 1 = SSC OFF 0

0 Outputs (all outputs) enable bit 0 = Running1 = Tristate all outputs

0

Byte5 48MHz Clock & SSC Control Register

Bit Description Contents Default7 (Reserved) 0

6 (Reserved) 0

5 24MHz or 48MHz select When this bit = “0”, pin26 outputs 48MHzWhen this bit = “1”, pin26 outputs 24MHz 1

4 48MHz or 12MHz select When this bit = “0”, pin27 outputs 48MHzWhen this bit = “1”, pin27 outputs 12MHz 0

3 Spread Spectrum Control bit3 0



0 Spread Spectrum Control bit0

0000 = –0.5% (Default) 1000 = ±0.25%0001 = –0.75% 1001 = ±0.375%0010 = –1.0% 1010 = ±0.5%0011 = –1.5% 1011 = ±0.75%0100 = –2.0% 1100 = ±1.0% 0

HD151TS407SS


I2C Controlled Register Bit Map (cont.)

Byte6 Multi Input-pin Read Back Register


7 (Reserved bit) 0

6 (Reserved bit) 0

5 MULTISEL (pin26) read back Read only X

4 FS4 (pin15) read back Read only X





Byte7 Byte Count Read Back Register

Bit Description Contents Default7 Byte count setting bit7 0

6 Byte count setting bit6 0






0 Byte count setting bit0

Writing to this register will configure byte countand how many bytes will be read back.Default is 1Ehex = 30 bytes.

0

HD151TS407SS



Byte8 Byte Vendor/Device ID Read Back Register


7 Vendor ID bit3 1

6 Vendor ID bit2 1

5 Vendor ID bit1 1

4 Vendor ID bit0

Hitachi = “1111”Read Only

1

3 Device ID bit3 0

2 Device ID bit2 0

1 Device ID bit1 0

0 Device ID bit0

Read Only

1Note: Don’t write to this byte.

Byte9 Clock Stop Control Register

Bit Description Contents Default7 (Reserved bit) 0

6 (Reserved bit) 0

5 (Reserved bit) 0

4 CPU1T/C state control at powerdown mode.

0 = CPU1T outputs 2 × Iref current and CPU1C istristate when PD# asserted.1 = Both CPU1T and CPU1C are tristate whenPD# asserted.

0

3 CPU0T/C state control at powerdown mode.

0 = CPU0T outputs 2 × Iref current and CPU0C istristate when PD# asserted.1 = Both CPU0T and CPU0C are tristate whenPD# asserted.

0

2 PCI_STP# (pin12) function enable 0 = Enable, 1 = Disable 0

1 CPU_STP# (pin45) function enable 0 = Enable, 1 = Disable 0

0 PD# (pin33) function enable 0 = Enable, 1 = Disable 0

HD151TS407SS

Rev.1, Nov. 2002, page 10 of 35


Byte10 CPU_STP# Control Register


7 AGPCLK1 (pin30) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1

6 AGPCLK0 (pin31) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1

5 CPU_STP# (pin45) function(AGPCLK1 control)

1 = AGPCLK1 will be stopped by CPU_STP#0 = AGPCLK1 will not be stopped by CPU_STP#(AGPCLK1 = free running)

0

4 CPU_STP# (pin45) function(AGPCLK0 control)

1 = AGPCLK0 will be stopped by CPU_STP#0 = AGPCLK0 will not be stopped by CPU_STP#(AGPCLK0 = free running)

0

3 CPU1T/C output enable 1 = Enable, 0 = Disable (Tristate) 1

2 CPU0T/C output enable 1 = Enable, 0 = Disable (Tristate) 1

1 CPU_STP# (pin45) function(CPU1T/C control)

1 = CPU1T/C will be stopped by CPU_STP#0 = CPU1T/C will not be stopped by CPU_STP#(CPU1T/C = free running)

1

0 CPU_STP# (pin45) function(CPU0T/C control)

1 = CPU0T/C will be stopped by CPU_STP#0 = CPU0T/C will not be stopped by CPU_STP#(CPU0T/C = free running)

1

Byte11 PCI_STP# Control Register

Bit Description Contents Default7 PCI_STP# (pin12) function

(PCI_F1 Control)0

6 PCI_STP# (pin12) function(PCI_F0 Control)

0

5 PCI_STP# (pin12) function(PCI5 Control)

1


1


1


1


1


1 = PCI_F[1:0] & PCI[5:0] will be stopped byPCI_STP# pin.0 = PCI_F[1:0] & PCI[5:0] will not be controlled byPCI_STP# pin. (free running)

1

HD151TS407SS

Rev.1, Nov. 2002, page 11 of 35


Byte12 PCI Clock Outputs Control Register


7 PCI_F1 (pin15) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1

6 PCI_F0 (pin14) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1

5 PCI5 (pin23) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1






Byte13 Peripheral clocks Control Register

Bit Description Contents Default7 REF2 (pin4) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1

6 REF1 (pin3) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1

5 REF0 (pin2) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1

4 24_48MHz (pin26) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1

3 48MHz (pin27) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1

2 ZCLK1 (pin10) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1

1 ZCLK0 (pin9) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1

0 SDCLK (pin47) output enable 1 = Enable, 0 = Disable (DC Low fixed) 1

HD151TS407SS

Rev.1, Nov. 2002, page 12 of 35


Byte14 CPU Clock Skew Control Register


7 CPUT/C skew control bit3 1



4 CPUT/C skew control bit0

1000 = Delay 0 ps 0111 = Ahead 250 ps1001 = Delay 250 ps 0110 = Ahead 500 ps1010 = Delay 500 ps 0101 = Ahead 750 ps1011 = Delay 750 ps 0100 = Ahead 1000 ps1100 = Delay 1000 ps 0011 = Ahead 1250 ps1101 = Delay 1250 ps 0010 = Ahead 1500 ps1110 = Delay 1500 ps 0001 = Ahead 1750 ps1111 = Delay 1750 ps 0000 = Ahead 2000 ps

0




0 CPUT/C skew control bit0


0

Byte15 SDCLK & ZCLK Clock Skew Control Register

Bit Description Contents Default7 ZCLK skew control bit3 1

6 ZCLK skew control bit2 0

5 ZCLK skew control bit1 0

4 ZCLK skew control bit0


0

3 SDCLK skew control bit3 1



0 SDCLK skew control bit0


0

HD151TS407SS

Rev.1, Nov. 2002, page 13 of 35


Byte16 AGP Clock Skew Control Register


7 AGPCLK skew2 control bit3 0



4 AGPCLK skew2 control bit0

1000 = Delay 4000 ps 0111 = Delay 3500 ps1001 = Delay 4500 ps 0110 = Delay 3000 ps1010 = Delay 5000 ps 0101 = Delay 2500 ps1011 = Delay 5500 ps 0100 = Delay 2000 ps1100 = Delay 6000 ps 0011 = Delay 1500 ps1101 = Delay 6500 ps 0010 = Delay 1000 ps1110 = Delay 7000 ps 0001 = Delay 500 ps1111 = Delay 7500 ps 0000 = Delay 0 ps

0




0 AGPCLK skew1 control bit0

Set Early Skew1000 = Delay 0 ps 0111 = Ahead 500 ps1001 = Delay 500 ps 0110 = Ahead 1000 ps1010 = Delay 1000 ps 0101 = Ahead 1500 ps1011 = Delay 1500 ps 0100 = Ahead 2000 ps1100 = Delay 2000 ps 0011 = Ahead 2500 ps1101 = Delay 2500 ps 0010 = Ahead 3000 ps1110 = Delay 3000 ps 0001 = Ahead 3500 ps1111 = Delay 3500 ps 0000 = Ahead 4000 ps

0

Byte17 PCI_F & PCI Clock Skew Control Register

Bit Description Contents Default7 PCI_F & PCI skew2 control bit3 0

6 PCI_F & PCI skew2 control bit2 0


4 PCI_F & PCI skew2 control bit0

1000 = Delay 4000 ps 0111 = Delay 3500 ps1001 = Delay 4500 ps 0110 = Delay 3000 ps1010 = Delay 5000 ps 0101 = Delay 2500 ps1011 = Delay 5500 ps 0100 = Delay 2000 ps1100 = Delay 6000 ps 0011 = Delay 1500 ps1101 = Delay 6500 ps 0010 = Delay 1000 ps1110 = Delay 7000 ps 0001 = Delay 500 ps1111 = Delay 7500 ps 0000 = Delay 0 ps

0




0 PCI_F & PCI skew1 control bit0

Set Early Skew1000 = Delay 0 ps 0111 = Ahead 500 ps1001 = Delay 500 ps 0110 = Ahead 1000 ps1010 = Delay 1000 ps 0101 = Ahead 1500 ps1011 = Delay 1500 ps 0100 = Ahead 2000 ps1100 = Delay 2000 ps 0011 = Ahead 2500 ps1101 = Delay 2500 ps 0010 = Ahead 3000 ps1110 = Delay 3000 ps 0001 = Ahead 3500 ps1111 = Delay 3500 ps 0000 = Ahead 4000 ps

0

HD151TS407SS

Rev.1, Nov. 2002, page 14 of 35


Byte18 AGP & PCI Skew Independent Control Register


7 AGPCLK1 skew2 control bit 0 = Disable, 1 = Enable 0

6 AGPCLK0 skew2 control bit 0 = Disable, 1 = Enable 0

5 PCI5 skew2 control bit 0 = Disable, 1 = Enable 0






Byte19 Clock Slew Rate Control Register

Bit Description Contents Default7 PCI slew rate control bit1 1

6 PCI slew rate control bit010 = Normal, 11 = –, 01 = + +, 00 = +

0

5 PCI_F slew rate control bit1 1

4 PCI_F slew rate control bit010 = Normal, 11 = –, 01 = + +, 00 = +

0

3 AGPCLK slew rate control bit1 1

2 AGPCLK slew rate control bit010 = Normal, 11 = –, 01 = + +, 00 = +

0

1 ZCLK slew rate control bit1 1

0 ZCLK slew rate control bit010 = Normal, 11 = –, 01 = + +, 00 = +

0

HD151TS407SS

Rev.1, Nov. 2002, page 15 of 35


Byte20 Clock Slew Rate Register


7 (Reserved) 0

6 (Reserved) 0

5 REF slew rate control bit1 1

4 REF slew rate control bit0

10 = Normal, 11 = –, 01 = + +, 00 = +

0

3 24_48M slew rate control bit1 1

2 24_48M slew rate control bit0

10 = Normal, 11 = –, 01 = + +, 00 = +

0

1 48MHz slew rate control bit1 1

0 48MHz slew rate control bit0

10 = Normal, 11 = –, 01 = + +, 00 = +

0

Byte21 Clock Invert Control Register


6 24_48MHz invert control bit 0 = Normal, 1 = Inverted 0

5 48MHz invert control bit 0 = Normal, 1 = Inverted 0

4 PCI_F/PCI invert control bit 0 = Normal, 1 = Inverted 0

3 AGPCLK invert control bit 0 = Normal, 1 = Inverted 0

2 ZCLK invert control bit 0 = Normal, 1 = Inverted 0

1 SDCLK invert control bit 0 = Normal, 1 = Inverted 0

0 CPUT/C invert control bit 0 = Normal, 1 = Inverted 0

Byte22 Watchdog Timer Control Register

Bit Description Contents Default7 Watchdog enable 0 = Disable, 1 = Enable 06 Watchdog status 0 = Normal, 1 = Alarm 05 PLL divide control register select 0 = Byte 4 (Bit 2, 7, 6, 5, 4)

1 = Byte 22 (Bit 4, 3, 2, 1, 0)0

4 Watchdog safe freq. setting Bit4 Correspond to Byte4/bit2 (FS4) Read Only 03 Watchdog safe freq. setting Bit3 Correspond to Byte4/bit7 (FS3) Read Only 02 Watchdog safe freq. setting Bit2 Correspond to Byte4/bit6 (FS2) Read Only 01 Watchdog safe freq. setting Bit1 Correspond to Byte4/bit5 (FS1) Read Only 00 Watchdog safe freq. setting Bit0 Correspond to Byte4/bit4 (FS0) Read Only 0

HD151TS407SS

Rev.1, Nov. 2002, page 16 of 35


Byt23 Watchdog Timer Control Register

Bit Description Contents Default7 PLL unlock detector sensitivity control

bit10

6 PLL unlock detector sensitivity controlbit0

00 = ±50%01 = ±40%10 = ±30%11 = ±20%

0

5 Watchdog Timer count bit5 04 Watchdog Timer count bit4 13 Watchdog Timer count bit3 02 Watchdog Timer count bit2 01 Watchdog Timer count bit1 00 Watchdog Timer count bit0

The decimal representation of these 6 bitscorresponds to how many 293 ms thewatchdog timer will wait before it goes to alarmmode and reset the frequency to the setting.Default at power up is 16 × 293 ms = 4.69s

0

Byte24 Reserved Register


6 (Reserved) 0

5 (Reserved) 0

4 (Reserved) 0

3 (Reserved) 0

2 (Reserved) 0

1 (Reserved) 0

0 (Reserved) 0

HD151TS407SS

Rev.1, Nov. 2002, page 17 of 35

I2C Controlled Register Bit Map (cont.)Byte25 Clock Frequency Control Register

Bit Description Contents Default7 (Reserved) 06 AGP/PCI/ZCLK PLL select bit1 0 = CPU_PLL (Normal)

1 = USP_PLL (AGP/PCI/ZCLK frequency fixed)0

5 AGP/PCI/ZCLK PLL select bit0 0 = AGP/PCI/ZCLK = 66/33/66 MHz1 = AGP/PCI/ZCLK = 66/33/132 MHzWhen Byte25 bit6 = 1.

0

4 CPU_PLL output frequency (VCOfrequency) control bit

0 = Determined by FS[4:0] or Byte4[7:2]1 = Determined by Byte25[3:0] & Byte26[7:0]

0

3 VCO frequency control bit11 02 VCO frequency control bit10 11 VCO frequency control bit9 00 VCO frequency control bit8

The 100 MHz digit of VCO frequency.0010 = 2…. 0111 = 7

0

Byte26 Clock Frequency Control Register

Bit Description Contents Default7 VCO frequency control bit7 06 VCO frequency control bit6 05 VCO frequency control bit5 04 VCO frequency control bit4

The 10 MHz digit of VCO frequency.0000 = 0, 0001 = 1 …. 1001 = 9

03 VCO frequency control bit3 02 VCO frequency control bit2 01 VCO frequency control bit1 00 VCO frequency control bit0

The 1 MHz digit of VCO frequency.0000 = 0, 0001 = 1 …. 1001 = 9

0Notes: 1. Byte25[4:0] & 26 must be written together in every case.

2. How to set and confirm clock frequency.(1) How to set VCO frequency to 666 MHz.

0 0 0 1

6ON

0 1 1 0 0 1 1 0

66

0 1 1 0

WriteByte25 Byte26

⇒max 720

min 200

(2) How to read actual frequency of VCO, CPU, SDCLK, ZCLK, AGP and PCI clock (See Byte28 – 33)

0 1 1 0

66

0 1 1 0 0 1 1 0

86

1 0 0 0

Byte25[4] = 1 actual VCO freg. read back. Byte28 Byte29

Note: Case of VCO = 666.8 MHz.Other clock frequency are able to read using the same way as shown at upper.Byte30,31 = Read back of CPU actual frequency.Byte32,33 = Read back of SDCLK actual frequency.

HD151TS407SS

Rev.1, Nov. 2002, page 18 of 35

I2C Controlled Register Bit Map (cont.)Byte27 Clock Output Divider Control Register


7 (Reserved) 0

6 Clock output divider enable bit 0 = Output divider (CPU & SDCLK) value will bedetermined by FS[4:0] or Byte4[7:2].1 = Output divider (CPU & SDCLK) value will bedetermined by Byte27[5:0].

0

5 SDCLK output divider control bit2 0

4 SDCLK output divider control bit1 0

3 SDCLK output divider control bit0

000 = 1/2, 100 = 1/6001 = 1/3, 101 = 1/7010 = 1/4, 110 = 1/8011 = 1/5, 111 = 1/9 0

2 CPU output divider control bit0 0

1 CPU output divider control bit0 0

0 CPU output divider control bit0

000 = 1/2, 100 = 1/6001 = 1/3, 101 = 1/7010 = 1/4, 110 = 1/8011 = 1/5, 111 = 1/9 0

Byte28 Clock Frequency Read Back Register

Bit Description Contents Default7 VCO Frequency read back bit15 X

6 VCO Frequency read back bit14 X


4 VCO Frequency read back bit12

The 100 MHz digit of VCO frequency0000 = 0, 0001 = 1 …. 1001 = 9Enable at Byte25[4] = 1Read only

X





The 10 MHz digit of VCO frequency.0000 = 0, 0001 = 1 …. 1001 = 9Enable at Byte25[4] = 1Read only

X

HD151TS407SS

Rev.1, Nov. 2002, page 19 of 35









X





The 0.1 MHz digit of VCO frequency.0000 = 0, 0001 = 1 …. 1001 = 9Enable at Byte25[4] = 1Read only

X


Bit Description Contents Default7 CPU Frequency read back bit15 X

6 CPU Frequency read back bit14 X


4 CPU Frequency read back bit12

The 100 MHz digit of CPU frequency.0000 = 0, 0001 = 1 …. 1001 = 9Enable at Byte25[4] = 1Read only

X






X







The 1 MHz digit of CPU frequency.0000 = 0, 0001 = 1 …. 1001 = 9Enable at Byte25[4] = 1Read only

X





The 0.1 MHz digit of CPU frequency.0000 = 0, 0001 = 1 …. 1001 = 9Enable at Byte25[4] = 1Read only

X

HD151TS407SS

Rev.1, Nov. 2002, page 20 of 35




7 SDCLK Frequency read back bit7 X



4 SDCLK Frequency read back bit4

The 100 MHz digit of SDCLK frequency.0000 = 0, 0001 = 1 …. 1001 = 9Enable at Byte25[4] = 1Read only

X






X


Bit Description Contents Default7 SDCLK Frequency read back bit7 X





X





The 0.1 MHz digit of SDCLK frequency.0000 = 0, 0001 = 1 …. 1001 = 9Enable at Byte25[4] = 1Read only

X

HD151TS407SS

Rev.1, Nov. 2002, page 21 of 35

CPU_STP#

CPUT

CPUC#

CPU_STP# Assertion/De-assersion

CPU_STP# Assertion/Deassertion Waveforms

CPU internal

High

Hi–Z

PCI_STP#

PCI_F

PCI

PCI_STP# Assertion/De-assersion

PCI_STP# Assertion/Deassertion Waveforms

Low

PD#

CPUT

CPUC#

CPUC#

CPUT

PD# Assertion/De-assersion

PD# Assertion/Deassertion Waveforms

2*Iref (Note) High

Hi–Z (Note) High

< 1.8 ms

Byte9[4:3]

2*Iref 2*Iref

2*Iref 2*Iref

00 01 10 11

CPU1T

CPU1C

CPU2T

CPU2C

Hi-Z

Hi-Z

Hi-Z Hi-Z

Hi-Z

Hi-Z Hi-Z Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

HD151TS407SS

Rev.1, Nov. 2002, page 22 of 35

Hitachi clock generator I2C Serial Interface Operation

1. Write mode1.1 Controller (host) sends a start bit.1.2 Controller (host) sends the write address D2 (h).1.3 Hitachi clock generator will acknowledge (Hitachi clock gen. sends “Low”).1.4 Controller (host) sends a begin byte M.1.5 Hitachi clock generator will acknowledge (Hitachi clock gen. sends “Low”).1.6 Controller (host) sends a byte count N.1.7 Hitachi clock generator will acknowledge (Hitachi clock gen. sends “Low”).1.8 Controller (host) sends data from byte M to byte M+N–1.1.9 Hitachi clock generator will acknowledge each byte one at a time.1.10 Controller (host) sends a stop bit.

Start bit

1 bit 1 bit 1 bit 1 bit 1 bit7 bits 8 bits 8 bits 8 bits

Byte MSlaveaddress

Begin Byte = M Byte Count = NR/WD2(h)

Ack

1 bit

Ack

1 bit

Ack

Ack Ack

Byte M+1

8 bits 1 bit 1 bit

Stop bit

8 bits

Byte M+N–1 Ack

HD151TS407SS

Rev.1, Nov. 2002, page 23 of 35

Hitachi clock generator I2C Serial Interface Operation (cont.)

2. Read mode2.1 Controller (host) sends a start bit.2.2 Controller (host) sends the write address D2 (h).2.3 Hitachi clock generator will acknowledge (Hitachi clock gen. sends “Low”).2.4 Controller (host) sends a begin byte M.2.5 Hitachi clock generator will acknowledge (Hitachi clock gen. sends “Low”).2.6 Controller (host) sends a restart bit.2.7 Controller (host) sends the read address D3 (h).2.8 Hitachi clock generator will acknowledge (Hitachi clock gen. sends “Low”).2.9 Hitachi clock generator will send the byte count N.2.10 Controller (host) will acknowledge.2.11 Hitachi clock generator will send data from byte M to byte M+N–1.2.12 When Hitachi clock generator sends the last byte, controller (host) will not acknowledge.2.13 Controller (host) sends a stop bit.

Start bit

1 bit 1 bit 1 bit 1 bit 1 bit7 bits 8 bits 7 bits1 bit

Restart bitSlaveaddress

Slaveaddress

R/WD2(h)

R/WD3(h)

Ack

1 bit

Ack

1 bit

Ack

1 bit

Ack

1 bit

Ack

Ack

Begin Count = N

8 bits 1 bit 1 bit

Stop bit

8 bits

Byte M+N–1

8 bits 8 bits

Byte M Byte M+1 Not Ack

Begin Byte = M

Notes: 1. Hitachi clock generator is a slave/receiver, I2C component. It can read back the data stored inthe latches for the verification.

2. The data transfer rate supported by this clock generator is 100k bits/sec or less (standardmode).

3. The input is operating at 3.3 V logic levels.4. The data byte format is 8 bit bytes.5. To simplify the clock generator I2C interface, the protocol is set to use only block-write from

the controller.6. The bytes must be accessed in sequential order from lowest to highest byte with the ability to

stop after any complete byte has been transferred. The data is loaded until a stop sequence isissued.

7. At power-on, all registers are set to a default condition, as shown.

HD151TS407SS

Rev.1, Nov. 2002, page 24 of 35

Absolute Maximum Ratings

Item Symbol Ratings Unit Conditions

Supply voltage VDD –0.5 to 4.6 V

–0.5 to 5.5 V SDATA, SCLKInput voltage VI

–0.5 to 4.6 V

Output voltage *1 VO –0.5 to VDD +0.5 V

Input clamp current IIK –50 mA VI < 0

Output clamp current IOK –50 mA VO < 0

Continuous output current IO ±50 mA VO = 0 to VDD

Maximum power dissipationat Ta = 55°C (in still air)

0.7 W

Storage temperature Tstg –65 to +150 °CNotes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage

to the device. These are stress ratings only, and functional operation of the device at these orany other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute maximum rated conditions for extended periods may affect devicereliability.

1. The input and output negative voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.

Recommended Operating Conditions

Item Symbol Min Typ Max Unit ConditionsSupply voltage VDD 3.135 3.3 3.465 V

DC input signal voltage –0.3 — VDD+0.3 V

High level input voltage VIH 2.0 — VDD+0.3 V

Low level input voltage VIL –0.3 — 0.8 V

Operating temperature Ta 0 — 70 °C

HD151TS407SS

Rev.1, Nov. 2002, page 25 of 35

Pin Descriptions

Pin name No. Type Description

GND 5,8,18,24,2532,41,46

Ground GND pins

VDD 1,11,13,19,2829,42,48

Power Power supplies pins. Nominal 3.3 V.

VDDA 36 Power Power supply for PLL core.

GNDA 37 Power Power supply for PLL core.

CPUT [1:0] 44,40 OUTPUT “True” clocks of differential pair CPUCLK. These pins areHCSL outputs.

CPUC [1:0] 43,39 OUTPUT “Complementary” clocks of differential pair CPUCLK. Thesepins are HCSL outputs.

SDCLK 47 OUTPUT 3.3 V Memory clock outputs.

CPU_STP# 45 INPUT CPUCLK STOP pin.This asynchronous input halts CPU, SDRAM and AGP clocks atlogic “0” level when driven low, the stop selection can beprogrammed through I2C. 120 kΩ internal pulled-up.

PCI_F0 14 OUTPUT Free running PCI clock 3.3 V output.

(*FS3) INPUT Latch input multi function pin for frequency select.This pin is internal pull-down to GND.

PCI_F1 15 OUTPUT Free running PCI clock 3.3 V output.

(*FS4) INPUT Latch input multi function pin for frequency select.This pin is internal pull-down to GND.

PCICLK [5:0] 16,17,20,2122,23

OUTPUT 3.3 V PCI clock outputs.

PCI_STP# 12 INPUT PCICLK stop pin. Stops PCICLKs at logic “0” level when inputlow, the stop selection can be programmed through I2C.120 kΩ internal pulled-up.

OUTPUT When Byte22 bit7 = 1, this pin becomes WDRESET# opendrain output.

ZCLK [1:0] 9,10 OUTPUT Hyper Zip clock outputs.

HD151TS407SS

Rev.1, Nov. 2002, page 26 of 35

Pin Descriptions (cont.)

Pin name No. Type Description

REF0 OUTPUT 14.318 MHz reference clock.

(*FS0)

2

INPUT Latch input multi function pin for frequency select.This pin is internal pull-down to GND.

REF1 OUTPUT 14.318 MHz reference clock

(*FS1)

3


REF2 OUTPUT 14.318 MHz reference clock.

(*FS2)

4


24MHz/48MHz OUTPUT SIO clock output. Default is 24 MHz.This pin’s output frequency is able to change for 48 MHz by I2Cregister.

(*MULTISEL)

26

INPUT Latch input multi function pin for CPUCLK ’s output currentsetting.This pin is internal pull-up.

48MHz/12MHz 27 OUTPUT 3.3 V, 48 MHz USB clock output.This pin’s output frequency is able to change for 12 MHz by I2Cregister (Byte5 bit4).

AGPCLK0 31 OUTPUT AGP clock output.

AGPCLK1 30 OUTPUT AGP clock output.

VTT_PWRGD/PD#

33 INPUT Power down pin. All circuits will be powered down.(Output state of each outputs are shown in page6 Table2.)Asynchronous active low input pin used to power down thedevice into low power state. The internal clocks are disabledand VCO and the crystal are stopped. The latency of powerdown will not be greater than 3ms.

X1 6 INPUT XTAL input.

X2 7 OUTPUT XTAL output.

SDATA 34 INPUT Data input for I2C logic.This pin is internal pull-up to VDD by 120 kΩ resistor.

SCLK 35 INPUT Clock input for I2C logic.This pin is internal pull-up to VDD by 120 kΩ resistor.

IREF 38 IN A fixed resistor provides a reference current for the differentialHCSL clock outputs.

Note: FS [4:0] & MULTISEL Input logic levels are latched an internal power-on reset. Use 10 kΩ resistor toprogram logic High to VDD or GND for logic low.

HD151TS407SS

Rev.1, Nov. 2002, page 27 of 35

DC Electrical Characteristics / Serial Input Port

Ta = 0°C to 70°C, VDD = 3.3 V

Item Symbol Min Typ *1 Max Unit Test Conditions

Input Low Voltage VIL 0.8 V

Input High Voltage VIH 2.0 V

Input Current II –50 +50 µA VI = 0 V or 3.465 V,VDD = 3.465 V

Input capacitance CI 10 pF SDATA & SCLK *2

Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommendedoperating conditions.

2. Target of design, not 100% tested in production.

AC Electrical Characteristics / Serial Input port

Item Symbol Min Typ Max Unit Test Conditions NotesSCLK Frequency FSCLK 100 kHz Normal Mode

Start Hold Time tSTHD 4.0 µ s

SCLK Low Time tLOW 4.7 µ s

SCLK High Time tHIGH 4.0 µ s

Data Setup Time tDSU 250 ns

Data Hold Time tDHD 300 ns

Rise Time tr 1000 ns SDATA & SCLK 0.8 V to2.0 V

Fall Time tf 300 ns SDATA & SCLK 2.0 V to0.8 V

Stop Setup Time tSTSU 4.0 µ s

BUS Free Time betweenStop & Start Condition

tSPF 4.7 µ s

Note: Target of design, not 100% tested in production.

HD151TS407SS

Rev.1, Nov. 2002, page 28 of 35

DC Electrical Characteristics / SDCLK

Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF


VOH 3.1 V IOH = –1 mA, VDD = 3.3 VOutput voltage

VOL 50 mV IOL = 1 mA, VDD = 3.3 V

IOH –22 mA VOH = 2.0 VOutput Current

IOL 25 mA VOL = 0.8 VNote: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended

operating conditions.

AC Electrical Characteristics / SDCLK

Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF

Item Symbol Min Typ Max Unit Test Conditions NotesCycle to cycle jitter tCCS |100| ps 133 MHz, Fig1 *1

Slew rate tSL 1.0 V/ns 0.4 V to2.4 V

Clock Duty Cycle 45 50 55 %

SDCLK to CPU ClockSkew

–2.0 0 2.0 ns

Output Impedance 30 Ω

Notes: Target of design, not 100% tested in production.1. Difference of cycle time between two adjoining cycles.

HD151TS407SS

Rev.1, Nov. 2002, page 29 of 35

DC Electrical Characteristics / CPUCT/C HCSL Clock

Ta = 0°C to 70°C, VDD = 3.3 VItem Symbol Min Typ *1 Max Unit Test Conditions

Output voltage VO 1.2 V

Output Current IO I(nom) mA VDD = 3.3 V *2

Output resistance 3000 Ω VO = 1.2 VNotes: Target of design, not 100% tested in production.

1. For conditions shown as Min or Max, use the appropriate value specified under recommendedoperating conditions

2. I(nom) is output current(Ioh) shown in Page6 Table3.

AC Electrical Characteristics / CPUT/C HCSL Clock

Ta = 0°C to 70°C, VDD = 3.3 V, CL = 2 pF, Rref = 475 Ω, 6 × Iref

Item Symbol Min Typ Max Unit Test Conditions NotesCycle to cycle jitter tCCS |100| ps 133 MHz *1

CPU Group Skew(CPU clock out to CPUclock out)

tskS 150 ps

Rise time tr 175 700 ps VO = 0.14 V to0.56 V

Fall time tf 175 700 ps VO = 0.14 V to0.56 V


CPU (early) to AGP Skew 1.0 2.0 4.0 ns

CPU (early) to PCI Skew 1.0 2.0 4.0 ns

CPU (early) to ZCLKSkew

1.0 2.0 4.0 ns

Cross point voltage Vcross 0.45 ×Voh

0.55 ×Voh

V 100/133 MHz


HD151TS407SS

Rev.1, Nov. 2002, page 30 of 35

DC Electrical Characteristics / PCI Clock

Ta = 0°C to 70°C, VDD = 3.3 V, CL = 30 pF




IOH –22 mA VOH = 2.0 VOutput current



AC Electrical Characteristics / PCI Clock

Ta = 0°C to 70°C, VDD = 3.3 V, CL = 30 pF

Item Symbol Min Typ Max Unit Test Conditions NotesCycle to cycle jitter tCCS |100| ps 33.3 MHz, Fig1 *1

PCI Group Skew(PCI clock out to PCI clockout)

tskS 500 ps Rising [email protected] V to 1.5 VFig.2





HD151TS407SS

Rev.1, Nov. 2002, page 31 of 35

DC Electrical Characteristics / AGP Clock & ZCLK

Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF




IOH –22 mA VOH = 2.0 VOutput current



AC Electrical Characteristics / AGP Clock & ZCLK

Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF

Item Symbol Min Typ Max Unit Test Conditions NotesCycle to cycle jitter tCCS |200| ps 66.6 MHz, Fig1 *1

AGP Group Skew &ZCLK Group Skew

tskS 175 ps Rising [email protected] V to 1.5 VFig.2





HD151TS407SS

Rev.1, Nov. 2002, page 32 of 35

DC Electrical Characteristics / 48/12 MHz, 24/48 MHz & REF Clock

Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF




IOH –22 mA VOH = 2.0 VOutput Current



AC Electrical Characteristics / 48/12 MHz, 24/48 MHz & REF Clock

Ta = 0°C to 70°C, VDD = 3.3 V, CL = 20 pF

Item Symbol Min Typ Max Unit Test Conditions NotesCycle to cycle jitter tCCS |200| ps 48 MHz, Fig1 *1





HD151TS407SS

Rev.1, Nov. 2002, page 33 of 35

Clock Out

tcycle n

t = (tcycle n) - (tcycle n+1)CCS

tcycle n+1

Figure1 Cycle to Cycle Jitter (3.3 V Single Ended Clock Output)

Clock Outx

Clock Outy

1.5 V

tskS

1.5 V

Figure2 Output Clock Skew (3.3 V Single Ended Clock Output)

RP =49.9 Ω

RP =49.9 Ω

ZLT = ZLC = 50 ΩRS = 33.2 Ω

CPUCLKT LT

CPUCLKC

TS407

CL = 2 pFCL = 2 pF

RS = 33.2 ΩLC

RI(ref) =475 Ω

Figure3 Load Circuit for CPUCLKT/C

HD151TS407SS

Rev.1, Nov. 2002, page 34 of 35

Package Dimensions

Unit: mm

0.13 M

0.15

7.50

± 0

.31 24

2548

15.85 ± 0.3

0.635

0.78 Max

0.10

Min

2.65

Max 10.40 ± 0.4

0.60 ± 0.2

1.45

0.25 ± 0.1

0.15

± 0

.05

0˚ - 10˚

HD151TS407SS

Rev.1, Nov. 2002, page 35 of 35

Disclaimer

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,copyright, trademark, or other intellectual property rights for information contained in this document.Hitachi bears no responsibility for problems that may arise with third party’s rights, includingintellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you havereceived the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,contact Hitachi’s sales office before using the product in an application that demands especially highquality and reliability or where its failure or malfunction may directly threaten human life or cause riskof bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularlyfor maximum rating, operating supply voltage range, heat radiation characteristics, installationconditions and other characteristics. Hitachi bears no responsibility for failure or damage when usedbeyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeablefailure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or otherconsequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.

Sales offices

Hitachi, Ltd.Semiconductor & Integrated CircuitsNippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, JapanTel: (03) 3270-2111 Fax: (03) 3270-5109

Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.

Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-6538-6533/6538-8577 Fax : <65>-6538-6933/6538-3877URL : http://semiconductor.hitachi.com.sg

URL http://www.hitachisemiconductor.com/

Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://semiconductor.hitachi.com.tw

Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk

Hitachi Europe GmbHElectronic Components GroupDornacher Str 3D-85622 FeldkirchenPostfach 201, D-85619 FeldkirchenGermanyTel: <49> (89) 9 9180-0Fax: <49> (89) 9 29 30 00

Hitachi Europe Ltd.Electronic Components GroupWhitebrook ParkLower Cookham RoadMaidenheadBerkshire SL6 8YA, United KingdomTel: <44> (1628) 585000Fax: <44> (1628) 778322

Hitachi Semiconductor (America) Inc.179 East Tasman DriveSan Jose,CA 95134 Tel: <1> (408) 433-1990Fax: <1>(408) 433-0223

For further information write to:

Colophon 7.0

Documents

Regarding the change of names mentioned in the document ... · PDF filecircuit application examples contained in these materials. ... FS4 FS3 FS2 FS1 FS0 CPU SDCLK ZCLK AGP ... MULTISEL