Register Transfer Language - Springer978-3-540-47774-7/1 · Appendix A Register Transfer Language Usually, a register transfer language is used, to specify the meaning of machine

Appendix A

Register Transfer Language

Usually, a register transfer language is used, to specify the meaning of machine instructions and to specify how they should be executed. In this book, we therefore use the following notations in order to describe how to manipulate the contents of a machine's registers and main memory.

P [m: n]

xr~y

<< arith, >>ari th

A,V,|

indicates a data transfer or assignment of n-bit length. The subscript n is omitted when the length is clear. Rd = Rs The contents of the source register Rs is transferred to the destination register Rd.

specifies a bit range of register Rs, to select parts of the register's contents. Rl[4 : 0] accesses the 5 least significant bits of register R1.

concatenates the fields X '~ and Y. The superscript n replicates the field X. Rd = 0311 The least significant bit of register Rd is set to 1 all other are cleared (0).

indicate logical left shift, logical right shift, arithmetic left shift and arithmetic right shift. The two left shifts are identical. R1 << 3 shifts the contents of register R1 3 bits to the left.

indicate the logical operations AND, OR and XOR. They are performed bitwise.

202 A P P E N D I X A. R E G I S T E R T R A N S F E R L A N G U A G E

M[ea]

( test ? argl :

specifies a memory access, The effective address ea selects a 1-byte data from memory. Rd = 024M[ea] reads a byte from memory, extends it with zero and assigns it to register Rd,

arg2 ) If the test is true, argument argl is taken otherwise argument arg2 is taken. Rd = (Rsl > Rs2 ? 1 : 0) If the contents of register Rsl is greater than the one of register Rs2 then Rd is set to 1 and to 0 otherwise,

Appendix B

Cost and Run Time Programs

This chapter lists all the programs required to compute the cost and the cycle time of the designs described in this book. The programs are written in the programming language C and comprise several modules.

The module eva lua te provides the quality ratio Qq(A, B,) and the equal quality parameter EQ(A, B,) of section 2.3, and module recline handles the technology specific part of our architecture model, i.e., it defines the cost and the delay of the basic components of section 2.4.1. The modules ha rdc t r and raicroctr provide the cost and the delay functions of the hardwired control respectively of the microcoded control. Module macro provides the combinatorial circuits of chapter 3 as a macro library of some sort. In order to refer to all these modules as a whole, we use the term service modules.

The architecture specific part is implemented in the main module which we call the archilectural module. The architectural module comprises several parts. First, it specifies the cost and the delay of the different environments. It then provides functions for the cost of the data paths and of the whole machine, and it provides functions for the duration of all the cycles involved. Finally, the third part implements the evaluation of the design variants.

In order to enable a module m to access the functions of a service module without any problems, each of the service modules consists of two files. The code file f i l e . c, where file indicates the name of the service module, contains the actual C functions. The header file f i l e . h specifies the types of the variables and functions and defines the data structures used.

All programs are available via FTP at f tp-wjp , c s . u n i - s b . d e in directory /pub/architecture/{programs. tar.gz, programs, tar} or via WWW at address http://www-wjp, cs. uni-sb, de/teaching/books .html.

204 APPENDIX B. COST AND RUN TIME PROGRAMS

B . 1 M o d u l e o f t h e Q u a l i t y M e t r i c

In section 2.3, we introduced the quality ratio Qq(A, B, ) of two designs and their equal quality parameter EQ(A, B,). These functions are required to evaluate different variants of a design. We therefore added module e v a l u a t e .

B.1.1 Header File of the Qual i ty Funct ions **************************************************************** ** evaluate.h quality ratio Q(q,A,B) and equal quality ** ** parameter EQ(A,B) of two designs A,B ** **************************************************************** /* q : quality parameter q */ /* ca, ta : cost, delay of A cb, tb : cost, delay of B */ / , */ /* Let F be the faster and S be the slower of the designs. */ /* Eq(F,S) = Eq(S,F) defined for */ /* a) ts > tf and cs <= cf; b) ts >= tf and cs < cf */

/* Degenerated cases: */ /* ts = tf and cs = cf: always same quality: EQ(S,F) := +2 */ /2 ts > tf and cs > cf: never same quality: EQ(S,F) := -2 */ / , */

#ifndef EVALUATE_H #define EVALUATE_H

extern double eval_q(); extern double eval_EQ();

#endif

/ * q, ca , t a , cb, t b * / /2 ca, t a , cb, t b * /

B.1.2 Code File for the Qual i ty Funct ions **************************************************************** ** evaluate.c quality ratio q(q,A,B) and equal quality ** ** parameter Eq(A,B) of two designs A,B **

#include <math.h>

double evalQ(q,ca,ta,cb,tb) double q; int ca,ta,cb,tb;

double c,t,r;

r = (1.0*cb)/(1.0*ca); c = pow(r, q); r = (1.0*tb)/(1.0*ta); t = pow(r, i.O-q); r = c*t ;

B.2. TECHNOLOGY SPECIFICATION 205

return r;

double eval_Eq(ca,ta,cb,tb) int ca,ta,cb,tb; { double c,t,r;

c = ( 1 . 0 * c a ) - ( 1 . 0 * c b ) ; t = ( 1 . 0 * t a ) - ( 1 . 0 * t b ) ; r= c,t;

if ( r > O) { /* faster design is cheaper */

r e t u r n -2 ; } e l s e { if ((c :: o) ~ (t :: o))

{ /* both designs of equal quality */ return +2;

}

else { /* standard case */

C = (l.O*ca)/(l.O*cb); t = (l.O*ta)/(l.O*tb); r = log(t)/log(t/c); return r;

B.2 Technology Specification Cost and delay of the basic components (section 2.4.1) are the only technology specific parameters. Here, we use two sets of technology parameters, described by the following two files. One set indicated as Motorola technology is based on Motorola's H4C CMOS sea-of-gate design series [NB93]. The other set is based on the VENUS design system [tINS86, Sie88].

B.2.1 Header File of the Technology Module ****************************************************************

** techno.h technology header module ** ****************************************************************

#ifndef TECHNO_H #define TECHNO_H

#define MOTOROLA 0 #define VENUS I

/* Motorola H4C technology, 1993 */ /* Venus Design System,

206 A P P E N D I X B. C O S T A N D R U N T I M E P R O G R A M S

extern extern extern extern extern extern

extern extern

extern

extern

#endif

(Arno, SMM PhD Thesis) */

int cinv, cand, cot, cnand, cnor; int cxor, cxnor, cmux, cdriv, cff; int cramcell, delta; double romfac; int dinv, dand, dor, dnand, dnor; int dxor, dxnor, dmux, ddriv, dff;

int cram(), cram2(), crom(); int dram(), dram2(), drom();

int init_techno();

char* name_techno();

/* initialize technology parameters */

/* name: current technology */

B.2.2 Code File of the Technology Module ****************************************************************

** t e c h n o . c t e c h n o l o g y pa rame te r module ** ****************************************************************

#define IN_TECHNO #include <stdio.h> #include <math.h> #include "techno.h"

extern int ld(); static int technology=O;

int cinv, cand~ cot, cnand, cnor; int cxor, cxnor, cmux, cdriv, cff; int cramcell, delta; double romfac; int dinv, dand, dot, dnand, dnor; int dxor, dxnor~ dmux, ddriv, dff;

char* name techno() {

switch(technology) case MOTOROLA:

return (char*)"Motorola"; break;

case VENUS: return (char*)"Venus"; break;

default:

/* name of current technology */


return (char*)"unknown"; break;

int init_techno(par)

int par; (

/* initialize cost and delay of basic components */

switch(par) { case MOTOROLA:

cinv=l; cand=2; cot =2; cnand=2; cnor=2; cxor=4; cxnor=4; cmux=3; cdriv=5; cff=8; cramcell=2; romfac=8.0; delta=l; dinv=l; dand=2; dot =2; dnand=l; dnor=l; dxor=2; dxnor=2; dmux=2; ddriv=2; dff=4; break;

case VENUS: cinv=l; cand=2; cor =2; cnand=2; cnor=2; cxor=6; cxnor=6; cmux=3; cdriv=6; cff=12; cramcell=12; romfac=6.0; delta=l; dinv=l; dand=l; dor =I; dnand=l; dnor=l; dxor=2; dxnor=2; dmux=2; ddriv=l; dff=4; break;

" default: fprintf(stderr,

"techno.c: inittechno() unknown parameter\n"); exit(1);

} technology=par; return O;

/* */ /* /*

ROM and RAM units (A x n) *I ,I

int cram(A,n) /* on chip static RAM */ int A,n; { switch(technology)

case MOTOROLA: if (n>l)

return (A+3)*(id(id(n))§ ; else

return (A+3)*n*cramcell ; break;

case VENUS: return A*n*cramcell ; break;

default:


fprintf(stderr,"techno.c: cram() unknown technology\n"); exit(1);

int dram(A,n) int A,n; { switch(technology)

{ case MOTOROLA: if (A >= 128)

return I0 + 3*id(A); else

return ld(n) + A/4; break;

case VENUS: return ceil(l.5*ld(A)); break;

default: fprintf (stderr, "techno. c : dram() unknown technology\n") ; exit (I) ;

}

int cram2(A,n) /* Dualport RAM; int A,n; { switch(technology)

case MOTOROLA: case VENUS: return ceil(cram(A,n)*l.6); break;

default:

A < 128 * /

fprintf(stderr,"techno.c: cram2() unknown technology\n"); exit(l);

int dram2(A,n) int A,n; { switch(technology)

{ case MOTOROLA: case VENUS:

return ceil(dram(A,n)*l.5); break;

default: fprintf(stderr,"techno.c: dram2() unknown technology\n"); exit(1);

}

int crom(A,n) int A,n;

/* on chip ROM */


~return (int)(cram(A,n)/romfac); }

int drom(A,n) int A,n; <return dram(A,n) ; }


B.3 Library of Functional Circuits

In chapter 3, we specified some combinatorial circuits, which are repeatedly used in all our designs. These include decoders, an encoder, a shifter, different kinds of adders and some other useful functional circuits. Module macro implements their cost and delay formulae.

B.3.1 Header File of the Macro L ib ra ry

** macro.h commonly used functional modules ** ****************************************************************

#ifndef MACRO_H #define MACRO_H

extern int max(); extern int id(); extern int power2();

/* max of two integers */ /* log base 2, rounded to next integer */ / , 2~n , /

extern int cdecs(), ddecs(); /* decoder, slow */ extern int cdecf(), ddecf(); /* decoder, fast */ extern int chdec(), dhdec(); /* half decoder */ extern int cenf(), denf(); /* encoder, with flag */ extern int cenc(), denc(); /* encoder, no flag */

extern int czero(), dzero(); /* zero tester */ extern int cinc(), dinc(); /* incrementer, ripple carry */ extern int ccls(), dcls(); /* cyclic left shifter */

extern int cFA(), dFA(); /* full adder */ extern int cKCA(), dRCA(); /* adder (carry ripple) */ extern int cPP(), dPP(); /* parallel prefix */ extern int cCLA(), dCLA(); /* adder (carry look ahead) */ extern int cCSA(), dCSA(); /* adder (conditional sum) */

#endif

B.3.2 Code File of the Macro L ib ra ry

** macro.c commonly used functional modules **

#include "techno.h" /* extern decl. of basic components */

/* === Some useful functions */

int max(a, b) /* maximum of two integers */

B.3. L I B R A R Y OF FUNCTIONAL CIRCUITS 211

int a, b; { return (a>b) ? a:b ; }

int id(n) /* log base 2, rounded to the next integer */ int n; { return (n==1) ? O:ld((n+l)/2) + I; }

int power2(n) /* 2"n */ int n; { return (n==O) ? 1:power2( n-i )*2 ; }

/* === Functional Modules (Macros) ,/

/* --- Cost and delay of n-bit decoders: n -> 2"n ,/

int cdecs(n) /* simple decoder, but slow */ int n; { return (n==l) ? cinv : cdecs(n-l) + power2(n)*cand +cinv; }

int ddecs(n) int n; { return (n==l) ? dirty : max(ddecs(n-l),dinv) + dand; }

int cdecf(n) /* fast decoder */ int n; { return (n==1) ? cinv :

cdecf(n/2) + cdecf((n+l)/2) + power2(n)*cand; }

int ddecf(n) int n; { return (n==l) ? dirty : ddecf((n+l)/2) + dand; }

/* --- Cost and delay of n-bit half-decoder: n -> 2"n ,/

int chdec(n) int n;

return (n==l) ? 0 : chdec(n-1) + power2(n-1)*(cand + cot); }

int dhdec(n) int n; { return (n==1) ? 0 : dhdec(n-1) + max(daad, dot);


/* --- Cost, delay of n-bit encoder 2^n -> n (with flag) --- */

int cenf(n) int n;

return (n==l) ? cot : 2* cenf(n-l) + n,cot;

int denf(n) int n;

return (n==l) ? dot : denf(n-1) + dor;

/* --- Cost, delay of n-bit encoder 2~n -> n (no flag) ..... */

int cenc(n) int n;

return (n==l) ? 0 : cenf(n-l) + cenc(n-l) + (n-l)*cor;

int denc(n) int n;

return (n==!) ? 0 : max(denf(n-l), denc(n-1)) + dor; }

/* --- Cost and delay n-bit Zero Test ,/

int czero(n) int n;

return (n-2)*cor +cnor;

int dzero(n) int n;

return ld(n/2)*dor + dnor;

/* --- Cost and delay n-bit Ripple Carry Incrementer ,/

int cinc(n) int n;

return (n-l)*(cand + cxor) + cinv;

int dinc(n) int n; { return (n==1) ?dinv :

max(dinv, max((n-1)*dand, (n-2)*dand +dxor)); }


/* --- Cyclic left shifter int ccls(n) int n;

return ld(n)*n*cmux; }

int dcls(n) int n;

return Id(n)*dmux; }

,/

/* === different adder types (RCA, CLA, CSA) ,/

/* --- Cost and delay of Parallel Prefix, n power of 2 ...... ,/

int cPP(n) int n; { return (n==l) ? 0 }

: cPP(n/2) + n - 1;

int dPP(n) int n; { return (n==l) ? 0 : dPP(n/2) + 2; }

/* --- Carry look-ahead adder, n power of 2 */ int cCLA(n) int n;

return cPP(n)*(2*cand +cor)+ (2*n+2)*cxor + (n+1)*cand + cor; }

int dCLA(n) int n;

return dPP(n)*(dand + dot) + 2*dxor + dand + dot; }

/* --- Full Adder int cFA() { return 2*cxor + 2*cand + cot; }

,/

int dFAab_s() return 2*dxor;

}

i n t dFAabc_c() { return dxor + dand + dor; }


int dFAc_c() { return dand + dor; }

int dFAc_cs() < return max(dxor, dand + dot); }

int dFA() { return max( max( dFAab s(), dFAabc_c()),

max(dFAc_c(), dFAc cs())); }

/* --- Ripple Carry Adder ,/

int cRCA(n) int n; < return n*cFA() + 2*cxor; }

int dRCA(n) int n; { if (n==l)

return dxor + max(max(dFAabc_c(), dFAab_s()), dFAc_cs());

else return dxor + max(dFAab_s(),

dFAabc_c() + (n-2)*dFAc_c() + dFAc_cs()); }

/* --- A2(n) adder */

int cA2(n) int n; { if (n==l)

return cxor + cxnor + cand + cot ; else

return cA2(n/2) + cA2((n+l)/2) + 2.(n/2+1)* cmux; }

int dA2(n) int n; { i~ (n==1)

return max( max(dxor, dxnor), max(dand, dor)) ;

else return dA2((n+l)/2) + dmux;

}

/* --- Conditions Sum Adder */


int cCSA(n) int n;

return cA2(n) + (n+l)*cmux + 2*cxor; }

int dCSA(n) int n; { return dA2(n) + dmux + 2*dxor; }


B.4 H a r d w i r e d Control

In chapter 4, we derived cost and run t ime formulae for a Moore and a Mealy implementa t ion of a hardwired control automaton. The states can be coded in binary or in unary. Module h a r d c t r provides the corresponding C routines of all four versions.

B.4.1 Header File of the H a r d w i r e d Cont ro l

****************************************************************

** hardctr.h hardwired control logic module ** ** Mealy and Moore implementations of the control automaton ** ****************************************************************

#ifndef CONTKOL_H #define CONTKOL_H

extern int set_contype();

extern int set conpar();

extern int aOut(); /* int alN(); extern int canto(); extern int tauto();

/* set ctrl automaton type */ /* par: mealy, binary */ /* set automaton parameters */ /* states, inputs, outputs,

#monomials, length max/sum, nu max/sum, fanin max/sum */

/* accum, delay of outputs */ to be defined in machine spec */ /* cost of the automaton */ /* cycle time of the automaton */

extern int clLL(); extern int aILL();

/* circuit ILL detects illegal instructions */

/* cost of ILL */ /* accumulated delay of ILL */

extern void forall_line(); extern void forall_header(); extern void forallprint();

/* print horizontal line */ /* print two line header */ /* evaluate function and print */

struct control_parameters { int states, zeta; int sigma, gamma; int monom;

int Imax, isum; int numax, nusum;

};

int faninmax, faninsum; int mealy, binary;

/* #States, Id(states) */ /* #input/output signals */ /* #monomials m in state

transitions */ /* max, sum of literals in m */ /* max, sum of signal

activations */ /* max, sum fanin of states */ /* moore/mealy, unary/binary */

#endif CONTKOL_H

B.4. HARDWIRED CONTROL 217

B.4.2 Code File of the Hardwired Control

****************************************************************

** hardctr.c hardwired control logic module ** ****************************************************************

#include <math. h> #include "techno .h" #include "macro. h" #include "hardctr. h"

static struct control_parameters con = {0,0, 0,0, 0,0,0, 0,0, 0,0, 0,0};

/* private control parameters */

/* must be set by set_con... */

int set_contype(m;b) int m,b; {

con.mealy = m; con.binary = b; return O;

}

/* set ctrl automaton type */ /* mealy, binary */

int set_conpar(s,i,o,m,mlm,mls,nm,ns,fm,fs) int s,i,o,m,mlm,mls,nm,ns,fm,fs;

/* set automaton parameters */ {

con.states = s; con.zeta = ld(s); con.sigma = i; con.gamma = o; con.monom = m; con.lmax = mlm; con.lsum = mls; con. numax = rim;

con.nusllm = ns;

con.faninmax = fm; con.faninsum = fs; return O;

/* #states */

/* input/output signals */

/* monomials */

/* frequency of activity */

I* fanin *I

/* === Cost and delay: Output circuit of the automaton ...... ...... */

int cO() /* output circuit O: Moore automaton */ { return (con.nusum - con.gamma)*cor; }


int dO() { return ld(con.numax) *dot; }

int cOD() /* circuit OD (unary/binary) */ { if (con.binary==O)

return cO(); else return cdecf(con.zeta) + cO();

}

int aOD() /* accumulated delay of circuit OD */ { if (con.bin&ry==O)

return dO(); else return ddecf(con.zeta) + dO();

}

int aOut() { if (con.mealy)

return O; else return aOD();

}

/* accum, delay: outputs of the automaton */

/* === Cost and delay: Next state circuit of the automaton == */

extern int aln(); /* accumulated delay: inputs In */

/* --- Control Automaton ,/

int cCM() /* Circuit CM (monomials) */ { return con.sigma *cinv + (con.lsum - con.monom)* cand;}

int dCM() { return dinv+ Id(con.lmax) *dand;}

int aCM() { return aln() + dCM();}

int cCN() /* Circuit CN (next state) */ { return con.fa_ninsum * (cand + cor) + (con.states - I)* cor;}

int dCN() { return id(con.faninmax) * dot + d~d;}

intcNSE() /* Circuit NSE (unary/binary) */ { if (con.binary==O)

return cCM() + cCN(); else


return cCM() + cCN() + cenc(con.zeta); }

int aNSE() { int delay;

if (con.binary==O) delay = aCM() + dCN() + dzero(con.states-1);

else delay = max(aCM(), ddecf(con.zeta)) + dCN() + denc(con.zeta);

if (con.mealy) delay += dand;

return delay; }

int aO() { int delay;

/* for Mealy automata only */

delay = dand + max(dzero(con.states -I), dO()) + dot;

if (con.binary==O) return aCM() + dCN() + delay;

else return max(aCM(), ddecf(con.zeta)) + dCN() + delay;

/* === Cost of control automaton */

int cauto() { int cost;

if (con.binary==O)

{ cost = cOD() +cNSE() +con.states *cff +czero(con.states-l) + cot +cinv + (con.states -1) * cand;

if (con.mealy) cost += con.gamma * cff - cot;

} else

{ cost = cOD() + cNSE() + con.zeta *(cff + cand) +cinv;

if (con.mealy) cost += con.gamma *cff + czero(con.states -I)

+ (con.states - I - con.zeta) * cand;

return cost; }


/* === cycle time of the control automaton

int tauto() { if (con.mealy)

return max(aNSE(), aO()) + dff + delta; else { if (con.binary==O)

return aNSE() + max(dand, dot) + dff + delta; else return aNSE() + dand + dff + delta;

} }

,/

/* === Testing for illegal instruction int cILL() { if ((con.binary==1)~(con.mealy == 0))

return czero(con.states -I) + cand; else return cand;

}

,/

int alLL() { if (con.binary == O)

return aNSE() + dand; else return aNSE() + dand - denc(con.zeta) + dzero(con.states -I);

}

/* === Print functions void forall line () {

printf ( 14__

*/

in"); return;

}

void f o r a l l _ h e a d e r ( s t r l , s t r 2 ) char * s t r ! , *str2; {

printf("Z~21s i t Moore printf("Z-21s it unary binary forall_line(); return;

void forall_print(str,func) char *str; int (*func)();

unary Mealyin",strl);

binaryin",str2);


printf("~2Os:",str); set_contype(O, 0); printf("\t~7d",(*func)()); set_contype(O, i); printf("\t~7d",(*func)()); set_contype(i, 0); printf("\t~7d",(*func)()); set_contype(1, I); printf("\t~7d\n",(*func)()); return;


B.5 M A R K 1 like Des igns

B.5.1 Original M A R K 1 Design

The following C-module is the architectural module of the original MARK 1 design introduced in chapter 5. The module also contains routines for the comparison of the different design variants.

/* */ /* redesigned Mark I (hardwired control) */ /* 950817 TGR 1.0 - final version */

I* *I

#include <stdio.h> #include <math.h> #include "techno.h" #include "macro.h" #include "hardctr.h" #include "evaluate.h"

struct variable_parameters { int nd; int na; int dmem; int adder type;

} var;

/* data bus width */ /* address bus width */ /* memory access time */ /* choosen adder type */

I* *I /* Environments (user defined macros) */

I* * I

/* -- Composing the n-bit arithmetic unit AU (= subtractor) - */

int cau() { switch (var.adder_type) {

case O: return var.nd*cxor + cRCA(var.nd); break;

case I: return var.nd*cxor + cCLA(var.nd); break;

case 2: return var.nd*cxor + cCSA(var.nd); break;

default: fprintf(stderr,"cau(): undefined adder type\n"); exit(1);

}

int dau() { switch (vat.adder_type) {

case O: return dxor + dRCA(var.nd); break;

case I: return dxor + dCLA(var.nd);

B.5. MARK 1 LIKE DESIGNS 223

}

break; case 2: return dxor + dCSA(var.nd);

break; default: fprintf(stderr,"dau(): undefined adder type\n");

exit(1); }

/* */

/* calculation of the data path cost */

*/

int caccenv() {return var.nd*cff;}

/* register and check ACC<O (no cost) */

int cirenv() /* IK only */ {return (var.na+3)*cff;}

in t cpcenv() { in t cadder;

/* PC, adder, AMUX, PMUX and powerup */

switch(var.addertype) { case O: cadder=cRCA(var.na); break; case I: cadder=cCLA(power2(ld(var.na))); break; case 2: cadder=cCSA(power2(ld(var.na))); break; default: fprintf(stderr,"cpenv: undefined adder type\n");

exit(1); } return var.na*cff+ cadder + 2*var.na*cmux

+ var.na*cand +cinv + 2*cot;

int cmenv() /* Memory and preceding MMUX */ {return var.na*cmux;}

/* --- Cost of the data path int cDP() /* all above parts + LMUX */ {return cau() + cirenv() + caccenv().

+ cpcenv() + cmenv() + var.nd*cmux; }

*/

/* */ /* /*

calculation of the cycle time */ */

int amadr() /* memory addressing (PC, IK, MMUX) */ { return dmux+max(aOut(),O); }

i n t amrd() /* memory read ( i n c l . MMux) */


{return var.dmem+max(amadr(),aOut());}

int tmemw() /* memory write */ {return delta+var.dmem+max(amadr(),aOut());}

int tacc() /* ACC */ {return (dff+delta)+dau()+max(amrd(),dmux + max(aOut(),O));}

int taddpc() /* PC adder and AMUX */ { int dadder;

switch(vat.adder_type) { case O: dadder=dRCA(var.na); break; case I: dadder=dCLA(power2(ld(var.na))); break; case 2: dadder=dCSA(power2(ld(var.na))); break; default: fprintf(stderr,"cpenv: undefined adder type\n");

exit(1); } return dadder+dmux+max(aOut()+dor,amrd());}

int tpc() /* PC */ {return (dff+delta)+dmux+max(aOnt(),max(taddpc(),dand+amrd()));}

int tir() /* IR */ {return (dff+delta)+max(aOut(),amrd());}

/* --- Cycle time of the data paths int tDP() {return max(tmemw(),

max(tacc(), max(tpc(), tit() )));

}

*/

/* */ /* /*

Cost and cycle time of the Mark-1 Design *I ,I

/* ..... Control Unit

int aln() {return O; }

int cCONenv() { return canto(); }

/* delay: inputs In of CON */

,/

B.5. M A R K 1 L I K E DESIGN S 225

in t tCON() { r e tu rn t au to ( ) ; }

/* ..... whole machine

int cMarkl() {return cDP() + cCONenv();}

in t tMarkl() {re turn max(tDP(), tCDN());}

int cCONrel() { return (int)(1OO.*cCONenv()/cMark1()); }

/*

*/

*/ /* /*

Evaluation of the design */ , /

void main() {

char my_str[200]; int i;

/* temporary s t r ing */ /* loop var iable */

init_techno(MOTOROLA); /* select technology */

set_conpar( /* Control logic parameters */

9, /* s ta tes of c t r l automaton */ 4, 8, /* input/output of c t r l logic */ 7, 3, 21, /* monomials (#, max, sum) */ 4, 12, /* signal a c t i v i t y (max, sum) */ 2, 9); /* fanin (max, sum) */

/* design parameters */ var.dmem = 20; /* main memory access time */ var.nd = 32; /* width of data bus */ var.na = 13; /* width of address bus */

for(i=O;i<3;i++) { vat.adder_type=i; /* Select RCA, CLA, CSA */

printf("\n\n\n Cost Delay Analysis of the Markl Design \n"); printf(" Technology: ~s, ", name_techno()); switch(vat.adder_type) {

case O: strcpy(my_str,"carry ripple"); break; case I: strcpy(my_str,"carry look ahead"); break; case 2: strcpy(my_str,"conditional sum"); break; default: strcpy(my_str,"unkno~n");

}


printf(" Adder type: ~s\n", my_str); printf(" Dwidth = ~d, Awidth= ~d, Mem access time = ~d\n",

var.nd,var.na,var.dmem);

forall_line(); /* cost analysis */ forall_header("cost", .... ); forall_print("arithmetic unit",cau); forall_print("PC environment",cpcenv); forall line(); forall_print("data path",cDP); forall_print("control",cCONenv); forall_line(); forall_print("Markl",cMarkl); forallprint("control/Markl [~]",cCONrel);

}

forall_line(); /* cycle time analysis */ sprintf (my_str, "(dmem = Y,d) ", var. dmem) ; forall header ("delay" ,my_str) ; forall_print ("control signals", aOut) ; forall_print ("memory read", amrd) ; f orall_print ("arithmetic unit", dau) ; f orall_line ( ) ; forall print ("memory write" ,tmemw) ; f orall_print ("accumulator" ,tacc) ; forall_print("instr, register",tir) ; f orall_print ("program count er", tpc) ; forall_line () ; forall_print("data path" ,tDP) ; f orall_print ( "control", tCON); forall line ( ) ; f orall_print ("Markl", tMarkl ) ;

/* Quality ratios: (moore/bin), (moore/unary), (mealy/bin) */ { double q; /* quality parameter */

int dmem; /* memory access time */ int cost_O, cost I, cost_2, cost_n; /* cost */ int time 0, time I, time_2, time_n; /* time */ double vl, v2, v3; /* temporary variables */ FILE *fil; /* file struct */

var.adder_type = 2; /* Choose CSA */

fil=fopen("ml_q.dat","w")~ if(fil!=NULL)

for(q=O.O; q<=l.O; q+=O.Ol) {

set_contype(O,l); cost_n = cMarkl(); time_n = tMarkl(); set_contype(O,O); cost_O = cMarkl(); time_O = tMarkl(); set_contype(l,l); cost_l = cMarkl(); time I = tMarkl();

B.5. M A R K 1 LIKE DESIGNS 227

}

set_contype(l,O); cost_2 = cMarkl(); time_2 = tMarkl();

vl=eval q(q, cost_O, time_O, cost_n, time_n);

v2=eval_q(q, cost_l, time_l, cost_n, time_n);

v3=eval_Q(q, cost_2, time_2, cost_n, time_n);

fprintf(fil,"%6.21f %8.51f %8.51f Z8.51f\n", q, vl, v2, v3);

} else { fprintf(stderr,"Could not open file 'ml_q.dat'\n");

exit(1); } fclose(fil);

B.5.2 M o d i f i e d D e s i g n M1_1

The following C-fragment lists the changes in the architectural description from the original MARK 1 design to the modified design M1_1.

/* */ /* calculation of the data path cost */ /* , /

int cacc() /* register, test ACC<O (no cost) */ {return var.nd*cff;}

int cir() /* IK only */ {return (var.na+3)*cff;}

int cpcenv() /* PC, incrementer, powerup and PMUX */ {

return var.na*cff+ cinc(var.na)+ var.na*cand+ cinv+ 2*cot+ var.na*cmux;

}

int cmenv() /* Memory and preceding MMUX */ {return var.na*cmux;}

/* --- Cost of the data path int cDP() /* all above parts + LMUX */ {return cau() + cir() + cacc() + var.nd *cff + cpcenv() + cmenv() + var.nd*cmux; }

,/


/* */

/* calculation of the cycle time */

*/

int amadr() /* memory addr (PC, IK and MMUX) */ { return dmux+max(aOut(),O); }

int amrd() /* memory read (incl. MMux) */ {return var.dmem+max(amadr(),aOut());}

int tmdreg() {return (delta+dff)+ max(amrd(), aOut());}

int tmemw() /* memory write */ {return delta+ var.dmem+max(amadr(),aOut());}

int tacc() /* ACC */ {return (delta+dff)+ dau()+max(O,dmux + max(aOut(),O));}

int aincpc() /* PC, incrementer and powerup logic */ {

return dand+dinc(var.na); )

int tpc() /* PC */ {return (delta+dff)+ dmux+max(aOut()+dor,max(aincpc(),O ));}

in t t i r ( ) /* IR */ {return (del ta+dff)+ max(aOut(),amrd());}

/* --- Cycle time of the datapath int tDP() ~return max(tmemw(), max(tmdreg(), max(tacc(), max(tpc(), tit() )))); )

,/

B.6. DLX WITHOUT I N T E R R U P T HANDLING 229

B.6 DLX without Interrupt Handling

Module d lx l is the architectural module of the DLX design of chapter 6, i.e., it specifies the cost and the delay of the DLX specific part of the design. The module also compares this design for the four implementations of the hardwired control.

The parameters of the struct var are implementation dependent. They include the width of the data paths, the number of general purpose registers and the access and status time of the main memory.

I* *I /* dlxl.c /* /*

architectural module non-pipelined DLX */ no interrupt handling, hardwired control, CLA adder */

*/

#include <stdio.h> #include <math.h> #include "techno.h" #include "macro.h" #include "hardctr.h" #include "evaluate.h"

struct variable_parameters { int n; int A; int dmem; int dmstat;

} var;

/*

/* width of the data paths */ /* # GP-Registers */ /* memory access time */ /* memory status time */

*/ /* /*

Control Environment (I): Control Signals *I *I

/* --- Delay: outputs Csig of the control automaton int aCON_Csig() { return aOut(); }

/* --- Memory Control circuit MC int cMC() { return cdecf(2) + 16*cand + lO*cor + 3*cinv; }

int aMC_R_Mw() { return max(ddecf(2), dinv+ dand) + 2*dand + 2*dor; }

int aMC_R_mis() { return max(dinv + 3*da/Id + 2*dor,

ddecf(2) + 2*dor + 2*dand + max(dinv, dor)); }

*/

, /


int dMC_C_Mw() { return dand + 2*dor; }

int dMC_C_mis() { return dand; }

int aCON_Mw() return max(aCON_Csig() + dMC_C Mw(), aMC_R Mw());

int aCON_mis() { return max(aCON_Csig() + dMC_C_mis(), aMC R mis()); }

/* --- Control circuit PCC of the PC environment int cPCC()

return cor; }

,/

int dPCC() { return dor; }

int aCON_PCce() { return aCON_Csig() + dPCC(); }

/* */ /* /*

ALU Environment (width: vat.n) ,I ,I

/* --- Arithmetic unit AU (with carry look-ahead adder) int cau() { return var.n * cxor + cCLA(var.n); }

,/

int dau() { return dxor + dCLA(var.n); }

/* --- Comparator int ccomp()

return czero(var.n) + 2*tiny + 4*cand + 2*cor; }

,/

int dcomp() return max(dinv+dand, max(dzero(var.n)+dor, dzero(var.n)+dinv))

+ dand + dot;

B.6. DLX WITHOUT I NTERRUPT HANDLING 231

}

/* --- ALU ,/ int calu() { return cau() +ccomp() +var.n *(cand +cot +cxor) +4*var.n*cmux; }

int dALU zc() { return dau() + dcomp(); }

/* delay of zc */

int dALU_zr() /* delay of zr */ { return max(dau() +dmux, max(dand, max(dor, dxor)) +3*dmux); }

int dALU_ovf() { return dau(); }

/* delay of ovf */

/* --- ALU Environment int caluenv() { return calu() + 2 *var.n *cdriv +2*3*cmux + cot; }

,/

int daluglue() { return 2*dmux + dor; }

/* delay of alu control */

int dalue_s_ZC() { return dALU zc() + ddriv; }

/* delay of ZC */

int dalue_s_ZR() return dALU_zr() + ddriv;

I* delay of ZR *I

int dalue s ovf() return dALU_ovf();

}

/* delay of ovf */

int dalue c ZC() /* delay of ZC */ return daluglue() + dALU_zc() + ddriv;

}

int dalue_c_ZR() /* delay of ZR */ { return daluglue() + dALU_zr() + ddriv; }

int dalue_c_ovf() { return daluglue() + dALU_ovf();

/* delay of ovf */


}

I* */ /* /*

Shifter Environment */ */

/* --- Distance computation (Dist) int cdist() { return cinc(5) + 6*cinv + I3*cmux; }

,/

int ddist() { return dinv+ max(dinc(5), dmux) + 2*dmux; }

/* --- Fill Bit int cfill() { return 7*cmux + 2*cand +cinv; }

,/

int drill() { return max(3*dmux, dinv)+ dand + dmux; }

/* --- Mask Generation (Mask) int cmask() { return chdec(5) + 4 * var.n * cmux + cor; }

,/

int dmask() { return max(dhdec(5), max(dmux, dot)) + 2*dmux; }

/* --- Shift Unit */ int csh() { return ccls(var.n) +cdist() +cfill() +cmask() +var.n * cmux; }

int dsh() { return max(ddist()+dcls(var.n), max(drill(), dmask())) + dmux; }

/* --- Shifter Environment int cshenv() { return csh() + var.n * cdriv; }

,/

int dshenv() { return dsh() + ddriv; }


/* */ /* /*

Further DP Environments *I *I

/* --- IR Environment int cirenv()

return 15*cmux +2*var.n*cdriv +var.n*cff; }

,/

i n t d i renv( ) { r e t u r n dmux + ddriv; }

/* --- GPR Environment (# Registers: var.A, width: var.n) --- */

int cgpr() return cram2(var.A, var.n) + 3. vat.n* cff+ 3. vat.n* cdriv

+ czero(var.n) + 2* czero(id(var.A)) + 2* cinv

+ 2. ld(var. A)* cmux + 2* var.n* cand; }

i n t dgpr_RF() { r e t u r n 2*dmux + dram2(var.A, va r .n ) ; }

i n t dgpr_dout() { r e t u r n max(dram2(var.A, v a r . n ) , dze ro ( ld (va r .A) ) +dinv)

+ dand; }

int dgpr_Sb() { return ddriv; }

i n t agpr_aeqz() r e t u r n dze ro (va r . n ) ;

/* --- PC Environment

int cpcenv()

{ return 2 * var.n * cdriv + var.n * cff + var.n * cmux; }

,/

int dpcenv() { return ddriv; }

/* --- Memory Environment int cmenv()

{ return 2 * var.n *cff + var.n * cmux + 2 * var.n * cdriv; }

,/


int dmenv_Sl() return ddriv;

)

/* */ /* /*

Cost and delay of the DLX Data Paths ,I ,I

int oDP() { return caluenv() + cshenv() + cirenv() + cgpr()

+ cpcenv() + cmenv(); }

/$ --- clocking of registers in the data paths int tRegce() { return max(aCON_Csig(), aCON PCce()) + dff + delta; }

,/

/* --- register file write back int tgpr__RF()

return aCON_Csig() + dgpr RF() + delta; }

,/

/* --- register Tile read cycle int tgpr_RF() { return aCON_Csig() + dgpr_dout() + dff + delta; }

,/

/* --- data on Si and $2 bus int aRegS()

return aCON Csig() + max(max(direnv(), dpcenv()), max(dgpr_Sb(), dmenv_Sl()));

}

,/

/* --- data from D bus into registers int dRegw() { return dmux; }

,/

/* --- shift cycles int tSH()

return aRegS() + dshenv() + dRegw() + dff + delta; }

,/

/* --- ALU cycles */ int talu_ZR() { return max(aC0N_Csig() + dalue_c_ZR(), aRegS() + dalue_s_ZR())

+ dRegw() + dff + delta; }


int talu_ZC() { return max(aCON_Csig() + dalue_c ZC(), aRegS() + dalue_s ZC())


int aalu_ovf() { return max(aCON_Csig() + dalue_c_ovf(),

aRegS() + dalue_s_ovf()); }

/* --- Cycle time of the data paths int tDP() { return max(max(tgpr__RF(), tgpr_RF()), max(tSH(),

max(max(talu_ZR(), talu_ZC()), tRegce()))); }

,/

/* --- Memory cycle time tM */ int tM() { return max(aRegS(), aCON_Mw()) +var.dmem +dRegw() +dff +delta; }

int aMenv_mstat() return max(aRegS(), aCON Mw()) + var.dmstat;

}

I* *I /* Control Environment (2): Next State Computation /*

*I *I

/* --- accumulated delay: inputs In of control automaton .... int aIn()

return max(agpr_aeqz(), aMenv_mstat()); }

/* ..... Control Unit int cCONenv() { return cauto() + cMC() + cPCC(); }

int tCON() return tauto();

}

/*

*/

*/

*/

/* Cost and cycle time of the DLX Design *I

*I int cDLX() < return cDP() + cCONenv(); }

int tDLX()

236 APPENDIX B. COST AND RUN TIME P R O G R A M S

return max(tDP(), tCON());

int cCONrel() return (int)((iO0.O* cCONenv())/ cDLX());

int cGPRrell() return (int)((lO0.O* cgpr())/ cDP());

int cGPKrel2() { return (int)((lO0.O* cgpr())/ cDLX()); }

void set(ctr, techno) int ctr, techno; { if (techno == O)

init_techno(MOTOKOLA); else

inittechno(VENUS);

switch (ctr) { case O: set_contype(O, 0); return;

case I: set contype(O, I); return; case 2: set_contype(l, 0); return; case 3: set contype(l, I); return; default: fprintf(stderr,

"dlxl.c: set() unknown control type\n"); exit(1);

/* */ /* /*

Evaluation of the design , I , I

void main()

char my str[200]; int i, x, y; int cl, c2, tl~ t2; double res, q;

init_techno(MOTOKOLA);

set_conpar( 22, 14, 28, 22, I0, 97,

/* temporary strings */ /* loop variables */ /* cost, time values */ /* result, quality parameter */

/* select technology */

/* Control logic parameters */ /* states of state machine */ /* input/output of control */ /* monomials (#, max, sum) */

B.6. D L X W I T H O U T I N T E R R U P T H A N D L I N G 237

10, 93, 4, 32);

/* signal activity (max, sum) */ I* fanin (max, sum) *I

var.n = 32; var.A = 32; var.dmem = 25; var.dmstat = 5;

/* design parameters */ /* width of the data paths */ /* number of GP-Kegisters */ /* memory access time */ /* memory status time */

for (i=O; i<2; i++) {

printf("\n\n\n Cost Delay Analysis of the DLX Design \n"); printf(" No pipelining, hardwired control, no interrupt\n"); printf(" Technology: %s, ", name_techno());

strcpy(my_str,"carry look ahead"); printf(" Adder type: ~s\n", my_str); printf( " width n = ~d, Keg-number = ~d, Mem status time = ~d\n", var.n,var.A,vax.dmstat);

/* */

/* Cost of the DP environments and the control */ I* *I

forall_line(); /* cost analysis */ forall_header("cost", .... ) ; forall print ("ALUenv", caluenv) ; forall_print ("SHenv", cshenv) ; forall_print ("IKenv", cirenv) ; forall_print ("GPKenv", cgpr) ; forall_print ("PCenv", cpcenv) ; forall_print ("Menv", cmenv) ; forall line ( ) ;

forall_print ("DP", cDP) ; forall_print ("Control", cCONenv) ; forall line() ; forall_print ("DLX", cDLX) ; forall print ("CON/DLX [Y.] ", cCONrel) ;

forall_line () ; forall_print ("GPRenv", cgpr) ; forall_print ("DP", cDP) ; forall_print ("DLX", cDLX) ; forall line ( ) ; forall print ("GPK/DP [Y.] ", cGPKrell) ; forall_print ("GPK/DLX [Y.] ", cGPKrel2) ; forall_line () ;


/* */

/* Cycle time and delay of DP environments */

,/ forall_line(); /* cycle time analysis */ sprintf(my_str,"(dmem = %d)",var.dmem); forall_header("delay",my_str);

forall_print("aCON_Csig",aCON_Csig); forall_print("aCON_Mw",aCON_Mw); forallprint("aCON_PCce",aCON_PCce); forall_print("agpr_aeqz",agpraeqz); forall_print("aMenv_mstat",aMenv_mstat); forall_line(); forall_print("t_KFwrite",tgpr__KF); forallprint("t_KFread",tgpr_KF); forall_print("tSH",tSH); forall_print("taluZK",talu_ZK); forall_print("taluZC",talu_ZC); forall line(); forall_print("tDP",tDP); forallprint("tCON",tCON); forall line(); forall_print("tDLX",tDLX); forallprint("T_M()",tM); forall_line(); var.dmem = 10; forall_print("T_M(lO)",tM); var.dmem = 50; forall_print("TM(50)",tM); forall line(); var.dmem = 25;

/* memory access time */



init_techno(VENUS); /* select technology */ }

forall_line(); I* *I /* CPI independent */ I* */ printf("Computing the EQ-values for the DLX designs \n"); printf("non-pipelined~ no interrupts, hard~ired control \n"); for (i=O; i<2; i++) { set(O,i);

forall_line(); printf(" Technology: %s \n", name_techno()); forall_line(); for (x=O; x<4; x++) { printf("\t \t ");

for(y=O; y<4; y++) { if (x!= y)

B.6. DLX WITHOUT INTERRUPT HANDLING 239

} }

{ set(x, i); cl = cDLX(); tl = tDLX(); set(y, i); c2 = cDLX(); t2 = tDLX(); res = eval_EQ(cl, tl, c2, t2);

} else

res = 0.0; pr in t f ( "Z .3 f ",res);

} print f ("\n") ;

/ * * / /* Quality r a t i o Q(q, Vi, Mealy) */ /* */ forall_line(); printf("\n Moore(un, bin) vs. Mealy(un): Motorola x Venus\n"); forall_line(); for (q=O.O; q<I.01; q+=O.02) { printf("Z.2f ", q);

for(i=O; i<2; i++) { /* Motorola vs Venus Technology */

for(x=O; x<2; x++) { set(x, i);

CI = cDLX(); tl = tDLX(); set(2, i); c2 = cDLX(); t2 : tDLX(); res = eval_Q(q, cl, tl, c2, t2); printf("Zf ",res);

} } print f (" 1 . o \n");


B.7 D L X wi th I m p r o v e d A L U

In chapter 7, we modified the ALU in order to speed up the DLX design. Those design changes only impact a few routines of the architectural file d l x l . c of the DLX design. Moreover~ we also require new functions for the evaluation of the design variants. Only the new or modified procedures are listed below.

/* */ /* dlx2.c /* /*

architectural module DLX Trade-o~f Analysis */ non-pipelined DLX without interrupt handling */ ( no interrupt handling, hardwired control) */

/*

I* I* I* I* I*

ADDER = TEST = 0 : ripple carry adder 0 : test AU result i : carry look-ahead adder 1 : test AU inputs 2 : conditional sum adder 2 : 2-cycle test

*I *I *I ,I *I *I

/* */ /* /*

ALU Environment (width: vat.n) *I *I

/* --- Arithmetic unit AU (with different adders) int cau() { switch(vat.ADDER)

{ case O: return var.n*cxor + cRCA(var.n);

case I: return var.n*cxor + cCLA(var.n);

case 2:

return var.n*cxor + cCSA(var.n); default:

,/

/* Ripple Carry */

/* Carry look-ahead */

/* Conditional Sum */

fprintf(stderr,"dlx2.c: cau() unknown adder type\n"); exit(1);

int dau() switch(vat.ADDER) < case O:

return dxor + dRCA(var.n); case I:

return dxor + dCLA(var.n); case 2:

return dxor + dCSA(varon); default:

/* Ripple Carry */

/* Carry look-ahead */

/* Conditional Sum */

fprintf(stderr,"dlx2.c: dau() unknown adder type\n"); exit(1);

B. 7. D L X W I T H I M P R O V E D A L U 241

/ * --- ALU * / int calu() { int help;

h e l p = cau ( ) +ccomp() + v a r . n * ( c a n d +cor +cxor ) + 4*var .n*cmux;

if ( v a r . TEST != 2) return help;

else return help + (var.n + 4)*cff;

/* I cycle condition test */

/* 2 cycle condition test */

int dALU_zc() {

/* delay of zc */

if (var. TEST != I) return dan() + dcomp(); /* Testing ALU Outputs */

else /* Testing ALU Inputs */ return dand + dor + max(dau() + max(dot, dinv),

dxor + dzero(var.n) + max(dot, dand +dinv));

/* --- ALU Environment */ int dalue_c_ZC() /* delay of ZC */ { if (vat.TEST != 2 )

return daluglue() + dALU zc() + ddriv; /* i cycle test */ else return ddriv; /* 2 cycle test */

}

/* ..... Delays: two cycle condition test only int aalueCOND_ZC() /* (reg) COND -> ZC { return dcomp() + ddriv; }

*I *I

int dalue_s_COND() { return dau(); }

/* Sbus -> (reg) COND */

int dalue_c_COND() { return daluglue() + dau(); }

/* contr. -> COND */

I* *I /* Cost and delay of the DLX Data Paths */ I* *I /* --- ALU cycles */ int talu_ZR() { return max(aCON_Csig() + dalue_c ZR(), aRegS() + dalue_s_ZR())



int talu_ZC() { iS (var.TEST != 2 )

return max(aCON_Csig() +dalue_c_ZC(), aRegS() +dalue s_ZC()) + dRegw() + dff + delta; /* I cycle test */

else return max(aCONCsig() + dalue_c_ZC(), aalueCOND_ZC())

+ dRegw() + dff + delta; /* 2 cycle test */ }

int talu_COND() /* Update COND register */ { if (var.TEST == 2 )

return max(aCON Csig() + dalue_c COND(), aRegS() + dalue s COND()) + dff + delta;

else return O; /* I cycle test */

}

/* --- Cycle time of the data paths int tDP() { return max(max(tgpr__RF(), tgpr RF()),

max(tSH()~ max(max(talu_ZK(), talu_ZC()), max(talu_COND(), tRegce()) )

) );

*/

/* */ /* /*

Print Functions (3 adders and 3 test implementations) */ */

void line6() {

printf(" \n") ;

return; }

void h e a d e r 6 ( s t r l , s t r 2 ) char * s t r l , *str2; {

printf("~-14s \t Test Outputs 2 Cycle Test\n",strl);

printf("~-14s \t RCA CLA CSA CSA KCA CLA CSA\n",str2);

line6(); return;

RCA

Test Inputs\

CLA\

void print6(a,b,str,func)

B. 7. D L X W I T H I M P R O V E D A L U 243

i n t a[], b[]; char *str; int (*func)(); { int add, test; /* loop counters */

printf ("Y. 14s : " , str);

for( test=O; test < 3; test++) { if (test == 2)

{ /* 2 cycle condition test: parameter set 2 */ set_conpar(b[O], bill, b[2], b[3], b[4], hi5], b[6], bell, hi8], b[9]);

} else { /* 1 cycle condition test: parameter set I */

set_conpar(a[O], a[l], a[2], a[3], a[4], a[5], a[6], a [ ~ ] , a[8], a[9] ) ;

}

for( add=O; add < 3; add++) { var.ADDER = add;

var.TEST = test;

printf("\t%Td",(*func)()); }

} printf("kn"); return;

/* */ /* /*

Evaluation of the design * / * /

void main() {

char my_str[200]; int i;

/* temporary strings */ /* loop variable */

/* Control logic parameters: setl and set2 */ /* # states, inputs, outputs of the control automaton, */ /* monomials (#, max, sum), signal activity (max, sum) */ /* fanin (max, sum) */ int setl[] = { 2 2 , 1 4 , 2 8 , 2 2 , 1 0 , 9 7 , 1 0 , 9 3 , 4 , 3 2 } ; int set2[] = {24,14,28,22,10,97,I0,93,4,34};

init_techno(MOTOROLA); /* select technology */

set_contype( i, I); /* Mealy automaton, binary */


var.n = 32; var.A = 32; var.dmem = 25; var.dmstat = 5;

/* design parameters */ /* width of the data paths */ /* number of GP-Kegisters */ /* memory access time */ /* memory status time */

for (i=O; i<2; i++) {

printf("\n\n\n Cost Delay Analysis of the DLX Design \n"); printf(" No pipelining, hardwired control, no interrupts,\

Mealy automaton, states coded in binary \n"); printf(" different adders and test implementations \n"); printf( " width n = ~d, Reg-nnmber = ~d, Mem status time = ~d\n", var.n,var.A,var.dmstat);

line6(); printf(" Technology: ~s\n", name techno());

/* */ /* Cost of the DP environments and the control */ /* */

/*

line6(); header6("cost", .... ); print6(setl,set2 "ALUenv",caluenv); print6(setl,set2 "SHenv",cshenv); print6(setl,set2 "IKenv",cirenv); print6(setl,set2 "GPKenv",cgpr); print6(setl,set2 "PCenv",cpcenv); print6(setl,set2 "Menv",cmenv); line6(); print6(setl,set2,"DP",cDP); print6(setl,set2,"Control",cCONenv); line6(); print6(setl,set2,"DLX",cDLX); print6(setl,set2,"CON/DLX [~]",cCONrel); line6();

/* cost analysis */

*/ /* /*

Cycle time and delay of DP environments *I *I

line6(); /* cycle time analysis */ sprintf(my_str,"(dmem = ~d)",var.dmem); header6("delay",my_str);

print6(setl,set2,"aCON_Csig",aCON_Csig); print6(setl,set2,"aCON_Mw",aCON_Mw); print6(setl,set2,"aCON_PCce",aCON_PCce); print6(setl,set2,"agpr_aeqz",agpr_aeqz);

B. 7. DLX WITH IMPROVED AL U 245

print6(setl,set2,"aMenv_mstat",aMenvmstat); line6(); p r i n t 6 ( s e t l , s e t 2 , " t _ R F w r i t e " , t g p r _ _ R F ) ; p r i n t 6 ( s e t 1, s e t 2 , " t_RFread" , t gpr_RF ) ; p r i n t 6 ( s e t 1, s e t 2 , "tSH" ,tSH) ; p r i n t 6 ( s e t 1, s e t 2 , " t a l u ZR", t alu_ZR) ; p r i n t 6 ( s e t 1, s e t 2 , " ta lu_ZC", talu_ZC) ; l i n e 6 ( ) ; print6(setl,set2,"tDP",tDP); print6(setl,set2,"tCON",tCON); line6(); print6(setl,set2,"tDLX",tDLX); print6(setl,set2,"T_M()",tM); var.dmem = I0; print6(setl,set2,"T_M(lO)",tM); line6(); var.dmem = 25;

/* memory a c c e s s t ime * /




B.8 DLX with Interrupt Handling

In chapter 8, we modified the original DLX design to enable interrupt handling. The design change only impacts a few environments of the DLX. Thus, only a few routines of section B.6 need to be modified. Those routines are listed below.

/* */

/* dlx3.c architectural module non-pipelined DLX */ /* with interrupt handling, hardwired control, CLA adder */ /* */

I* */ /* Control Environment (I): Control Signals */ /* */ /* --- SPR control circuit (ce and oe for SPRenv) int cSPRcon() { return cdecf(3) + lO*cand + lO*cor; }

int aSPRcon() { return max(ddecf(3), aCON Csig()) + dand + dot; }

/* --- Cause Processing Circuit int cCaPro() { return 32.cor + 25*cand; }

int aCaPro() { return 5*dot + dand; }

*/

,/

I* *I /* Further DP Environments */ /* */ /* --- Memory Environment */ int cmenv() { return 2 * var.n * cff +var.n * cmux +2 * var.n * cdriv +cot; }

int dmenv_S1() { return ddriv; }

/* */ /* SPR Environment /*

, / , /

int cSPRenv() { return 5*var.n*cff + 5*var.n*cdriv + 2*var.n*cmux; }

B.8. DLX WITH I N T E R R U P T HANDLING 247

int aSPR__D() { return aSPRcon() + ddriv; }

int dSPR_D() { return dmux; }

int dSPR_MCA() { return 0;}

/* --- SPR intern cycle int tSRsel_SR_SR() { return max(aSPRcon(), aCON_Csig() +2*dmux) + dff + delta; }

*/

/* */

/* Cost and delay of the DLX Data Paths */

*/ int cDP()

return caluenv() + cshenv() + cirenv() + cgpr() + cpcenv() + cmenv() + cSPRenv();

}

/* --- clocking of registers in the data paths int tRegce()

return aCON_Csig() + dff + delta;

,/

/* --- Cycle through the SPRenv /* --- Cycle in SPR: MCA -> ECA int tSPR MCA() { return aCaPro() + dSPR_MCA() + dff + delta; }

*/ , /

/* --- Reading out an SPR register int tSPR_SR_D() { return aSPR D() + dRegw() + dff + delta; }

,/

/* - - - Cycle time of the da ta paths i n t tDP() { r e t u r n max( max( max(tSRsel SR SR(),

max(tSPR_SR_D(), tSPR_MCA())), max(tgpr__RF(), tgpr_RF())),

max(tSH(), max(max(talu_ZR(), talu_ZC()),

tRegce())));

,/


/* --- Memory cycle time tM int aMenv_nready() { return max(aMenv_mstat(), aCON_mis()) + dor; }

/*

*/

*/ /* Control Environment (2): Next State Computation /*

*I ,I

/* --- accumulated delay: inputs In o~ control automaton .... int aIn()

return max(aCaPro(), max(agpr_aeqz(), aMenv_nready())); }

/*

*/

*/ /* /*

Composing the CA environment * / , /

/* --- Generation of event signals int cevent() { return cILL()+ 5*cand + cor;}

int aevent() { return max(max(alLL(),

aMenv_mstat() + dand), max(max(aCON_Csig() + dor,

aCON_mis() ) + dand, max(aCON_Csig() + dand,

aalu_ovf()) + dand )

);

int cCAenv() { return var.n*cff + 7*cmux + 7*cot + cevent(); }

int tCAenv() { return max(aevent(), aCON_Csig() + dmux) + dot +dff + delta; }

,/

/* ..... Control Unit int cCONenv() { return cauto() + cMC() + cSPRcon() + cCaPro() + cCAenv(); }

int tCON() { return max(tauto(), tCAenv()); }

,/

B.8. DLX W I T H I N T E R R U P T HANDLING 249

/* */ /* /*

Evaluation of the design */ */

void main() K

char my_str[200]; int i, x, y; int cl, c2, tl, t2; double res, q;

/* temporary strings */ /* loop variable */ /* cost, time values */ /* result, quality parameter */

init_techno(MOTOROLA); /* s e l ec t technology */

set_conpar( /* Control logic parameters */

32, /* states of state machine.*/ 17, 39, /* inpu t /ou tpu t : ctr automaton*/ 36, 12, 174, /* monomials (#, max, sum) */ 15, 137, /* s igna l a c t i v i t y (max, sum) */ 6, 52); /* fan in (max, sum) */

/* design parameters */ var.n = 32; /* width of the data paths */ var.A = 32; /* number of GP-Registers */ var.dmem = 25; /* memory access time */ var.dmstat = 5; /* memory status time */

for (i=O; i<2; i++) {

printf("\n\n\n Cost Delay Analysis of the DLX Design \n"); printf(" No pipelining, hardwired control, interrupts \n"); printf(" Technology: ~s, ", name_techno());

strcpy(my_str,"carry look ahead"); printf(" Adder type: ~s\n", my_str); printf(" width n = ~d, Reg-no = ~d, Mem status time = ~d\n",

var.n,var.A,var.dmstat);

I* *I /* Cost of the DP environments and the control */ I* *I

forall_line(); /* cost analysis */ forall_header ("cost", .... ) ; forall_print ("ALUenv", caluenv) ; forall print ("SHenv", cshenv) ; f orall_print (" IRenv", cirenv) ; forall_print ("GPRenv", cgpr) ; fora11_print ("PCenv", cpcenv) ; f orall_print ( "Menv", cmenv) ;


/*

forall_print("SPRenv",cSPRenv); forall_line();

forall_print ("DP", cDP) ; f orall_print ( "Control", cCONenv) ; f orall_line ( ) ; f orall_print ( "DLX", cDLX) ; forall_print ("CON/DLX [Y.] ", cCONrel) ;

forall_line(); forall_print("GPRenv",cgpr); forall_print("DP",cDP); forallprint("DLX",cDLX); forall_line(); forall_print("GPR/DP [~]",cGPRrell); forall_print("GPK/DLX [~]",cGPKrel2); forall_line();

*/

/* Cycle time and delay of DP environments , /

, / forall_line(); /* cycle time analysis */ sprintf(my_str,"(dmem = Zd)",var.dmem); forall_header("delay",mystr);

forall_print ("aCON_Csig", aCON_Csig) ; forall_print ( "aCON_Mw", aCGN_Mw) ; forall_print ("aSPRcon", aSPRcon) ; f orall_print ("aCaPro" ,aCaPro) ; f orall_print (" agpr_aeqz", agpr_aeqz) ; f orall_print (" aMenv_nready", aMenv_nready) ; f orall_print ( "aalu_ovf ", aalu ovf ) ; f orall_line ( ) ; f orall_print ("t RFwrite", tgpr__RF) ; forall print ( "t RFread", tgpr_RF) ; forall_print ("tSH", tSH) ; forall_print ("t alu_ZR", talu ZR) ; f orall_print ( "talu ZC", talu ZC ) ; f orall_print ("tSRsel_SR", tSRsel SR SK) ; forall print ("tSPR_SR_D", tSPR SK_D) ; f orall_print ("tSPR_MCA" ,tSPR_MCA) ; forall_line () ; forall_print ("tDP", tDP) ; forall_print ("tauto", tauto) ; forall_print ("tCAenv" ,tCAenv) ; forall_print ("tCON", tCON) ; forall line(); f orall_print ("tDLX", tDLX) ; f orall_print ("T_M() ", tM) ; forall_line ( ) ;

B.8. D L X W I T H I N T E R R U P T H A N D L I N G 251

var.dmem = I0; forall_print("T_M(lO)",tM); var.dmem = 50; forallprint("T_M(50)",tM); forall_line(); var.dmem = 25;





forall_line(); I* *I /* CPI independent */ /* ,/ printf("Computing the EQ-values for the DLX designs \n"); printf("non-pipelined, with interrupts, hardwired control\n"); for (i=O; i<2; i++) { set(O,i);

forall_line(); printf(" Technology: ~s \n", name_techno()); forall_line(); for (x=O; x<4; x++) { printf("\t \t ");

for(y=O; y<4; y++) { if (x!= y)

{ set(x, i); cl = cDLX(); tl = tDLX(); set(y, i); c2 = cDLX(); t2 : tDLX(); res = eva!_EQ(cl , tl, c2, t2);

} else

res = 0.0; printf("~.3f ",res);

} printf ("\n") ;

}

I* *I /* Quality ratio Q(q, Vi, Mealy) ./ I* ,I forall_line(); printf("\n Moore(un,bin) vs. Mealy(bin): Motorola x Venuskn"); forall_line(); for (q=O.O; q<l.01; q+=O.02) { printf("~.2f ", q);

for(i=O; i<2; i++)


}

{ /* Motorola vs Venus Technology */ for(x=O; x<2; x++) { set(x, •

cl = cDLX(); tl = tDLX(); set(S, i); c2 = cDLX(); t2 = tDLX(); res = eval_Q(q, cl, tl, c2, t2); printf("Zf ",res);

} } printf(" i.O \n"),

B.9. DLX W I T H MICROPROGRAMMED CONTROL 253

B.9 DLX with Microprogrammed Control

In chapter 9, we replaced the hardwired control by six versions of microprogrammed control. That only impacts directly the cost and the delay of the control automaton, but the hardwired implementation of the control automaton is covered in the service module h a r d c t r .

Thus, a new service module m i c r o c t r is required for the microcoded control. Its header and code file are listed in sections B.9.1 and B.9.2. The architectural file of the DLX with interrupt handling (section B.8) can almost literally be copied, but the evaluation part must be adapted. This part of the new DLX module is listed below.

I* *I /* dlx4.c architectural module non-pipelined DLX */ /* no interrupt handling, microcoded control, CLA adder */ I* *I I* *I /* Evaluation of the design */ I* *I

void main() {

char my_sir[200]; int i, x, y; int ci, c2, ch, tl, t2, th; double res, fac;

/* temporary strings */ /* loop variable */ /* cost, time values */ /* result, scaling of RGM cost*/

static int MCcost = 15087; static int MCtc = 80; static int VEcost = 33480; static int VEtc = 49;

/* Cost, delay of the best DLX with hardwired control */

/* cost DLX, Motorola */ /* cycle time, Motorola */ /* cost DLX, Venus */ /* cycle time, Venus */

init_techno(MOTOKOLA); /* select technology */

/* Control logic parameters */ set_micropar( 32, /* states of state machine */

54, 29, /* output (decoded, encoded) */ 12, 7); /* decode table (full, opt.) */

/* design parameters */ var.n = 32; /* width of the data paths */ var.A = 32; /* number of GP-Registers */ var.dmem = 25; /* memory access time */ var.dmstat = 5; /* memory status time */

for (i=O; i<2; i++) {

printf("\n\n\n Cost Delay Analysis of the DLX Design \n");


printS(" No pipelining, microcoded control, interrupts \n"); printf(" Teclmology: ~s, ", name_techno());

strcpy(my_str,"carry look ahead"); printS(" Adder type: ~s\n", my_str); printS(" width n = ~d, Keg-no = Zd, Mem status time = Zd\n",

var.n,var.A,var.dmstat);

I* *I /* Cost o5 the DP environments and the control */ / * * /

/*

slxall_line(); /* cost analysis */ sixall_header ("cost", .... ) ; sixall_print ("ALUenv", caluenv) ; sixall_print ("SHenv", cshenv) ; sixall_print("IRenv",cirenv); sixall_print("GPRenv",cgpr); sixall_print("PCenv",cpcenv); sixall_print("Menv",cmenv); sixall_print("SPRenv",cSPRenv); sixall line();

sixall_print ("DP", cDP) ; s ixall pr int ( "Cont rol", cCONenv) ; sixall_line () ; sixall_print ("DLX", cDLX) ; sixall_print ("CON/DLX [Y.] ", cCONrel) ;

sixall_line(); sixall_print("GPRenv",cgpr); sixall_print("DP",cDP); sixall_print("DLX",cDLX); sixall line(); sixall_print("GPR/DP [~]",cGPRrell); sixall_print("GPR/DLX [~]",cGPRrel2); sixall_line();

*/

/* Cycle time and delay o5 DP environments , /

, / sixall_line(); /* cycle time analysis */ sprintf(my_str,"(dmem = Zd)",var.dmem); sixall_header("delay",my_str);

sixall_print("aCON_Csig",aCON_Csig); sixall_print("aCON_Mw",aCON_Mw); sixall_print("aSPRcon",aSPRcon); sixall_print("aCaPro",aCaPro); sixall_print("agpr_aeqz",agpr_aeqz);

B.9. DLX WITH MICROPROGRAMMED CONTROL 255

/*

sixall_print("aMenv_nready", sixall_print("aalu_ovf",aalu_ovf); sixall_line(); sixall_print("t_RFwrite",tgpr__KF); sixall_print("tRFread",tgpr_RF); sixall_print ("tSH", tSH) ; s ixall_print ( "t alu_ZR", t alu_ZR) ; sixall_print ("talu_ZC", talu_ZC) ; sixall_print ("t SRsel_SR", t SRs el_SK_SK) s ixall_print ("tSPK_SK_D", tSPR SR_D) ; sixallprint("tSPR_MCA",tSPR_MCA); sixall line(); s ixall_print ( "tDP", tDP ) ; sixall_print ("tauto", tanto ) ; sixall_print ("tCAenv", tCAenv) ; s ixall_print ("tCON", tCON) ; sixall line(); sixall_print("tDLX",tDLX); sixall print("T M()",tM); sixall line(); var.dmem = 10; sixall_print("T_N(lO)",tM); var.dmem = 50; sixall print("T M(50)",tM); sixall line(); var.dmem = 25; sixall line();

aMenv_nready);

I* memory access time *I

I* memory access time */

/* memory access time *I

*/

/* Parameter study: T(auto, dmstat) *I

*I sixall_line(); sixall_header("tauto","dmstat ="); y = var.dmstat; for (x = O; x < SS; x+=lO)

var.dmstat = x; sprintf(my_str," ~d ",var.dmstat); sixall_print(my_str,tauto);

var.dmstat = S;

init_techno(VENUS); /* select technology */

sixall_line(); I* *I /* Standard scaling of KOM cost: EQ() for Encoding /* *I printf("Computing the EQ-values for the DLX designs \n~ printf ("non-pipelined, with interrupt, microcoded control\n") ;


printf("(Table optimal): unary, binary-pre, binary-post \n"); for (i=O; i<2; i++) { if (i == o)

init_techno(MOTOROLA); else

init_techno(VENUS);

sixall_line(); printf(" Technology: %s \n", name_techno()); sixall_line(); for (x=O; x<3; x++) { printf("\t \t ");

for(y=O; y<3; y++) { if (x!= y)

{ set_microtype(i, x); cl = cDLX(); ti = tDLX(); set_microtype(l, y); c2 = cDLK(); t2 = tDeX(); res = eval_EQ(cl, tl, c2, t2);

} else

res = 0.0; printf("Z.3f

} printf("\n");

",res);

/* */ /* Variable scaling of the ROM cost /*

, / , /

sixall_line(); printf(" I MOTOROLA printf(" EQ Cost printf(" rfac Vl,V2 VI,HW sixall_line(); for (fac=l.O; fat<40.2; fac+=0.20) { printf("~5.2f ",fac);

for(i=O; i<2; i++) { /* Motorola vs Venus Technology */

if (i == O) { init_techno(MOTOROLA);

ch = MCcost; th = MCtc;

} else { init_techno(VENUS);

ch = VEcost;

I VENUS EQ

VI,V2

\n"); Cost in") ; V1,HW \n") ;

B.9. DLX W I T H MICROPROGRAMMED CONTROL 257

th = VEtc; }

romfac =fac;

set_microtype(l, I); cl = cDLX(); t l = tDLX();

set_microtype(l, 2); c2 = cDLX(); t2 = tDLX();

res = eval_EQ(cl, tl, c2, t2); printf("Zf ",res);

res = (I.0 * cl)/(l.O * ch); printf("Zf ",res);

} printf(" 1.0 \n");

/ * scaling of ROM cost * /

/* Opt. Table, pre-binary * /

/* Opt. Table, post-bin. */

/ , EQ(vl,v2) , /

/* Cost(Vl,Hardwired) * /

B . 9 . 1 H e a d e r F i l e of the Microcoded Cont ro l /* *************************************************************

** microctr.h microcoded control module **

/* Table = Coding = */ /* 0 : full decode table 0 : unary coded micro-instruction */ /* i : optimized decode I : bin, decoders infront micro-IK */ /* 2 : bin, decoders behind micro-IK */

#ifndef MICKOC_H #define MICKOC_H

extern int set_microtype();

extern int set_micropar();

extern int aOut(); extern int cauto(); extern int tauto();

/ * a C a P r o ( ) , a g p r _ a e q z ( ) ; / * aMenv_nready( ) ;

/* set type of microcoded ctr */ /* Table, Coding */ /* set automaton parameters */ /* states, alpha, widtha,

fsize, osize */ /* accum, delay of outputs */ /* cost of microcoded ctr */ /* cycle time of micro-ctr */

to be defined in machine spec */ accum, delay of inputs */


extern int clLL(); extern int aILL();

/* circuit ILL detects illegal instructions */

/* cost of ILL */ /* accum, delay of ILL */

extern void sixall_line(); extern void sixall_header(); extern void sixall_print();

/* print horizontal line */ /* print two line header */ /* evaluate function, print */

struct micro_parameters { int states, zeta; /* #States of automaton, ld(states) */ int alpha, widtha; /* output: width (decoded, encoded) */ int fsize, osize; /* width: decode table (full, optimal */ int Table, Coding; /* ctr type: decode table, outputs */

};

#endif MICKOC_H

B.9.2 Code File of the Microcoded Control

/* *************************************************************

** microctr.c microcoded control module ** ****************************************************************

#include <stdio.h> #include "techno.h" #include "macro.h" #include "microctr.h"

static struct micro_parameters con = {o,o, o,o o,o, o,o};

/* private control parameters */

/* must be set by set_micro.. */

int set_microtype(t,c) int t,c; {

con.Table = t; con. Coding = c~ return O;

}

/* set type of microcoded ctr */ /* Table, Coding */

int set_micropar(s,al,a,fs,os) int s,al,a,fs,os;

con.states = s; con.zeta = ld(s); con.alpha = al; con.widtha = a;

/* set micro ctrl parameters */

/* #states */

/* #outputs (decoded) */ /* #outputs (encoded) */

B.9. D L X W I T H M I C R O P R O G R A M M E D C O N T R O L 259

con.fsize = f s ; con.osize = os; return O;

/* size decode table, full */ /* size decode table, optimal */

/* --- Decode Unit: decoding the micro-instruction int cMuDec() { return 5*cdecf(3) + 4*cdecf(2) + cdecf(1); }

,/

int dMuDec() { return ddecf(3); }

/* --- Accumulated delay: Csig and microcondition int aOut() { if (con. Coding == 2)

return dHuDec(); else return O;

}

*/

/* --- Accum. delay: inputs of the microcoded automaton ..... extern int aCaPro(), aMenv nready(), agpr aeqz();

,/

/* --- Decode Lookup Table int cDecTab() { if (con.Table == I)

return crom(power2(con.osize), con.zeta) + czero(con.zeta) + con.zeta * cmux;

else return crom(power2(con.fsize), con.zeta);

}

,/

int aDecTab() { if (con.Table == I)

return drom(power2(con.osize), con.zeta) + dzero(con.zeta) + dmux;

else return drom(power2(con.fsize), con.zeta);

}

/* --- Address Selection Unit */ int cAdrSel() { return cDecTab() + 6*con.zeta*cmux + 6*cand + 6*cor + cxnor;}

int aAdrSel() { int dl, d2, d3, d4;


dl = max(max(aDecTab(), aOut() + dmux), dinc(con.zeta)) + 3*dmux;

d2 = max(aOut(), aCaPro()) + dand + dor + dmux + max(dmnx, dot);

d3 = aMenv_nready() + 4*dmux; d4 = max(aOut() + 3*dor, agpr_aeqz() + dxnor + dor)

+ dand + 3*dmux;

return max( max(d1, d2), max(d3, d4)); }

/* --- Cost of control automaton */ int cauto() { int cost;

cost = con.zeta *(cff +cand) +cinv +cinc(con.zeta) +cAdrSel();

switch(con.Coding) { case O:

return cost +crom(con.states, con.alpha) +con.alpha *cff; break;

case 1: return

break ;

cost + crom(con.states, con.widtha) + con.alpha * cff + cMuDec();

case 2: return

break;

cost + crom(con.states, con.widtha) + con.widtha *cff + cMuDec();

default: fprintf(stderr,

"micro.c: cauto() con. Coding out of range\n"); exit(1);

/* --- cycle time of the control automaton int tauto() { int delay;

,/

delay = delta + dff + dand + aAdrSel();

switch(con.Coding) { case O:

r e t u r n de lay + d r o m ( c o n . s t a t e s , con .a lpha ) ; break;

B.9. DLX WITH MICROPROGRAMMED CONTROL 261

case 1: r e t u r n b r e a k ;

delay + drom(con.states, con.widtha) + dMuDec();

case 2: return break;

delay + drom(con.states, con.widtha);

}

default: fprintf(stderr,

"micro.c: tauto() con. Coding out of range\n"); exit(1);

/* --- Testing for illegal instruction int clLL() { return czero(con.zeta) + cand; }

,/

int aILL() { return max(aCON_Csig(), aDecTab() + dzero(con.zeta)) + dand; }

/* === Print functions void sixall_line() {

printf( ...................... '\n");

return; }

*/

void sixall_header(strl,str2) char *strl, *str2; {

printf( "%-14s \t ROM (unary) strl);

printf( "~-14s \t full opt. str2);

sixall_line(); return;

binary Pre-IR

full opt.

bin. Post-IR\n",

full opt.\n",

void sixall_print(str,func) char *str; int (*func) () ; { printf("~i4s:",str);


set_microtype(O set_microtype(l set_microtype(O set microtype(1 set_microtype(O set_microtype(l return;

0); printf("\t~Td",(*func)()); 0); printf("\t~Td",(*func)()); 1); printf("\t~Td",(*func)()); 1); printf("\t~Td",(*func)()); 2); printf("\t~Td",(*func)()); 2); printf("\t~Td\n",(*func)());

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Index

adder, 30-37 carry look-ahead, 34 comparison, 71,123-140, 178 conditional sum, 35 fanout, 42 flags, 30, 31 full adder, 32 overflow, 30, 31 ripple carry, 32

admissible control signal, 16 interrupt service routine, 174

alignment, 77 ALU, 29, 82-86 architectural module, s e e module architecture, 5

comparison, 7 model, 5-20 performance, 6 quality, 6

arithmetic logic unit, s e e ALU arithmetic unit, 38, 123 atomic, 146 automaton

Mealy, 43 Moore, 43

basic component, 9 n-bit version, 21

benchmark, 6, 66, 133 binary number, 23 branch target computation, 78 buffer, 41

carry look-ahead adder, 34 cause environment, 156 cause processing, 157

cause register, 144 circuit, 11, 12, 15 clocked circuit, 12 clocking overhead, 13 combinatorial circuit, 11, 21 comparator, 83, 124 comparison, 5, 7, 198

workload dependent, 132 workload independent, 129

condition test, 83, 124-128 testing inputs, 125 two cycles, 126

conditional sum adder, 35 control~ 15, 62, 100-110,152

automaton, 43, 157 hardwired, 43-58, 100 microcoded, 179-198 microprogrammed, 179-198 parameters, 47, 106

control circuit CaPro, 157 CM, 46 CN, 46 MC (memory), 98 NSD, 50 NSE, 47 OD, 45 PCC, 97 SPRCon, 151 zO, 50

control signals, 15, 43 admissible, 16 encoding, 183, 192 naming, 82 standard, 112 valid, 112

268 I N D E X

correctness, 173-177 CPI, 5, 68, 133, 135 cycle time, 16

data paths, 15 DLX, 81 Markl, 61 modified hardware, 16

decoder, 24 delay

accumulated, 19 gate, 9 nomenclature, 18

design evaluation, s e e evaluation disjunctive normal form, s e e DNF DLX, 77

cost, 110, 164, 195 cycle time, 112, 166, 194, 195 instruction format, 77, 78 instruction set, 78, 106, 145 interrupt, 148-172 simplified view, 113, 167

DLX control, 100-110,152, 157 DNF, 103, 106, 160 FSD, 103, 158, 160 microcoded, 185-198 microprogram, 188 parameters, 106, 163 signal frequency, 106, 163 signals, 101,158, 160

DLX data paths, 81-100, 148 DLX environment

special purpose registers, 149 ALU, 82-86, 123, 124 cause, 156 instruction register, 93 main memory, 97-100, 148 PC, 96, 148 register file, 94-96 shifter, 86-92

DNF, 44, 103, 106, 160

encoder, 26 encoding, s e e control signals environment, 81 equal quality parameter, 8

evaluation, 5, 63, 119, 123-140,171, 178, 196

exception registers, 144 execution scheme, 101

fanout, 22, 41, 42 fanout tree, 41 finite state diagram, s e e FSD finite state transducer, 43 FSD, 43, 101, 103, 158, 160

fanin, 44 weight, 44

full adder, 32 functional library, 21-42,210-215

gate delay, 9 gate equivalent, 9 generate signal, 35

half-decoder, 26 hardware

modified, 13 hardware model, 8-20

Ltype instruction, 78 illegal instruction, 154, 191 incrementer, 28 input

external, 18 open, 15

instruction format, 78 instruction register, 93 instruction set

DLX, s e e DLX interrupt, 141-178,182

caught, 173 completion, 175 correctness, 173-177 event signal, 141,153 external, 142 finite space, 175 maskable, 141 nested, 145 occurred, 173 pending, 144, 173 precise, 175

I N D E X 269

priority, 142, 175 receives service, 173 response time, 174 resume, 142 termination, 175 type, 141

interrupt convention, 143 interrupt level, 173, 174 interrupt service routine, 141, 145

admissible, 174 interrupt stack, 145 interrupt support, 143-164, 172

hardware, 144, 148 software, 145

J-type instruction, 78

library functional, 21-42, 210-215

logic unit, 84

main memory, 16, 97-100, 148 access time, 17 control, 98 modified hardware, 17 protection, 100 status signals, 17, 98, 100, 154 status time, 17, 121,177

Markl, 59-75 cost, 63 cycle time, 64 data paths, 61 instruction set, 60 quality, 68, 74

Mealy automaton, 43 Mealy implementation, 49-53, 56

binary, 49 unary, 53

micro state, 15 micro-address selection, 181,188 microcondition, 180 microinstruction, 179 microinstruction format, 185 microprogram, 179, 188 microprogram ROM, 179 model

architecture, 5-20 hardware, 5, 8-20 performance, 5

modified hardware, 13 data paths, 16 main memory, 17 RAM, 14 tristate driver, 13

module architectural, 203, 222-257 service, 203-221,257-262

Moore automaton, 43, 100 Moore implementation, 45-49, 54

binary, 45 unary, 48

Motorola H4C technology, 9

number binary, 23 two's complement, 29

overflow, 30, 31,154

parallel prefix, 34 performance, 6 performance model, 5 performance ratio, 7 powerup convention, 18 powerup mechanism, 45, 50, 62, 96,

148, 177, 180 powerup signal, 45, 156 propagate signal, 35 protected region, 147

q-range global, 135 local, 132

quality, 6 EQ, 8, 130 metric, 6 parameter, 6 ratio, 7, 74, 129

R-type instruction, 78 RAM, 9

modified hardware, 14 multiport, 10

270 I N D E X

register, 12, 22 general purpose, 94 special purpose, 144, 145, 149

register transfer language, 43, 201- 202

ripple carry adder, 32 incrementer, 28

P~OM, 10 ROMfac, 10, 196, 198

sequencing data, 180 service module, see module shift

arithmetical, 86 explicit, 86 left, 86 logical, 86 parameters, 87 right, 40, 86 special, 86

shifter, 86-92 barrel, 39 block diagram, 89 cyclic, 38 distance, 90 fill, 90 mask, 92

sign extension, 77 status

restore, 147, 174 save, 146, 174

status register, 144, 145, 149, 151 subtraction, 37

table lookup, 182, 183,190 technology

Motorola, 9 optimization, 41 Venus, 9

trade-off, 69-74, 123-140, 178 trap, 145, 154 two's complement number, 29

Venus design system, 9

workload, 5

zero test, 28

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Register Transfer Language - Springer978-3-540-47774-7/1 · Appendix A Register Transfer Language Usually, a register transfer language is used, to specify the meaning of machine