Research Article FPGA Control Implementation of a Grid …downloads.hindawi.com/journals/jcse/2013/713293.pdf · 2019-07-31 · e practical viability of the system is evaluated in

Hindawi Publishing CorporationJournal of Control Science and EngineeringVolume 2013 Article ID 713293 10 pageshttpdxdoiorg1011552013713293

Research ArticleFPGA Control Implementation of a Grid-ConnectedCurrent-Controlled Voltage-Source Inverter

Rickard Ekstroumlm and Mats Leijon

Division of Electricity Swedish Centre for Renewable Electric Energy Conversion Uppsala University PO Box 534751 21 Uppsala Sweden

Correspondence should be addressed to Rickard Ekstrom rickardekstromangstromuuse

Received 8 April 2013 Revised 20 September 2013 Accepted 25 September 2013

Academic Editor Mohamed Zribi

Copyright copy 2013 R Ekstrom and M Leijon This is an open access article distributed under the Creative Commons AttributionLicense which permits unrestricted use distribution and reproduction in any medium provided the original work is properlycited

The full control system of a grid-connected current-controlled voltage-source inverter (CC-VSI) has been designed andimplemented on a field-programmable gate array (FPGA) Various control functions and implementation methods are describedand discussedThe practical viability of the system is evaluated in an experimental setup where a VSI supplies 30 kW into the localgrid at 400V A phase-locked loop (PLL) is used for grid phase tracking and evaluated for simulated abnormal grid conditionsPower factor is kept at unity and the implemented control system is stressed with step responses in the supplied active power Amoving-average filter is implemented to reduce the effects of noise and harmonics on the current control loops A coupling betweenactive and reactive power flow is observed for the step responses but may be ignored in this context The proposed system is fullycomparable with more conventional microprocessor-based control systems

1 Introduction

The voltage source inverter (VSI) has become increasinglyused for grid connection of renewable energy sources suchas wind power turbines or solar cells Improved ratings insemiconductor components like the insulated-gate bipolartransistor (IGBT) are gaining market for more and morepowerful applications where only the thyristor-controlledcurrent-source converter has been used earlier The VSIis dominating the market of distributed generation andmay be controlled by either voltage or current feedbackCurrent-control (CC) is favoured due to its excellent dynamiccharacteristics and its inherent overcurrent protectionThereare three major groups of current-control modulations forVSIs namely hysteresis control [1] predictive current control[2] and ramp comparison [3] A survey on current-controlmethods is presented in [4]

Depending on the control strategy the power convertercontrol system has traditionally been designed with micro-controllers or complex programmable logic devices (CPLDs)However increased complexity and more real-time dataanalysis have called for the development of digital signal pro-cessors (DSPs) The DSPs have very good programmability

and can easily manage conditional code Due to their abilityto work with floating point arithmetics they can handlecomplex mathematical functions well

Alternatively the application-specific integrated circuit(ASIC) may be used where all the functions are designedinto a fixed integrated circuit The ASIC has to implementall functions in gates and very complex conditional programsmay result in very poor gate utilization Also the ASICis limited to fixed point arithmetic As the gates can beprogrammed in parallel the ASIC can operate simpler logicat a much faster rate than its DSP counterpart Howeveronce the ASIC is designed and manufactured it cannot bemodified for bugs or changed system characteristics whichmakes it less useful in development projects

The advent of the FPGA has resolved this issue andmakes it superior to the ASIC for researchers and develop-ers Even though the FPGA requires much more area andpower consumption and is about three times slower thanits ASIC counterpart [5] its short time to market and field-programmable ability make it a tempting solution

The FPGA structure is based on a matrix of controllablelogic blocks (CLBs) These consist of a look-up table (LUT)which can be configured either as a RAMROM or as logic

2 Journal of Control Science and Engineering

functions and aD-type flip-flop that can handle for exampleregisters The CLBs are interconnected by a programmablewire network synchronized with a top level clock ModernFPGAs can also have extra inbuilt features such as dedicatedDSP-blocks that can handle complex computations in oneclock cycle Also external LUT blocks may be used asmemory

The use of FPGA technique within power electronicsis mostly seen where rapid inputoutput (IO) is requestedReviews of control system implementation in FPGA is foundin [6ndash8] Grid impedance analysis using FPGA are done in[9] An FPGA-based grid phase trackingmethod is describedin [10] and pulse-width modulation (PWM) implementa-tions for inverters are found in [11 12] A combination of DSPand FPGA for SVM-control of a matrix converter is usedin [13] and more FPGA-based SVPWM implementationscan be found in [14 15] FPGA-implementations for faultdetection in a VSI control is made in [16]

In this paper the control system of a grid-connectedCC-VSI has been designed and implemented on an FPGAThe control system includes phase tracking of the gridvoltage inverter logic output control active and reactivepower flow control high-speed burst logging and faultdetection Hardware implementations are discussed as wellas their limitations and the number of gates required forspecific functions are summarized The control system isimplemented on the FPGA-chip of a compactRIO moduleand the VHDL-code is generated by LabView G-code Thesystem allows for integration of a RT-controller if heavierdata analysis is required The practical viability of the systemis evaluated in an experimental setup with a grid-connectedVSI 30 kW at unity power factor is injected into the localelectric grid and the current-control loops are evaluated bymaking step responses in the active power flow

2 FPGA Programming

The initial step in FPGA design is to define the algorithmsused An algorithm can be characterized by its complexityand time constraints The accuracy of IO-variables is set bytheir bit sizes

Once this is done the possibility of reusing modulesin the system has to be explored By smart time sharingan algorithm may be put as a subroutine and routed toseveral different parts of the FPGAmodule Finally the samefunction may be expressed in different ways with the logicgates available The most gate-efficient algorithm should beused based on the available gate resources on the FPGAThere are various ways of implementing the VHDL-codeon the FPGA Many compilers offer the programmer towrite in a more user-friendly language which seldom isas efficient as direct VHDL-programming The conversioninto VHDL from another language will be a compromisebetween compilation time space optimization or clock cycleoptimization Below a few key functions are summarized

21 Integer Numbers The fundamental building blocks ofan FPGA are best utilized with integer maths operations

FXP (16 1) FXP (16 0)

2minus2

2minus4

2minus6

2minus8

+

+

+

Figure 1 Multiplication by the use of adders and decimal pointshifters

Floating-point (FP) operation is possible but provides poorutilization of the logic cells [17] If decimal points arerequired fixed-point numbers (FXP) are used instead A FXPis predefined by its bit length and the number of bits allocatedfor decimal accuracy and may be signed or unsigned Onedrawback of FXP compared with FP is that they rapidlygrow in size with the computations performed on them Caremust be taken to avoid saturation or overflow of a FXP Anevaluation of FXP precision is found in [18 19]

22 IntegerMultiplication While adding and subtracting arerather straightforward operationswith little space demand onthe FPGA multiplication is a big ldquogate-hogrdquo that should beavoided if possible However if the multiplication is fixedthis is not true if the multiplying factor is a multiple of 2Multiplication with 2119873may easily be replaced with a decimalpoint shift 119873 times to the left or right on the FXP Thisrequires no resources since it is only a matter of rerouting ofthe FXP between logic cells If the multiplying factor cannotbe approximated to a factor of 2 it may be simplified to a sumof fractions of 2 and then added For example the multiplier13 may be approximated as1

3asymp85

256=64 + 16 + 4 + 1

256=1

4+1

16+1

64+1

256(1)

which will give an error of about 04 Depending on theaccuracy required the number of fractions may be variedFigure 1 shows the implementation of this The resourceallocation for the proposed method compared to using anormal multiplication block is shown in Table 1 for imple-mentations on a Xilinx-5 chip Here the first method cansave approximately 2 of the dedicated DSP blocks on theFPGA Implementation of division should be converted intomultiplication instead as this will save lots of space

23 Integrals On the contrary to derivatives the integral ofa signal is very straightforward on the FPGA The integral of119881in(119905)may be approximated as a finite sum according to

int

119905

0

119881in (119905) d119905 asymp Δ119905 sdot119899

sum

119894=1

119881in (119905119894) (2)

where Δ119905 is the sampling time and is assumed constant hereBy using shift registers the cumulative value of the signal is

Journal of Control Science and Engineering 3

Δt

Vin

Set loop time

Shift register

intVindt+times

Figure 2 Implementation of the discrete integral in FPGA by theuse of shift registers

Table 1 FPGA gate utilization for two different types of multiplica-tion

Multiplier Decimal shift and addersTotal slices 43 43Slice registers 22 20Slice LUTs 20 22DSP48s 21 0Block RAMs 0 0

stored locally in the CLB and used directly for the next loopcycle as shown in Figure 2 The sampling time Δ119905 sets theaccuracy of the integral and is also used as a scaling factorfor the output

24 Advanced Functions More advanced calculations forexample trigonometric logarithmic or square-root func-tions would require large amounts of resources if imple-mented as in a DSP counterpart In the early age of FPGAwork was put into expressing these functions as combinationof the simpler blocks [20] As memory sizes grew the useof look-up tables (LUTs) became a better option Todaygeneric DSP blocks are often integrated on the FPGA semi-conductor chip and may perform these high through-putcomputations within one clock cycle In Table 2 a resourcecomparison is done between a sinecosine LUT-block anda trigonometric computational block producing the sameoutput implemented on the Xilinx-5 The speed resolutionand functionality of the two are equivalent but it is clear howthe LUT locks up one third of the total block RAM availablemaking it less attractive However the RAM space demandof the LUT will decrease proportionally with reduced outputresolution

3 Grid Phase Tracking

There are various known methods of tracking 120579 the gridphase Zero-crossing detection is a simple method to imple-ment but is sensitive to noise and does not give any phaseinformation between the zero-crossings More advancedmethods include the phase-locked loop (PLL) Kalman filtersor the discrete Fourier transform (DFT) A good comparisonbetween these may be found in [21] In this paper grid

Table 2 FPGAgate utilization for sine and cosine calculations usinga LUT or a computational block

Computational block LUTTotal slices 46 50Slice registers 20 20Slice LUTs 25 27DSP48s 0 0Block RAMs 0 312

phase tracking is performed using a three-phase synchronousreference frame PLL loop due to its robustness and relativelysimple implementation The PLL structure is shown inFigure 3

The closed-loop transfer function119867PLL(119904) of the PLL canbe written as [21]

119867PLL (119904) =119870119875119904 + 119870119868

1199043119879119878+ 1199042+ 119870119875119904 + 119870119868

(3)

where 119870119875and 119870

119868are the gains of the PI-controller and 119879

119904is

the sampling time of the PLL If the sampling frequency issufficiently high the above expression can be simplified to

119867PLL (119904) =119870119875119904 + 119870119868

1199042+ 119870119875119904 + 119870119868

(4)

The sampling frequency is usually set to the switchingfrequency or half of it depending on the control algorithmused The design of the PLL is discussed in [22 23] and is acompromise between speed and noise immunity A discretebit-stream PLL implementation is discussed in [24]

4 Power Flow Control

Assuming a stiff grid the active power 119875 and reactive power119876 for a grid-connected VSI are governed by

119875 =

10038161003816100381610038161003816119881119892

10038161003816100381610038161003816

10038161003816100381610038161198811198941003816100381610038161003816

119883sin (120575)

119876 =

10038161003816100381610038161003816119881119892

10038161003816100381610038161003816

10038161003816100381610038161198811198941003816100381610038161003816

119883cos (120575) minus

10038161003816100381610038161003816119881119892

10038161003816100381610038161003816

2

119883

(5)

where 119881119892is the grid voltage 119881

119894the inverter voltage 120575 the

phase angle and119883 the reactance between theVSI and the gridTo simplify the current-control feed-back system all

phase currents are transformed into the 1198891199020-frame by

1198681198891199020= 119879 lowast 119868

119886119887119888 (6)

where 119879 is the ClarkePark transformation matrix [25]

119879 = radic2

3(

cos (120579) cos(120579 minus 21205873) cos(120579 + 2120587

3)

sin (120579) sin(120579 minus 21205873) sin(120579 + 2120587

3)

1

radic2

1

radic2

1

radic2

) (7)


Vgabc120572120573

Vddq

120572120573

Km120579lowast sin

cossin(120579lowast)cos(120579lowast)

Vlowastd = 0

120596lowast

PLL

+PI120576+minus

1

s

120596FF

Figure 3 Schematic of the phase-locked loop for grid phase tracking

DCsource

InverterTransformer LCL-filter

SPWM

Control system

ilowastq

abc120572120573

120572120573

dq

120572120573

120572120573

abc

dq

ilowastd = 0

iq

Ig Vg

id

Vgrid

PI

PIPLL

PI+minus

+minus

+minus

sin(120579)cos(120579)

Vlowasta Vlowast

b Vlowastc

Vlowastdc

Vdc

Figure 4 Experimental setup and control system overview for the grid-connected CC-VSI

In this paper the sinusoidal pulse-width modulation(SPWM) will be used [26] where a control signal 119881

119888is

compared with a carrier wave signal to generate the inverteroutput pulses 119881

119888is generated by

119881119888= 119881lowast

119888119889sdot sin (120596119905) + 119881lowast

119888119902sdot cos (120596119905)

= 119898119886sin (120596119905 + 120575)

(8)

where 119881lowast119888119889

and 119881lowast119888119902

are current-control feed-back variablesused to control the active and reactive power flows Theamplitude modulation index is 119898

119886= radic(119881

lowast

119888119889)2+ (119881lowast

119888119902)2 and

the load angle is 120575 = tanminus1(119881lowast119888119902119881lowast

119888119889) If 119898

119886lt 1 the inverter

fundamental output phase voltage 1198811198941is derived as

1198811198941= 119898119886

119881DC

2radic2

(9)

5 Experimental Setup

The one-line diagram of the experimental setup is shownin Figure 4 The three-phase inverter is made from 3 dual-package 400GB126D IGBT modules with 2SC0108T2Ax-17driver boards mounted above as shown in Figure 5(a) Thesehave in-built short-circuit protections set to trigger 25120583safter fault detection The inverter is directly connected toa three-phase 345V1 kV YY-connected transformer Thetransformer ratings are given in Table 3

An LCL-filter is placed on the secondary side of thetransformer The primary and secondary filter inductors are

Table 3 Transformer rating

Power rating 80 kVAVoltage ratio 345V1 kVPrimary winding resistance 17mΩPrimary leakage reactance 1mHSecondary winding resistance 012ΩSecondary leakage reactance 22mHMagnetizing impedance (50Hz) 23HMagnetizing resistance (50Hz) 173Ω

both designated the value of 15mHThese are manufacturedon two three-phase cores and there is an unbalance betweenthe phases ofplusmn10The shunt capacitors are connected in starconfiguration with 20120583F per phase The grid main voltage atthe point of common coupling (PCC) is 400V at 50Hz

A compactRIO NI-9014 module with integrated RT-controller and FPGA chip from the National Instrumentswas used as shown in Figure 5(b) The FPGA chip is ofmodel Xilinx-5 [27] with an internal clock frequency of40MHz The RT-controller is of the model NI-9022 Twoof the four available IO-slots in the chassis are used Inthe first an NI9205 analogue differential input module isput for data sampling It has a total of 16 available channelswhen set in differential mode with an analogue-to-digitalconversion (ADC) speed of 250 kSs for a single-ended inputand 16 bit resolution A differential input requires threetimes the sampling time In the given control strategy sevenmeasurements have to be made 3 grid voltages 3 grid


(a) (b)

Figure 5 (a) Three-phase inverter with driver circuits mounted on top (b) The compactRIO-based control system

Table 4 FPGA gate utilization for various implemented functions

Loop function Total slices Slice registers Slice LUTs DSP blocks Block RAM (kbit) Loop timeabc120572120573-transform 458 880 851 0 0 9 ticks120572120573dq-transform 476 1010 760 8 0 8 ticksPLL (without transforms) 1360 2581 3342 4 0 36 120583119904Control signal generation 722 1676 1479 15 0 5 ticksSPWM 541 1017 1103 0 0 7 ticksOvercurrent protection 703 1009 1465 1 0 84 120583119904Grid monitor with burst log mdash 1375 2621 1 0936 84 120583119904Gate usage 4260 9548 8279 29 0936Gates available 7200 28800 28800 48 1728Gate usage () 5916 3315 4035 6042 5417

currents and 1 DC voltage measurement (To slim the systemfurther only two voltage and current measurements maybe used for the grid if the system neutral is floating) Thehardwired ADC MUX will share these equally allowing thesampling frequency to reach 119 kHzThe second IO-slot inthe chassis is used for the inverter control signal output HereanNI9401module is utilized with 8 digital outputs eachwitha delay time of 8120583s For the three-phase inverter only six ofthe outputs are required

6 FPGA implementations

The control system of Figure 4 was implemented usingLabview G-code This is compiled into VHDL-code beforeprogrammed onto the FPGA chip The advantage of usingLabview is a relatively user-friendly interface with the draw-back of a not completely optimized VHDL design and somelimitations in the code writing

A general overview of the various control loops is foundin Figure 6 All the necessary parts of the system are imple-mented in the FPGA As can be seen there is also provisionto connect a RT-controller and a PC These are not crucialfor the control system but provide auxiliary functions TheRT-controller can be used for harmonic analysis of the gridcurrents fault handling and transfer of data from the FPGAburst log The burst log is triggered at any fault detection likean overcurrentThe PCworks as a remote interface and long-term data

The gate utilization of all the functions implementedabove is summarized in Table 4 This is not claimed to becompletely optimized Also some auxiliary functions forinitializing the system and general protections are excludedas they are not the scope of this paper The dominant delaytime of the control system is the input sampling time of theADCs requiring 12120583s per sample The data processing andinternal logic have time delays in the order of ticks whichbecome negligible in comparison To improve the systemdynamics further the ADCs must become faster

Below the major functions are described

61 abc-dq0 Transformation The 1198861198871198881198891199020 transform is usedin both the PLL and the current-control loop It is imple-mented as a subroutine and used for the two instances As canbe seen in Figure 6 the subroutine is implemented in seriesfor the two computations making it possible to reuse moreefficiently In the calculation of the SPWM control signals119881119888 the 1198891199020119886119887119888-transform is used instead and this has to be

coded separately However the terms sin(120579) and cos(120579) arestill the same and may be called by local variables for a moreefficient gate utilization If we assume a balanced steady statethree-phase system the 0-componentmay be omitted and sothe ClarkePark transform is reduced to

119879 = radic2

3(

cos (120579) cos(120579 minus 21205873) cos(120579 + 2120587

3)

sin (120579) sin(120579 minus 21205873) sin(120579 + 2120587

3)

) (10)


cos(120579)

Stop

Analogueinputs

Burst log

Overcurrent

FPGA

PLL

RTPC

Faultdetection

Writetofile

Gridharmonicanalysis

Control signal generation SPWM

Digitaloutput

Sawtoothwave

Vabc

Iabc

abcdq

abcdq

Vd

idiq

ilowastq

ilowastd = 0

+minus

MAF

MAF

PI

PI

Vlowastcd

Vlowastcq

sin(120579) cos(120579)

sin(120579) cos(120579)

Ith

gt

gt

dqabc

Vlowastcd

Vlowastcq

Vc

Vc

+minus

+minus

PI

sin(120579)

Set Vlowastdc

Vdc

Figure 6 Overview of the FPGA implementation of the grid connection control system

Since the FPGA used has generic DSP-blocks some ofthese are used for generation of sine and cosine waveforms asdiscussed in Section 24 For any trigonometric phase inputa 16-bit output is generated within one clock cycle Howevertrigonometric functions are still rather space demandingand the matrix transformation in (10) requires six of theseAlternatively 119881

119889119902can be calculated by

119881119889= radic2

3[119881119886cos (120579) + 119881119887 (minus

1

2cos (120579) +

radic3

2sin (120579))

+119881119888(minus1

2cos (120579) minus

radic3

2sin (120579))]

119881119902= radic2

3[119881119886sin (120579) + 119881119887 (minus

1

2sin (120579) minus

radic3

2cos (120579))

+119881119888(minus1

2sin (120579) +

radic3

2cos (120579))]

(11)

which only requires two trigonometric functions but has twoextra multiplication functions instead The two implementa-tions of the 119886119887119888119889119902-transformation are illustrated graphicallyin Figures 7 and 8 A comparison of the gate utilizationfor the two types is found in Table 5 In this case thereis no difference between the two but it illustrates how thesame function can be implemented in different ways If thetrigonometric functions are more gate demanding type 1is more efficient whereas if the multiplication blocks aremore gate demanding type 2 should be selected In theexperimental setup type 1 has been implemented

62 PLL The major delay of the PLL loop is the gridvoltage ADC delay times This sets the loop frequency at119 kHz which is sufficient for the reduction of (3) to (4)

Table 5 Comparing two types of implementations of the abcdq-transformation

Type 1 Type 2Slice registers 308 308Slice LUTs 319 313DSP48s 126 126Block RAMs 0 0

The integral of the frequency to get the phase is done bythe procedure explained in Section 23The PI-controller canbe implemented by either using shift registers or using thegenericDSP-blocksHere the latter is chosen as it has slightlybetter dynamics at the expense of more gates required Thevariables sin(120579) and cos(120579) are fed into local variables thatmay be used in parallel loops on the FPGA Local variablesare designated double frames in Figure 6

63 SPWM and Current Control Calculation of the bipolarSPWM control signals 119881

119888for all three phases is done with

the inverse ClarkePark transformation reusing the trigono-metric results from the PLL by the local variables mentionedabove The inverter digital outputs are generated by com-parison of 119881

119888with a carrier waveform like a sawtooth wave

or a triangular wave The harmonic content of 119881119894does not

differ much between the two [28] Here the sawtooth waveis selected due to its easiness to implement To implementthe sawtooth wave a simple counter with 2N steps is usedstarting at minus119873 and going up to 119873 If the SPWM loop timeshown in Figure 6 takes 119905SPWM119904 to run once the switchingfrequency 119891

119904of the sawtooth wave can be calculated as

119891119904=119891FPGA2119873119905SPWM

(12)


Vq

120579

cos

Va

minus2minus1

minus2minus1

sin

Vc

Vd

Vbradic 23

radic3

2

times

times

times

times

times

times

times

times

times

times+

++

+

minus

minus

Figure 7 119886119887119888119889119902-transform with type 1

Vq

120579

cos

Va

sin

Vc

Vd

Vb radic 23

times

times

times times

times

times times

times

+

+

minus2120587

3

+2120587

3

sin

sin

cos

cos


where 119891FPGA is the clock frequency of the FPGA here it is40MHz If the SPWM-loop is put in series with the PLLthe run time becomes 84 120583s If the required 119891

119904is 35 kHz

the resolution of the carrier wave becomes limited to 4 stepsmaking the output useless Since 119881

119888will not change signifi-

cantly between sampling times it is valid to put the SPWMloop as a parallel process on the FPGA Now the SPWMloop time is only 8 ticks and by setting for example 119873 =512 steps we obtain a switching frequency of 119891

119904= 488 kHz

This gives a good compromise between switching frequencyand carrier wave resolutionThe switching frequency may bealtered either by changing 119873 or introducing a delay time toprolong 119905SPWM

The control variables 119881119888119889

and 119881119888119902

are derived by com-paring the measured 119894

119889119902with the set 119894lowast

119889119902and applying two

PI-control blocks on the result 119894lowast119889is always set to zero to

get unity power factor into the grid 119894lowast119902is derived based

on the difference of the measured 119881119889119888

and the set 119881lowast119889119888 To

reduce the effects of harmonics and noise on the currentsignals a moving average filter is applied on 119894

119889119902 This is easily

implemented by calculating themean of the last 100measuredvalues stored in shift registers

7 Results and Discussion

Initially the PLL was tested by simulating a three-phase gridvoltage internally on the FPGA using LUTs In Figure 9(a)the grid phase for a distortion-free 50Hz grid voltage istracked by the PLL with perfect results In Figure 9(b)5 of the 3rd 5th and 7th harmonics are added to thegrid voltage The phase tracking is still stable and doesnot completely follow the grid phase harmonic derivativessince these will be partially filtered out by the PLL transferfunction


0 20 40 600

1

2

3

4

5

6

Time (ms)

Phas

e (ra

d)

PLLVg

(a)

0 20 40 600

5

4

3

2

1

6

Time (ms)

Phas

e (ra

d)

PLLVg

(b)

Figure 9 PLL phase tracking versus the grid phase for (a) a perfect grid and (b) a grid polluted with 5 of the 3rd 5th and 7th harmonics

minus400 minus200 0 200 400minus1

minus05

0

05

1

Time (120583s)

Grid voltagePLL signal

Volta

ge (V

)

(a)

0 5 10 15 20minus1

minus05

0

05

1

PLL

Time (ms)

Volta

ge (V

)

Vg

(b)

Figure 10 Time domain phase tracking of the grid voltage In (a) the discrete steps of the PLL output are shown based on a sampling timeof 84 120583s around the zero-crossing of the grid voltage In (b) 20 Gaussian noise is added to the grid voltage and the resultant PLL outputacts as a lowpass filter

In Figure 10(a) the time-domain zero-crossings of thegrid voltage and the PLL signal are compared The PLL isupdated with the analogue input sampling time of 84 120583s andis set constant in between Since the grid voltage does notchange significantly between samples the discrete PLL is agood representation of the grid voltage In Figure 10(b) thenoise immunity of the PLL is evaluated Here 20 Gaussiannoise is added to the grid voltage and as can be seen this iseffectively filtered out by the PLL since the integrals act as alow-pass filter

Figure 11 shows the three phase currents at 30 kW activepower injection into the grid The reactive power flow isset to zero The system is stable but there is a minorunbalance between the phase currents due to an unbalancein the harmonic LCL-filter This can be mitigated by eithercompensation of the SPWM control signals or the controlsystem can be extended to three individual current-controlloops one per phase However this mitigation will not belinear due to the power transformer that will try to cancelany voltage unbalances by its internal flux For a more stable


0 10 20 30 40 50 60minus100

minus50

0

50

100

Time (ms)

minus200

0

200

I LN

(A)

VLN

(V)

Ia Ib IcVa

Figure 11 Grid currents and one phase voltage when the invertersupplies to the grid with 30 kW active power at unity power factor

0 100 200 300 400 500minus15

minus10

minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id

Figure 12 Step-up response in active power from 1 kW to 21 kW119876lowast= 0

current-control loop symmetrical filtering may be applied tothe measured currents

With intermittent renewable energy sources theremay bea swift change in power input to the grid unless there is someintermediate energy storage Thus the current-control sys-tem has to manage step responses in active power while stillkeeping reactive power flows at the desired level In Figure 12a step-up response is made from 1 kW to 21 kWwhile keepingthe desired reactive power flow zero and in Figure 13 thecorresponding step-down response is performed Since thegrid voltage is stable 119894

119902is directly proportional to the active

power and 119894119889proportional to the reactive power

Due to the distortion in the grid voltage the injectedcurrent will carry lower order harmonics which cannot beremoved by the low-pass LCL-filter These are clearly presentin the ripple of 119894

119889119902of Figures 12 and 13 The presence of

these harmonics makes it harder to tune the sensitivity ofthe current-control feed-back loops and there are two waysof resolving this Either the 50Hz fundamental frequency ofthe currents is filtered by a high-order bandpass filter Thisis preferably implemented as an analogue filter as its FPGA-implemented counterpart though possible will require alarge number of gates The other way is by filtering the 119894

119889119902-

currents In 119889119902-frame the DC-component corresponds tothe fundamental frequency and a simple moving average

0 100 200 300 400 500minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id

Figure 13 Step-down response in active power from 21 kW to 1 kW119876lowast= 0

filter will do the trick However this will reduce the speedof the current-control The method chosen depends on therequired sensitivity of the current-control loop In this papera smoothing moving-average filter has been applied on theFPGA The moving average values of the 119894

119889119902currents can be

seen as dotted lines in the figures and are used as inputs forthe PI-controllers The resultant current response takes a fewcycles to settle at the new power level but is sufficiently goodfor these kind of applications

It is also worth pointing out how the sudden step changein active power results in a fluctuation of reactive powerwhich reflects the coupling of the two in (5) A step-up changein 120575 results in a drop of reactive power119876This is counteractedby the 119894

119889feedback control loop by increasing |119881

119894| till 119876 again

has settled at zero The increase in |119881119894| will give a further

increase in active power and finally the system settles at anew steady-state pointThe inverse phenomena occur for thestep-down case For step changes within these ranges 119875 and119876 can confidently be treated by separate control loops withrelatively stable outputs The response time can be decreasedfurther by tuning the PI-coefficients more aggressively If theoscillations between 119875 and 119876 become an issue feed-forwardcross-coupling terms may be introduced to make the controlloop more dynamic

8 Conclusions

In this paper the control system for a grid-connected current-controlVSI has been designed and implemented on anFPGAwhich differs from the more conventional microprocessor-based implementations The system has proven viable fora grid-connected VSI supplying the local grid with 30 kWand full reactive power control The development of FPGAtechnology especially the generic DSP-blocks makes thisa competitive control hardware and is very suitable fordevelopment projects Also a complementary systemmay beused if heavier computations or data logging is required Inthe article a RT-controller is used for for example harmonicanalysis burst log and fault detection

A PLL is implemented and shows steady phase trackingof the grid voltage Grid voltages have been simulated with


added harmonic contents and noise still maintaining a stablephase tracking in the PLL

There is a minor unbalance between the phase currentsdue to an unbalance in the LCL-filter This can be relievedby individual phase control of the inverter Step responseshave been performed in active power while maintaining thereactive power at zero Due to the lower-order harmonic con-tent of the grid currents a moving average filter is added toget smoother 119894

119889119902control variables This results in a stable but

slightly slower step response In the power range evaluated119875-and119876-control can be treated with uncoupled current controlloops still maintaining stable step responses To reduce theoscillations further feed-forward cross-coupling terms haveto be added between 119875 and 119876

References

[1] K D Brabandere J V denKeybus B Bolsens J Driesen and RBelmans ldquoSampled-data dual-band hysteresis current controlof three-phase voltage source invertersrdquo in Proceedings of the15th International Conference of Electrical Machines (ICEM rsquo02)Brugge Belgium 2002

[2] K D Brabandere J van den Keybus B Bolsens J Driesenand R Belmans ldquoFPGA-based current control of PWM voltagesource invertersrdquo in Proceedings of the 10th European PowerElectronics and Drives Association Toulouse France 2003

[3] D M Brod and D W Novotny ldquoCurrent control of VSI-PWMinvertersrdquo IEEE Transactions on Industry Applications vol 21no 3 pp 562ndash569 1985

[4] M P Kazmierkowski and L Malesani ldquoCurrent control tech-niques for three-phase voltage-source pwm converters a sur-veyrdquo IEEE Transactions on Industrial Electronics vol 45 no 5pp 691ndash703 1998

[5] I Kuon and J Rose ldquoMeasuring the gap between FPGAsand ASICsrdquo IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems vol 26 no 2 pp 203ndash215 2007

[6] E Monmasson and M N Cirstea ldquoFPGA design methodologyfor industrial control systems a reviewrdquo IEEE Transactions onIndustrial Electronics vol 54 no 4 pp 1824ndash1842 2007

[7] Z Fang J E Carletta and R J Veillette ldquoA methodology forFPGA-based control implementationrdquo IEEE Transactions onControl Systems Technology vol 13 no 6 pp 977ndash987 2005

[8] M-W Naouar E Monmasson A A Naassani I Slama-Belkhodja and N Patin ldquoFPGA-based current controllers forAC machine drives a reviewrdquo IEEE Transactions on IndustrialElectronics vol 54 no 4 pp 1907ndash1925 2007

[9] A Knop and FW Fuchs ldquoHigh frequency grid impedance anal-ysis with three-phase converter and FPGAbased tolerance bandcontrollerrdquo in Proceedings of the 6th International Conference-Workshop on Compatability and Power Electronics (CPE rsquo09) pp286ndash291 May 2009

[10] T Ostrem W Sulkowski L E Norum and C Wang ldquoGridconnected photovoltaic (PV) inverter with robust phase-lockedloop (PLL)rdquo in Proceedings of the IEEE PES Transmission andDistribution Conference and Exposition Latin America (TDCrsquo06) Caracas Venezuela August 2006

[11] Y-Y Tzou and H-J Hsu ldquoFPGA realization of space-vectorPWM control IC for three-phase PWM invertersrdquo IEEE Trans-actions on Power Electronics vol 12 no 6 pp 953ndash963 1997

[12] H Abu-Rub J Guzinski Z Krzeminski and H A ToliyatldquoPredictive current control of voltage-source invertersrdquo IEEE

Transactions on Industrial Electronics vol 51 no 3 pp 585ndash5932004

[13] M Hamouda H F Blanchette K Al-Haddad and F FnaiechldquoAn efficient DSP-FPGA-based real-time implementationmethod of SVM algorithms for an indirect matrix converterrdquoIEEE Transactions on Industrial Electronics vol 58 no 11 pp5024ndash5031 2011

[14] A M Omar and N A Rahim ldquoFPGA-based ASIC designof the three-phase synchronous PWM flyback converterrdquo IEEProceedings vol 150 no 3 pp 263ndash268 2003

[15] O Lopez J Alvarez J Doval-Gandoy et al ldquoComparison ofthe FPGA implementation of twomultilevel space vector PWMalgorithmsrdquo IEEE Transactions on Industrial Electronics vol 55no 4 pp 1537ndash1547 2008

[16] S Karimi P Poure and S Saadate ldquoFast power switch fail-ure detection for fault tolerant voltage source inverters usingFPGArdquo IET Power Electronics vol 2 no 4 pp 346ndash354 2009

[17] Z Salcic J Cao and S K Nguang ldquoA floating-point FPGA-based self-tuning regulatorrdquo IEEE Transactions on IndustrialElectronics vol 53 no 2 pp 693ndash704 2006

[18] C H Ho C W Yu P Leong W Luk and S J E WiltonldquoFloating-point FPGA Architecture and modelingrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol17 no 12 pp 1709ndash1718 2009

[19] D Menard and O Sentieys ldquoAutomatic evaluation of the accu-racy of fixed-point algorithmsrdquo in Proceedings of the IEEEACMConference on Design Automation and Test 2002

[20] R Andraka ldquoA survey of CORDIC algorithms for FPGA basedcomputersrdquo in Proceedings of the ACMSIGDA 6th InternationalSymposium on Field Programmable Gate Arrays (FPGA rsquo98) pp191ndash200 February 1998

[21] M S Padua S M Deckmann G S Sperandio F P Marafaoand D Colon ldquoComparative analysis of synchronization algo-rithms based on PLL RDFT and Kalman filterrdquo in Proceedingsof the IEEE International Symposium on Industrial Electronics(ISIE rsquo07) pp 964ndash970 June 2007

[22] V Kaura and V Blasko ldquoOperation of a phase locked loopsystemunder distorted utility conditionsrdquo IEEE Transactions onIndustry Applications vol 33 no 1 pp 58ndash63 1997

[23] S-K Chung ldquoPhase-locked loop for grid-connected three-phase power conversion systemsrdquo IEE Proceedings vol 147 no3 pp 213ndash219 2000

[24] J Bradshaw U Madawala and N Patel ldquoBit-stream implemen-tation of a phase-locked looprdquo IET Power Electronics vol 4 no1 pp 11ndash20 2011

[25] R Park ldquoTwo reaction theory of synchronous machinesrdquo AIEETransactions vol 48 no 4 pp 716ndash730 1929

[26] N Mohan T Undeland and W Robbins Power ElectronicsmdashConverters Applications and Design John Wiley amp Sons NewDehli India 5th edition 2007

[27] ldquoXilinx data bookrdquo 2006 httpwwwxilinxcom[28] D G Holmes and T A Lipo PulseWidthModulation for Power

Converters Principles and Practice IEEE Press 10th edition2003

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014


Active and Passive Electronic Components

Control Scienceand Engineering

Journal of



RotatingMachinery


Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design



Shock and Vibration


Civil EngineeringAdvances in

Acoustics and VibrationAdvances in



Electrical and Computer Engineering

Journal of

Advances inOptoElectronics


Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of


Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014


Chemical EngineeringInternational Journal of Antennas and

Propagation




Navigation and Observation



DistributedSensor Networks



functions and aD-type flip-flop that can handle for exampleregisters The CLBs are interconnected by a programmablewire network synchronized with a top level clock ModernFPGAs can also have extra inbuilt features such as dedicatedDSP-blocks that can handle complex computations in oneclock cycle Also external LUT blocks may be used asmemory

The use of FPGA technique within power electronicsis mostly seen where rapid inputoutput (IO) is requestedReviews of control system implementation in FPGA is foundin [6ndash8] Grid impedance analysis using FPGA are done in[9] An FPGA-based grid phase trackingmethod is describedin [10] and pulse-width modulation (PWM) implementa-tions for inverters are found in [11 12] A combination of DSPand FPGA for SVM-control of a matrix converter is usedin [13] and more FPGA-based SVPWM implementationscan be found in [14 15] FPGA-implementations for faultdetection in a VSI control is made in [16]

In this paper the control system of a grid-connectedCC-VSI has been designed and implemented on an FPGAThe control system includes phase tracking of the gridvoltage inverter logic output control active and reactivepower flow control high-speed burst logging and faultdetection Hardware implementations are discussed as wellas their limitations and the number of gates required forspecific functions are summarized The control system isimplemented on the FPGA-chip of a compactRIO moduleand the VHDL-code is generated by LabView G-code Thesystem allows for integration of a RT-controller if heavierdata analysis is required The practical viability of the systemis evaluated in an experimental setup with a grid-connectedVSI 30 kW at unity power factor is injected into the localelectric grid and the current-control loops are evaluated bymaking step responses in the active power flow

2 FPGA Programming

The initial step in FPGA design is to define the algorithmsused An algorithm can be characterized by its complexityand time constraints The accuracy of IO-variables is set bytheir bit sizes

Once this is done the possibility of reusing modulesin the system has to be explored By smart time sharingan algorithm may be put as a subroutine and routed toseveral different parts of the FPGAmodule Finally the samefunction may be expressed in different ways with the logicgates available The most gate-efficient algorithm should beused based on the available gate resources on the FPGAThere are various ways of implementing the VHDL-codeon the FPGA Many compilers offer the programmer towrite in a more user-friendly language which seldom isas efficient as direct VHDL-programming The conversioninto VHDL from another language will be a compromisebetween compilation time space optimization or clock cycleoptimization Below a few key functions are summarized

21 Integer Numbers The fundamental building blocks ofan FPGA are best utilized with integer maths operations

FXP (16 1) FXP (16 0)

2minus2

2minus4

2minus6

2minus8

+

+

+

Figure 1 Multiplication by the use of adders and decimal pointshifters

Floating-point (FP) operation is possible but provides poorutilization of the logic cells [17] If decimal points arerequired fixed-point numbers (FXP) are used instead A FXPis predefined by its bit length and the number of bits allocatedfor decimal accuracy and may be signed or unsigned Onedrawback of FXP compared with FP is that they rapidlygrow in size with the computations performed on them Caremust be taken to avoid saturation or overflow of a FXP Anevaluation of FXP precision is found in [18 19]

22 IntegerMultiplication While adding and subtracting arerather straightforward operationswith little space demand onthe FPGA multiplication is a big ldquogate-hogrdquo that should beavoided if possible However if the multiplication is fixedthis is not true if the multiplying factor is a multiple of 2Multiplication with 2119873may easily be replaced with a decimalpoint shift 119873 times to the left or right on the FXP Thisrequires no resources since it is only a matter of rerouting ofthe FXP between logic cells If the multiplying factor cannotbe approximated to a factor of 2 it may be simplified to a sumof fractions of 2 and then added For example the multiplier13 may be approximated as1

3asymp85

256=64 + 16 + 4 + 1

256=1

4+1

16+1

64+1

256(1)

which will give an error of about 04 Depending on theaccuracy required the number of fractions may be variedFigure 1 shows the implementation of this The resourceallocation for the proposed method compared to using anormal multiplication block is shown in Table 1 for imple-mentations on a Xilinx-5 chip Here the first method cansave approximately 2 of the dedicated DSP blocks on theFPGA Implementation of division should be converted intomultiplication instead as this will save lots of space

23 Integrals On the contrary to derivatives the integral ofa signal is very straightforward on the FPGA The integral of119881in(119905)may be approximated as a finite sum according to

int

119905

0

119881in (119905) d119905 asymp Δ119905 sdot119899

sum

119894=1

119881in (119905119894) (2)

where Δ119905 is the sampling time and is assumed constant hereBy using shift registers the cumulative value of the signal is


Δt

Vin

Set loop time

Shift register

intVindt+times












119867PLL (119904) =119870119875119904 + 119870119868

1199043119879119878+ 1199042+ 119870119875119904 + 119870119868

(3)

where 119870119875and 119870


119904is


119867PLL (119904) =119870119875119904 + 119870119868

1199042+ 119870119875119904 + 119870119868

(4)




119875 =

10038161003816100381610038161003816119881119892

10038161003816100381610038161003816

10038161003816100381610038161198811198941003816100381610038161003816

119883sin (120575)

119876 =

10038161003816100381610038161003816119881119892

10038161003816100381610038161003816

10038161003816100381610038161198811198941003816100381610038161003816

119883cos (120575) minus

10038161003816100381610038161003816119881119892

10038161003816100381610038161003816

2

119883

(5)





1198681198891199020= 119879 lowast 119868

119886119887119888 (6)


119879 = radic2

3(

cos (120579) cos(120579 minus 21205873) cos(120579 + 2120587

3)

sin (120579) sin(120579 minus 21205873) sin(120579 + 2120587

3)

1

radic2

1

radic2

1

radic2

) (7)


Vgabc120572120573

Vddq

120572120573

Km120579lowast sin


Vlowastd = 0

120596lowast

PLL

+PI120576+minus

1

s

120596FF


DCsource


SPWM

Control system

ilowastq

abc120572120573

120572120573

dq

120572120573

120572120573

abc

dq

ilowastd = 0

iq

Ig Vg

id

Vgrid

PI

PIPLL

PI+minus

+minus

+minus

sin(120579)cos(120579)

Vlowasta Vlowast

b Vlowastc

Vlowastdc

Vdc



119888is



119881119888= 119881lowast

119888119889sdot sin (120596119905) + 119881lowast

119888119902sdot cos (120596119905)

= 119898119886sin (120596119905 + 120575)

(8)

where 119881lowast119888119889

and 119881lowast119888119902


119886= radic(119881

lowast

119888119889)2+ (119881lowast

119888119902)2 and


119888119889) If 119898



1198811198941= 119898119886

119881DC

2radic2

(9)









(a) (b)












119879 = radic2

3(

cos (120579) cos(120579 minus 21205873) cos(120579 + 2120587

3)

sin (120579) sin(120579 minus 21205873) sin(120579 + 2120587

3)

) (10)


cos(120579)

Stop

Analogueinputs

Burst log

Overcurrent

FPGA

PLL

RTPC

Faultdetection

Writetofile



Digitaloutput

Sawtoothwave

Vabc

Iabc

abcdq

abcdq

Vd

idiq

ilowastq

ilowastd = 0

+minus

MAF

MAF

PI

PI

Vlowastcd

Vlowastcq

sin(120579) cos(120579)

sin(120579) cos(120579)

Ith

gt

gt

dqabc

Vlowastcd

Vlowastcq

Vc

Vc

+minus

+minus

PI

sin(120579)

Set Vlowastdc

Vdc




119881119889= radic2

3[119881119886cos (120579) + 119881119887 (minus

1

2cos (120579) +

radic3

2sin (120579))

+119881119888(minus1

2cos (120579) minus

radic3

2sin (120579))]

119881119902= radic2

3[119881119886sin (120579) + 119881119887 (minus

1

2sin (120579) minus

radic3

2cos (120579))

+119881119888(minus1

2sin (120579) +

radic3

2cos (120579))]

(11)













119891119904=119891FPGA2119873119905SPWM

(12)


Vq

120579

cos

Va

minus2minus1

minus2minus1

sin

Vc

Vd

Vbradic 23

radic3

2

times

times

times

times

times

times

times

times

times

times+

++

+

minus

minus


Vq

120579

cos

Va

sin

Vc

Vd

Vb radic 23

times

times

times times

times

times times

times

+

+

minus2120587

3

+2120587

3

sin

sin

cos

cos



119904is 35 kHz




119904= 488 kHz



and 119881119888119902














0 20 40 600

1

2

3

4

5

6

Time (ms)

Phas

e (ra

d)

PLLVg

(a)

0 20 40 600

5

4

3

2

1

6

Time (ms)

Phas

e (ra

d)

PLLVg

(b)



minus05

0

05

1

Time (120583s)


Volta

ge (V

)

(a)

0 5 10 15 20minus1

minus05

0

05

1

PLL

Time (ms)

Volta

ge (V

)

Vg

(b)





0 10 20 30 40 50 60minus100

minus50

0

50

100

Time (ms)

minus200

0

200

I LN

(A)

VLN

(V)

Ia Ib IcVa


0 100 200 300 400 500minus15

minus10

minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id









119889119902-


0 100 200 300 400 500minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id







119894| till 119876 again



8 Conclusions








References
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










Δt

Vin

Set loop time

Shift register

intVindt+times












119867PLL (119904) =119870119875119904 + 119870119868

1199043119879119878+ 1199042+ 119870119875119904 + 119870119868

(3)

where 119870119875and 119870


119904is


119867PLL (119904) =119870119875119904 + 119870119868

1199042+ 119870119875119904 + 119870119868

(4)




119875 =

10038161003816100381610038161003816119881119892

10038161003816100381610038161003816

10038161003816100381610038161198811198941003816100381610038161003816

119883sin (120575)

119876 =

10038161003816100381610038161003816119881119892

10038161003816100381610038161003816

10038161003816100381610038161198811198941003816100381610038161003816

119883cos (120575) minus

10038161003816100381610038161003816119881119892

10038161003816100381610038161003816

2

119883

(5)





1198681198891199020= 119879 lowast 119868

119886119887119888 (6)


119879 = radic2

3(

cos (120579) cos(120579 minus 21205873) cos(120579 + 2120587

3)

sin (120579) sin(120579 minus 21205873) sin(120579 + 2120587

3)

1

radic2

1

radic2

1

radic2

) (7)


Vgabc120572120573

Vddq

120572120573

Km120579lowast sin


Vlowastd = 0

120596lowast

PLL

+PI120576+minus

1

s

120596FF


DCsource


SPWM

Control system

ilowastq

abc120572120573

120572120573

dq

120572120573

120572120573

abc

dq

ilowastd = 0

iq

Ig Vg

id

Vgrid

PI

PIPLL

PI+minus

+minus

+minus

sin(120579)cos(120579)

Vlowasta Vlowast

b Vlowastc

Vlowastdc

Vdc



119888is



119881119888= 119881lowast

119888119889sdot sin (120596119905) + 119881lowast

119888119902sdot cos (120596119905)

= 119898119886sin (120596119905 + 120575)

(8)

where 119881lowast119888119889

and 119881lowast119888119902


119886= radic(119881

lowast

119888119889)2+ (119881lowast

119888119902)2 and


119888119889) If 119898



1198811198941= 119898119886

119881DC

2radic2

(9)









(a) (b)












119879 = radic2

3(

cos (120579) cos(120579 minus 21205873) cos(120579 + 2120587

3)

sin (120579) sin(120579 minus 21205873) sin(120579 + 2120587

3)

) (10)


cos(120579)

Stop

Analogueinputs

Burst log

Overcurrent

FPGA

PLL

RTPC

Faultdetection

Writetofile



Digitaloutput

Sawtoothwave

Vabc

Iabc

abcdq

abcdq

Vd

idiq

ilowastq

ilowastd = 0

+minus

MAF

MAF

PI

PI

Vlowastcd

Vlowastcq

sin(120579) cos(120579)

sin(120579) cos(120579)

Ith

gt

gt

dqabc

Vlowastcd

Vlowastcq

Vc

Vc

+minus

+minus

PI

sin(120579)

Set Vlowastdc

Vdc




119881119889= radic2

3[119881119886cos (120579) + 119881119887 (minus

1

2cos (120579) +

radic3

2sin (120579))

+119881119888(minus1

2cos (120579) minus

radic3

2sin (120579))]

119881119902= radic2

3[119881119886sin (120579) + 119881119887 (minus

1

2sin (120579) minus

radic3

2cos (120579))

+119881119888(minus1

2sin (120579) +

radic3

2cos (120579))]

(11)













119891119904=119891FPGA2119873119905SPWM

(12)


Vq

120579

cos

Va

minus2minus1

minus2minus1

sin

Vc

Vd

Vbradic 23

radic3

2

times

times

times

times

times

times

times

times

times

times+

++

+

minus

minus


Vq

120579

cos

Va

sin

Vc

Vd

Vb radic 23

times

times

times times

times

times times

times

+

+

minus2120587

3

+2120587

3

sin

sin

cos

cos



119904is 35 kHz




119904= 488 kHz



and 119881119888119902














0 20 40 600

1

2

3

4

5

6

Time (ms)

Phas

e (ra

d)

PLLVg

(a)

0 20 40 600

5

4

3

2

1

6

Time (ms)

Phas

e (ra

d)

PLLVg

(b)



minus05

0

05

1

Time (120583s)


Volta

ge (V

)

(a)

0 5 10 15 20minus1

minus05

0

05

1

PLL

Time (ms)

Volta

ge (V

)

Vg

(b)





0 10 20 30 40 50 60minus100

minus50

0

50

100

Time (ms)

minus200

0

200

I LN

(A)

VLN

(V)

Ia Ib IcVa


0 100 200 300 400 500minus15

minus10

minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id









119889119902-


0 100 200 300 400 500minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id







119894| till 119876 again



8 Conclusions








References
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










Vgabc120572120573

Vddq

120572120573

Km120579lowast sin


Vlowastd = 0

120596lowast

PLL

+PI120576+minus

1

s

120596FF


DCsource


SPWM

Control system

ilowastq

abc120572120573

120572120573

dq

120572120573

120572120573

abc

dq

ilowastd = 0

iq

Ig Vg

id

Vgrid

PI

PIPLL

PI+minus

+minus

+minus

sin(120579)cos(120579)

Vlowasta Vlowast

b Vlowastc

Vlowastdc

Vdc



119888is



119881119888= 119881lowast

119888119889sdot sin (120596119905) + 119881lowast

119888119902sdot cos (120596119905)

= 119898119886sin (120596119905 + 120575)

(8)

where 119881lowast119888119889

and 119881lowast119888119902


119886= radic(119881

lowast

119888119889)2+ (119881lowast

119888119902)2 and


119888119889) If 119898



1198811198941= 119898119886

119881DC

2radic2

(9)









(a) (b)












119879 = radic2

3(

cos (120579) cos(120579 minus 21205873) cos(120579 + 2120587

3)

sin (120579) sin(120579 minus 21205873) sin(120579 + 2120587

3)

) (10)


cos(120579)

Stop

Analogueinputs

Burst log

Overcurrent

FPGA

PLL

RTPC

Faultdetection

Writetofile



Digitaloutput

Sawtoothwave

Vabc

Iabc

abcdq

abcdq

Vd

idiq

ilowastq

ilowastd = 0

+minus

MAF

MAF

PI

PI

Vlowastcd

Vlowastcq

sin(120579) cos(120579)

sin(120579) cos(120579)

Ith

gt

gt

dqabc

Vlowastcd

Vlowastcq

Vc

Vc

+minus

+minus

PI

sin(120579)

Set Vlowastdc

Vdc




119881119889= radic2

3[119881119886cos (120579) + 119881119887 (minus

1

2cos (120579) +

radic3

2sin (120579))

+119881119888(minus1

2cos (120579) minus

radic3

2sin (120579))]

119881119902= radic2

3[119881119886sin (120579) + 119881119887 (minus

1

2sin (120579) minus

radic3

2cos (120579))

+119881119888(minus1

2sin (120579) +

radic3

2cos (120579))]

(11)













119891119904=119891FPGA2119873119905SPWM

(12)


Vq

120579

cos

Va

minus2minus1

minus2minus1

sin

Vc

Vd

Vbradic 23

radic3

2

times

times

times

times

times

times

times

times

times

times+

++

+

minus

minus


Vq

120579

cos

Va

sin

Vc

Vd

Vb radic 23

times

times

times times

times

times times

times

+

+

minus2120587

3

+2120587

3

sin

sin

cos

cos



119904is 35 kHz




119904= 488 kHz



and 119881119888119902














0 20 40 600

1

2

3

4

5

6

Time (ms)

Phas

e (ra

d)

PLLVg

(a)

0 20 40 600

5

4

3

2

1

6

Time (ms)

Phas

e (ra

d)

PLLVg

(b)



minus05

0

05

1

Time (120583s)


Volta

ge (V

)

(a)

0 5 10 15 20minus1

minus05

0

05

1

PLL

Time (ms)

Volta

ge (V

)

Vg

(b)





0 10 20 30 40 50 60minus100

minus50

0

50

100

Time (ms)

minus200

0

200

I LN

(A)

VLN

(V)

Ia Ib IcVa


0 100 200 300 400 500minus15

minus10

minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id









119889119902-


0 100 200 300 400 500minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id







119894| till 119876 again



8 Conclusions








References
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










(a) (b)












119879 = radic2

3(

cos (120579) cos(120579 minus 21205873) cos(120579 + 2120587

3)

sin (120579) sin(120579 minus 21205873) sin(120579 + 2120587

3)

) (10)


cos(120579)

Stop

Analogueinputs

Burst log

Overcurrent

FPGA

PLL

RTPC

Faultdetection

Writetofile



Digitaloutput

Sawtoothwave

Vabc

Iabc

abcdq

abcdq

Vd

idiq

ilowastq

ilowastd = 0

+minus

MAF

MAF

PI

PI

Vlowastcd

Vlowastcq

sin(120579) cos(120579)

sin(120579) cos(120579)

Ith

gt

gt

dqabc

Vlowastcd

Vlowastcq

Vc

Vc

+minus

+minus

PI

sin(120579)

Set Vlowastdc

Vdc




119881119889= radic2

3[119881119886cos (120579) + 119881119887 (minus

1

2cos (120579) +

radic3

2sin (120579))

+119881119888(minus1

2cos (120579) minus

radic3

2sin (120579))]

119881119902= radic2

3[119881119886sin (120579) + 119881119887 (minus

1

2sin (120579) minus

radic3

2cos (120579))

+119881119888(minus1

2sin (120579) +

radic3

2cos (120579))]

(11)













119891119904=119891FPGA2119873119905SPWM

(12)


Vq

120579

cos

Va

minus2minus1

minus2minus1

sin

Vc

Vd

Vbradic 23

radic3

2

times

times

times

times

times

times

times

times

times

times+

++

+

minus

minus


Vq

120579

cos

Va

sin

Vc

Vd

Vb radic 23

times

times

times times

times

times times

times

+

+

minus2120587

3

+2120587

3

sin

sin

cos

cos



119904is 35 kHz




119904= 488 kHz



and 119881119888119902














0 20 40 600

1

2

3

4

5

6

Time (ms)

Phas

e (ra

d)

PLLVg

(a)

0 20 40 600

5

4

3

2

1

6

Time (ms)

Phas

e (ra

d)

PLLVg

(b)



minus05

0

05

1

Time (120583s)


Volta

ge (V

)

(a)

0 5 10 15 20minus1

minus05

0

05

1

PLL

Time (ms)

Volta

ge (V

)

Vg

(b)





0 10 20 30 40 50 60minus100

minus50

0

50

100

Time (ms)

minus200

0

200

I LN

(A)

VLN

(V)

Ia Ib IcVa


0 100 200 300 400 500minus15

minus10

minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id









119889119902-


0 100 200 300 400 500minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id







119894| till 119876 again



8 Conclusions








References
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










cos(120579)

Stop

Analogueinputs

Burst log

Overcurrent

FPGA

PLL

RTPC

Faultdetection

Writetofile



Digitaloutput

Sawtoothwave

Vabc

Iabc

abcdq

abcdq

Vd

idiq

ilowastq

ilowastd = 0

+minus

MAF

MAF

PI

PI

Vlowastcd

Vlowastcq

sin(120579) cos(120579)

sin(120579) cos(120579)

Ith

gt

gt

dqabc

Vlowastcd

Vlowastcq

Vc

Vc

+minus

+minus

PI

sin(120579)

Set Vlowastdc

Vdc




119881119889= radic2

3[119881119886cos (120579) + 119881119887 (minus

1

2cos (120579) +

radic3

2sin (120579))

+119881119888(minus1

2cos (120579) minus

radic3

2sin (120579))]

119881119902= radic2

3[119881119886sin (120579) + 119881119887 (minus

1

2sin (120579) minus

radic3

2cos (120579))

+119881119888(minus1

2sin (120579) +

radic3

2cos (120579))]

(11)













119891119904=119891FPGA2119873119905SPWM

(12)


Vq

120579

cos

Va

minus2minus1

minus2minus1

sin

Vc

Vd

Vbradic 23

radic3

2

times

times

times

times

times

times

times

times

times

times+

++

+

minus

minus


Vq

120579

cos

Va

sin

Vc

Vd

Vb radic 23

times

times

times times

times

times times

times

+

+

minus2120587

3

+2120587

3

sin

sin

cos

cos



119904is 35 kHz




119904= 488 kHz



and 119881119888119902














0 20 40 600

1

2

3

4

5

6

Time (ms)

Phas

e (ra

d)

PLLVg

(a)

0 20 40 600

5

4

3

2

1

6

Time (ms)

Phas

e (ra

d)

PLLVg

(b)



minus05

0

05

1

Time (120583s)


Volta

ge (V

)

(a)

0 5 10 15 20minus1

minus05

0

05

1

PLL

Time (ms)

Volta

ge (V

)

Vg

(b)





0 10 20 30 40 50 60minus100

minus50

0

50

100

Time (ms)

minus200

0

200

I LN

(A)

VLN

(V)

Ia Ib IcVa


0 100 200 300 400 500minus15

minus10

minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id









119889119902-


0 100 200 300 400 500minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id







119894| till 119876 again



8 Conclusions








References
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










Vq

120579

cos

Va

minus2minus1

minus2minus1

sin

Vc

Vd

Vbradic 23

radic3

2

times

times

times

times

times

times

times

times

times

times+

++

+

minus

minus


Vq

120579

cos

Va

sin

Vc

Vd

Vb radic 23

times

times

times times

times

times times

times

+

+

minus2120587

3

+2120587

3

sin

sin

cos

cos



119904is 35 kHz




119904= 488 kHz



and 119881119888119902














0 20 40 600

1

2

3

4

5

6

Time (ms)

Phas

e (ra

d)

PLLVg

(a)

0 20 40 600

5

4

3

2

1

6

Time (ms)

Phas

e (ra

d)

PLLVg

(b)



minus05

0

05

1

Time (120583s)


Volta

ge (V

)

(a)

0 5 10 15 20minus1

minus05

0

05

1

PLL

Time (ms)

Volta

ge (V

)

Vg

(b)





0 10 20 30 40 50 60minus100

minus50

0

50

100

Time (ms)

minus200

0

200

I LN

(A)

VLN

(V)

Ia Ib IcVa


0 100 200 300 400 500minus15

minus10

minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id









119889119902-


0 100 200 300 400 500minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id







119894| till 119876 again



8 Conclusions








References
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










0 20 40 600

1

2

3

4

5

6

Time (ms)

Phas

e (ra

d)

PLLVg

(a)

0 20 40 600

5

4

3

2

1

6

Time (ms)

Phas

e (ra

d)

PLLVg

(b)



minus05

0

05

1

Time (120583s)


Volta

ge (V

)

(a)

0 5 10 15 20minus1

minus05

0

05

1

PLL

Time (ms)

Volta

ge (V

)

Vg

(b)





0 10 20 30 40 50 60minus100

minus50

0

50

100

Time (ms)

minus200

0

200

I LN

(A)

VLN

(V)

Ia Ib IcVa


0 100 200 300 400 500minus15

minus10

minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id









119889119902-


0 100 200 300 400 500minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id







119894| till 119876 again



8 Conclusions








References
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










0 10 20 30 40 50 60minus100

minus50

0

50

100

Time (ms)

minus200

0

200

I LN

(A)

VLN

(V)

Ia Ib IcVa


0 100 200 300 400 500minus15

minus10

minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id









119889119902-


0 100 200 300 400 500minus5

0

5

10

15

20

Time (ms)

I dq

(A)

Iq

Id







119894| till 119876 again



8 Conclusions








References
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation














References
































RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









Documents

Research Article FPGA Control Implementation of a Grid …downloads.hindawi.com/journals/jcse/2013/713293.pdf · 2019-07-31 · e practical viability of the system is evaluated in