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Resistance and passivation of metal contacts using n-types amorphous Si for Si solar cells
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Resistance and passivation of metal contacts using n-type amorphousSi for Si solar cells
Riet Labie,1 Twan Bearda,1 Ounsi El Daif,1 Barry O’Sullivan,1 Kris Baert,2 and Ivan Gordon1
1IMEC, Kapeldreef 75, Leuven 3001, Belgium2Katholieke Universiteit Leuven, Kasteelpark Arenberg 10, Leuven 3001, Belgium
(Received 23 October 2013; accepted 28 April 2014; published online 13 May 2014)
A low fill factor remains one of the critical issues for successful implementation of amorphous Si
layers in back-contact solar cells. In this work, the metal-phosphorous doped hydrogenated
amorphous silicon (a-Si:H) contact is studied in terms of contact resistance while maintaining a
high passivation level of the crystalline silicon bulk material after metal deposition and during
long-term solar cell operation. On top of these contacting and passivation-preservation
requirements, the metal back-surface reflection has to be large in order to reflect as much light as
possible to generate high output current densities. Two different contact metals, Al and Ti, with Ti
being combined in a stack with either Al, Pd/Ag or Cu, are investigated. For these two metals with
comparable metal work function, the material choice shows only a minimal effect on the contact
resistance value. The main parameters for obtaining a low-resistive, ohmic contact lie in the tuning
of the nþ a-Si:H layer thickness and the application of a thermal annealing step. Contact resistance
values down to 10 mX cm2 are obtained on an intrinsic/nþ a-Si:H layer stack with a remaining
effective lifetime of several milliseconds after metallization and anneal. It is shown that a thin Ti
(5 nm) layer is needed in order to obtain a thermally stable contact that guarantees a reliable
long-term solar cell operation. The optical disadvantage of having Ti at the backside of a Si solar
cell can be compensated by combining this very thin Ti layer with Cu. This results in an
improvement of the back-reflectance compared to a direct Al contact. VC 2014 AIP Publishing LLC.
[http://dx.doi.org/10.1063/1.4875635]
I. INTRODUCTION
The advantages of using amorphous Si (a-Si) for crystal-
line silicon (c-Si) solar cell applications have been discussed
repeatedly.1–3 The excellent passivation quality of a-Si leads
to extremely low values of the surface recombination veloc-
ity which are mandatory to realize ultimate efficiencies for
thin c-Si cells. Furthermore, its larger bandgap (compared to
c-Si) increases the open-circuit voltage (Voc). Apart from
these beneficial intrinsic material properties, a-Si can be de-
posited at low temperature which avoids any degradation of
the c-Si bulk minority carrier lifetime. Another more practi-
cal and process oriented advantage of this low temperature
formation of the doped electrode contacts is the compatibil-
ity with substrates and structures with limited temperature
stability.
At IMEC, a-Si layers are integrated in hybrid back-
contact solar cells for which part of the back-contact process-
ing is performed on module level when the Si cells are glued
to the front glass substrate with silicones. The process flow
of this novel module concept is described in more detail in
previous publications.4,5 In short, thin n-doped wafers with
front side texturing and ARC (anti-reflective coating) layers,
and at the back a blanket B-diffused c-Si emitter are bonded
to glass by a silicone layer. Patterning of the emitter, deposi-
tion, and patterning of the i/nþ a-Si BSF (back-surface-field)
contact and metallization are all performed on module level
when semi-processed cells are attached to the glass front
sheet. A schematic build-up of this novel module approach is
shown in Figure 1. This process flow has several benefits
like reducing the wafer handling that facilitates the future
use of thinner wafers, processing of multiple cells in one
step, and the potential for combining module and cell metal-
lization steps.
It is known to be difficult to form an ohmic contact on
amorphous-Si layers.6 According to Kanicki,6,7 it is mainly
the effective doping concentration Neff that has to be greater
than 1021 at/cm3 in order to achieve an ohmic contact. This
reflects in high series resistance values and relatively low fill
factor (FF) values for Si hetero-junction (SHJ) solar cells in
general and is even more restrictive for back-contact struc-
tures. While a full cell area contact with TCO (Transparent
Conductive Oxide) layers is usually applied for standard SHJ
cells with 2-sided electrode contacts, this is no longer possi-
ble for back-contact structures. The reduced contacting area
leads to a larger contribution of the contact resistance to the
total cells series resistance. In their overview paper, De Wolf
et al.3 list the best SHJ cells ever reported with a maximum
FF of 80.9 for 2-sided contacted cells while only 77.4 is
obtained for their back-contact counterpart.
In this work, the impact of the a-Si layer build-up (Sec.
III A) as well as the annealing conditions on the resulting
contact resistivity are investigated. In view of the limited
thermal stability of the amorphous Si, careful control of the
thermal budget is needed in order to maintain the wafer pas-
sivation properties which are discussed in Secs. III B and
III D. The metal work function and therefore the choice of
contact metal have only a minimal impact on the contact
0021-8979/2014/115(18)/183508/8/$30.00 VC 2014 AIP Publishing LLC115, 183508-1
JOURNAL OF APPLIED PHYSICS 115, 183508 (2014)
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resistance. Especially for commonly used solar cell contact
materials like Ti, Al, or Ag, only minor improvements are
expected by moving to lower work function metals (Sec.
III C). The generally applied TCO layers for SHJ cells are
not investigated in this work since transparent contacting
layers are not strictly needed for back-contact cells. Apart
from a low-ohmic contact, an additional requirement for the
solar cell backside metallization is the low light absorption
and high reflectance in order to absorb as much light as pos-
sible in the thin Si cell. Al is known to be a better back-
reflector compared to Ti-based contacts8,9 and is therefore
often a preferred candidate for contacting back-contact solar
cells. Finally, the optical properties of the different metal
stacks are discussed in Sec. III E.
II. EXPERIMENTAL
Both Al and Ti are investigated as contact metals. In view
of the poor conductivity of Ti, this layer is combined with a
stack of metals in order to obtain a minimal finger resistivity.
The following stacks are used in this work: Ti(50 nm)/Pd/Ag,
Ti(5 nm)/Al, and Ti(5–30 nm)/Cu. The hydrogenated intrinsic
and doped a-Si (i/nþ a-Si:H) layers are deposited by a
plasma-enhanced chemical vapour deposition (PECVD) sys-
tem on n-type c-Si substrates. The intrinsic (i a-Si:H) layer is
deposited first to passivate the c-Si substrate. The gas flow
(SiH4: PH3: H2) is subsequently adapted in order to reach a
heavily doped nþ layer with an elemental P-concentration
level of 2.1021 at/cm3 (measured by SIMS; the effective dop-
ing concentration is not measured in this work). A layer
resistivity around 300 X cm is measured by a four-point-probe
method for a 50 nm thick a-Si stack deposited on silicon oxide.
This result is at the lower end of the reported a-Si resistivity
values and close to the micro-crystalline layer resistivity
(<100 X cm).6
A Transmission Electron Microscopy (TEM) inspection
is performed in order to confirm the layer structure as well as
the layer thickness. While ellipsometry measurements give
an indication of the total stack thickness (for single layer fit-
ting), an HAADF-STEM (high angle annular dark field–
scanning transmission electron microscopy) image based on
hZi2 contrast distinguishes both layers. Such a cross-section
is shown in Figure 2(a), indicating approximate i/nþ a-Si:H
layer thicknesses of, respectively, 5 and 20 nm. A rough
c-Si/i a-Si:H interface is observed that is likely due to epitax-
ial growth at the beginning of the deposition. A local
zoom-in of this interface is shown in Figure 2(b) and will be
further discussed in Sec. III B.
Various contact resistance test structures, as described by
Schroder,10 are prepared and compared: (C)TLM ((Circular)
Transfer Length Method), Kelvin four-point-structures and
two-terminal vertical test structures. These structures are
defined by photolithography and metal patterning is per-
formed by wet chemical etching or by lift-off (for Ti/Pd/Ag).
FIG. 1. Schematic cross-section of Imec’s i2-module concept for hybrid
back-contact solar cells (with c-Si emitter and a-Si BSF). Structure not
drawn to scale. Structure after bonding to quartz substrate with silicones (a)
and after full processing (b).
FIG. 2. HAADF-STEM cross-section of c-Si/ i/nþ a-Si:H/ Al stack, indicat-
ing thicknesses [nm] of i and nþ a-Si layers (a). Zoom-in of c-Si/a-Si inter-
face, after deposition (b) and after a thermal treatment of 30 min at 120 �C(c). Areas of suspected nano-crystallinity are highlighted by circles.
183508-2 Labie et al. J. Appl. Phys. 115, 183508 (2014)
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In view of process simplicity and measurement accuracy, all
of the experiments reported in following paragraphs are per-
formed on CTLM test structures.11 The a-Si:H is deposited
on the Si substrate without any isolating layer in between.
Due to the high resistivity and limited thickness of the a-Si
layer, such a non-isolating structure is preferred in order to be
able to apply a measurement current density comparable to
the expected cell output current density (a 40 mA/cm2 cell
output corresponds to 142 mA/cm2 BSF electrode contact
current density for 28% BSF/cell area coverage). Most of the
current will flow vertically through the a-Si stack and then
travel through the substrate. The measured contact resistance
is therefore the sum of the metal/a-Si contact, the resistance
of the a-Si stack as well as the contact to the bare Si substrate.
For solar cell applications this sum is the value that contrib-
utes to the total series resistance and therefore most relevant
to know. A schematic cross-section and top view of the test
structure is given in Figure 3(b). Various CTLM dimensions
are used for deriving the contact resistivity qc. This is done
by fitting the corrected resistance values as function of the
spacing and deriving the transfer length LT (Figure 3(a)).
Although they differ widely in obtained Rsheet, they all con-
verge to similar qc values. The significantly variable Rsheet
(that is derived from the slope) is expected to be caused by a
different effective current path and corresponding Si penetra-
tion depth contributing to the Rsheet that is depending on the
spacing width. For larger metal-to-metal gaps, a larger frac-
tion of the Si substrate will contribute to the current conduc-
tion and therefore the Rsheet value will converge to the Rsheet
of the used Si substrate (200 X/�).
The passivation quality of the non-metalized i/nþ a-Si:
H stack is qualified by QSSPC (quasi-steady-state-photo-
conductance) measurements on n-FZ wafers with double
sided i/nþ a-Si passivation layers. The impact of metalliza-
tion on the effective lifetime is investigated by calibrated
photo-luminescence (PL) by a BT imaging tool.
III. RESULTS AND DISCUSSION
A. Variations in the a-Si:H layer stack
An intrinsic a-Si:H layer is needed to passivate the c-Si
substrate. In absence of this layer, the effective lifetime
(measured by QSSPC) is reduced from several milliseconds
down to a lifetime well below 1 ms. The i-layer thickness is
fixed at approximately 5 nm, while the deposition time of the
P-doped nþ a-Si:H layer is varied over 20, 40, 60, 120, 180,
and 240 s. The TEM cross-section shown earlier (Figure 2)
corresponds to a deposition time of 120 s (resulting in about
20 nm). The layer thicknesses for the other deposition times
can be deduced by assuming a constant growth rate
(�10 nm/min). This batch of samples is metalized with a 1
lm Al layer, deposited by e-beam evaporation, and CTLM
measurements are performed. A strong effect of the nþ layer
thickness is observed: a low-ohmic contact resistance of
0.2–0.1 X cm2 is obtained for doped layer thicknesses of
10 nm and above while a higher ohmic value is obtained for
a thinner layer with expected thickness of 7 nm and a
non-ohmic contact is obtained for even thinner layers. The
different qc values for the various deposition times are
shown in Figure 4. The reported values are the average of 3
measurements. The measured variations for deposition times
above 60 s are expected to fall within the measurement error
and sample-to-sample variation. For the specific case of
120 s, more than 6 different samples are prepared and meas-
ured, with an average resistivity value of 0.09 X cm2, a
standard deviation of 0.04 and minimum and maximum
values of 0.04 and 0.14 X cm2, respectively. Although one
could intuitively expect larger values for thicker a-Si layers,
the contribution of the additional nþ a-Si thickness to the
total resistance (qnþ a-Si. t / Ac) is negligible compared to the
measured combined contact resistance. For thinner layers,
the high-ohmic to non-ohmic contact could be explained by
FIG. 3. CTLM-fitting for different di-
mensional test structures (a). Schematic
cross-section and top view 9 (b).
FIG. 4. Contact resistivity for various deposition times of the nþ a-Si:H
layer with a fixed 5 nm i a-Si layer. Values obtained after an annealing step
(30 min at 120 �C) are added for some layer thicknesses by the hatched area.
183508-3 Labie et al. J. Appl. Phys. 115, 183508 (2014)
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the need for a required minimal a-Si layer thickness that is
larger than the depletion region, as suggested earlier by
Schade and Smith.12
In a second phase, the deposition conditions of the i-
layer are modified by adding small amounts of PH3 to the
gas flow creating a minor doped layer. With this doping, a
substrate lifetime of still more than 1 ms could be obtained.
However, it did not show any added value for lowering the
contact resistance as similar values in the order of 0.1 X cm2
are measured.
At last, the contact surface is modified by adding a micro-
crystalline layer on top of the i/nþ a-Si:H stack, since lower
contact resistance values have been reported on such
layers.13,14 These lower values are confirmed on samples with
such a single micro-crystalline layer deposited immediately
on top of the bare c-Si substrate (without intrinsic layer).
Values as low as 2.10�5 X cm2 are then measured. However,
when adding this layer to the i/nþ stack, similar values as
obtained for samples without the top micro-crystalline layer
are measured. This indicates that the contact resistance is
dominated by the nþ a-Si/ i a-Si/ c-Si interfaces in which the
i-layer acts as a barrier layer between the Al/nþ a-Si contact
and the (lowly doped) n-type substrate. Due to the limited
bandgap difference between i a-Si and c-Si, conduction can
occur through this 5 nm thick i a-Si barrier layer.
B. Impact of thermal annealing
For standard c-Si contacts, a sintering step is performed
in order to obtain inter-diffusion, surface “cleaning” and/or
to form silicides which leads to a further lowering of the con-
tact resistance.15 In view of the limited thermal stability of
amorphous Si, this cannot be performed on a-Si layers. On
top of this, a phenomenon known as “metal induced crystal-
lization” exists that facilitates the crystallization of a-Si by
metal inter-diffusion. Especially Al is known for such behav-
ior.16 For reasons that will be further explained in Sec. III D
on the thermal reliability of the metal/a-Si contacts, it has
been decided to limit the temperature of a contact annealing
step to 120 �C in order to maintain a reasonable passivation
level for device purposes. Despite this fairly low tempera-
ture, a tremendous reduction of almost one order of magni-
tude, down to 0.04–0.01 X cm2 is measured for the contact
resistances on the 10, 20, and 30 nm thick i/nþ a-Si samples
(Figure 4). Such an improvement could not be achieved for
the non-ohmic contact indicating that thermal modifications
are not sufficient for extremely thin doping layers. The rea-
son for this strong reduction for the ohmic samples is not yet
fully understood. For standard c-Si metal contacts, an
annealing step can lead to a reduction of the Si/metal surface
oxide.17 TEM-EDX/EELS (Energy Dispersive X-ray
analysis/Electron Energy Loss Spectroscopy) inspection of
the a-Si/Al interface showed the presence of O at the inter-
face between a-Si and Al. Due to the limited thickness of the
affected region as well as Ga accumulation at this interface
due to the FIB-TEM sample preparation, it could not be veri-
fied whether the oxygen was bonded to Si or to Al or more
importantly, whether this bonding-site changed after anneal.
An interfacial oxide-exchange from Si to Al could therefore
not be confirmed. Anyway, minor impact on the contact re-
sistance is expected since it is dominated by the intrinsic bar-
rier layer as mentioned earlier in Sec. III A. Another
possibility could be the structural changes of the a-Si layer.
It is observed that the layer resistivity of the a-Si stack is fur-
ther reduced from 300 down to 100 X cm after the contact
annealing step of 30 min at 120 �C. This improved conduc-
tivity could be explained by an increased activation of the
dopants but is again expected to have a negligible contribu-
tion to the contact resistance considering the thin doping
layers. Furthermore, an increased crystallinity of the amor-
phous phase could also facilitate the conduction mechanism
by lowering the effective barrier height. In the (larger magni-
fication) TEM cross-sections shown earlier in Figures 2(b)
and 2(c) some small, suspected nano-crystalline areas can be
observed for both the annealed and non-annealed structure.
Due to the localized inspection inherent to TEM, there is no
quantitative information available regarding the amount and
size of these crystallites, and therefore, it is not possible to
conclude whether there is indeed an increase in crystallinity
after annealing. However, the beneficial impact of such
structural (thermal) modifications is expected to cause simi-
lar contact resistance improvements independent of the (Al)
metallization technique that is applied. For thermal evapora-
tion, this is not observed in this work what will be further
discussed in the following paragraph.
C. Variations in metallization type and method
The experiments of Secs. III A and III B are all obtained
by using e-beam evaporated Al as contact metal. In this part,
different metallization types and techniques are investigated:
e-beam evaporation of Ti/Pd/Ag and Ti/Al and thermal evap-
oration of Al and Ti/Cu. The results for the contact resistance
for the different metal stacks (both after deposition as well as
after the contact anneal step at 120 �C) are shown in Table I.
They all converge to similar values of 0.03–0.01 X cm2 after
the thermal treatment. For thermal evaporation, however, in-
dependent of the chosen contact metal, low contact values
are already obtained as deposited. A subsequent annealing
step that was shown to be beneficial for the e-beam evapo-
rated Al has only limited to no effect on the final contact re-
sistance. Thermal evaporation could lead to a higher
deposition temperature which could give rise to a beneficial
in-situ annealing. Another noticeable difference with thermal
evaporation is the absence of damage after metallization.
TABLE I. Contact resistivity values for various materials and deposition
methods.
Metal Contact resistivity [X cm2]
Type Deposition method As deposited After 30 min @ 120 �C
Al E-beam 0.12 0.02
Thermal evap. 0.02 0.01
Ti/Pd/Ag E-beam 0.03 0.01
Ti (5 nm)/Cu Thermal evap. 0.02 0.01
Ti/Al E-beam 0.11 0.03
183508-4 Labie et al. J. Appl. Phys. 115, 183508 (2014)
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The effect of the deposition method on the remaining
passivation quality is measured by PL (photo-luminescence)
on double sided i/nþ (5/20 nm) a-Si:H passivated n-FZ
wafers that are partially metallized on one side. Calibrated
PL measurements are executed for which the lifetime is
monitored by QSSPC in the non-metalized region, and this
result is used for calibrating the flux of emitted photons for
the (single-sided) metalized area. A schematic drawing of
the measurement procedure is shown in Figure 5(a). A cali-
brated PL image for an e-beam evaporated Al metallization
is shown in Figure 5(b) showing a small reduction compared
to the non-metalized area. A difference in back-reflectance
by the presence of a metal layer that may have an impact on
the generated carriers and their radiative recombination is
not taken into account. While this may be important for a
quantitative lifetime calibration, it is not for a qualitative,
relative comparison. Thermal evaporation shows no degrada-
tion of the passivation quality. For e-beam, a better resist-
ance to metallization damage was obtained for thicker layers
by increasing the doped layer thickness from 10 to 20 and
even 30 nm. In general, it is known that e-beam deposition
induces passivation degradation. This finding has been con-
firmed in other work by capacitance-voltage analysis techni-
ques.18 It confirms e-beam passivation degradation by Si
dangling bond defects at the c-Si/a-Si interface and in the
a-Si (bulk) passivation layer while this is not observed for
thermal evaporation. The surface state defects density QSS
leads to an increase of the ideal barrier height by Eq. (1) as
given by Sze.19 With the following terms defined before the
metal//semiconductor (in this case the Al/nþ/i a-Si // n-type
c-Si) interface is formed and therefore independent of the
deposition technique: D/ (Schottky barrier lowering), /o
(Energy level at surface) and Eg (semi-conductor bandgap),
and with Ds (acceptor surface states) a constant value up to
the Fermi-level. An increase of the surface state defects QSS
(as seen for e-beam metallized samples) increases therefore
the barrier height which on its turns leads to an increased
contact resistivity
q:ub ¼QSS
q:DSþ Eg � quo � Du: (1)
Barrier height measurements, either before or after
anneal, were not performed in this work. The contact anneal
step (30 min at 120 �C) was also applied on the double-sided
passivated samples and PL measurements showed no change
in lifetime values for the non-effected thermal evaporated
sample while a slight improvement of the lifetime value was
measured for the e-beam sample (with the thinner a-Si
layer). It is therefore believed that this thermal treatment
resulted in a reduction of the surface state defects induced by
e-beam evaporation and hence a reduction of the contact re-
sistance. More damage is observed for thinner a-Si layers
what coincides with the higher contact resistance values that
are measured.
D. Reliability investigation
The Al/a-Si:H interface has been studied before and dif-
ferent temperatures at which the interaction starts have been
reported. Values as low as 150 �C have shown to have an
impact on the sheet resistance of the amorphous Si layer as
well as a beneficial impact on the contact resistance13 due to
suspected crystallization of the amorphous Si film. Light op-
tical inspection has shown pitting at the Al surface after
treatment at 170 �C,20 indicating inter-diffusion, and
Plagwitz et al.21 reported increased surface recombination
velocities and a reduction of the bulk lifetime after 1–2 h at
210 �C. In this work, the thermal reliability of the metal/a-Si
contacts is investigated in a similar way as was done for the
study of the impact of the deposition method. The (cali-
brated) lifetime is subsequently monitored as function of
temperature and time till failure occurs. The failure is
FIG. 5. Schematic measurement build-up for calibrated PL (a). Structure is
not drawn to scale. Calibrated PL images for various stages of ageing after
partial metallization of the sample by e-beam evaporation of Al (b) and
Ti/Al (c).
183508-5 Labie et al. J. Appl. Phys. 115, 183508 (2014)
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arbitrarily chosen when roughly most of the metalized sam-
ple area shows a reduced lifetime value below 1 ms. An
example of such a calibrated PL analysis after deposition
versus different stages of ageing at 120 �C is shown in
Figure 5(b). The time to failure is monitored for three differ-
ent temperatures which gives information on the kinetics of
the degradation process. The corresponding Arrhenius plot
of the lifetime degradation by interaction with Al and Ti/Al
is shown in Figure 6. The chosen temperature range is
slightly higher for the Ti/Al samples in order to speed-up the
failure time. A linear fit indicates a constant failure mecha-
nism for the tested temperature range. By assuming a similar
failure mechanism for the lower temperature region, one can
extrapolate the survival time at a specific temperature or one
can calculate the maximum operating temperature for a
required cell/module warranty of 20–25 yr The only temper-
ature-stress-test in the IEC (International Electrotechnical
Commission) module qualification specifications is a
requirement to survive 1000 h at 85RH/85 �C (this point is
indicated by a cross in Figure 6). Although both metalliza-
tion types would survive this stress test, a clear difference in
reliability and failure time can be observed when testing
beyond these specifications. This approach differs from the
referred works by measuring the rate of degradation rather
than listing up the effects at different isolated thermal budg-
ets what allows predicting the reliability of the metal contact.
This systematic failure rate investigation could however not
be obtained for the Ti/Cu stack due to a (too) long failure
time: even for annealing at a relatively high temperature of
200 �C, the a-Si/Ti/Cu stack did not show a significant life-
time reduction after more than 80 h while the lifetime of the
a-Si passivated substrate without any metallization started to
show a first reduction.
It is believed that the lifetime degradation is caused by
Al/a-Si:H inter-diffusion. In the case of the Al contact,
“pitting” is seen after 30 min @ 180 �C by LOM (light opti-
cal microscopy) and a FIB cross-section of the Al/a-Si:H
interface (Figure 7) clearly shows inter-diffusion of Al and
Si. Si precipitation occurs along the grain boundary of Al
and Al in-diffusion into Si is shown as well. This latter in-
diffusion seems to be limited to a depth comparable to the
i/nþ stack thickness, indicating a faster diffusion rate in a-Si
compared to c-Si. Possible crystallization and/or alloying of
the remaining a-Si parts are not further investigated. For the
Ti/Al metallized samples, degradation clearly starts at the
edge of the metal contact what suggests possible Al surface
diffusion leading to a delayed in-diffusion compared to a
direct Al contact (Figure 5(c)).
E. Reflectivity
The last important property for the back-contact metal
that is investigated in this work is its tendency to act as a
back-reflector by not absorbing or transmitting the light that
has travelled through the Si substrate. Ideally, a metal with
high reflectance for long wavelength light is preferred in
order to increase internal reflection and subsequently light
trapping and maximize the generated current. This is particu-
larly important in case of a backside metal contact on a-Si.
In view of the relatively high contact resistivity compared to
doped c-Si layers, a full contact area is required in order to
limit the total contact resistance and its contribution to theFIG. 6. Arrhenius plot of passivation degradation by monitoring the effec-
tive lifetime below 1 ms for different contact metal stacks.
FIG. 7. FIB cross-section of the Al/a-Si interface after thermal treatment at
180 �C (a) and 120 �C (b). The interaction of Al and a-Si at the highest tem-
perature is shown in more detail in the inset of (a).
183508-6 Labie et al. J. Appl. Phys. 115, 183508 (2014)
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cells series resistance. This means that the addition of a
dielectric layer between the silicon and the metal, with mini-
mal contact opening area, which would help enhancing the
reflection, is therefore not possible to use. The TCO contact-
ing layers mentioned earlier would be beneficial as well22
but they are costly to use and still show free carrier absorp-
tion in the near infrared region, which is the spectral region
of interest for a c-Si solar cell back-side reflector. The reflec-
tion spectra for the different full backside metallization
stacks studied here on mirror-polished c-Si samples are
shown in Figure 8. When the measured reflectance of the Al
sample is used as reference value, the addition of a 5 nm Ti
layer in between Si and Al reduces the reflectance value at
1200 nm (just below the c-Si bandgap) by almost 8%. When
this thin Ti layer is used in combination with Cu, it enhances
the total reflectance with 16%. A thicker Ti layer (30 nm),
that may be beneficial for reliability reasons, shows a very
poor reflectance value due to the large light penetration
depth (and thus absorption) in Ti at these wavelengths.
IV. CONCLUSIONS
Various metal stacks based on Ti or Al as contact mate-
rial are investigated on their capability for forming a reliable,
low-ohmic contact on i/nþ hydrogenated amorphous Si. A
heavily doped a-Si:H layer with an elemental P-concentration
of 2.1021 at/cm3, measured by SIMS, is used on top of a 5 nm
intrinsic a-Si:H layer resulting in bulk lifetimes of several
milliseconds. It is shown that a minimal doped layer thick-
ness of 10 nm is needed for achieving a low-ohmic contact.
Values as low as 10 mX cm2 are measured on 20–40 nm thick
nþ layers, independent of the used contact material as well as
the used deposition technique. Although an annealing step of
30 min at 120 �C was needed to reduce the contact resistance
for e-beam evaporated contact layers, this was not needed in
case of thermal evaporation. The difference between these
two deposition methods is believed to be caused by an
increased amount of surface state defects for the e-beam
evaporated samples that subsequently increases the barrier
height and contact resistance. The surface state density is
expected to reduce after anneal since a slight increase of the
lifetime is measured for e-beam samples. Thermal evaporated
samples show no impact of the metallization step and achieve
the low contact resistance values as from the start. While
other references show very harsh thermal treatments needed
to obtain low contact resistivity values, this is not needed for
the a-Si stack investigated in this work and the mild thermal
treatment at 120 �C for further contacting improvement did
not lead to a passivation degradation. The reliability perform-
ance is investigated by monitoring the bulk lifetime as mea-
sure for the passivation quality as a function of time for
different temperatures. This allows the extraction of the acti-
vation energy and describes the kinetics of the passivation
degradation. The addition of a thin interfacial Ti layer is
needed to improve the cells lifetime beyond the standard IEC
testing requirements. This layer however reduces the meas-
ured back-reflectance in combination with Al while the com-
bination of such a 5 nm thin Ti layer with Cu shows a
significant benefit in terms of back-reflectance. A trade-off
between reliability and back-reflector properties will have to
be made when choosing the metallization stack for hybrid
back-contact modules.
ACKNOWLEDGMENTS
The authors gratefully acknowledge the support of
IMEC’s Industrial Affiliation Program (IIAP-PV) and the
assistance of Richard Olivier for the TEM inspection and
analysis.
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Journal of Applied Physics is copyrighted by the American Institute of Physics (AIP).Redistribution of journal material is subject to the AIP online journal license and/or AIPcopyright. For more information, see http://ojps.aip.org/japo/japcr/jsp