Resonance Control Chassis

A Partnership of:

US/DOE

India/DAE

Italy/INFN

UK/UKRI-STFC

France/CEA, CNRS/IN2P3

Poland/WUST

Resonance Control Chassis

James Latshaw

PIP-II LLRF Preliminary Design Review

September 9, 2021

• Presentation Outline

• Introduction

• Resonance Control Chassis Scope

– RCC block diagram

• Functional Requirements / Preliminary Design

– Steppers

– Piezo

– Power Distribution PCB

– Communication (Chitchat)

– Software Interface and Control (EPICS)

• Accomplishments

• Bench Test Plan

• Path Forward

• Summary

LLRF PDR Content

Sept 9, 20212 RCC

• Presenter: James Latshaw

• Electrical Engineer at Jefferson Lab since 2019

– Experience working with Resonance and Interlocks control for

JLab LLRF 3.0

• Electrical Engineer at Huntington Ingalls Industries

– Sonar and combat systems

• Hardware Engineer at Lockheed Martin

– Circuit and firmware debug and testing

Introduction

Sept 9, 20213 RCC

• General overview: To provide a mechanism to mechanically tune four cavities as directed by

two RFS control satiations or via manual commands.

• This is achieved through various operational modes of four stepper motors and four piezo

drivers.

• Heavily leverages LCLS II RCC Design

Introduction - Resonance Control Chassis (RCC)

Sept 9, 20214 RCC

• The LCLS II system was successfully tested on the SSR1 Cryomodule

during PIP2IT

• The goal is to leverage this firmware and EPICS interface in the PIP-II

RCC design

– Similar firmware control algorithms as LCLS II

– Similar EPICS screens as LCLS II

– Similar EPICS control and functionality as LCLS II

Introduction

Jul 31, 20205

Block Diagram

Sept 9, 20216 RCC

Block Diagram

Sept 9, 20217 RCC

FPGA/Processing:FPGA CarrierFMC compatible

DC Power Breakout Board:

Stepper Driver:8 Drive Coils4 Stepper Channels

Piezo Driver:Pdu-150 Driven by 18 bit DAC4 Piezo Driver PCBs

Networking:2 QSFP Optic (U90-A111-1001)1 SFP (TE 2227302)1 Copper Ethernet (RJ45)

J10-J13

J5-J8

J9

J1-J4

Connection

Power

Breakout board replaces ribbon cable to Piezo drivers.

• External Hardware:

– 3U chassis design: T-ED0013968 - B001, B002, B003, B005

– Analog monitors and drive available external to the chassis via

front mounted TRS jacks: T-ED0013968 - B009, D005, D013

– All stepper and piezo drive signals delivered to rear of chassis: T-ED0013968 - B011, C008, D012

Functional Requirements / Preliminary Design

Sept 9, 20218 RCC : T-ED0013968

• External Hardware:


Sept 9, 20219 RCC : T-ED0013968

Rear

DC Power Entry

DB9 Stepper Drive

Neutrik Piezo Drive

Analog Drive (top)Analog Monitor (bottom)

Network Access

3U x 20” Chassis

• Steppers:

– Chassis will control four stepper channels: T-ED0013968 - C003

– The system shall have at least 2 Hz/step resolution stepper motor

control: T-ED0013968 - A006, C001

– Each Coil should produce no more than 2.5 A/phase: T-ED0013968 - C005

• Drive current can be set in software.

• TMC2660 drive chip uses 256 micro steps per full step.

• TMC2660 uses SPI configuration with standard DIR/STEP controls.

• 200 full steps per revolution.

– Stepper will be turned off when not in use (0 hold current):

T-ED0013968 - C002

• Enable/Disable MOSFET on TMC2660 drive chip

– Limit switches : T-ED0013968 - A011, C006

– Digital isolators shall be used on digital signals: T-ED0013968 - D010


Sept 9, 202110 RCC : T-ED0013968

• Steppers:

– Same as LCLS II


Sept 9, 202111 RCC : T-ED0013968

DB9

TMC2660 Stepper Driver

IDC Ribbon Cable

15 VDC(power entry)

Temperature Sensor

Digital Isolation (control)

Digital Isolation (limit switches)

• Piezo Drives:

– The system shall have better than 1 Hz resolution piezo tuner control: T-ED0013968 - A006, D002

– Amplifier selected shall be PDu150: T-ED0013968 - D008

– ADC monitors shall be updated at a rate of 4 kHz: T-ED0013968 - D007

• Sample Rate may be set in software (nominally 2 KHz)

– Digital isolators shall be used on digital signals: T-ED0013968 - D010


Sept 9, 202112 RCC : T-ED0013968

• Piezo Drives:

– Functionally, same

design as LCLS II


Sept 9, 202113 RCC : T-ED0013968

+16 VDC (fused)

-16 VDC (fused)

Analog Input

Analog Monitor

Pluggable IDC(no ribbon cable)

PDu150 footprint

8 Channel 18 bit ADC, 200 KSPS

18 bit DAC

Digital Isolators

Piezo Drive Output

18 bit DAC

Analog Input

Analog Monitor

• Power Distribution:

– Panel mount power distribution board

– +12 VDC , + 15 VDC, + 16 VDC


Sept 9, 202114 RCC : T-ED0013968

FPGA Carrier

Breakout Board Stepper DriverPanel Mount

• Communication:

– The RCC will receive detune data using high speed fiber (QSFP) with

common communication modules in all systems (Chitchat): T-ED0013968 - A003, E001, E002, E003, E005

– Network communication via SFP: T-ED0013968 - E004, E006, E007, E008, F002


Sept 9, 202115 RCC : T-ED0013968

QSFP (RFS Detune)

SFP (EPICS)

Copper RJ45 (spare)

• Software Control:

– RCC shall be capable of being controlled via EPICS with auto and

manual tuning mode options: T-ED0013968 - A003, A007, A010, F002

– Configuration, alarm reporting and data acquisition will be made

available to EPICS: T-ED0013968 - A009, A010, A011, A012, D004, F001


Sept 9, 202116 RCC : T-ED0013968

• Software Control: EPICS, Tuning, Register read backs


Sept 9, 202117 RCC : T-ED0013968

• Software Control: Resonance Control, Piezo


Sept 9, 202118 RCC : T-ED0013968

Leverages Berkley Firmware

• Software Control: EPICS, ADC/DAC waveform display


Sept 9, 202119 RCC : T-ED0013968

• Software Control: Resonance Control, Stepper


Sept 9, 202120 RCC : T-ED0013968

Detune info & RF ON/OFF

RF OFF

Cavity Tuned

RF ON

NO

Piezo Centered

YES

Move Piezo by1 Hz to tune Cavity

NOMove Stepper by 1Hz to center

Piezo

Piezo Centered

Turn MOSFETs Off (Zero Hold Current)

Set Stepper Current

RFS Update

YES

NO YES

Leverages Berkley Firmware

• Software Interface

– Able to communicate with chassis via LEEP scripts (SFP)

• EPICS to chassis communication also achieved (SFP)

• Able to see waveforms in EPICS (SFP)

– Able to communicate RFS to RCC via Chitchat (QSFP)

• Firmware

– Able to configure ADCs

– Able to configure and drive DAC (manually and with NCO)

– Able to configure stepper driver chip

• Other Functions

– Able to drive DAC via front input jacks

– Able to monitor DAC drive via front input jacks

– Able to move motors, monitor limit switches

– Working front panel LEDs

Accomplishments

Sept 9, 202121 RCC

• Additional details on bench testing are in the ‘back up’ slides

• Tests:

– Front monitor control port test

– DAC and ADC test

– Manual stepper mode test

– Auto mode stepper test

– PDu150 Drive test

Bench Tests

Sept 9, 202122 RCC

• Develop Chitchat detune data interface. We are receiving

complete packets from RFS to RCC via QSFP. Other data

sent over QSFP (such as chassis ID, counts, etc.) are being

received.

• Work on EPICS screen initialization to ensure that all

registers are being initialized to their desired value.

• FPGA carrier down select and associated pinout interface

modifications.

• Test with Cryomodule / real motors and piezo loads in the

loop.

• Will be used at the Cryomodule Test Facility.

Path Forward

Sept 9, 202123 RCC

• New RCC is adapted from proven LCLS II design

– Functionally the same Piezo Driver/PDu150 and Stepper driver

as LCLS II

• Communication between RFS and RCC / EPICS and RCC

has been achieved

• Basic functionality of motors and ability to drive piezo loads

has been verified through bench testing

Summary

Sept 9, 202124 RCC

Backup Slides

Sept 9, 202125 RCC

Chassis Pictures

Sept 9, 202126 RCC

RCCPower Supply

Chassis Pictures

Sept 9, 202127

FPGA Carrier

Stepper Drive

PDU

Motherboard

Monitor Ports

Neutrik

Piezo Drive

SFP

PDu150

• Connect a signal generator to manually drive the PDu150

(bypass DAC)

• Connect an Oscilloscope to monitor port

• Dump waveforms using LEEP commands or view on EPICS

• Also tests ADCs

Bench Test Plan – Front monitor ports

Sept 9, 202128 RCC

O-Scope Source

EPICS

RFS1

RFS2

• Connect an Oscilloscope to monitor port

• Ensure both RFSs are sending a valid detune angle

• Set DAC to be driven by received detune angle

• Use epics screens to see waveform plots

• Verify Oscilloscope signal against anticipated detune signal

Bench Test Plan – DAC / ADC

Sept 9, 202129 RCC

O-Scope

EPICS

RFS1

RFS2

RFS1RFS2

• Using epics screens, manually move each stepper motor in

both directions one full rotation (256*200 steps)

• Perform test at different currents

• Ensure motor does not move if its respective directional limit

switch is reporting a fault (HFLF and LFLF)

– Adjust the stepper so that it tunes for higher frequency

– Engage HFLF and ensure motor stops moving and cannot

move further

– Perform the same test but for LFLF

Bench Test Plan – Stepper in Manual mode

Sept 9, 202130 RCC

Stepper Test Fixture

• Use DAC/ADC test bench configuration

• Ensure RFS detune is a constant

• Ensure motor turns in one direction

• Reverse detune sign and ensure motor turns in opposite

direction

Bench Test Plan – Stepper in Auto mode

Sept 9, 202131 RCC

Stepper Test Fixture

• Front monitor port configuration

• Drive input monitor with known detune waveform (verify with

waveforms/ADC)

• Connect capacitive load to Piezo drive which is being tested

Bench Test Plan – PDu150 Drive

Sept 9, 202132 RCC

Capacitive Load (2)

Resource Utilization (Cyclone 10 GX)

Sept 9, 202133 RCC

• General overview: To provide a mechanism to mechanically

tune four cavities as directed by two RFS control satiations or

via manual commands.

• This is achieved through various operational modes of four

stepper motors and four piezo drivers.

Resonance Control Chassis Scope

Sept 9, 202134 RCC

SFP - Fiber

Documents

Resonance Control Chassis